JP2012163458A - Coulomb counter and electronic information apparatus - Google Patents

Abstract

The charge / discharge amount (coulomb amount) of a secondary battery can be integrated internally, the accumulated coulomb amount can be read at an arbitrary timing, and the circuit scale can be reduced and the cost can be reduced. Get a promising coulomb counter.
In a coulomb counter 100a that outputs a count value proportional to the input voltage using a potential difference generated between both ends of a detection resistor as an input signal, the input voltage is used as an input signal and has a duty ratio corresponding to the input voltage. When the clock signal is input to the output delta-sigma modulator 100, the pulse signal is counted up when the output pulse of the delta-sigma modulator is high, and when the clock signal is input, the delta-sigma modulator is counted. And an up / down counter 101 that counts down when the output pulse is low level.
[Selection] Figure 1

Description

  The present invention relates to a coulomb counter and an electronic information device, and more particularly to a coulomb counter capable of reducing the circuit scale and an electronic information device equipped with such a coulomb counter.

  Conventionally, in the field of mobile devices using a secondary battery such as a notebook personal computer (PC), a mobile phone, a game machine, etc., a device having a battery residual detection device for detecting the remaining battery level of the secondary battery in use Is widely used.

  This battery residual detection device, also called a coulomb counter, converts charge / discharge current flowing through a detection resistor (sense resistor) into voltage, and detects the remaining battery level of the secondary battery based on the converted voltage value. It is.

  FIG. 10 is a diagram for explaining the coulomb counter disclosed in Patent Document 1, for example, and conceptually shows the relationship between the coulomb counter and the system to which it is applied.

  The system S to which the coulomb counter 200 is applied is, for example, an electronic device such as a notebook computer, a mobile phone, or a game machine. In such a system S, for example, a rechargeable secondary battery such as a lithium ion battery is detachably mounted.

  The coulomb counter 200 includes a detection resistor (hereinafter referred to as a sense resistor) Rs and an IC unit 50 that outputs a count value proportional to the input voltage using a potential difference generated between both ends of the sense resistor as an input voltage. Here, the sense resistor Rs is a resistance element for detecting a current flowing into or out of the secondary battery (that is, a charge / discharge current), and one end thereof is connected to the secondary battery on the system S side, for example. The other end is connected to a ground potential, for example.

  Further, the IC unit 50 is provided with two input terminals Vin + and Vin−, and these input terminals Vin + and Vin− are respectively connected to both ends of the sense resistor Rs. Therefore, when a charging / discharging current flows through the sense resistor Rs, a potential difference (that is, an input voltage) is generated between the input terminals Vin + and Vin− according to the direction and magnitude of the current. In other words, the charge / discharge current is converted into the input voltage by the sense resistor Rs. Then, for example, a 13-bit count value is output from the IC unit 50 in proportion to the input voltage.

  FIG. 11 is a block diagram illustrating a configuration example of the IC unit 50.

  The IC unit 50 constituting the coulomb count 200 includes, for example, switches A1, A2, B1, B2, C1, C2, D1, D2, S1, S2, R1, R2, I1, I2, and sampling capacitors Cs1, Cs2. , Integration capacitors Ci1 and Ci2, a fully differential input operational amplifier 1, a reference voltage generation circuit (hereinafter referred to as a VREF circuit) 3, a comparator 5, and a logic circuit 10.

  That is, in the IC unit 50, the input side electrode of the sampling capacitor Cs1 is connected to the input terminal Vin + through the switch A1 and is connected to the input terminal Vin− through the switch B1. The input side electrode is connected to the X terminal of the VREF circuit 3 through the switch C1 and is connected to the Y terminal of the VREF circuit 3 through the switch D1. The output side electrode of the sampling capacitor Cs1 is connected to the positive (+) input terminal of the fully-differential input operational amplifier 1, and is connected to a common voltage (hereinafter referred to as VCM) via the switch S1. The VCM is 1V, for example.

  In the IC section 50, the input side electrode of the sampling capacitor Cs2 is connected to the input terminal Vin− via the switch A2 and to the input terminal Vin + via the switch B2. The input electrode of the sampling capacitor Cs2 is connected to the X terminal of the VREF circuit 3 through the switch D2, and is connected to the Y terminal of the VREF circuit 3 through the switch C2. The output electrode of the sampling capacitor Cs2 is connected to the negative (−) input terminal of the fully-differential input operational amplifier 1 and to the common voltage (VCM) via the switch S2.

  These switches A1, A2, B1, B2, C1, C2, D1, D2, S1, S2, R1, R2, I1, and I2 are composed of, for example, MOS field effect transistors, and the on / off of the logic circuit 10 This is performed by a control signal output from.

  Further, in the IC unit 50, the input side electrode of the integration capacitor Ci1 is connected to the positive input terminal of the fully differential input operational amplifier 1, and the output side electrode thereof is connected to the negative of the fully differential input operational amplifier 1 via the switch I1. Connected to the output terminal. The input side electrode of the integration capacitor Ci2 is connected to the negative input terminal of the fully differential input operational amplifier 1, and the output side electrode thereof is connected to the positive output terminal of the fully differential input operational amplifier 1 via the switch I2. Further, discharge switches R1 and R2 are connected to both ends of the integration capacitors Ci1 and Ci2, respectively.

  The negative output terminal and the positive output terminal of the fully-differential input operational amplifier 1 are connected to the comparator 5, respectively. The potential Vout− on the negative output terminal side is input to the input terminal In + of the comparator 5, and the potential Vout on the positive output terminal side. + Is input to the input terminal In− of the comparator 5. Further, the comparator 5 is connected to the logic circuit 10, and a non-inverted signal (signal Q) output from the output terminal Q of the comparator 5 and an inverted signal (signal QB) output from the output terminal QB of the comparator 5 are respectively received. The signal is input to the logic circuit 10. Although not shown, the oscillation circuit is also connected to the logic circuit 10, and a clock (CLOCK) signal generated by the oscillation circuit is input to the logic circuit 10.

  FIG. 12 is a block diagram illustrating a configuration example of the logic circuit 10.

  The logic circuit 10 includes an internal counter 11, a frequency divider 13, an update pulse generator 15, a current measurement register (CMR: Current Measurement Register) 17, an arithmetic circuit 18, and an integrated current register (ACR: Accumulated Current Register). 19). The current measurement register (CMR) 17 and the accumulated current register (ACR) 19 are registers each composed of a plurality of flip-flops, for example.

  As shown in FIG. 12, the internal counter 11 has a clock (CLOCK) signal generated by an oscillation circuit (not shown) and the CLOCK signal divided by, for example, two by the frequency divider 13 (that is, the pulse width is doubled). Frequency-divided signal ClkDiv1), a register update pulse (hereinafter, update pulse) generated by the update pulse generator 15 based on the CLOCK signal, and a signal Q output from the comparator 5 (see FIG. 11), QB is input.

  Furthermore, the internal counter 11 has at least two or more output terminals, the first terminal is connected to the current measurement register (CMR) 17, and the second terminal is connected to the integrated current register (ACR) via the arithmetic circuit 18. ) 19.

  Here, the current measurement register (CMR) 17 holds the internal count value output from the internal counter 11 as the “count value per conversion time” when the update pulse is input, and the value to be held Is output to the outside. The arithmetic circuit 18 performs predetermined arithmetic processing on the internal count value output from the internal counter 11 when the update pulse is input, and outputs the arithmetic value. The ACR 19 accumulates the calculated values sequentially to hold a “count value per unit time” and outputs the held value to the outside. The “count value per conversion time” and the “count value per unit time” are both data indicating the charge / discharge state of the secondary battery.

  Next, an operation example of the coulomb counter will be described.

  FIG. 13 is a timing chart illustrating an operation example of a switch or the like included in the coulomb counter.

  In FIG. 13, “CLKR” indicates the clock operation of the switches R1 and R2 shown in FIG. 11, “CLKA” indicates the clock operation of the switches A1 and A2, and “CLKB” indicates the clock operation of the switches B1 and B2. , “CLKC” indicates the clock operation of the switches C1 and C2, “CLKD” indicates the clock operation of the switches D1 and D2, “CLKS” indicates the clock operation of the switches S1 and S2, and “CLKI” indicates the switch S1, The clock operation of S2 is shown. “EN” indicates an output control signal (Enable) input to the comparator 5.

  First, at Timing (timing) 1, the switches R1 and R2 are turned on, and the charges of the integration capacitors Ci1 and Ci2 are discharged. As a result, the accumulated charge of the integration capacitor becomes 0 (zero). This discharge operation is performed only before the start of the counting operation by the coulomb counter, that is, at the time of resetting.

  Next, in Timing 2, the switches A1, A2, S1, and S2 are turned on, and all other switches are turned off. Thereby, an input voltage sampling operation is performed.

  Next, in Timing 3, the switches B1, B2, I1, and I2 are turned on, and all other switches are turned off. Thereby, the integration operation of the input voltage is performed.

  Next, at Timing 4, the switches C1, C2, S1, and S2 are turned on, and all other switches are turned off. Thereby, the reference voltage sampling operation is performed.

Next, in Timing 5, the switches D1, D2, I1, and I2 are turned on, and all other switches are turned off. Thereby, the integration operation of the reference voltage is performed.
Thereafter, the operations of Timing 2 to 4 are repeated, and the input voltage is converted into signals Q and QB by the comparator 5, and the comparator 5 has a duty ratio corresponding to the magnitude of the input voltage as the signals Q and QB. Complementary pulse signals are output.

  Specifically, for example, in the state where no current flows through the detection resistor, the duty ratio of the signal Q is 50%, and in the discharge state, the duty ratio becomes a value larger than 50% according to the amount of current. In the state, the duty ratio becomes a value smaller than 50% according to the amount of current.

  FIG. 14 is a diagram for explaining a method of counting the signals Q and QB output from the comparator 5 by the logic circuit 10.

In FIG. 14, one cycle of the frequency-divided signal ClkDiv1 is set to 102 μsec (≈0.8 sec / 8192, 8192 = 2 ¹³ ), for example. Further, one cycle of the update pulse is set to, for example, 0.8 sec (≈3600 sec / 4096, 4096 = 2 ¹² ), and the update pulse is output approximately 2 ¹² times per hour.

  In FIG. 14, when ClkDiv1 is LOW (low) and the CLOCK signal falls, the internal counter 11 counts +1 if the signal Q is input and counts -1 if the signal QB is input. To do. At the input timing of the update pulse, the internal counter 11 outputs a value obtained by adding the signals Q and QB (hereinafter referred to as an internal count value) to both the CMR 17 and the ACR 19 and sets the internal count value to zero (0). Reset to.

  For example, in FIG. 11B, 6726 is described as an example of the internal count value when the update pulse is input, but this internal count value (6726) is output to both the CMR 17 and the ACR 19 simultaneously. The

  Incidentally, when only the signal Q is input to the internal counter 11 between the input of the update pulse and the input of the next update pulse, the internal count value is 8192, for example. Conversely, when only the signal QB is input to the internal counter 11, the internal count value is, for example, -8192.

  As described above, when the internal count value (6726) is simultaneously output to both the CMR 17 and the ACR 19, the CMR 17 holds the internal count value as “count value per one conversion time”. Here, the one-time conversion time is the time from when an update pulse is input until the next update pulse is input (that is, one cycle of the update pulse).

Further, the internal count value (6726) output to the ACR 19 is input to the ACR 19 after being processed by the arithmetic circuit 18. For example, the internal count value (6726) is divided by 4096 (= 2 ¹² ) by the arithmetic circuit, and a value (for example, integer 1) rounded down after the decimal point is input to the ACR 19. Each time an update pulse is input, the ACR 19 adds such an integer value and holds it as a “count value per unit time”. Here, the unit time is a time that can be arbitrarily set, for example, one conversion time × 4096 times (≈0.8 sec × 4096≈1 hour). The “count value per unit time” held by the ACR 19 indicates the charge / discharge amount per unit time, and this value is output to the outside.

  And the charge / discharge amount measured in the time equivalent to the frequency | count of an update pulse is obtained by adding the count value per said conversion time for every update pulse.

JP 2009-192464 A

  By the way, in the battery residual detection device (Coulomb counter) disclosed in Patent Document 1, as described above, the output value from the digital-sigma modulator is held at the timing of the output of the frequency divider or the update pulse. That is, the count value per unit time obtained based on the output of the frequency divider (that is, the amount of current per unit time) and the conversion time per conversion time obtained based on the output of the update pulse generator The amount of current consumed or charged is calculated using the count value (current amount measurement time). For this reason, in the above conventional example, a frequency divider or update pulse is generated to calculate the remaining battery level. There is a problem that a circuit is required, and the circuit scale is increased by at least that much.

  Further, in the above-described conventional battery residual detection device, the coulomb amount is determined at an arbitrary timing because the coulomb amount is determined based on the count value converted from the output of the digital-sigma modulator at regular intervals. The counter value cannot be read because the count value is read from the internal counter of the logic IC and the coulomb amount (current amount) corresponding to the count value is added. If you can not add the amount of coulomb.

  The present invention has been made in order to solve the above-described problems, and the charge / discharge amount (coulomb amount) of the secondary battery can be integrated internally, and the coulomb amount integrated at an arbitrary timing can be obtained. It is an object of the present invention to obtain a coulomb counter that can be read and can be reduced in cost, and can be reduced in circuit scale, and an electronic information device using such a coulomb counter.

  A coulomb counter according to the present invention is a coulomb counter that outputs a count value proportional to the input voltage using a potential difference generated between both ends of a detection resistor as an input signal. When the clock signal is input, the pulse signal having a duty ratio is counted up when the output pulse of the delta-sigma modulator is at a high level, and the delta-sigma modulator is input when the clock signal is input. And an up / down counter that counts down when the output pulse of the sigma modulator is at a low level, thereby achieving the above object.

  In the present invention, the coulomb counter preferably includes a counter circuit that counts the number of clock signals input to the up / down counter.

  In the present invention, the coulomb counter preferably includes a switch for short-circuiting the detection resistor.

  In the present invention, the coulomb counter preferably includes an addition circuit for adding an arbitrary value to the count value output from the up / down counter.

  According to the present invention, the coulomb counter preferably includes a subtracting circuit that subtracts an arbitrary value from the count value output from the up / down counter.

  The present invention includes a multiplier circuit that multiplies a count value output from the up / down counter by an arbitrary value and a storage circuit that stores a multiplication value obtained by the multiplier circuit. Is preferred.

  The present invention includes the above-described coulomb counter, including a division circuit that divides a count value output by the up / down counter by an arbitrary value, and a storage circuit that stores a division value obtained by the division circuit. Is preferred.

  According to the present invention, the coulomb counter preferably includes a storage circuit that holds a counter value output from the up / down counter at an arbitrary timing.

  According to the present invention, the coulomb counter preferably includes a reset circuit that resets a counter value of the up / down counter.

  According to the present invention, in the coulomb counter, the delta-sigma modulator preferably has an input terminal that receives a differential signal as an input signal.

  According to the present invention, in the coulomb counter, the delta-sigma modulator preferably includes a standby circuit that switches its operation mode to a standby mode.

  An electronic information device according to the present invention is an electronic information device that includes a functional circuit that performs a predetermined circuit operation and a secondary battery that drives the functional circuit, and that detects a remaining amount of the secondary battery. The remaining amount detection circuit includes a coulomb counter according to claim 1, thereby achieving the above object.

  Next, the operation of the present invention will be described.

  In the present invention, in a coulomb counter that outputs a count value proportional to the input voltage using a potential difference generated across the detection resistor as an input voltage, a delta-sigma modulator that uses the input voltage as an input signal, In the up / down counter, an up / down switching signal, which is the output of the delta-sigma modulator, counts +1 every time the output of the delta-sigma modulator is high, for example, every clock. The time is counted by -1.

  According to such a configuration, the amount of current flowing through the detection resistor can be grasped from the count value of the up / down counter. Therefore, for example, when one end of the detection resistor is connected to the secondary battery, the amount of charge / discharge current flowing through the detection resistor can be determined from the count value.

  The count value of the up / down count circuit is a number proportional to the potential difference (that is, input voltage) generated at both ends of the detection resistor, and is a number proportional to the current flowing through the detection resistor. Therefore, a frequency divider and an update pulse generator are unnecessary, and the circuit scale can be reduced.

  In the present invention, the coulomb counter includes a counter circuit that counts the clock signal that has entered the up / down counter, so that the count value of the counter circuit circuit that counts the clock signal is multiplied by the clock frequency. The total current flowing through the detection resistor can be known.

  In the present invention, since the coulomb counter includes a switch for short-circuiting the detection resistor, when the switch for short-circuiting the detection resistor is used, the potential difference generated at both ends of the resistor becomes zero, and the up-down counter The count value should also be zero. If the count value of the up / down counter becomes a value other than zero, an offset value is generated in the coulomb counter, and the offset value can be known.

  In the present invention, the coulomb counter includes a circuit for adding an arbitrary value to the count value of the up / down counter, so that the offset value that can be known by the coulomb counter as described above is added to the counter value. By doing so, the offset value can be corrected.

  In the present invention, the coulomb counter is provided with a circuit for subtracting an arbitrary value from the count value of the up / down counter, so that the offset value that can be known by the coulomb counter as described above is subtracted from the counter value. By doing so, the offset value can be corrected.

  In the present invention, the coulomb counter includes a multiplication circuit that multiplies the count value of the up / down counter and an arbitrary value, and a storage circuit that stores the multiplication value of the multiplication circuit. Even when the resistance value of the detection resistor varies and the potential difference generated at both ends also changes, the change in the count value relative to the change in the potential difference generated in the detection resistor can be corrected.

  In the present invention, the coulomb counter includes a division circuit that divides the count value of the up / down counter by an arbitrary value, and a storage circuit that stores the division value of the division circuit. Even when the resistance value of the detection resistor varies and the potential difference generated at both ends also changes, the change in the count value relative to the change in the potential difference generated in the detection resistor can be corrected.

  In the present invention, the coulomb counter includes a storage circuit that holds the counter value of the up / down counter at an arbitrary timing, so that the counter value of the up / down counter can be held before reading. It is possible to avoid reading the wrong count value because the counter value changes at the timing.

  In the present invention, the coulomb counter includes a reset circuit that resets the counter value of the up / down counter. Therefore, when the coulomb counter is started, the counter value of the previous up / down counter can be reset, The count value can be reset before the count value of the down counter overflows, that is, before the upper limit value is exceeded.

  In the present invention, in the above-described coulomb counter, the delta-sigma modulator is configured to operate by differential signal input, so that the common-mode signal entering the coulomb counter can be removed, and the S / N ratio is increased. Can do.

  In the present invention, since the delta-sigma modulator is provided with a standby circuit in the coulomb counter, in a state where the portable device does not require a coulomb counter such as an OFF state, the standby circuit counts the coulomb counter, The operation of the digital-sigma modulator and the up / down counter can be stopped, and the power consumption can be reduced.

  As described above, according to the present invention, the charge / discharge amount (coulomb amount) of the secondary battery can be integrated internally, the accumulated coulomb amount can be read at an arbitrary timing, and the circuit scale can be reduced. Therefore, it is possible to obtain a coulomb counter that can reduce costs and an electronic information device using such a coulomb counter.

FIG. 1 is a diagram for explaining a coulomb counter according to the first embodiment of the present invention, and shows a relationship among a coulomb counter 1000, a detection resistor 2000, a load 3000, and a secondary battery 4000. FIG. 2 is a diagram for explaining a coulomb counter according to the second embodiment of the present invention, and shows a configuration including a counter circuit for counting clocks. FIG. 3 is a diagram for explaining a coulomb counter according to the third embodiment of the present invention, and shows a configuration including a switch for short-circuiting a detection resistor. FIG. 4 is a diagram for explaining a coulomb counter according to the fourth embodiment of the present invention, and shows a configuration including an arithmetic unit for calculating a count value. FIG. 5 is a diagram for explaining a coulomb counter according to the fourth embodiment of the present invention. The relationship between the count value and the offset correction (FIG. 5A), and the relationship between the count value and the inclination correction (FIG. 5B). )). FIG. 6 is a diagram for explaining a coulomb counter according to the fifth embodiment of the present invention, and shows a configuration including a storage circuit for holding a counter value and a reset circuit. FIG. 7 is a diagram for explaining a coulomb counter according to a sixth embodiment of the present invention, and shows a delta-sigma modulator using a differential signal as an input signal. FIG. 8 is a diagram for explaining the coulomb counter according to the sixth embodiment of the present invention, and shows the arrangement of the coulomb counter on the printed circuit board (FIGS. (A) and (b)). FIG. 9 is a diagram for explaining a coulomb counter according to a seventh embodiment of the present invention, and shows a delta-sigma modulator including a standby circuit. FIG. 10 is a diagram for explaining a conventional coulomb counter 100 disclosed in Patent Document 1, and shows a relationship between the coulomb counter and the system S. FIG. 11 is a diagram illustrating a configuration example of the IC unit 50 configuring the conventional coulomb counter 100. FIG. 12 is a diagram illustrating a configuration example of the logic circuit 10 included in the IC unit. It is a figure explaining operation | movement of the IC part 50 which comprises the said conventional coulomb counter 100, and operation | movement of a switch etc. is shown with the timing chart. It is a figure explaining the operation | movement of the said conventional coulomb counter 100, and has shown the counting method of the signal Q and the signal QB which the delta-sigma modulator which comprises this IC part 50 outputs.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram for explaining a coulomb counter 100a according to a first embodiment of the present invention, and shows a configuration example of a coulomb counter.

  The coulomb counter 100a according to the first embodiment is a coulomb counter that outputs a count value proportional to the input voltage with the potential difference generated between both ends of the detection resistor 200 as an input voltage.

  Here, the detection resistor 200 is connected in series to a load 300 and a battery (secondary battery) 400 as a power source. When the battery is charged, the load 300 and a charging circuit (not shown) are switched.

  Here, the detection resistor 200 is a resistance element for detecting a current flowing into or out of the secondary battery (that is, a charge / discharge current), one end of which is connected to the negative side of the secondary battery, for example. The other end is connected to a ground potential, for example.

  The coulomb counter 100a has a delta-sigma modulator 100 that outputs a pulse signal (output pulse) Q having an input voltage (IN_P) as an input signal and a duty ratio corresponding to the input voltage. When the output pulse Q of the delta-sigma modulator 100 is high level, it counts up, and when the clock signal CLK is input, it counts down when the output pulse Q of the delta-sigma modulator 100 is low level. And an up / down counter 101. Here, the delta-sigma modulator 100 has the same circuit configuration as the delta-sigma modulator 50 in the conventional coulomb counter 200 shown in FIG. 11, and one input terminal Vin + is connected to the battery side end of the detection resistor 200. And the other input terminal Vin− is grounded.

  Next, the function and effect will be described.

  In such a coulomb counter 100 a, the up / down counter 101 switches between up-counting and down-counting based on the output Q of the delta-sigma modulator 100. For example, the count is performed according to whether the output of the delta-sigma modulator is high or low every clock. Specifically, when the output of the delta-sigma modulator is high, the count is +1 (up-count), When the output is low, -1 count (down count) is performed.

  In the coulomb counter 100 a having such a configuration, the amount of current flowing through the detection resistor 200 can be grasped from the count value of the up / down counter 101. Therefore, for example, when one end of the detection resistor 200 is connected to the secondary battery, the amount of charge / discharge current flowing through the detection resistor can be determined from the count value.

  The count value of the up / down counter 101 is a number proportional to the potential difference (that is, input voltage) generated at both ends of the detection resistor, and is a number proportional to the current flowing through the detection resistor. Therefore, unlike the coulomb counter disclosed in Patent Document 1, a pulse signal from a frequency divider, an update pulse generator, or the like, which is a timing signal for obtaining the current flowing through the detection resistor from the count value, is unnecessary. The circuit scale can be reduced.

As described above, in the first embodiment, in the coulomb counter 100a that outputs the count value proportional to the input voltage using the potential difference generated between both ends of the detection resistor as the input voltage, the input voltage is used as the input signal, and the input voltage is determined according to the input voltage. When the clock signal is input, the pulse signal having a duty ratio is counted up when the output pulse of the delta-sigma modulator is at a high level and the clock signal is input. Since the up / down counter 101 counts down when the output pulse of the delta-sigma modulator is at a low level, the charge / discharge amount (coulomb amount) of the secondary battery can be integrated inside the coulomb counter. , You can read the coulomb amount accumulated at any time, It can be obtained coulomb counter that allows a reduction in the road size and the cost reduction can be expected.
(Embodiment 2)
FIG. 2 is a diagram for explaining a coulomb counter according to the second embodiment of the present invention, and shows a configuration including a counter circuit for counting clocks.

  The coulomb counter 100b of the second embodiment includes a counter circuit that counts clock signals input to the up / down counter 101 in addition to the configuration of the coulomb counter 100a of the first embodiment.

In the coulomb counter 100b configured as described above, in addition to the effect of the first embodiment, the time from the start of counting by the coulomb counter to the present time is obtained by multiplying the count value of the counter circuit 102 that counts the clock signal and the clock cycle. As a result, it is possible to obtain the effect of knowing the total current flowing through the detection resistor during the elapsed time from the start of counting by the coulomb counter to the present time.
(Embodiment 3)
FIG. 3 is a diagram illustrating a coulomb counter according to the third embodiment of the present invention.

  The coulomb counter 100c of the third embodiment includes a switch 103 connected in parallel to the detection resistor 200 in addition to the configuration of the coulomb counter 100a of the first embodiment.

  In the coulomb counter 100c of the third embodiment having such a configuration, the detection resistor can be short-circuited by turning on the switch 103. Thus, when the detection resistor 200 is short-circuited, the input voltage to the delta-sigma modulator 100 becomes 0, and the offset value of the coulomb counter 100 can be measured.

  That is, when the switch 103 for short-circuiting the detection resistor 200 is turned on, the potential difference generated at both ends of the detection resistor 200 should be zero, and the count value of the up / down counter should be zero.

Accordingly, if the count value of the up / down counter becomes a value other than zero, an offset value has occurred in the coulomb counter, and the count value other than zero at this time can be detected as the offset value.
(Embodiment 4)
FIG. 4 is a diagram illustrating a coulomb counter according to the fourth embodiment of the present invention.

  In addition to the configuration of the coulomb counter 100a of the first embodiment, the coulomb counter 100d of the fourth embodiment includes an arithmetic unit 104 that performs arithmetic processing using an arbitrary value for the output of the up / down counter 101, and the calculation result. And a storage circuit 105 for storing.

  Here, the arbitrary value is data DATA such as the offset value and gain of the digital-sigma modulator 100. In this embodiment, the arbitrary value is calculated from the outside of the coulomb counter 100d by the calculator 104 of the coulomb counter. It is the composition which supplies to.

  For example, the arithmetic unit 104 is used to set the offset value (that is, the count value corresponding to the value of the signal Q of the digital-sigma modulator when the input voltage is 0) to the output (count value) of the up / down counter. As shown in FIG. 5A, the output (count value) with respect to the input voltage of the coulomb counter is in a normal state indicated by a solid line grab 10 as indicated by a broken line graph 12 by using an addition circuit for addition. When the offset is negative by a certain amount, the offset can be corrected to obtain a normal state.

  On the other hand, the arithmetic unit 104 determines the offset value (that is, the count value corresponding to the value of the signal Q of the digital-sigma modulator when the input voltage is 0) from the output (count value) of the up / down counter. By using a subtraction circuit for subtraction, as shown in FIG. 5A, the output (count value) with respect to the input voltage of the coulomb counter is in a normal state indicated by a solid line grab 10 as indicated by a broken line graph 11. When the offset is offset to the plus side by a certain amount, the offset can be corrected to obtain a normal state.

  Further, the arithmetic unit 104 is a multiplication circuit that multiplies a predetermined correction gain (that is, the correction amount of the change amount of the counter value with respect to the unit change amount of the input voltage) by the output (count value) of the up / down counter. Thus, as shown in FIG. 5B, the change of the output (count value) with respect to the change of the input voltage of the coulomb counter is in the normal state indicated by the solid line grab 10 as shown by the two-dot chain line graph 14. When it is larger by a certain amount than the object, the gain in the coulomb counter can be corrected to obtain a normal state.

  On the other hand, the arithmetic unit 104 includes a division circuit for dividing the output (count value) of the up / down counter by a predetermined correction gain (that is, the correction amount of the change amount of the counter value with respect to the change of the unit amount of the input voltage). Thus, as shown in FIG. 5B, the change of the output (count value) with respect to the change of the input voltage of the coulomb counter is in the normal state shown by the solid line graph 10 as shown by the two-dot chain line graph 13. When a certain amount is smaller than the above, the gain in the coulomb counter can be corrected to be in a normal state.

  In particular, even if the value of the detection resistor varies, or sometimes the resistance value of the detection resistor changes to change the potential difference that occurs at both ends, the potential difference (offset) of the resistor and the slope (gain) of the count value are It can be corrected.

As described above, the fourth embodiment includes a computing unit that performs arithmetic processing using an arbitrary value for the up / down counter. By adding, subtracting, multiplying, or dividing the value, the offset of the count value of the coulomb counter or its gain can be adjusted.
(Embodiment 5)
FIG. 6 is a diagram illustrating a coulomb counter according to the fifth embodiment of the present invention.

  In addition to the configuration of the coulomb counter 100a of the first embodiment, the coulomb counter 100e includes a storage circuit 106 that holds the counter value of the up / down counter 101 at an arbitrary timing and resets the stored counter value at an arbitrary timing. It is provided.

  Here, the storage circuit 106 is configured to store a latch (LAT) signal from the outside of the coulomb counter 100e, and to reset the stored counter value by a reset (RESET) signal from the outside of the coulomb counter 100e. .

  In the coulomb counter 100e having such a configuration, the storage circuit 106 can store the counter value of the up / down counter 101 at the timing of the LAT signal, and therefore can hold the counter value of the up / down counter before reading out. The counter value changes at the read timing, and the wrong count value is not read out.

  Further, since the memory circuit 106 can reset the counter value with the RESET signal, the counter value of the up / down counter so far is reset at the start of the coulomb counter, or before the counter value of the up / down counter overflows. The value can be reset to

In the fifth embodiment, the storage circuit that holds the counter value of the up / down counter 101 at an arbitrary timing is configured to reset the stored counter value at an arbitrary timing. The counter 101 may be configured such that the counter value is reset by a predetermined reset signal, and a reset circuit that generates the reset signal may be provided.
(Embodiment 6)
FIG. 7 is a diagram for explaining a coulomb counter according to a sixth embodiment of the present invention, and shows a delta-sigma modulator using a differential signal as an input signal.

  The coulomb counter 100f includes a digital sigma modulator 110 that uses a differential signal as an input signal instead of the digital sigma modulator 100 constituting the coulomb counter 100a of the first embodiment. This is the same as the coulomb counter of the first embodiment.

  That is, in the coulomb counter 100f of this embodiment, unlike the delta-sigma modulator 100 of the first embodiment in which the difference between the IN_P potential and the GND potential is counted as the input voltage (IN), the potential at both ends of the detection resistor is A digital-sigma modulator 110 is used in which a difference between a certain IN_P potential and IN_N potential is an input voltage (IN).

  In the coulomb counter 100f of the sixth embodiment having such a configuration, both ends of the detection resistor 200 and a pair of differential input terminals of the digital-sigma modulator are directly connected by a dedicated conductor pattern without using a substrate wiring. As a result, the input voltage error caused by the substrate wiring can be reduced.

  Further, by making the input signal of the digital-sigma modulator 110 a differential signal, it is possible to obtain an effect of removing common mode noise that reduces noise mixed in the GND and the power supply and clock noise, and an S / N ratio. Can be raised.

  Furthermore, the degree of freedom of arrangement of the IC as a coulomb counter on the printed circuit board can be increased.

  FIG. 8 is a diagram for explaining the arrangement of an IC as a coulomb counter on a printed circuit board. The arrangement of a differential input coulomb counter (FIG. (A)) and the arrangement of a coulomb counter that is not a differential input (FIG. 8). (B)) is shown in comparison.

  For example, as shown in FIG. 8A, electrically separated conductor layers T1 and T2 are formed on a printed circuit board, and one conductor layer T1 is connected to the negative terminal of the battery 400, The other conductor layer T <b> 2 is connected to the positive terminal of the battery 400 through the load 300. In addition, a resistance layer 200a constituting the detection resistor 200 is formed so as to straddle the conductor layers T1 and T2 at a portion where the pair of conductor layers T1 and T2 are opposed to each other. The conductor layer T1 is connected via a contact portion C, and the other end of the resistance layer 200a is connected to the other conductor layer T2 via a contact portion C.

  Further, a pair of differential input terminals of the coulomb counter 100f are connected to both ends of the resistance layer 200a via a pair of wiring layers L1 and L2.

  On the other hand, as shown in FIG. 8B, when the coulomb counter 100 of the first embodiment that is not a differential input is connected to the detection resistor 200, one input of the digital-sigma modulator constituting the coulomb counter is As in the case shown in FIG. 8 (a), it is connected to one end of the resistance layer T1 through the wiring layer L, and the other input of the digital-sigma modulator is grounded, that is, of the pair of conductor layers. Connected to the grounded conductor layer T2 that is grounded.

  In this case, the resistance component ΔR from the other end side of the resistance layer 200a as the detection resistor 200 to the portion of the ground side conductor layer T2 to which the other input of the digital-sigma modulator is connected has an influence on the counter output. In order to suppress this, it is necessary to arrange the IC as a coulomb counter as close as possible to the resistance layer 200a.

Therefore, as in the sixth embodiment, the configuration in which the coulomb counter uses a differential signal as an input signal can increase the degree of freedom of arrangement of the IC as the coulomb counter on the printed circuit board.
(Embodiment 7)
FIG. 9 is a diagram illustrating a coulomb counter according to the seventh embodiment of the present invention.

  The coulomb counter 100g according to the seventh embodiment has a digital-sigma modulator 120 including a standby circuit 107 in place of the digital-sigma modulator 100 constituting the coulomb counter 100a according to the first embodiment. The configuration is the same as the coulomb counter of the first embodiment.

  The standby circuit 107 operates based on a standby (STB) signal from the outside of the coulomb counter 100g so that the delta-sigma modulator 100 is not operated and an operation that operates the delta-sigma modulator 100. Switching control is performed between states.

  In the coulomb counter 100g according to the seventh embodiment of the present invention having such a configuration, when the coulomb count is not performed, the standby circuit 107 sets the digital-sigma modulator to a standby state in which it does not operate, thereby reducing the operating current. This can extend the battery life of the portable device.

  Further, although not particularly described in the first to seventh embodiments, the coulomb counter according to any of the first to seventh embodiments is used in a battery-powered mobile device such as a mobile phone or a laptop computer, and the remaining battery. In the mobile device using the coulomb counter according to any one of the first to seventh embodiments, the number of circuits constituting the coulomb counter can be reduced and the cost can be reduced. It is also possible to accurately detect the remaining battery level at any time.

  For example, such an electronic information device as a mobile device is an electronic information device including a functional circuit that performs a predetermined circuit operation and a battery that drives the functional circuit, and the remaining battery that is a secondary battery. A remaining amount detection unit that detects the amount is provided, and the remaining amount detection circuit includes the coulomb counter according to any one of the first to seventh embodiments.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention can provide a coulomb counter capable of reducing the circuit scale in the field of a coulomb counter and an electronic information device, and an electronic information device equipped with such a coulomb counter.

100, 110, 120 Delta-sigma modulator 100a to 100g Coulomb counter 101 Up / down counter 102 Counter circuit 103 Switch 104 Operator 105, 106 Memory circuit 107 Standby circuit 200 Detection resistor 200a Resistance layer 300 Load 400 Secondary battery T1, T2 conductor layer L, L1, L2 wiring layer

Claims (12)

A coulomb counter that outputs a count value proportional to the input voltage with a potential difference generated across the detection resistor as an input voltage,
Using the input voltage as an input signal, and outputting a pulse signal having a duty ratio according to the input voltage as an output delta-sigma modulator;
Counts up when the delta-sigma modulator output pulse is high when the clock signal is input, and counts down when the clock signal is input when the delta-sigma modulator output pulse is low. Coulomb counter with down counter.   2. The coulomb counter according to claim 1, further comprising a counter circuit that counts the number of clock signals that have entered the up / down counter.   The coulomb counter according to claim 1, further comprising a switch for short-circuiting the detection resistor.   The coulomb counter according to claim 1, further comprising an addition circuit that adds an arbitrary value to the count value output by the up / down counter.   The coulomb counter according to claim 1, further comprising a subtraction circuit that subtracts an arbitrary value from a count value output by the up / down counter. A multiplication circuit for multiplying the count value output by the up / down counter by an arbitrary value;
The coulomb counter according to claim 1, further comprising a storage circuit that stores a multiplication value obtained by the multiplication circuit. A division circuit for dividing the count value output by the up / down counter by an arbitrary value;
The coulomb counter according to claim 1, further comprising a storage circuit that stores a division value obtained by the division circuit.   The coulomb counter according to claim 1, further comprising a storage circuit that holds a counter value output by the up / down counter at an arbitrary timing.   The coulomb counter according to claim 1, further comprising a reset circuit that resets a counter value of the up / down counter.   The coulomb counter according to claim 1, wherein the delta-sigma modulator has an input terminal for receiving a differential signal as an input signal.   The coulomb counter according to claim 1, wherein the delta-sigma modulator includes a standby circuit that switches its operation mode to a standby mode. An electronic information device comprising a functional circuit that performs a predetermined circuit operation and a secondary battery that drives the functional circuit,
A remaining amount detection unit for detecting the remaining amount of the secondary battery;
2. The electronic information device, wherein the remaining amount detection circuit includes the coulomb counter according to claim 1.

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