JP2012160576A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

A semiconductor device is provided with an improved degree of freedom in wiring design.
A semiconductor device according to an embodiment is provided with an insulating base material, a plurality of wirings constituting a first wiring layer provided on an upper surface side of the insulating base material, and a lower surface side of the insulating base material. A circuit board having a plurality of wirings constituting a second wiring layer and a plurality of vias penetrating from the upper surface to the lower surface of the insulating base, and a semiconductor element mounted on the upper surface side of the circuit board And a sealing resin layer that seals the semiconductor element and is provided on the upper surface of the circuit board. Furthermore, the semiconductor device includes a conductive shield layer that covers an upper surface of the sealing resin layer and a part of a side surface of the sealing resin layer, and the conductive material that covers a part of the side surface of the sealing resin layer. And a conductive member that electrically connects at least one of the plurality of wirings constituting the first wiring layer.
[Selection] Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  It is important to shield a noise radio wave generated from the semiconductor device and protect the semiconductor device from an external noise radio wave. For example, in a high-frequency module used in a mobile communication device such as a mobile phone, a high-frequency circuit is mainly formed by a high-frequency semiconductor element on a substrate and a peripheral circuit.

  Generally, when a current flows through a semiconductor element or a peripheral circuit, an electric field and a magnetic field are induced around the current, and unnecessary noise radio waves (electromagnetic noise) are generated. As an example, noise radio waves emitted from a semiconductor device mounted on a mobile communication device such as a mobile phone may enter an antenna and cause radio wave reception failure.

  In order to shield such noise radio waves and protect the semiconductor element, there is a method of providing a shielding plate that covers the semiconductor device. However, the method of covering the semiconductor device with the shielding plate has a problem that the semiconductor device cannot be reduced in size.

  On the other hand, there is a semiconductor device (semiconductor package) in which a semiconductor element is mounted on a substrate (interposer substrate) and a shielding film is formed on the outer periphery of the semiconductor element itself. If such a semiconductor element is incorporated in a high-frequency module, the high-frequency module can be reduced in size. Such semiconductor devices are increasingly required to be miniaturized, and accordingly, a higher degree of design freedom is required for the wiring routed on the substrate.

JP 2010-103574 A

  The problem to be solved by the present invention is to provide a semiconductor device with improved wiring design freedom and a manufacturing method for manufacturing the semiconductor device.

  The semiconductor device according to the embodiment includes an insulating base material, a plurality of wires constituting a first wiring layer provided on the upper surface side of the insulating base material, and a second wiring layer provided on the lower surface side of the insulating base material. A circuit board having a plurality of wirings, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating base, a semiconductor element mounted on the upper surface side of the circuit board, and the semiconductor And a sealing resin layer provided on the upper surface of the circuit board. Furthermore, the semiconductor device includes a conductive shield layer that covers an upper surface of the sealing resin layer and a part of a side surface of the sealing resin layer, and the conductive material that covers a part of the side surface of the sealing resin layer. And a conductive member that electrically connects at least one of the plurality of wirings constituting the first wiring layer.

  The method of manufacturing a semiconductor device according to the embodiment includes an insulating base material, a plurality of wirings constituting a first wiring layer provided on the upper surface side of the insulating base material, and a first surface provided on the lower surface side of the insulating base material. A plurality of circuit boards having a plurality of wirings constituting two wiring layers and a plurality of vias penetrating from the upper surface to the lower surface of the insulating base material in a direction parallel to the main surface of the circuit board And a step of preparing a substrate provided in this manner, and a step of mounting a semiconductor element on each of the plurality of circuit boards. Furthermore, in the method of manufacturing a semiconductor device, any one of the plurality of wirings constituting the first wiring layer provided on each of the adjacent circuit boards among the plurality of circuit boards is electrically connected via a conductive member. A step of forming a sealing resin layer for sealing the plurality of semiconductor elements and the conductive member on the upper surface side of the substrate, and the sealing resin layer between each of the adjacent circuit boards Forming a groove in the groove, dividing the conductive member, exposing each cut surface of the divided conductive member from the inner wall surface of the groove, and electrically conducting the upper surface of the sealing resin layer and the groove. A step of forming a shield layer, and a step of dividing the conductive shield layer formed in the groove and the substrate under the groove.

It is a cross-sectional schematic diagram explaining the outline | summary of the semiconductor device which concerns on 1st Embodiment. 2A and 2B are schematic plan views of the semiconductor device according to the first embodiment, in which FIG. 1A is a schematic plan view on the upper surface side of the circuit board, and FIG. 2B is a schematic plan view on the lower surface side of the circuit board. It is a cross-sectional schematic diagram explaining the manufacturing process of a semiconductor device. It is a schematic diagram explaining the effect of a semiconductor device, (a) is a cross-sectional schematic diagram, (b) is a plane schematic diagram. It is a cross-sectional schematic diagram of the semiconductor device which concerns on 2nd Embodiment. It is a cross-sectional schematic diagram of the semiconductor device which concerns on 3rd Embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same members are denoted by the same reference numerals, and the description of the members once described is omitted as appropriate. Moreover, each embodiment described below can be combined suitably.

(First embodiment)
FIG. 1 is a schematic cross-sectional view for explaining the outline of the semiconductor device according to the first embodiment.
In FIG. 1, in addition to the semiconductor device 1 according to the first embodiment, a mounting substrate 100 on which the semiconductor device 1 is mounted is displayed.

  The semiconductor device 1 is an FBGA (Fine pitch Ball Grid Array) type semiconductor package. The semiconductor device 1 includes a circuit board 10. The circuit board 10 is also referred to as an interposer board. The circuit board 10 includes an insulating base material 11, a plurality of wiring layers (first wiring layers) 12 provided on the outer periphery on the upper surface side of the insulating base material 11, and a plurality of wiring layers provided on the lower surface side of the insulating base material 11. A wiring layer (second wiring layer) 13. The circuit board 10 further includes a plurality of vias 14 penetrating from the upper surface (first main surface) to the lower surface (second main surface) of the insulating base material. The number of vias 14 is not limited to the number shown in the figure, and a plurality of vias 14 are provided in the circuit board 10 vertically and horizontally. The first wiring layer is composed of a plurality of wiring layers 12. The second wiring layer is composed of a plurality of wiring layers 13.

  Each of the plurality of wiring layers 13 is a land electrode. An external connection terminal 17 that is a solder ball is connected to each of the plurality of wiring layers 13. A lead wire 19 extends from the external connection terminal 17 located on the outer periphery of the circuit board 10 to the outside of the circuit board 10. The lead wire 19 is connected to the lower end of the via 14 located in the vicinity of the side surface 10 w of the circuit board 10. A wiring layer 18 is connected to the upper end of the via 14. A solder resist layer 16 for covering a part of each wiring layer and a part of the lead line is formed on the upper surface and the lower surface of the circuit board 10. Each of the plurality of external connection terminals 17 is connected to each of the wiring layers 101 provided on the upper surface side of the mounting substrate 100.

  A semiconductor element 20 is mounted on the upper surface side of the circuit board 10. One end of a wire (bonding wire) 21 is connected to the upper surface of the semiconductor element 20. The other end of the wire 21 is connected to the wiring layer 12. The wire 21 is a conductive member, and electrically connects at least one of the plurality of wiring layers 12 and an electrode (not shown) provided on the surface of the semiconductor element. One of the wiring layers 12 is connected to one of the external connection terminals 17 via the via 14 in the circuit board 10.

  The outer periphery of the semiconductor element 20 and the wire 21 are sealed with a sealing resin layer 30 provided on the upper surface side of the circuit board 10. A mounting material (die bonding material) 22 is formed in the gap between the semiconductor element 20 and the circuit board 10.

  The upper surface of the sealing resin layer 30 and a part of the side surface of the sealing resin layer 30 are covered with the conductive shield layer 40. The lower end of the conductive shield layer 40 covering a part of the side surface of the sealing resin layer 30 is not in contact with the upper surface of the circuit board 10. The distance d between the lower end of the conductive shield layer 40 that covers a part of the side surface of the sealing resin layer 30 and at least one of the surfaces of the plurality of wiring layers 18 is 100 μm (micrometers) or less.

  The conductive shield layer 40 and at least one of the plurality of wiring layers 18 are electrically connected by the conductive member 25a or the conductive member 25b. In the embodiment, the potential of the wiring layer 18 connected to the conductive members 25a and 25b can be set to the ground (GND) potential.

  For example, by setting the potential of the external connection terminal 17 electrically connected to the wiring layer 18 to the ground potential, the potential of the wiring layer 18 is set to the ground potential. Thus, the ground potential is supplied from the wiring layer 18 to the conductive shield layer 40 via the conductive members 25a and 25b, and the potential of the conductive shield layer 40 can be set to the ground potential.

  The semiconductor element 20 is, for example, a storage element such as a flash memory or a DRAM, or an arithmetic element such as a microprocessor. The wire 21 is, for example, a metal wire such as gold (Au), aluminum (Al), or copper (Cu).

  The wiring layer 12, the wiring layer 13, the wiring layer 18, and the lead wire 19 are made of a conductive paste containing copper (Cu) foil, silver (Ag), or copper (Cu), etc., the wiring layer 12, the wiring layer 13, The wiring layer 18 is plated with nickel (Ni), gold (Au), or the like on the surface as necessary. The via 14 is, for example, a columnar electrode. The via 14 may be a columnar electrode in which all materials are made of a conductive material. In addition to the columnar electrode, the via 14 may include a cylindrical cylindrical electrode and a resin embedded in the hollow of the cylindrical electrode. Good. The material of the via 14 is copper (Cu), tungsten (W), or the like.

  The conductive shield layer 40 is desirably made of a material having a resistivity as low as possible in order to block high-frequency noise emitted from the semiconductor element 20. As a material of the conductive shield layer 40, for example, silver (Ag), copper (Cu), nickel (Ni) or the like is selected. More specifically, the conductive shield layer 40 is, for example, a film containing silver (Ag) obtained by curing a silver (Ag) paste, and its sheet resistance is adjusted to 0.1 (Ω / □) or less. Has been. The thickness of the conductive shield layer 40 is several tens of μm, and more preferably 10 to 90 μm.

  The conductive members 25a and 25b are a conductive wire, a conductive plate, a resistance element, a conductive paste, a conductive film, or the like. The conductive members 25a and 25b are made of gold (Au), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), tungsten (W), molybdenum (Mo), titanium (Ti), copper (Cu), nickel (Ni), aluminum (Al), solder material, and the like.

  2A and 2B are schematic plan views of the semiconductor device according to the first embodiment. FIG. 2A is a schematic plan view on the upper surface side of the circuit board, and FIG. 2B is a schematic plan view on the lower surface side of the circuit board. . FIG. 2 is a diagram of the circuit board 10 viewed from a direction perpendicular to the upper surface (or lower surface) of the insulating base material 11.

  As shown in FIG. 2A, a plurality of vias 14 are provided on the upper surface side of the circuit board 10. The plurality of vias 14 penetrate from the upper surface to the lower surface of the insulating base material 11. A rectangular area surrounded by reference numeral 23 is an element mounting area 23 of the semiconductor element 20. A plurality of vias 14 are arranged outside the device mounting region 23 or the device mounting region 23. The plurality of wiring layers 18 are provided outside the element mounting region 23. A lead line 12 a is provided from the via 14 in the element mounting region 23 to the wiring layer 12. The lead line 12 a is connected to the via 14 and the wiring layer 12. The lead line 12a is a signal line of the semiconductor element 20, a ground wiring, or the like. The lead wire 12a is a conductive paste containing copper (Cu) foil, silver (Ag) or copper (Cu), and the surface is plated with nickel (Ni), gold (Au) or the like as necessary. Has been. The conductive shield layer 40 and at least one of the plurality of wiring layers 18 are electrically connected by conductive members 25a and 25b. The distance at which the conductive members are adjacent to each other is adjusted to be half or less of the wavelength of noise radio waves (electromagnetic noise) emitted from the semiconductor element 20 or the like.

  As shown in FIG. 2B, a plurality of external connection terminals 17 are provided in rows and columns on the lower surface side of the circuit board 10. Some of the plurality of external connection terminals 17 are electrically connected to the lead-out line 12a on the upper surface side via the vias 14. That is, a part of the external connection terminal 17 is electrically connected to the wiring layer 12 via the wiring layer 13, the via 14, and the lead line 12a. In FIG. 2B, the wiring layer 13 illustrated in FIG. 1 is not displayed, but actually, the wiring layer 13 is in contact with the external connection terminal 17 (see FIG. 1).

  In the semiconductor device 1, some of the plurality of external connection terminals 17 can be at the ground potential. For example, after the semiconductor device 1 is mounted on the mounting substrate 100, some of the external connection terminals 17 become the ground potential by the ground wiring provided in the mounting substrate 100. For example, among the plurality of external connection terminals 17 arranged vertically and horizontally, the external connection terminals 17 located at the four corners can be at the ground potential. In addition, a lead wire 19 is electrically connected to the external connection terminal 17 having a ground potential. The via 14 connected to the lead wire 19 is connected to the wiring layer 18 on the upper surface side of the circuit board 10. That is, the ground potential can be supplied to the conductive shield layer 40 from the external connection terminal 17 having the ground potential via the conductive members 25a and 25b.

  The lead line 19 for supplying the ground potential to the via 14 may be provided on the upper surface side of the circuit board 10. Further, the number and arrangement of the external connection terminals 17 (or the wiring layers 13 in contact with the external connection terminals 17) that are at the ground potential are not limited to the above-described example.

Next, a manufacturing process of the semiconductor device 1 will be described.
FIG. 3 is a schematic cross-sectional view illustrating the manufacturing process of the semiconductor device.
FIG. 3 illustrates a manufacturing process in four stages (a) to (d). On the right side of each stage, an enlarged view of a portion surrounded by a broken line 200 on the left side is shown.

  First, in the stage shown in FIG. 3A, a substrate 10A in which a plurality of circuit boards 10 are continuously provided in a direction parallel to the main surface of the circuit board 10 is prepared. Subsequently, the semiconductor element 20 is mounted on each of the plurality of circuit boards 10. Then, at least one of the plurality of wiring layers 12 and an electrode provided on the surface of the semiconductor element are electrically connected via a wire 21.

  Furthermore, among the plurality of circuit boards 10, any one of the plurality of wiring layers 18 provided on each of the adjacent circuit boards 10 is electrically connected via the conductive member 25. For example, the conductive member 25 is formed by a wire bonding method in which the conductive member 25 is a metal wire. Subsequently, a sealing resin layer 30 that seals the plurality of semiconductor elements 20, the wires 21, and the conductive member 25 is formed on the upper surface side of the substrate 10A. At this stage, the circuit board 10 is in a state before cutting, and a plurality of semiconductor elements 20 are mounted on the board 10A.

  Next, in the stage shown in FIG. 3B, grooves 30 t are formed in the sealing resin layer 30 between the adjacent circuit boards 10. The groove 30t is formed by a so-called half dicing process in which the dicing blade 90 is inserted from above the sealing resin layer 30.

  In the half dicing process, the dicing blade 90 does not reach the upper surface side of the circuit board 10. That is, the insertion of the dicing blade 90 is stopped in the sealing resin layer 30 above the circuit board 10, and the sealing resin layer 30 is adjusted to remain below the dicing blade 90. However, the conductive member 25 is divided while forming the groove 30t.

  When the conductive member 25 is divided, the conductive member 25 is divided into a conductive member 25a and a conductive member 25b. Further, the cut surfaces of the divided conductive members 25a and 25b are exposed from the inner wall surface of the groove 30t. Thereafter, the sealing resin layer 30 is cured as necessary.

  Next, in the stage shown in FIG. 3C, the conductive shield layer 40 is formed on the upper surface of the sealing resin layer 30 and the groove 30t. The conductive shield layer 40 is formed by, for example, a transfer method, a screen printing method, a spray coating method, a jet dispensing method, an ink jet method, an aerosol method, an electroless plating method, an electrolytic plating method, or a vacuum processing method.

  At this stage, the cut surfaces of the conductive members 25 a and 25 b are in contact with the conductive shield layer 40.

Thereafter, as shown in FIG. 3D, the conductive shield layer 40 formed in the groove 30t and the substrate 10A under the groove 30t are divided by dicing.
Through such a manufacturing process, the continuous circuit board 10 is separated into pieces, and the semiconductor device 1 is formed.

The effect of the semiconductor device 1 will be described.
4A and 4B are schematic diagrams for explaining the effects of the semiconductor device, in which FIG. 4A is a schematic cross-sectional view, and FIG. 4B is a schematic plan view.

  As described above, the wiring layers 12 and 18 are plated with nickel (Ni), gold (Au) or the like on the surface as necessary. In FIG. 4, a plurality of plating wirings 10 c for performing electrolytic plating treatment on the wiring layers 12 and 18 are displayed.

  Temporarily, the entire side surface of the sealing resin layer 30 is covered with the conductive shield layer 40, and the lower end of the conductive shield layer 40 covering the side surface of the sealing resin layer 30 is in contact with the upper surface of the circuit board 10. If it is located below the upper surface of the wiring, the plating wiring 10 c comes into contact with the conductive shield layer 40 on the outer periphery of the circuit board 10. That is, even if the wiring layers 12 and 18 are used for the signal lines, the wiring layers 12 and 18 connected to the plating wiring 10c are supplied with the ground potential from the conductive shield layer 40, and are inevitably ground potential. It will be shorted.

  As a means for avoiding this, a method of drawing the plating wiring 10c connected to the wiring layers 12 and 18 to the lower surface side of the circuit board 10 through a via in the circuit board 10 is conceivable. However, as the number of signal lines on the circuit board 10 increases, the means for routing the plating wiring 10c only on the lower surface side of the circuit board 10 is limited in the degree of freedom in wiring design.

  As another avoidance measure, a method of removing the unnecessary plating wiring 10c by etching after the electrolytic plating treatment on the wiring layer 12 and the wiring layer 18 is conceivable. However, if a step of removing the plating wiring 10c is provided, the manufacturing cost of the semiconductor device increases.

  On the other hand, in the semiconductor device 1, the lower end of the conductive shield layer 40 that covers a part of the side surface of the sealing resin layer 30 is not in contact with the upper surface of the circuit board 10. For example, the distance between the lower end of the conductive shield layer 40 and the upper surface of the circuit board 10 is adjusted to be longer than the thickness of the plating wiring 10c. Therefore, even if the plating wiring 10c is provided, the plating wiring 10c and the conductive shield layer 40 do not come into contact with each other. That is, the ground potential is not supplied from the conductive shield layer 40 to the wiring layers 12 and 18 connected to the plating wiring 10c, and the wiring layers 12 and 18 are used as signal lines that are originally used. Function.

  Further, in the semiconductor device 1, the plating wiring 10c does not come into contact with the conductive shield layer 40 even if the plating wiring 10c is left, and therefore a manufacturing process for removing the plating wiring 10c is not required. Therefore, in the embodiment, it is not necessary to increase the manufacturing cost of the semiconductor device.

  In the semiconductor device 1, the plating wiring 10 c can be routed not only on the lower surface side of the circuit substrate 10 but also on the upper surface side of the circuit substrate 10. Therefore, the degree of freedom in designing the wiring including the wiring for plating (for example, the signal line, the wiring for plating, the wiring for grounding, etc.) to the circuit board 10 is improved.

  In the semiconductor device 1, the conductive shield layer 40 covers not only the upper surface of the sealing resin layer 30 but also a part of the side surface of the sealing resin layer 30. Therefore, in the semiconductor device 1, noise radio wave shielding is higher than the configuration in which the conductive shield layer 40 covers only the upper surface of the sealing resin layer 30.

  For example, the above-mentioned distance d is desirably 100 μm or less. In this way, the distance d can be made half or less of the wavelength of the noise radio wave. For this reason, it is difficult for noise radio waves to leak from the gap of the distance d. Further, in the semiconductor device 1, the distance between the conductive members 25a and 25b is adjusted to be half or less of the wavelength of the noise radio wave. For this reason, it is difficult for noise radio waves to leak from between the conductive members 25a and 25b.

  As for the plating process, there is an electroless plating process in addition to the electrolytic plating process. However, in the embodiment, an electrolytic plating process that can form a plating film with higher reliability than the electroless plating process is adopted.

(Second Embodiment)
FIG. 5 is a schematic cross-sectional view of a semiconductor device according to the second embodiment.
The basic configuration of the semiconductor device 2 according to the second embodiment is the same as that of the semiconductor device 1, and the same effect as that of the semiconductor device 1 is obtained. However, in the semiconductor device 2, the via 14 connected to the wiring layer 18 is exposed on the side surface 10 w of the circuit board 10.

  With such a structure, the element area can be reduced as compared with the semiconductor device 1. As a result, the semiconductor device 2 can be made more compact than the semiconductor device 1.

(Third embodiment)
FIG. 6 is a schematic cross-sectional view of a semiconductor device according to the third embodiment.
The basic configuration of the semiconductor device 3 according to the third embodiment is the same as that of the semiconductor device 1, and the same effect as that of the semiconductor device 1 is obtained. However, in the semiconductor device 3, the circuit board 10 is cut further inside the via 14 near the side surface 10 w of the circuit board 10 in the semiconductor device 1. The wiring layer 18 is at a ground potential through the wiring layer disposed on the circuit board 10.

  With such a structure, the element area can be reduced as compared with the semiconductor device 2. As a result, the semiconductor device 3 can be made smaller than the semiconductor device 2.

  The embodiment has been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the embodiments as long as they include the features of the embodiments. Each element included in each of the specific examples described above and their arrangement, material, condition, shape, size, and the like are not limited to those illustrated, and can be appropriately changed.

  In addition, each element included in each of the above-described embodiments can be combined as long as technically possible, and combinations thereof are also included in the scope of the embodiment as long as they include the features of the embodiment. In addition, in the category of the idea of the embodiment, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the embodiment. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1, 2 and 3 Semiconductor device 10 Circuit board 10A Substrate 10c Plating wiring 10w Side surface 11 Insulating substrate 12 Wiring layer 12a, 19 Lead line 13 Wiring layer (second wiring layer)
14 via 16 solder resist layer 17 external connection terminal 18 wiring layer (first wiring layer)
DESCRIPTION OF SYMBOLS 20 Semiconductor element 21 Wire 22 Mounting material 23 Element mounting area 25, 25a, 25b Conductive member 30 Sealing resin layer 30t Groove 40 Conductive shield layer 90 Dicing blade 100 Mounting board 101 Wiring layer

Claims (4)

An insulating base, a plurality of wirings constituting the first wiring layer provided on the upper surface side of the insulating base material, and a plurality of wirings constituting the second wiring layer provided on the lower surface side of the insulating base material; A circuit board having a plurality of vias penetrating from the upper surface to the lower surface of the insulating base, and
A semiconductor element mounted on the upper surface side of the circuit board;
Sealing the semiconductor element, and a sealing resin layer provided on the upper surface of the circuit board;
A conductive shield layer covering the top surface of the sealing resin layer and a part of the side surface of the sealing resin layer;
A conductive member that electrically connects the conductive shield layer covering a part of the side surface of the sealing resin layer and at least one of the plurality of wirings constituting the first wiring layer;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein a lower end of the conductive shield layer covering a part of the side surface of the sealing resin layer is not in contact with an upper surface of the circuit board.   The distance between at least one of the surfaces of the plurality of wirings constituting the first wiring layer and the lower end of the conductive shield layer covering a part of the side surface of the sealing resin layer is 100 micrometers or less The semiconductor device according to claim 1, wherein: An insulating base, a plurality of wirings constituting the first wiring layer provided on the upper surface side of the insulating base material, and a plurality of wirings constituting the second wiring layer provided on the lower surface side of the insulating base material; And a step of preparing a substrate in which a plurality of circuit boards having a plurality of vias penetrating from the upper surface to the lower surface of the insulating base material are continuously provided in a direction parallel to the main surface of the circuit board When,
Mounting a semiconductor element on each of the plurality of circuit boards;
Electrically connecting any one of the plurality of wirings constituting the first wiring layer provided on each of the adjacent circuit boards among the plurality of circuit boards via a conductive member;
Forming a sealing resin layer for sealing a plurality of the semiconductor elements and the conductive member on the upper surface side of the substrate;
A step of dividing the conductive member while forming a groove in the sealing resin layer between each of the adjacent circuit boards and exposing each cut surface of the divided conductive member from the inner wall surface of the groove. When,
Forming a conductive shield layer on the upper surface of the sealing resin layer and the groove;
Dividing the conductive shield layer formed in the groove and the substrate under the groove;
A method for manufacturing a semiconductor device, comprising:

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