JP2012155788A - Nand type flash memory - Google Patents

Abstract

A NAND flash memory capable of storing more information of a bad block newly generated during a test while suppressing an increase in the area of a ROM fuse block.
A NAND flash memory receives a first determination signal when the power is turned on, stores the first determination signal while shifting the logic of the first determination signal, and then receives a second determination signal in a test mode. Only the logic corresponding to the judgment of the bad block of the second judgment signal is overwritten to the logic of the normal block to which the address corresponds, and the bad that the stored logic is assigned in conjunction with the addressing A shift register circuit that sequentially outputs block flag signals is provided.
[Selection] Figure 1

Description

  Embodiments described herein relate generally to a NAND flash memory.

  Conventionally, in a memory cell array of a NAND flash memory, ROM fuses that store different setting information for each chip, such as information on bad blocks that are prohibited from being used according to test results, redundancy replacement information, and various voltage setting conditions Is provided.

  This ROM fuse has the same structure as the memory cell of the flash memory. Several blocks in the memory cell array are assigned as ROM fuse blocks composed of ROM fuses.

  Further, since the use of the bad block is prohibited as described above, writing or erasing to the memory cell cannot be performed. For this reason, the user needs to read the bad block information written in the memory cell of the designated address in each bad block and control so that these blocks are not used.

  For example, the bad block registration area of the ROM fuse block may be used to store the bad block under test. In this case, the number of bad blocks that can be registered is limited. Therefore, the reliability test must be performed within a range where the bad block can be registered.

  In particular, in a reliability test, a large number of samples are generally measured simultaneously. For this reason, in order to store all bad blocks with the test program, a large amount of memory area is required in the test apparatus, which is not practical.

  Therefore, a method for storing the address of the bad block generated during the reliability test inside the flash memory chip is required.

JP-A-11-144495

  Provided is a NAND flash memory capable of storing more information of a bad block newly generated during a test while suppressing an increase in a ROM fuse block area.

  The NAND flash memory according to the embodiment is composed of a plurality of memory cells, and is composed of a plurality of normal blocks serving as data write / erase units and a plurality of memory cells, and access is made among the plurality of normal blocks. A ROM fuse block storing a bad block address of a prohibited bad block and a memory cell array are provided.

  The NAND flash memory includes a row decoder that is connected to the memory cell via a word line and selects one of the plurality of normal blocks or the ROM fuse block in accordance with addressing by an address signal.

  The NAND flash memory includes a bit line control circuit which is connected to the memory cell via a bit line and reads data stored in the memory cell or writes data to the memory cell.

  The NAND flash memory has a normal block for each normal block corresponding to whether or not the normal block to be addressed is a bad block based on the bad block address read from the ROM fuse block at power-on. A first determination signal to which 1-bit logic is assigned is output in the order of the address designation, and in the test mode, the first determination signal is output based on data read from the memory cell of the addressed normal block. It is determined whether or not the addressed normal block is a bad block, and a second determination signal in which 1-bit logic is assigned to each normal block corresponding to the determination result is used as the address specification. A determination circuit for sequentially outputting in order is provided.

  The NAND flash memory receives the first determination signal when the power is turned on, stores the first determination signal while shifting the logic of the first determination signal, and then stores the second determination signal in the test mode. Is input, only the logic corresponding to the bad block determination of the second determination signal is overwritten with the logic of the normal block corresponding to the address, and the stored logic is assigned in conjunction with the addressing. And a shift register circuit for sequentially outputting bad block flag signals.

  The NAND flash memory controls operations of the row decoder, the bit line control circuit, the determination circuit, and the shift register circuit, and receives the bad block flag signal, and the logic of the bad block flag signal And a control circuit for recognizing a bad block address of the bad block based on the logic input order of the bad block flag signal.

1 is a block diagram illustrating an example of a configuration of a NAND flash memory 100 according to Embodiment 1. FIG. FIG. 2 is a circuit diagram showing an example of a configuration of a memory cell array 1 of the NAND flash memory 100 shown in FIG. 1. FIG. 2 is a diagram showing an example of block allocation of the memory cell array 1 of the NAND flash memory 100 shown in FIG. 1. FIG. 2 is a diagram showing an example of a configuration of a shift register circuit 13 of the NAND flash memory 100 shown in FIG.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating an example of a configuration of a NAND flash memory 100 according to the first embodiment. FIG. 2 is a circuit diagram showing an example of the configuration of the memory cell array 1 of the NAND flash memory 100 shown in FIG. FIG. 3 is a diagram showing an example of block allocation of the memory cell array 1 of the NAND flash memory 100 shown in FIG. FIG. 4 is a diagram showing an example of the configuration of the shift register circuit 13 of the NAND flash memory 100 shown in FIG.

  As shown in FIG. 1, the NAND flash memory 100 includes a memory cell array 1, a bit line control circuit 2, a column decoder 3, a data input / output buffer 4, a data input / output terminal 5, a row decoder 6, A control circuit 7, a control signal input terminal 8, a source line control circuit 9, a well control circuit 10, an address register 11, a determination circuit 12, and a shift register circuit 13 are provided.

  As will be described later, the memory cell array 1 includes a plurality of bit lines, a plurality of word lines, and a source line. The memory cell array 1 is composed of, for example, a plurality of blocks (FIG. 2) in which memory cells made of EEPROM cells and electrically rewritable data are arranged in a matrix.

  The memory cell array 1 is connected to a bit line control circuit 2 for controlling the voltage of the bit line and a row decoder 6 for controlling the voltage of the word line. During the data write operation, one of the blocks is selected by the row decoder 6 and the remaining blocks are not selected.

  The bit line control circuit 2 is connected to the memory cell via a bit line. The bit line control circuit 2 reads data stored in the memory cells in the memory cell array 1 through the bit lines, detects the state of the memory cells through the bit lines, and transmits the data through the bit lines. Data is written to the memory cell by applying a write control voltage to the memory cell.

  In addition, a column decoder 3 and a data input / output buffer 4 are connected to the bit line control circuit 2. The data storage circuit in the bit line control circuit 2 is selected by the column decoder 3, and the memory cell data read to the data storage circuit is externally supplied from the data input / output terminal 5 via the data input / output buffer 4. Is output.

  Write data input from the outside to the data input / output terminal 5 is stored in the data storage circuit selected by the column decoder 3 via the data input / output buffer 4. From the data input / output terminal 5, in addition to write data, various commands and addresses such as write, read, erase, and status read are also input.

  The row decoder 6 is connected to the memory cells of the memory cell array 1 through word lines.

  The row decoder 6 is connected to a plurality of normal blocks or ROM fuse blocks of the memory cell array 1 in accordance with an address designation by an address signal for selecting a block input from the outside via the data input / output terminal 5 and the address register 11. Is selected.

  The row decoder 6 applies a voltage necessary for reading, writing, or erasing supplied from the control circuit 7 to the word line of the selected block. For example, during a test operation, the address signal is input from an external tester (not shown).

  That is, the row decoder 6 selects any one of a plurality of blocks to be described later of the memory cell array 1 according to the address signal, and controls the voltage of the word line.

  The source line control circuit 9 is connected to the memory cell array 1. The source line control circuit 9 controls the voltage of the source line SRC.

  The well control circuit 10 is connected to the memory cell array 1. The well control circuit 10 controls the voltage of the semiconductor substrate (well) on which the memory cells are formed.

  At the time of power-on, the determination circuit 12 is based on the bad block address read from the ROM fuse block, and corresponds to 1 bit for each normal block corresponding to whether or not the normal block to be addressed is a bad block. A determination signal (first determination signal) to which logic is assigned is output in the order of address designation.

  On the other hand, in the test mode, the determination circuit 12 determines whether or not this addressed normal block is a bad block based on data read from the memory cell of the addressed (test target) normal block. In response to this determination result, a determination signal (second determination signal) in which 1-bit logic is assigned to each normal block is sequentially output in the order of address designation.

  The shift register circuit 13 receives the first determination signal when the power is turned on, and stores the shift while shifting the logic of the determination signal (the first determination signal).

  Further, the shift register circuit 13 receives a determination signal (the second determination signal) in the subsequent test mode, and only the logic corresponding to the determination of the bad block of the second determination signal corresponds to the address. Normal block logic is overwritten.

  Further, the shift register circuit 13 sequentially outputs a bad block flag signal to which the stored logic is assigned in conjunction with address designation.

  The control circuit 7 includes a memory cell array 1, a bit line control circuit 2, a column decoder 3, a data input / output buffer 4, a row decoder 6, a source line control circuit 9, a well control circuit 10, a determination circuit 12, and a shift register circuit 13. The operation is controlled.

  The control circuit 7 receives control signals (command latch enable signal CLE, address latch enable signal ALE, ready / busy signal RY / BY, etc.) and data input / output terminals 5 that are input from the outside via the control signal input terminal 8. A control operation is performed in accordance with a command input via the data input / output buffer 4. That is, the control circuit 7 generates a desired voltage and supplies it to each part of the memory cell array 1 when data is programmed, verified, read, and erased in accordance with the control signal and command.

  The control circuit 7 receives a bad block flag signal.

  Here, the order of the normal blocks corresponding to the order in which the logic of the bad block flag signal is input to the control circuit 7 is equal to the order of address designation of the normal blocks. As a result, the control circuit 7 recognizes the bad block address of the bad block based on the logic of the bad block flag signal and the input order of the logic of the bad block flag signal. Then, the control circuit 7 prohibits access to the bad block based on the recognized bad block address.

  Further, the control circuit 7 causes the row decoder 6 to select (address specification) a block selected (addressed) by the address signal in accordance with the test command input from the tester described above. Yes.

  Here, as shown in FIG. 2, the memory cell array 1 includes blocks BLK <b> 0 to BLKM configured by connecting a plurality of NAND cell units 1 a (hereinafter, sometimes simply referred to as BLK for convenience). Have. The blocks BLK0 to BLKM serve as data write / erase units.

  The NAND cell unit 1a includes a plurality of (n + 1 (for example, 64)) memory cells M0 to MN, a drain side selection MOS transistor SGDTr, and a source side selection MOS transistor SGSTr that are connected in series to form a NAND string. Has been. The source side selection MOS transistor SGSTr is connected to a source line SRC (not shown). Note that the source side select gate transistor SGSTr and the drain side select gate transistor SGDTr are nMOS transistors here.

  The control gates of the memory cells M0 to MN arranged in each row are connected to the word lines WL0 to WLN, respectively.

  The bit lines BL0 to BLP are arranged so as to be orthogonal to the word lines WL0 to WLN.

  The gate of the drain side select MOS transistor SGDTr is connected to the drain side select gate line SGD. The drain side select gate transistor SGDTr is connected between one end of the NAND string 1a1 and the bit lines BL0 to BLP.

  The gate of the source side selection MOS transistor SGSTr is connected to the source side selection gate line SGS. The source side select gate transistor SGSTr is connected between the other end of the NAND string 1a1 and the source line SRC.

  That is, the row decoder 6 selects each block BLK0 to BLKM of the memory cell array 1 according to the input address, and controls the write / read operation of the selected block. That is, the row decoder 6 controls the voltage applied to the drain side selection gate line and the source side gate line according to the input address, and also applies the voltage applied to the word line (control gate of the memory cell). The memory cell is selected by controlling.

  Here, as shown in FIG. 3, the memory cell array 1 includes, for example, a plurality of (for example, 4096 in the example of FIG. 3) normal blocks 1 c and a ROM fuse block 1 a.

  The plurality of normal blocks 1c are composed of a plurality of memory cells and serve as data erasing units.

  The bad block 1b is a block in which access is prohibited among the plurality of normal blocks 1c.

  The ROM fuse block 1a stores a bad block address of the bad block 1b.

  As illustrated in FIG. 4, the shift register circuit 13 includes an OR circuit 13a, an AND circuit 13b, and a shift register 13c.

  In the OR circuit 13a, the determination signal (first and second determination signals) SF1 output from the determination circuit 12 is input via the terminal T1, and the bad block flag signal SF2 is input. .

  Note that the determination signal (first and second determination signals) SF1 output in conjunction (synchronization) with the input of the address signal (block address) from the determination circuit 12 is that the addressed normal block 1c is the bad block 1b. If the addressed normal block 1c is not a bad block 1b, it is at a "Low" level, that is, a logic "0".

  The AND circuit 13b receives, for example, a clock signal CLK generated by the control circuit 7 in synchronization with the input of the block address and a test mode signal STM defining the test mode output by the control circuit 7. The clock signal CLK may be generated by a clock signal generation circuit (not shown) provided separately from the control circuit.

  The test mode signal STM is, for example, “High” level, that is, logic “1” when the power is turned on or in the test mode, while “Low” level, that is, logic “0”, during normal operation. become.

  The clock signal CLK is interlocked (synchronized) with the input of the address signal (block address) and becomes “High” level, that is, logic “1”.

  Therefore, the AND circuit 13b outputs a “High” level signal, that is, a logic “1” signal in synchronization (synchronization) with the input of the address signal (block address) when the power is turned on or in the test mode.

  The register 13c is configured by arranging a plurality (n) of D-flip flops 13c-1 to 13c-n so that the data terminal and the output terminal are connected. In each of the D flip-flops 13c to 13f, the output of the AND circuit 13b is connected to a clock terminal.

  In the first-stage D-flip flop 13c-1, the output of the OR circuit 13a is connected to the data terminal.

  The final stage D-flip flop 13c-n has an output terminal connected to the input of the OR circuit 13a, and a bad block flag signal SF2 is connected to the control circuit 7 from the output terminal of the final stage D-flip flop 13c-n. The data is output via T4.

  In the example of FIG. 4, as an example, the case where the number of D-flip flops constituting the shift register is n, that is, the case where information of n blocks is stored is described. For example, the number n is set to the same value as the number of blocks (4096) in the memory cell array 1 shown in FIG. That is, the number of D-flip flops is equal to the number of the normal blocks.

  However, the number n of D-flip-flops constituting the shift register may be set according to the number of bad blocks to be stored. That is, the number of D-flip flops may be smaller than the number of normal blocks.

  Next, an example of the operation of the NAND flash memory 100 having the above configuration will be described with reference to FIGS.

  In the initial state, the logic stored in each D-flip-flop of the shift register 13c of the shift register circuit 13 is “0”. That is, the shift register circuit 13 holds a state where all the normal blocks to be stored are not bad blocks.

  First, when the power is turned on, a determination signal (second determination signal) SF1 is input to the shift register circuit 13 in conjunction (synchronization) with the input of an address signal (block address).

  At the time of turning on the power, the test mode signal STM becomes “High” level, that is, logic “1” as described above.

  As a result, the AND circuit 13b outputs a “High” level signal, that is, a logic “1” signal in synchronization (synchronization) with the input of the address signal (block address).

  Further, as described above, the determination signal (first determination signal) SF1 becomes logic “1” when the addressed normal block 1c is the bad block 1b, while the addressed normal block When 1c is not the bad block 1b, the logic is “0”.

  Thus, since the logic of the bad block flag signal SF2 is all “0”, the OR circuit 13a outputs a logic “1” when the addressed normal block 1c is the bad block 1b, When the designated normal block 1c is not the bad block 1b, the logic “0” is output.

  Accordingly, the shift register 13c stores the logic of the determination signal (first determination signal) SF1 while sequentially shifting in synchronization (synchronization) with the input of the address signal (block address). When the input of the block addresses for the number of normal blocks (n) is completed, the storage of the state of n normal blocks is completed.

  As a result, the logic corresponding to the state of the first addressed normal block is stored in the D-flip flop 13c-n at the last stage, and the D-flip flop 13c-1 at the first stage finally stores the logic. The logic corresponding to the state of the addressed normal block will be stored.

  As described above, when the power is turned on, the shift register circuit 13 receives the determination signal (first determination signal) SF1, and stores the logic of the first determination signal while shifting the logic.

  As a result, the address information of the bad block 1c stored in the ROM fuse block 1a is stored in the shift register circuit 13.

  Next, in the test mode, a determination signal (second determination signal) SF1 is input to the shift register circuit 13 in conjunction (synchronization) with the input of the address signal (block address).

  In this test mode, the test mode signal STM becomes “High” level, that is, logic “1” as described above.

  As a result, the AND circuit 13b outputs a “High” level signal, that is, a logic “1” signal in synchronization (synchronization) with the input of the address signal (block address).

  As described above, the determination signal (second determination signal) SF1 becomes logic “1” when the addressed normal block 1c is the bad block 1b, while the addressed normal block When 1c is not the bad block 1b, the logic is “0”.

  Thus, the OR circuit 13a performs a logical product of the logic of the bad block flag signal SF2 input in conjunction with (synchronized with) the input of the address signal (block address) and the logic of the determination signal (second determination signal) SF1. Is calculated. Here, the address of the normal block corresponding to the logic to be calculated is the same address.

  For example, the OR circuit 13a outputs a logic “1” when the addressed normal block 1c is the bad block 1b.

  On the other hand, when the logic of the bad block flag signal SF2 is “0”, that is, when the normal block 1c addressed at power-on is not determined to be a bad block, the normal block 1c addressed in the test mode is bad. If it is not the block 1b, the OR circuit 13a outputs a logic “0”. However, if the logic of the bad block flag signal SF2 is “1”, that is, if the already addressed normal block 1c is determined to be a bad block, the OR circuit 13a outputs a logic “1”.

  Accordingly, the shift register 13c sequentially operates the logic obtained by calculating the logic of the determination signal (second determination signal) SF1 and the logic of the bad block flag signal SF2 in synchronization (synchronization) with the input of the address signal (block address). Memorize while shifting. When the input of the block addresses for the number of normal blocks (n) is completed, the storage of the state of n normal blocks is completed.

  As a result, the logic corresponding to the state of the first addressed normal block is stored in the D-flip flop 13c-n at the last stage, and the D-flip flop 13c-1 at the first stage finally stores the logic. The logic corresponding to the state of the addressed normal block will be stored.

  As described above, in the test mode, the shift register circuit 13 receives the determination signal (second determination signal) SF1 and calculates the logic of the logic of the second determination signal and the logic of the bad block flag signal SF2. Memorize while shifting.

  As a result, the state of the normal block determined by the reliability test in the test mode is overwritten in the shift register circuit 13.

  Further, the shift register circuit 13 sequentially outputs the bad block flag signal SF2 to which the stored logic is allocated in conjunction (synchronization) with the address designation.

  Further, the control circuit 7 controls the shift register circuit 13 to output the bad block flag signal SF2 by controlling the test mode signal STM and the clock signal CLK when the power is turned on or in the test mode. Get bad block information.

  As described above, the test mode of this embodiment is used in the reliability test. For this reason, it is assumed that the block address is accessed sequentially from the beginning. A reliability test is executed in order from the first block, and the shift register is shifted one by one in synchronization with the input of the address of the block to be tested (in synchronization with the increment of the address of the block to be tested). When a write or erase result is read by status read and a defect is detected, the block is regarded as a bad block, and the leading register is inverted to become bad block information. When this operation is repeated until the last block, the shift register makes a round and bad block information is set at the position of the block.

  Basically, if long-term data retention is not required, only one set of bad block information data is required. In this case, for example, all 4096 blocks can be stored with 512 bytes.

  In particular, if the power is not turned off during the reliability test, the address only needs to be held in the shift register circuit 13. Therefore, it is not necessary to change the bad block information written in the ROM fuse block.

  Further, a ROM fuse block is used for storing the bad block, but it is not necessary to increase the number of bits of the ROM fuse block as compared with the conventional case.

  As described above, according to the NAND flash memory of this embodiment, it is possible to store more information on the bad block newly generated during the test while suppressing an increase in the area of the ROM fuse block.

1 memory cell array 2 bit line control circuit 3 column decoder 4 data input / output buffer 5 data input / output terminal 6 row decoder 7 control circuit 8 control signal input terminal 9 source line control circuit 10 well control circuit 11 address register 12 decision circuit 13 shift register Circuit 100 Semiconductor memory device

Claims (8)

A plurality of normal blocks that are composed of a plurality of memory cells and serve as data write / erase units, and a bad block address that is composed of a plurality of memory cells and for which access is prohibited among the plurality of normal blocks is stored. ROM fuse block, memory cell array having,
A row decoder connected to the memory cell via a word line, and selecting one of the plurality of normal blocks or the ROM fuse block according to addressing by an address signal;
A bit line control circuit connected to the memory cell via a bit line, for reading data stored in the memory cell or writing data to the memory cell;
Based on the bad block address read from the ROM fuse block at power-on, one bit of logic is assigned to each normal block corresponding to whether the addressed normal block is a bad block or not. Output the first determination signal in the order of address designation, while in the test mode, based on the data read from the memory cell of the addressed normal block, this addressed normal block Is determined to be a bad block, and a second determination signal in which 1-bit logic is assigned to each normal block corresponding to the determination result is sequentially output in the order of address designation. Circuit,
When the power is turned on, the first determination signal is input and stored while shifting the logic of the first determination signal, and then in the test mode, the second determination signal is input and the first determination signal is input. Only the logic corresponding to the determination of the bad block of the determination signal of 2 is overwritten with the logic of the normal block corresponding to the address, and the bad block flag signal to which the stored logic is assigned in conjunction with the addressing is displayed. A shift register circuit for sequentially outputting;
Controls the operations of the row decoder, the bit line control circuit, the determination circuit, and the shift register circuit, and receives the bad block flag signal, and the logic of the bad block flag signal and the bad block flag signal And a control circuit for recognizing a bad block address of the bad block based on the logic input order. The shift register circuit includes:
An OR circuit to which the first and second determination signals output from the determination circuit are input and a bad block flag signal is input;
An AND circuit to which a clock signal generated in conjunction with the input of the address signal and a test mode signal defining a test mode output by the control circuit are input;
A plurality of D-flip flops are arranged side by side so that a data terminal and an output terminal are connected to each other, and each D-flip flop has an output of the AND circuit connected to a clock terminal. The output of the OR circuit is connected to the data terminal of the flip-flop, the output terminal of the D-flip flop of the final stage is connected to the input of the OR circuit, and the bad signal is output from the output terminal of the D-flip flop of the final stage. The NAND flash memory according to claim 1, further comprising: a shift register that outputs a block flag signal to the control circuit. The first and second determination signals are logical “1” when the normal block is a bad block, and are logical “0” when the normal block is not a bad block.
The test mode signal is logic “1” when the power is turned on or in the test mode, while it is logic “0” during normal operation.
3. The NAND flash memory according to claim 2, wherein the clock signal becomes logic “1” in conjunction with the input of the address signal.   4. The NAND flash memory according to claim 2, wherein the clock signal is generated by a control circuit.   5. The NAND flash memory according to claim 2, wherein the number of the D flip-flops is equal to the number of the normal blocks.   6. The NAND flash memory according to claim 2, wherein the number of the D-flip flops is smaller than the number of the normal blocks. The NAND flash memory according to claim 1, wherein the control circuit prohibits access to the bad block based on the recognized bad block address. 8. The order of the normal blocks corresponding to the order in which the logic of the bad block flag signal is input to the control circuit is equal to the order of address designation of the normal blocks. The NAND flash memory according to the item.

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