JP2012155569A - Digital signal processing device - Google Patents

Abstract

An object of the present invention is to improve the processing capability of a product-sum operation.
A digital signal processing device stores a plurality of registers, a data transfer unit that stores data in the plurality of registers in time series in synchronization with a clock signal, and the plurality of registers stored at the same timing. And an arithmetic unit that performs an operation on the data. In accordance with a given instruction, the data transfer unit stores the data stored in a certain register among the plurality of registers at a certain timing of the clock signal. Transfer to be stored in the other specified register. It is possible to improve the processing capability of the filter operation by SIMD.
[Selection] Figure 1

Description

  The present invention relates to digital signal processing. The present invention particularly relates to a technique for improving the efficiency of calculations such as filter operations in a SIMD processor.

  A digital signal processing apparatus generally needs to efficiently perform a large amount of operations on a group of data. Applications that can be applied include a wide range of applications such as machine control, high-efficiency speech encoding / decoding, and image processing.

  In digital signal processing by a RISC processor of a general load store architecture, a single instruction multiple data (SIMD) system that handles a plurality of data in parallel with one instruction is frequently used. FIG. 8 shows an example of an arithmetic unit of a digital signal processing apparatus using a general SIMD system. With respect to a set of one Dn and one Dm, four sets of data are processed in parallel by one instruction DopD → D, and four results Dd are obtained.

  Patent Document 1 proposes a method of setting the same data in a plurality of parallel processing target data holding registers in a SIMD type arithmetic unit as shown in FIG. This document states that the performance can be improved by specific processing such as multiplication of a vector variable and a scalar variable.

JP-A-2005-174300

  In high-efficiency speech encoding / decoding, a method for efficiently processing a large amount of data is required. However, the technique disclosed in Japanese Patent Application Laid-Open No. 2005-174300 is effective in the arithmetic processing of vector variables and scalar variables, but is not effective in the filter product-sum arithmetic processing frequently used in high-efficiency speech encoding / decoding.

  Hereinafter, means for solving the problem will be described using the numbers used in [DETAILED DESCRIPTION] in parentheses. These numbers are added to clarify the correspondence between the description of [Claims] and [Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

  In one aspect of the present invention, a digital signal processing device includes a plurality of registers (Kmn) and a data transfer unit (L) that stores data in the plurality of registers in time series in synchronization with a clock signal at the same timing. Computation units (Mul 0 to 3, prod 0 to 3, add 0 to 3, acc 0 to 3) that perform operations on data stored in a plurality of registers are provided. In accordance with a given instruction, the data transfer unit transfers data stored in a certain register among a plurality of registers at a certain timing of a clock signal to a specified other of the plurality of registers at a next timing. To be stored in the register.

  In another aspect of the present invention, a digital signal processing method includes a step of storing data in a plurality of registers in time series in synchronization with a clock signal, and an operation on data stored in the plurality of registers at the same timing. The process of performing. In the storing step, in accordance with a given instruction, data stored in a certain register among a plurality of registers at a certain timing of a clock signal is designated in the plurality of registers at a next timing. Transfer to store in another register.

  According to the present invention, the data transfer unit transfers the data stored in a certain register at a certain timing to another register at the next timing and uses it for calculation, so that the processing capability is improved. As an example, it is possible to improve the processing capability of the product-sum operation that is variously performed in the high-efficiency speech encoding / decoding processing by SIMD.

FIG. 1 is a schematic diagram of a digital signal processing apparatus according to an embodiment of the present invention. FIG. 2 is an explanatory diagram of the xtype and the data register group. FIG. 3 is a signal flow diagram illustrating an example of the filter calculation operation. FIG. 4 shows the second argument of mac_n. FIG. 5 shows the processing code of the analysis filter defined in the standard. FIG. 6 is a code for left shift and rounding in the code of FIG. FIG. 7A is a filter processing code according to an embodiment. FIG. 7B is a filter processing code according to an embodiment. FIG. 8 is an example of an arithmetic unit of a digital signal processing apparatus based on the SIMD system. FIG. 9 shows an arithmetic unit configuration for specific processing proposed in Japanese Patent Laid-Open No. 2005-174300.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The digital signal processing apparatus according to an embodiment of the present invention has a “product-sum operation unit operation mode” as an operand of a product-sum operation instruction.
The digital signal processor decodes the product-sum operation instruction and the “product-sum operation mode”, transfers data between the product-sum instruction dedicated data register and the multiplied data input register, and the data between the multiplied data input registers. Control the transfer.

  FIG. 1 is a schematic diagram of a digital signal processing apparatus according to this embodiment. The digital signal processing device includes an instruction memory immem, a data memory dmem, an arithmetic unit ACC, an instruction decoder DEC, and a register file RF. This digital signal processing apparatus uses a general SIMD (FIG. 8) and Japanese Patent Application Laid-Open No. 2005-174300 (FIG. 9) in order to efficiently process a filter product-sum operation frequently used in high-efficiency speech encoding / decoding processing. This has a different configuration from the arithmetic unit of the digital signal processing apparatus using SIMD. For this purpose, an extended product-sum operation instruction, an arithmetic unit ACC for processing the instruction, and an instruction decoder DEC are provided.

  The instruction decoder DEC has a function of decoding a special product-sum operation instruction mac4_n. In this instruction, “multiply-accumulator operation mode” can be specified as the second argument. The instruction decoder DEC decodes the “multiply-accumulate unit operation mode” along with the instruction code. In accordance with the decoding result, the data transfer unit L performs data transfer to the multiply-add instruction dedicated data registers arg0 / 1, data0-5, and the multiplied data input register Kmn in the arithmetic unit ACC.

For example, in the filter operation shown in FIG. 3, the data transfer unit L in FIG. 1 stores the digital signal data in the plurality of registers Kmn in time series in synchronization with the clock signal. Data includes, for example, a signal indicating, for example, brightness of pixels in the image processing data X _{m (m} is an integer), the _(n is an integer) coefficient data a _n indicating the characteristic of the filter is multiplied for the signals and. In the example of FIG. 3, K00, K02, K40, and K42 are used as data registers for storing signal data. K01, K03, K41, and K43 are used as coefficient registers for storing coefficient data, and are provided corresponding to the data registers K00, K02, K40, and K42, respectively.

  In response to the product-sum operation instruction, the arithmetic unit ACC receives the digital signal stored in each of the plurality of data registers K00, K02, K40, and K42 at the same timing of the operation clock signal and the plurality of coefficient registers K01, K03, A product-sum operation is performed on the time-series data of the set with the coefficient stored in the corresponding register among K41 and K43.

  The data transfer unit L designates a digital signal stored in each of the plurality of data registers at a certain timing according to a given instruction by a product-sum operation instruction of the plurality of data registers at the next timing. The data is transferred so as to be stored in another data register.

Specifically, the arithmetic unit ACC _displays a list of data from X ₀ , a _{0 in} the upper left of FIG. 3 to X _-7 , a _{10 in the} lower right from the lowermost stage in time series in synchronization with the clock signal. Take in order and accumulate. Furthermore, the product-sum operation is executed by sequentially taking the sum of the integration results obtained in time series order. The digital signal processing apparatus according to the present embodiment is a SIMD type processor, and this product-sum operation is executed in accordance with one product-sum operation instruction stored in the image.

The arithmetic unit ACC pays attention to the feature that certain data stored in the plurality of registers Kmn at the same timing is used in the next register in the next operation (FIG. 3: data (moving from the lower right to the upper left) x) is used). The data transfer unit L stores a plurality of registers K00, K02, K40, and K42 at a certain timing of the operation clock signal according to a given instruction (instruction stored in the instruction memory “imem” and decoded by the instruction decoder DEC). Data stored in a certain register (for example, X- ₇ stored in K42 at the bottom of the list of FIG. 3, X- ₈ stored in K40, X- ₉ stored in K02) The other registers specified by the instruction set definition (X- ₇ stored in K40, X- ₈ stored in K02, and X- ₉ stored in K00, respectively) from the bottom. Transfer to store.

  Specifically, when a code meaning “FILTER” is designated as the “multiply-accumulate unit operation mode”, the data transfer unit L transfers data between the multiple data input registers Kmn to be multiplied. In this way, the data transfer related to the multiply-add instruction dedicated data registers alg0 / 1, data0-5 and the multiplied data input register Kmn is made efficient. As a result, the processing capability of the product-sum operation frequently used in the high-efficiency speech encoding / decoding process is improved.

  Hereinafter, this embodiment will be described in more detail. The arithmetic unit ACC includes a product-sum instruction dedicated data register group alg0 / 1 and data 0 to 5, 16-bit multiplied data input register Kmn (m = 0, 4, n = 0 to 3), multipliers mul0 to 3, and addition And adders add0-3, 32-bit registers prod0-3 for holding outputs of multipliers mul0-3, and 32-bit registers acc0-3 for holding outputs of adders add0-3. imme is an instruction memory.

  dmem is a data memory having an interface for storing a 16-bit variable array to be processed and reading and writing in 128-bit access units. In this embodiment, “xtype” is prepared as a type representing this 128-bit access unit. As a result of the read access to the array starting from the address deviated from the interface boundary of “xtype”, the content from the top of the array to the next interface boundary is followed by the remaining content in the access unit. A dark shaded area in FIG. 2 indicates an area where data to be processed is stored.

  In order to appropriately process this, the data transfer unit L uses the multiply-add instruction dedicated data register group arg0 / 1, data0-5 to the 16-bit multiplied data input register Kmn (m = 0, 4, n = 0-3). ) To be multiplied. The data transfer unit L can transfer data between the Kmn registers. The register file RF is 128 bits.

  An instruction set for controlling the multiply-accumulate circuit configured as described above is prepared. mac4_n () (n = 0 to 5) is an instruction for performing the process indicated by the second argument on the first argument and storing the result in the product-sum instruction dedicated data register groups data0 to 5 and the register file RF. . mac_ina () is an instruction for storing an argument in the data sum instruction data alg0. mac_inb () is an instruction for storing an argument in the data sum instruction data register alg1. The CLR128 () takes two arguments and multiplies the multiply-add instruction dedicated data register group alg0 / 1, data 0-5 to the 16-bit multiplied data input register Kmn (m = 0, 4, n = 0-3). This is an instruction for determining a logic L for distributing data and initializing a data sum group for data sum instructions alg0 / 1 and data0-5. set_firex () is an instruction for setting four LSB shorts of xtype arguments in the multiplied data input registers K00, K02, K40, and K42.

  Of these, mac4_n (n = 0 to 5) is a special instruction used for the filter product-sum operation. In this instruction, a second argument “multiply-accumulate unit operation mode” for instructing a processing method for the first argument is defined as shown in FIG. For example, when FILTER in FIG. 4 is set in the second argument “multiply-accumulate unit operation mode”, the multiply-add instruction data register group arg0 / 1, data 0-5 to the 16-bit multiplied data input register Kmn42 are multiplied. The data transfer unit L is controlled so as to capture data and shift the data between the Kmn registers.

  Furthermore, the operation and effect of this embodiment will be described by taking as an example an analysis filter of a linear prediction method used in AMR (Adaptive Multi Rate), which is one of high-efficiency speech encoding / decoding methods. FIG. 5 shows a processing code of the analysis filter defined by the standard. a [], x [], and y [] are 16-bit variable arrays of linear prediction coefficients, input signals, and output signals, respectively. lg is the processing frame length. M = 11 is the order of linear prediction.

  Further, the left shift and round processing in the code are defined as shown in FIG. 6 in consideration of saturation processing for overflow / underflow.

  FIG. 7A and FIG. 7B are a series of codes, and are obtained by rewriting FIG. 5 using the instruction set. In (a), the linear prediction coefficient sequence a (0 to 10) is performed. In (b), the input signal sequence x is transferred from the memory to the register file. In (c), an analysis filter process is performed using a mechanism that is a feature of the present embodiment. The conventional SIMD digital signal processing apparatus requires 2400 steps, whereas the number of code execution steps is about 1700.

  In the above example, the analysis filter of the linear prediction method has been described. However, in various other filter processes, data stored in a certain register at a certain timing by the data transfer unit L is transferred to another register at the next timing. It is possible to improve the processing capability by transferring the data to and using it for calculation.

  As described above, the data transfer between the product-sum instruction dedicated data register and the data input register to be multiplied is made efficient by the “product-sum operation mode” as compared with the conventional SIMD digital signal processing device. . As a result, it is possible to reduce the number of steps of filter processing used in a high-efficiency speech encoding / decoding method and improve processing performance.

In particular, the present embodiment has the following features.
(1) “Product-sum operation mode” is provided as an operand of a product-sum operation instruction.
(2) The product-sum operation instruction and the “product-sum operation mode” are decoded, and the data transfer between the product-sum instruction dedicated data register and the multiplied data input register and the data transfer between the multiplied data input registers are controlled.
(3) An extended function control unit for controlling the operation mode of the product-sum operation unit is provided as an operand of the product-sum operation instruction.
(4) The extended function control unit controls data transfer between the product-sum instruction dedicated data register group and the register file.
(5) The extended function control unit controls data transfer between the product-sum instruction dedicated data registers.
(6) The extended function control unit controls the set value of the data register for the product-sum instruction.
(7) The product-sum operation circuit accesses the register file and the memory in parallel.

acc arithmetic unit acc0 to acc3 register add0 to add3 adders alg0, alg1 data sum instruction dedicated data register data0 to data5 product sum instruction dedicated data register DEC decoder dmem data memory imam instruction memory Kmn multiplied data input register L data transfer units mul0 to mul0 mul3 multiplier prod0-prod3 register RF register file sel selector

Claims (8)

Multiple registers,
A data transfer unit for storing data in the plurality of registers in time series in synchronization with a clock signal;
An arithmetic unit that performs an operation on the data stored in the plurality of registers at the same timing,
In accordance with a given instruction, the data transfer unit stores the data stored in a certain register among the plurality of registers at a certain timing of the clock signal. A digital signal processing device that transfers data to be stored in another designated register. The digital signal processing apparatus according to claim 1,
The digital signal processing device, wherein the arithmetic unit executes the arithmetic operation in response to one command being given. The digital signal processing apparatus according to claim 1 or 2,
The plurality of registers are:
Multiple data registers,
A plurality of coefficient registers respectively associated with the plurality of data registers,
The data transfer unit stores digital signals in each of the plurality of data registers and stores coefficients in each of the plurality of coefficient registers in time series in synchronization with the clock signal,
The arithmetic unit, in response to a product-sum operation instruction, calculates the digital signal stored in each of the plurality of data registers and the coefficient stored in the corresponding register among the plurality of coefficient registers at the same timing. Perform product-sum operation on a set of time series data,
The data transfer unit is configured to specify the digital signal stored in each of the plurality of data registers at the certain timing in accordance with the given instruction, and specify the digital signal among the plurality of data registers at the next timing. A digital signal processing device that transfers data to be stored in another data register. The digital signal processing apparatus according to claim 3,
The plurality of data registers include n data registers from the first to the n-th (n is an integer of 2 or more),
The data transfer unit stores the digital signal stored in the i-th data register (i is an integer between 1 and n−1) at the certain timing among the plurality of data registers at the next timing. Digital signal processor that transfers to the second data register. Storing data in a plurality of registers in time series in synchronization with a clock signal;
And performing an operation on the data stored in the plurality of registers at the same timing,
In the storing step, according to a given instruction, the data stored in a certain register among the plurality of registers at a certain timing of the clock signal is stored in the plurality of registers at the next timing. A digital signal processing method for transferring data to be stored in another specified register. A digital signal processing method according to claim 5, comprising:
The digital signal processing method, wherein the step of executing the operation is executed in response to a command being given. A digital signal processing method according to claim 5 or 6,
The plurality of registers are:
Multiple data registers,
A plurality of coefficient registers respectively associated with the plurality of data registers,
In the storing step, a digital signal is stored in each of the plurality of data registers and a coefficient is stored in each of the plurality of coefficient registers in time series in synchronization with the clock signal,
In the step of executing the operation, the digital signal stored in each of the plurality of data registers and the corresponding one of the plurality of coefficient registers are stored at the same timing according to a product-sum operation instruction. The product-sum operation is performed on the time series data of the set with the coefficient
In the storing step, the digital signal stored in each of the plurality of data registers at the certain timing in accordance with the given instruction is further transferred to the plurality of data registers at the next timing. A digital signal processing method that transfers data to be stored in another specified data register. The digital signal processing method according to claim 7, comprising:
The plurality of data registers include n data registers from the first to the n-th (n is an integer of 2 or more),
In the storing step, the digital signal stored in the i-th data register (i is an integer of 1 to n-1) at the certain timing among the plurality of data registers is processed at the next timing. A digital signal processing method for transferring to the i + 1th data register.

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