JP2012151748A - Power amplification synthesis circuit, and power amplification circuit, transmission device, and communication device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power amplification / synthesis circuit having high power supply efficiency, and a power amplification circuit, a transmission device and a communication device using the same.
A transistor having a first input signal at the source terminal and a signal having the same phase as the second input signal at the gate terminal, a second input signal at the source terminal, and a first input signal at the gate terminal. Of the transistor 34, the gate terminal of which is connected to the drain terminal of the first transistor, the source terminal of which is connected to the ground potential via the constant current source 6, the drain terminal of the transistor 4, and When the phase difference between the low-pass filter circuit 8 for connecting the power supply potential, the output matching circuit 16 connected to the drain terminal of the transistor 4 and the first input signal and the second input signal increases, the current flowing through the constant current source The power amplification and synthesis circuit includes a current control circuit 19 that outputs a current control signal for controlling the constant current source so as to decrease.
[Selection] Figure 1

Description

  The present invention relates to a power amplification / synthesis circuit, and a power amplification circuit, a transmission device, and a communication device using the same, and more particularly, a power amplification / synthesis circuit having high power efficiency and a power amplification circuit, a transmission device, and a communication using the same. It relates to the device.

  2. Description of the Related Art Conventionally, there is known a power amplification and synthesis circuit that amplifies a plurality of input signals and then combines them (see, for example, Patent Document 1).

Special Table 2005-512375

  However, the above-described conventional power amplification and synthesis circuit has a problem in that the efficiency decreases when the phase difference between the two input signals is large.

  The present invention has been devised in view of such problems in the prior art, and an object thereof is to provide a power amplification / synthesis circuit having high efficiency, a power amplification circuit using the same, a transmission device, and a communication device. There is to do.

  The power amplification and synthesis circuit of the present invention includes a first transistor in which a first input signal is input to a source terminal, a signal in phase with the second input signal is input to a gate terminal, and the second input to a source terminal. A second transistor having a gate terminal receiving a signal in phase with the first input signal, a gate terminal connected to the drain terminal of the first transistor, and a source terminal being fixed. A third transistor connected to the ground potential via a current source; a low-pass filter circuit having one end connected to the drain terminal of the third transistor and the other end connected to the power supply potential; An output matching circuit connected to a drain terminal of the third transistor; the first input signal; and the second input signal; And a current control circuit that outputs a current control signal for controlling the constant current source so that the current flowing through the constant current source decreases as the phase difference of the second input signal increases. is there.

  The power amplifier circuit according to the present invention includes a constant envelope signal generation circuit that converts an input signal having an envelope variation into a first constant envelope signal and a second constant envelope signal and outputs the first constant envelope signal, and the first constant envelope signal. And a power amplification / synthesis circuit configured as described above, wherein the second constant envelope signal is input as the first input signal and the second input signal.

  The transmitter of the present invention is characterized in that an antenna is connected to the transmitter circuit via the power amplifier circuit having the above-described configuration.

  The communication apparatus of the present invention is characterized in that an antenna is connected to the transmission circuit via the power amplifier circuit having the above-described configuration, and a reception circuit is connected to the antenna.

  According to the power amplification and synthesis circuit of the present invention, a highly efficient power amplification and synthesis circuit can be obtained.

  According to the power amplifier circuit of the present invention, a highly efficient power amplifier circuit can be obtained.

  According to the transmission device of the present invention, a transmission device with low power consumption can be obtained.

  According to the communication device of the present invention, a communication device with low power consumption can be obtained.

It is a circuit diagram which shows the power amplification synthetic | combination circuit of the 1st example of embodiment of this invention. FIG. 2 is a circuit diagram illustrating an example of a current control circuit in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of an output matching circuit in FIG. 1. It is a circuit diagram which shows an example of the low-pass filter in FIG. It is a circuit diagram which shows the power amplification synthetic | combination circuit of the 2nd example of embodiment of this invention. FIG. 6 is a circuit diagram illustrating an example of an output matching circuit in FIG. 5. It is a circuit diagram which shows the power amplifier circuit of the 3rd example of embodiment of this invention. It is a block diagram which shows the transmission apparatus of the 4th example of embodiment of this invention. It is a block diagram which shows the communication apparatus of the 5th example of embodiment of this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a power amplification and synthesis circuit of the present invention, a power amplification circuit using the same, a transmission device, and a communication device will be described in detail with reference to the accompanying drawings.
(First example of embodiment)
FIG. 1 is a circuit diagram showing a power amplification / synthesis circuit of the first example of the embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of the current control circuit in FIG. FIG. 3 is a circuit diagram showing an example of the output load circuit in FIG. FIG. 4 is a circuit diagram showing an example of the low-pass filter circuit in FIG.

  As shown in FIG. 1, the power amplification and synthesis circuit of this example includes an input terminal 1, an input terminal 2, an output terminal 3, a transistor 4, a transistor 33, a transistor 34, a constant current source 6, and a low current source. A band-pass filter circuit 8, a capacitor 14, an output matching circuit 16, and a current control circuit 19 are provided.

  The input terminal 1 receives a first input signal S1 from an external circuit (not shown), and the input terminal 2 receives a second input signal S2 from an external circuit (not shown). In the power amplification and synthesis circuit of this example, the first input signal S1 and the second input signal S2 are constant envelope signals having the same frequency.

The transistor 33 has a source terminal connected to the input terminal 1 and a gate terminal connected to the input terminal 2. In the transistor 33, the first input signal S1 is input to the source terminal, and the second input signal S2 is input to the gate terminal. The transistor 34 has a source terminal connected to the input terminal 2 and a gate terminal connected to the input terminal 1. In the transistor 34, the second input signal S2 is input to the source terminal, and the first input signal S1 is input to the gate terminal. The transistor 4 has a gate terminal connected to the drain terminal of the transistor 33 and a source terminal connected to the ground potential via the constant current source 6. The drain terminal of the transistor 34 is connected to the ground potential via the termination resistor 35. The transistors described in the embodiments of the present invention are all n-channel FETs, and the pinch-off voltage (threshold voltage for flowing a drain current) is Vp.

  The low-pass filter circuit 8 has one end (terminal 10) connected to the drain terminal of the transistor 4 and the other end (terminal 9) connected to the power supply potential Vdd. The output matching circuit 16 has one end (terminal 17) connected to the drain terminal of the transistor 4 and the other end connected to the output terminal 3.

  In the current control circuit 19, the terminal 20 is connected to the input terminal 1, the terminal 21 is connected to the input terminal 2, and the terminal 22 is connected to a current value setting terminal (not shown) of the constant current source 6. . The current control circuit 19 receives the first input signal S1 and the second input signal S2, and the current flowing through the constant current source 6 decreases as the phase difference between the first input signal S1 and the second input signal S2 increases. A current control signal for controlling the constant current source 6 is output.

  FIG. 2 shows a circuit configuration of the current control circuit 19. The first input signal S1 is input to the terminal 20, and the second input signal S2 is input to the terminal 21. The terminal 20 is connected to the gate terminal of the transistor 23, and the terminal 21 is connected to the gate terminal of the transistor 24. Note that a bias circuit (not shown) is provided, and a DC bias voltage is supplied to the gate terminals of the transistors 23 and 24.

  The drain terminal of the transistor 23 is connected to the power supply voltage Vdd, the source terminal of the transistor 23 is connected to the drain terminal of the transistor 24, and the source terminal of the transistor 24 is connected to the drain terminal of the transistor 26. The 26 source terminals are connected to the ground potential. The transistor 26 has a drain terminal and a gate terminal connected to each other, and functions as a reference current side transistor of the current mirror circuit.

  Normally, when a positive voltage equal to or higher than the pinch-off voltage is applied to the gate terminal, the n-channel transistor conducts between the drain and source terminals. Therefore, when the first input signal S1 and the second input signal S2 are positive voltages equal to or higher than the pinch-off voltage, the transistors 23 and 24 are turned on. In this circuit configuration, since the transistor 23 and the transistor 24 form an AND circuit, the drain terminal of the transistor 26 is only connected when the first input signal S1 and the second input signal S2 are both positive voltages equal to or higher than the pinch-off voltage. The power supply voltage Vdd is supplied.

  The time when both the transistor 23 and the transistor 24 are in the ON state corresponds to the phase difference between the first input signal S1 and the second input signal S2. That is, when the phase difference between the two input signals is small, the time for which both are in the ON state is long, and when the phase difference between the two input signals is large, the time for which both are in the ON state is short. Thereby, the increase / decrease in the phase difference between the first input signal S1 and the second input signal S2 is replaced with the increase / decrease in the supply time of the power supply voltage Vdd to the drain terminal of the transistor 26.

  The transistor 26 can be regarded as a diode equivalently because the gate terminal and the drain terminal are connected. As a result, a voltage corresponding to the current flowing through the drain terminal is obtained at the gate terminal. As described above, since the power supply voltage Vdd is supplied to the drain of the transistor 26 in accordance with the phase difference between the first input signal S1 and the second input signal S2, two transistors are supplied to the gate terminal of the transistor 26. A voltage corresponding to the phase difference of the input signal is generated. The gate voltage of the transistor 26 is supplied to a current value setting terminal (not shown) of the constant current source 6 through the output terminal 22 of the current control circuit 19. As a result, a constant current corresponding to the phase difference between the first input signal S1 and the second input signal S2 flows through the constant current source 6.

FIG. 3 shows a circuit configuration of the output matching circuit 16. Terminal 17 is a capacitor intended for DC blocking
Connected to one end of 27. The other end of the capacitor 27 is connected to one end of the inductor 29, the other end of the inductor 29 is connected to one end of the capacitor 30, and the other end of the capacitor 30 is connected to the output terminal 3. The inductor 29 and the capacitor 30 constitute a series resonance circuit for impedance matching with a fundamental wave. The inductance value of the inductor 29 and the capacitance value of the capacitor 30 are selected so as to resonate in series at the fundamental frequency. The output matching circuit 16 having such a configuration matches the impedance of the transistor 4 viewed from the drain terminal to the output terminal 3 side at the fundamental frequency.

  FIG. 4 shows a circuit configuration of the low-pass filter circuit 8. The inductor 32 is connected in series between the terminal 9 and the terminal 10, and the capacitor 31 is connected in series between the terminal 10 and the ground potential. The low-pass filter circuit 8 having such a configuration prevents the high frequency signal from flowing into the power supply voltage Vdd side by the action of the inductor 32 and allows an unnecessary harmonic signal to flow to the ground via the capacitor 31. Can do.

  In the power amplification and synthesis circuit of this example having such a configuration, the transistor 33 is turned on only when the voltage of the second input signal S2 is a positive voltage larger than the pinch-off voltage Vp, and the first input signal S1. (Similarly, the transistor 34 is turned on only when the voltage of the first input signal S1 is a positive voltage larger than the pinch-off voltage Vp, and allows the second input signal S2 to pass). As a result, the transistor 4 is turned on only during a period in which both the first input signal S1 and the second input signal S2 are positive voltages greater than the pinch-off voltage Vp.

  Therefore, the time during which the transistor 4 is ON corresponds to the phase difference between the first input signal S1 and the second input signal S2. That is, when the phase difference between the two input signals is small, the time during which the transistor 4 is in the ON state is long, and when the phase difference between the two input signals is large, the time during which the transistor 4 is in the ON state is short. Thereby, the increase / decrease in the phase difference between the first input signal S1 and the second input signal S2 is replaced with the increase / decrease in the time during which the transistor 4 is in the ON state.

  Note that the period in which both the first input signal S1 and the second input signal S2 are positive voltages greater than Vp is generated in the same cycle as the first input signal S1 and the second input signal S2, so that the transistor 4 is in the ON state. Is also generated in the same cycle as the first input signal S1 and the second input signal S2. Therefore, the drain voltage of the transistor 4 also includes the same frequency component as the first input signal S1 and the second input signal S2.

  Then, the fundamental wave component (the same frequency component as the first input signal S1 and the second input signal S2) is extracted from the drain voltage of the transistor 4 by the output matching circuit 16 and output from the output terminal 3. This output signal is increased or decreased contrary to the increase or decrease of the phase difference between the first input signal S1 and the second input signal S2, and is obtained by combining and amplifying the first input signal S1 and the second input signal S2. become.

  Note that the voltages of the first input signal S1 and the second input signal S2 are voltages sufficient for the transistor to saturate, and the inductance value of the inductor 29 and the capacitance values of the capacitor 30 and the capacitor 31 are set appropriately. The class E amplifier circuit can be obtained by selecting the above. The class E amplifier circuit operates as a high-efficiency amplifier circuit with low power consumption by switching amplification of the transistor 4.

When the transistor 4 is turned on, a current flows from the power supply voltage Vdd into the transistor 4 through the low-pass filter circuit 8. Of the current flowing into the transistor 4, the high frequency component including the fundamental wave passes through the capacitor 14 and flows to the ground, and the DC component flows to the constant current source 6.

  When the constant current source 6 is not provided on the source side of the transistor 4, the drain current of the transistor 4 flows freely. However, the direct current component of the drain current can be considered as a bias current, and is not a fundamental wave component of the high-frequency power, and thus becomes a loss. For this reason, when the phase difference between the first input signal S1 and the second input signal S2 is large and the combined output power is also small, the fact that a large drain current flows indicates that the power supply efficiency (supplied from the constant voltage power supply Vdd). The ratio of the fundamental wave output power to the generated power) was a factor that deteriorated. The power amplification and synthesis circuit of this example can improve power supply efficiency by limiting the drain current of the transistor 4 according to the phase difference between the two input signals S1 and S2 by the constant current source 6.

  When the phase difference between the first input signal S1 and the second input signal S2 is small, the control voltage from the current control circuit 19 is large, and the constant current source 6 is also set to a large current value. As a result, large power can be supplied to the output matching circuit 16. On the other hand, when the phase difference between the first input signal S1 and the second input signal S2 is large, the control voltage from the current control circuit 19 is small, and a small current value is set in the constant current source 6. As a result, the bias current that can flow through the transistor 4 can be reduced, and loss can be reduced.

  In this way, when the phase difference between the first input signal S1 and the second input signal S2 is large and the output power is thereby reduced, the bias current included in the drain current of the transistor is limited to be small, which is unnecessary. Power consumption can be reduced and power efficiency can be increased. As a result, it is possible to obtain a power amplification and synthesis circuit with high power supply efficiency that can combine power while amplifying the two input signals S1 and S2 with high efficiency.

  Further, according to the power amplification and synthesis circuit of this example, the impedance of the transistor 4 viewed from the drain matching terminal 16 side is changed according to the phase difference between the first input signal S1 and the second input signal S2. Thus, a more efficient power amplification / synthesis circuit can be obtained. Elements that change the impedance of the output matching circuit 16 viewed from the drain terminal of the transistor 4 include an inductor 29 and a capacitor 30 of the output matching circuit 16 and a capacitor 31 of the low-pass filter circuit 8.

  When there is no phase difference between the first input signal S1 and the second input signal S2, the series resonance circuit composed of the inductor 29 and the capacitor 30 is selected so as to resonate at the fundamental frequency. For the capacitor 31, a capacitance value based on the design theory of a known class E amplifier circuit is selected. As a result, the power from the constant voltage power supply Vdd converted into the high frequency power by the switching amplification of the transistor 4 can be efficiently supplied to an external circuit (not shown) via the output terminal 3.

  On the other hand, when the phase difference between the first input signal S1 and the second input signal S2 becomes large, the series resonance circuit including the inductor 29 and the capacitor 30 is selected to resonate at a frequency lower than the fundamental frequency. For the capacitor 31, a value smaller than the capacitance value based on the known design theory of the class E amplifier circuit is selected. As a result, the impedance of the output matching circuit 16 viewed from the drain terminal of the transistor 4 is increased, and the high-frequency signal is returned to the transistor 4 side and is not transmitted to the load circuit through the output matching circuit 16. Therefore, the power from the constant voltage power supply Vdd, which is converted into the high frequency power by the switching amplification of the transistor 4, is not supplied to the load circuit more than necessary, so that it is highly efficient even at low output power. It can be operated.

(Second example of embodiment)
FIG. 5 is a circuit diagram showing a power amplification / synthesis circuit of the second example of the embodiment of the present invention. FIG. 6 is a circuit diagram showing the output matching circuit 16 in the power amplification and synthesis circuit of FIG. Note that in this example, only differences from the first example of the above-described embodiment will be described, and the same components will be denoted by the same reference numerals and redundant description will be omitted.

  The power amplification and synthesis circuit of this example includes a transistor 5, a constant current source 7, a low-pass filter circuit 11 in addition to the power amplification and synthesis circuit of the first example of the embodiment of the present invention shown in FIG. And a capacitor 15. In addition, the output matching circuit 16 in the power amplification and synthesis circuit of this example includes a capacitor 28 and a terminal 18 in addition to the output matching circuit 16 shown in FIG.

The transistor 5 has a gate terminal connected to the drain terminal of the transistor 34 and a source terminal connected to the ground potential via the constant current source 7. A current value setting terminal (not shown) of the constant current source 7 is connected to the terminal 22 of the current control circuit 19. The source terminal of the transistor 5 is connected to the ground potential via the capacitor 15. The low-pass filter circuit 11 has the same configuration and function as the low-pass filter circuit 8.
One end (terminal 13) of the low-pass filter circuit 11 is connected to the drain terminal of the transistor 5, and the other end (terminal 12) of the low-pass filter circuit 11 is connected to the power supply potential Vdd.

  The output matching circuit 16 shown in FIG. 6 is connected to the other end of the capacitor 27 and one end of the inductor 29 with respect to the output matching circuit 16 shown in FIG. Terminal 18 is connected. The terminal 18 of the output matching circuit 16 is connected to the drain terminal of the capacitor 5.

  In the power amplification and synthesis circuit of this example having such a configuration, the transistor 5 functions in the same manner as the transistor 4. That is, the transistor 5 operates in response to the second input signal S2 just as the transistor 4 operates in response to the first input signal S1. Then, the transistor 5 is turned on at the same timing as the transistor 4, and the drain voltage of the transistor 5 includes the same frequency component as the first input signal S1 and the second input signal S2, similarly to the drain voltage of the transistor 4. Become.

  Then, the fundamental wave component is extracted from the drain voltages of the transistors 4 and 5 by the output matching circuit 16 and output from the output terminal 3. This output signal is increased or decreased contrary to the increase or decrease of the phase difference between the first input signal S1 and the second input signal S2, and is obtained by combining and amplifying the first input signal S1 and the second input signal S2. become.

  In the power amplification and synthesis circuit of this example, the current control signal output from the current control circuit 19 decreases the current flowing through the constant current source 6 as the phase difference between the first input signal S1 and the second input signal S2 increases. The constant current source 6 is controlled so that the current flowing through the constant current source 7 decreases as the phase difference between the first input signal S1 and the second input signal S2 increases. As a result, when the phase difference between the first input signal S1 and the second input signal S2 increases and the output power decreases, the bias current flowing through the transistor 4 and the transistor 5 can be reduced. Can be improved.

(Third example of embodiment)
FIG. 7 is a circuit diagram showing a power amplifier circuit according to a third example of the embodiment of the present invention. As shown in FIG. 7, the power amplifier circuit of this example includes a constant envelope signal generation circuit 62 that converts an input signal having an envelope variation into a first constant envelope signal and a second constant envelope signal and outputs the converted signal. And the above-described power amplification and synthesis circuit 61 in which the first constant envelope signal and the second constant envelope signal are input to the input terminal 1 and the input terminal 2 as the first input signal S1 and the second input signal S2, respectively. ing.

  According to the power amplifier circuit of this example having such a configuration, the first constant envelope signal and the second constant signal having a phase difference that increases or decreases the input signal having the envelope fluctuation in the opposite direction to the increase or decrease in the amplitude of the input signal. After being converted into an envelope signal, it can be amplified with high power supply efficiency, and an output signal having an amplified envelope variation can be output. Thereby, a power amplifier circuit with high power supply efficiency can be obtained.

(Fourth example of embodiment)
FIG. 8 is a block diagram showing a transmission apparatus according to a fourth example of the embodiment of the present invention.

  In the transmission apparatus of this example, as shown in FIG. 8, an antenna 82 is connected to a transmission circuit 81 via a power amplification circuit 70 shown in FIG. According to the transmission apparatus of the present example having such a configuration, the transmission signal output from the transmission circuit 81 is amplified using the power amplification circuit 70 of the present invention with low power consumption and high power supply efficiency, and is supplied to the antenna 82. Since it can output, the transmission apparatus with low power consumption and long transmission time can be obtained.

(Fifth example of embodiment)
FIG. 9 is a block diagram showing a communication apparatus according to a fifth example of the embodiment of the present invention.

  In the communication apparatus of this example, as shown in FIG. 9, an antenna 82 is connected to a transmission circuit 81 via a power amplification circuit 70 shown in FIG. 7, and a reception circuit 83 is connected to the antenna 82. An antenna sharing circuit 84 is inserted between the antenna 82 and the power amplifier circuit 70 and the receiving circuit 83. According to the communication apparatus of the present example having such a configuration, the transmission signal output from the transmission circuit 81 is amplified using the power amplifier circuit 70 of the present invention with low power consumption and high power supply efficiency, and is supplied to the antenna 82. Since it can output, a communication apparatus with low power consumption and long transmission time can be obtained.

  Next, a specific example of the power amplifier circuit of the present invention will be described.

The electric characteristics in the power amplification synthesis circuit of the second example of the embodiment of the present invention shown in FIG. 5 were calculated by circuit simulation. The transistors 4 and 5 were gallium arsenide FETs, and the power supply voltage was 4.5V. The transistors 23, 24, and 26 in the current control circuit 19 are n-channel MOSFETs, the power supply voltage is 1.5 V, and the frequency of the input signal is 1 GHz. As a result, when two input signals S1 and S2 having a phase difference of about 40 ° are input, the power added efficiency of the power amplification and synthesis circuit to which the present invention is not applied was 89%. The power added efficiency was improved to 94%. This confirmed the effectiveness of the present invention.

4, 5, 23, 24, 26, 33, 34: Transistor 6, 7: Constant current source 8, 11: Low-pass filter circuit
16: Output matching circuit
19: Current control circuit
61: Power amplification synthesis circuit
62: Constant envelope signal generation circuit
70: Power amplifier circuit
81: Transmitter circuit
82: Antenna
83: Receiver circuit

Claims (4)

A first transistor in which a first input signal is input to the source terminal and a signal in phase with the second input signal is input to the gate terminal;
A second transistor in which the second input signal is input to a source terminal and a signal in phase with the first input signal is input to a gate terminal;
A third transistor having a gate terminal connected to the drain terminal of the first transistor and a source terminal connected to a ground potential via a constant current source;
A low-pass filter circuit having one end connected to the drain terminal of the third transistor and the other end connected to the power supply potential;
An output matching circuit connected to the drain terminal of the third transistor;
When the first input signal and the second input signal are input and the phase difference between the first input signal and the second input signal increases, the constant current source is controlled so that the current flowing through the constant current source decreases. And a current control circuit that outputs a current control signal to be controlled.   A constant envelope signal generating circuit for converting an input signal having an envelope variation into a first constant envelope signal and a second constant envelope signal and outputting the first constant envelope signal and a second constant envelope signal, and the first constant envelope signal and the second constant envelope signal The power amplifier circuit according to claim 1, wherein the power amplifier circuit is input as the first input signal and the second input signal.   An antenna is connected to the transmission circuit via the power amplifier circuit according to claim 2.   An antenna is connected to the transmitting circuit via the power amplifier circuit according to claim 2, and a receiving circuit is connected to the antenna.

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