JP2012151400A - SiC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SiC SEMICONDUCTOR DEVICE - Google Patents

Abstract

An object of the present invention is to provide an SiC semiconductor device that greatly reduces the trap level at the SiC / SiO ₂ interface, has high dielectric strength, low leakage current, and stable threshold voltage.
An SiC semiconductor device according to the present invention is an SiC semiconductor device including an SiC substrate, a gate insulating film formed on the SiC substrate, and a gate electrode formed on the gate insulating film. The gate insulating film includes a first insulating film 5 made of SiO ₂ doped with phosphorus formed on the SiC substrate 1 and a diffusion of phosphorus element more than SiO ₂ formed on the first insulating film 5. And a second insulating film 6 made of a material having a lower band gap than SiC.
[Selection] Figure 1

Description

  The present invention relates to a SiC semiconductor device with low channel resistance and high reliability.

Like silicon (Si), silicon carbide (SiC) can form a silicon dioxide (SiO ₂ ) film by thermal oxidation. SiC has excellent physical property values, and enables the realization of a power device with high breakdown voltage and low loss. However, many interface states exist at the SiC / SiO ₂ interface. Due to the interface state close to the conduction band, the channel mobility of MOSFET (Metal Oxide Semiconductor Field Effect Semiconductor) becomes extremely smaller than the electron mobility in the bulk, and the on-resistance value becomes higher than the ideal value.

In order to inactivate the interface states, a reoxidation process in which thermal oxidation is performed again after forming a gate oxide film, or a nitrogen-based gas such as a nitrogen-oxidized gas (NO _x ) or ammonia (NH ₃ ) gas Heat treatment is performed in an atmosphere. In addition to these, it is known that the interface state density is reduced by doping the gate oxide film with phosphorus element by heat treatment in a phosphoryl chloride (POCl ₃ ) atmosphere (see Non-Patent Document 1). When heat treatment is performed in a phosphoryl chloride atmosphere, channel mobility is about three times higher than in the case where heat treatment is performed in a nitric oxide (NO) atmosphere.

Dai Okamoto, "Improved Inversion Channel Mobility in 4H-SiC MOSFETs on Si Face Utilizing Phosphorus-Doped Gate Oxide", IEEE Electron Device Letters, VOL.31, NO.7, July 2010, pp. 710-712.

In order to reduce the interface state density, a phosphorus element having a concentration higher than 1 × 10 ²¹ (cm ⁻³ ) is required. Elemental phosphorus from the easily diffuse SiO ₂ film, so that a high concentration of phosphorus is present in the entire region of the SiO ₂ film. SiO ₂ has a problem that the dielectric breakdown strength is reduced by adding a high concentration of phosphorus, and the leakage current increases when used as a gate insulating film.

Further, the SiO ₂ film containing phosphorus element has very high hygroscopicity, and phosphorus oxide (P ₂ O ₅ ) elutes from SiO ₂ due to moisture absorption to form phosphoric acid, and the hydrogen ion concentration in the gate insulating film increases. As a result of the increase, there is also a problem that the threshold voltage of the semiconductor device changes.

In the case of using the polycrystalline Si gate electrode, the segregation coefficient of phosphorus element in the SiO ₂ / Si boundary is 10, SiO ₂ phosphorus element is released from the film into the polycrystalline Si, phosphorus in the SiO ₂ film There is concern about a decrease in concentration and an increase in defect levels at the SiC / SiO ₂ interface.

In view of the above-described problems, the present invention greatly reduces the trap level at the SiC / SiO ₂ interface, improves the dielectric strength, reduces the leakage current, and stabilizes the threshold voltage. The purpose is to provide a method.

The SiC semiconductor device of the present invention includes a SiC substrate, a gate insulating film formed on the SiC substrate, and a gate electrode formed on the gate insulating film, and the gate insulating film is formed on the SiC substrate. A first insulating film made of SiO ₂ to which phosphorus is added, and a material formed on the first insulating film and having a lower diffusion rate of phosphorus element than SiO ₂ and a larger band gap than SiC A second insulating film.

The SiC semiconductor device manufacturing method of the present invention includes (a) a step of preparing a SiC substrate, (b) a step of forming a gate insulating film on the SiC substrate, and (c) a gate electrode on the gate insulating film. The step (b) includes: (d) forming a first insulating film made of SiO ₂ doped with phosphorus on the SiC substrate; and (e) on the first insulating film. And a step of forming a second insulating film having a lower diffusion rate of phosphorus element than SiO ₂ and a larger band gap than SiC.

In the SiC semiconductor device of the present invention, the gate insulating film includes a first insulating film made of SiO ₂ added with phosphorus formed on the SiC substrate, which is formed on the first insulating film, than SiO ₂ And a second insulating film made of a material having a low diffusion rate of phosphorus element and a band gap larger than that of SiC. The phosphorus added to the first insulating film significantly reduces the trap level generated between the SiC substrate and the second insulating film, and prevents the phosphorus in the first insulating film from diffusing. The leakage current is reduced and the threshold voltage is stabilized.

In the method for manufacturing a SiC semiconductor device according to the present invention, (b) the step of forming a gate insulating film on the SiC substrate includes (d) forming a first insulating film made of SiO ₂ doped with phosphorus on the SiC substrate. And (e) forming a second insulating film having a lower diffusion rate of phosphorus element than SiO ₂ and a larger band gap than SiC on the first insulating film. By forming the first insulating film to which phosphorus is added, the trap level generated between the SiC substrate and the SiC substrate is significantly reduced. Further, since the formation of the second insulating film prevents phosphorus in the first insulating film from diffusing, manufacturing of an SiC semiconductor device having a stable threshold voltage with a high dielectric strength, a low leakage current, and the like can be achieved. Is possible.

1 is a cross-sectional view showing a configuration of an SiC semiconductor device according to a first embodiment. 7 is a cross-sectional view showing a manufacturing step of the SiC semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the SiC semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the SiC semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the SiC semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the SiC semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the SiC semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the SiC semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the SiC semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view showing a configuration of an SiC semiconductor device according to a second embodiment. FIG. 12 is a cross-sectional view showing a manufacturing step of the SiC semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view showing a manufacturing step of the SiC semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view showing a manufacturing step of the SiC semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view showing a manufacturing step of the SiC semiconductor device according to the second embodiment. FIG.

(Embodiment 1)
In the following description, the terms “first conductivity type” and “second conductivity type” are used as the conductivity type of the semiconductor layer. If the first conductivity type is n type, the second conductivity type is p type, If the first conductivity type is p-type, the second conductivity type is n-type.

<Configuration>
FIG. 1 is a cross-sectional view showing the structure of a MOSFET which is a SiC semiconductor device according to the first embodiment.

  In the MOSFET according to the present embodiment, a drift layer 2 made of SiC of the first conductivity type is formed on the surface of the SiC substrate 1 of the first conductivity type. On the surface of the drift layer 2, base regions 3a and 3b of the second conductivity type separated from each other are formed. First conductivity type source regions 4a and 4b are formed on the surfaces of the base regions 3a and 3b, respectively.

Further, the gate insulating film is formed so as to overlap the drift layer 2 exposed from between the base regions 3a and 3b, the base regions 3a and 3b, and further part of the source regions 4a and 4b. The gate insulating film comprises a lower first insulating film 5 and an upper second insulating film 6. The first insulating film 5 is a SiO ₂ film to which phosphorus is added, and the second insulating film 6 is formed of an insulating film in which phosphorus element is less diffused than a SiO ₂ film such as a silicon oxynitride (SiON) film. .

In the first insulating film 5, trap levels generated at the interface with the SiC layer are suppressed by adding phosphorus to the SiO ₂ film. Further, by forming a SiON film as the second insulating film 6 on the first insulating film 5, the phosphorus of the first insulating film 5 is prevented from diffusing into the second insulating film 6, and the dielectric strength of the gate insulating film as a whole is increased. Avoiding a decline.

  Source electrodes 8a and 8b are formed on the source regions 4a and 4b, respectively. A gate electrode 7 is formed on the SiON film 6. SiC substrate 1, drift layer 2, base regions 3a and 3b, and source regions 4a and 4b constitute a base. A drain electrode 9 is formed on the back surface of the substrate.

<Operation>
When a voltage is applied to the gate electrode 7, an inversion channel layer is formed on the surfaces of the base regions 3 a and 3 b immediately below the gate electrode 7, and a path through which charges flow is formed between the source regions 4 a and 4 b and the drift layer 2. The When the MOSFET of the present embodiment is an n-channel MOSFET, the majority carriers are electrons, and the electrons flowing from the source regions 4a and 4b into the drift layer 2 drift according to the electric field formed by the voltage applied to the drain electrode 9. The drain electrode 9 is reached through the layer 2 and the substrate 1. Therefore, when a voltage is applied to the gate electrode 7, a current flows from the drain electrode 9 to the source electrodes 8a and 8b.

  When the MOSFET of this embodiment is a p-channel MOSFET, the majority carriers are holes, and holes injected from the drain electrode 9 reach the base regions 3a and 3b via the drift layer 2, and then It flows into the source regions 4a and 4b according to the electric field formed by the voltage applied to the source electrodes 8a and 8b via the inversion channel layer formed on the surface of the base regions 3a and 3b. Thereby, holes flow from the drain electrode 9 to the source electrodes 8a and 8b.

<Manufacturing process>
Hereinafter, the manufacturing process of the SiC-MOSFET shown in FIG. 1 will be described with reference to FIGS.

First, referring to FIG. 2, drift layer 2 composed of a first conductivity type SiC epitaxial layer is formed on first conductivity type SiC substrate 1 using an epitaxial growth method. The thickness of the drift layer 2 may be about 5 to 50 μm, and the impurity concentration is 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ . By forming the drift layer 2 under these conditions, a vertical high voltage MOSFET having a withstand voltage of several hundred V to 3 kV or more is realized.

  As a surface on which the SiC substrate 1 is epitaxially grown, a (0001) plane, a (000-1) plane, a (11-20) plane, or the like can be used. As the polytype of the SiC substrate 1, 4H, 6H, or 3C can be used.

  Next, a mask is formed with a resist, silicon dioxide, silicon nitride or the like by using a photoengraving technique so that a region for forming a base region is exposed on the surface of the drift layer 2. Impurities are ion-implanted using this mask as an impurity implantation blocking film to form a pair of second conductivity type base regions 3a and 3b. FIG. 3 shows a cross-sectional structure of the element after removing the mask used for this ion implantation.

  As the second conductivity type impurity introduced into the base regions 3a and 3b, for example, boron (B) or aluminum (Al) can be used when manufacturing an n-channel MOSFET, and when manufacturing a p-channel MOSFET, for example, phosphorus (P) or nitrogen (N) can be used.

  The depth of the base regions 3a and 3b is required not to exceed the thickness of the drift layer 2, and may be about 0.5 to 3 μm, for example.

The impurity concentration of the base regions 3a and 3b is set to a concentration exceeding the first conductivity type impurity concentration in the drift layer 2, and may be, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ .

  Next, a mask is formed on the surface of the substrate using a photoengraving technique, the source region forming portion is exposed, the first conductivity type impurity is ion-implanted into the base regions 3a and 3b using the mask as an impurity implantation blocking film, Source regions 4a and 4b of one conductivity type are formed respectively. FIG. 4 shows a cross section of the device after removing the masks for forming the source regions 4a and 4b.

  As an impurity of the first conductivity type introduced into the source regions 4a and 4b, for example, phosphorus (P) or nitrogen (N) can be used when manufacturing an n-channel MOSFET, and a p-channel MOSFET is manufactured. In this case, for example, boron (B) or aluminum (Al) can be used.

The source regions 4a and 4b are formed shallower than the base regions 3a and 3b. The impurity concentration of the first conductivity type introduced into the source regions 4a and 4b may be, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ .

  Subsequently, the SiC substrate is subjected to a heat treatment for about 10 seconds to 1 hour under a high temperature condition of 1300 to 1900 ° C., for example, by a heat treatment apparatus, whereby ions implanted into the base regions 3a and 3b and the source regions 4a and 4b are electrically Activated.

Next, the surface of the SiC substrate is heated and oxidized in a water vapor atmosphere containing water (H ₂ O), for example. Thereby, a SiO ₂ film having an average thickness of, for example, about 10 nm is formed on the surface of the SiC substrate. The oxidation temperature during thermal oxidation is 1000 ° C. or higher, preferably 1100 ° C. or higher and 1300 ° C. or lower.

Note that the method of forming the SiO ₂ film may be a method using heating in an oxygen gas atmosphere or a chemical vapor deposition method.

After forming the SiO ₂ film, the SiC substrate is introduced into the quartz tube furnace, the processing temperature is set to a predetermined temperature, and the phosphor is composed of phosphoryl chloride (POCl ₃ ), oxygen (O ₂ ), and nitrogen (N ₂ ). A SiO ₂ film to which phosphorus is added is formed as the first insulating film 5 by heat treatment in a mixed gas (FIG. 5). Here, as a method for introducing a phosphorus element into the SiO ₂ film, heat treatment may be performed in a POCl ₃ atmosphere, or a phosphorus element may be ion-implanted into the SiO ₂ film. Alternatively, phosphorus element may be ion-implanted into the SiC substrate before forming the SiO ₂ film, and the first insulating film 5 may be formed by thermally oxidizing the ion-implanted region, or phosphorus is added onto the SiC substrate. After depositing poly-Si, the first insulating film 5 may be formed by oxidizing poly-Si at a low temperature.

If ion implantation of phosphorus element in the SiO ₂ film, for example, if the thickness of the SiO ₂ film with 10 nm, the acceleration energy of ions is preferably not more than 2.5keV not reach the phosphorus element in the SiC substrate.

When the first insulating film 5 is formed by ion-implanting phosphorus element into the SiC substrate and forming the first insulating film 5 by thermally oxidizing the ion-implanted region before forming the SiO ₂ film, the film thickness of the first insulating film 5 is 10 nm. In this case, the acceleration energy is preferably about 0.5 keV.

The first insulating film 5 only needs to have a film thickness corresponding to the deposition depth of carbon atoms observed on the SiO ₂ side of the normal SiO ₂ / SiC interface, and the film thickness is desirably 5 nm or more.

Next, referring to FIG. 6, an SiC substrate is introduced into a chemical vapor deposition furnace (CVD furnace), a processing temperature is set to a predetermined temperature, and a CVD method is performed on the first insulating film 5. A silicon oxynitride (SiON) film is formed as the second insulating film 6 by a chemical vapor deposition method. For the material gas in the CVD furnace, for example, silane (SiH ₄ ), dichlorosilane (SiH ₂ Cl ₂ ), silicon tetrachloride (SiCl ₄ ), or the like can be used as a silicon source. As the nitrogen source, for example, nitrogen (N, N ₂ ) or ammonia (NH ₃ ) is used.

When the first insulating film is a general PSG (Phosphorus silicate glass) and the phosphorus concentration is 6 to 8 wt%, the reflow occurs at about 950 to 1100 ° C. or more depending on the phosphorus concentration. Above this temperature, phosphorus element easily diffuses into the deposited SiON film 6. Although the diffusion coefficient of phosphorus element in the SiON film 6 is smaller than that of the SiO ₂ film, the diffusion of phosphorus can be further prevented by depositing the SiON film 6 in a temperature region where reflow does not occur.

The nitrogen concentration in the SiON film 6 is preferably set to 1 × 10 ²⁰ to 1 × 10 ²¹ (cm ⁻³ ) in consideration of both diffusion prevention of phosphorus element and maintenance of the band gap width.

Instead of forming the SiON film as the second insulating film 6, an insulating film in which the phosphorus element is less likely to diffuse than the SiO ₂ film and has a larger band gap width than SiC may be formed.

  The total thickness of the first insulating film 5 and the second insulating film 6 is the thickness of the gate insulating film. In the MOSFET, the gate insulating film thickness greatly affects the threshold voltage and the insulation reliability, so that the total film thickness is preferably about 10 to 100 nm.

Further, a phosphorus concentration of about 5 wt% is required to reduce the defect level at the SiC / SiO ₂ interface, and the SiO ₂ film 5 having this phosphorus concentration undergoes reflow at 1150 ° C. or higher. Therefore, it is desirable not to take a temperature transition of 1150 ° C. or higher after the gate insulating film is formed.

  Next, a gate electrode 7 is formed on the SiON film 6, and the gate electrode 7 is patterned using photolithography (FIG. 7). The gate electrode 7 is patterned in such a shape that the base regions 3a and 3b and the source regions 4a and 4b are located at both ends in plan view, and the exposed drift layer 2 between the base regions 3a and 3b is located at the center thereof. Is done.

  The gate electrode 7 is preferably formed so as to overlap with the pair of source regions 4a and 4b in the range of, for example, 10 nm to 5 μm in plan view. Thereby, the influence of the fringe effect generated at the end portion of the gate electrode 7 is suppressed, and a voltage is uniformly applied to the surfaces of the base regions 3a and 3b, so that the inversion channel layer can be reliably formed.

  As a material of the gate electrode 7, n-type or p-type poly-Si or poly-SiC, a high melting point low resistance metal such as aluminum, titanium, molybdenum, tantalum, niobium, or tungsten can be used. Low resistance metal nitrides may be used.

After patterning the gate electrode 7, unnecessary portions of the SiO ₂ film 5 and the SiON film 6 to which phosphorus is added are removed by patterning using photolithography and wet or dry etching, as shown in FIG. The surfaces of the source regions 4a and 4b are exposed. The SiO ₂ film 5 and the SiON film 6 to which phosphorus is added are formed longer than the gate electrode 7, and the source electrodes 8a and 8b formed in the next step and the gate electrode 7 are reliably electrically separated.

  Next, source electrodes 8a and 8b are formed and patterned on the exposed portions of the source regions 4a and 4b (FIG. 9).

  Thereafter, the drain electrode 9 is formed on the back surface of the SiC substrate 1 to complete the main part of the SiC-MOSFET having the element structure shown in FIG.

  As materials for the source electrodes 8a and 8b and the drain electrode 9, aluminum, nickel, titanium, gold, or a composite thereof can be used. Further, in order to obtain ohmic contact between the source regions 4a and 4b and the SiC substrate 1, heat treatment at about 1000 ° C. may be performed after the source electrodes 8a and 8b and the drain electrode 9 are formed.

<Effect>
As described above, according to the method for manufacturing a silicon carbide semiconductor device according to the present invention, by adding a silicon oxynitride film, it is possible to prevent phosphorus element from diffusing throughout the gate insulating film, and to obtain a dielectric breakdown strength of the gate insulating film. Is not significantly reduced. In addition, the presence of the silicon oxynitride film can prevent water vapor from touching the gate insulating film and suppress a change in value voltage due to moisture absorption by the gate insulating film.

The SiC semiconductor device of the present invention includes a SiC substrate 1, a gate insulating film formed on the SiC substrate 1, and a gate electrode 7 formed on the gate insulating film, and the gate insulating film is a SiC substrate. The first insulating film 5 made of SiO ₂ to which phosphorus is added and formed on the first insulating film 5, and the diffusion rate of the phosphorus element formed on the first insulating film 5 is lower than that of SiO _{2 and} is larger than that of SiC. And a second insulating film 6 made of a material having By adding phosphorus to the first insulating film 5, an interface state generated between the SiC layer and the SiC layer is suppressed, and phosphorus added to the first insulating film 5 is prevented from diffusing by the second insulating film 6. High dielectric strength is maintained, and leakage current is reduced. In addition, the second insulating film 6 prevents water vapor from touching the first insulating film 5 and prevents the first insulating film 5 from absorbing moisture, so that the threshold voltage is stabilized.

  Further, since the second insulating film 6 is an SiON film, phosphorus added to the first insulating film 5 is prevented from diffusing, so that a high dielectric strength is maintained, a leakage current is reduced, and a threshold voltage is stabilized.

The manufacturing method of the SiC semiconductor device of the present embodiment includes (a) a step of preparing SiC substrate 1, (b) a step of forming a gate insulating film on SiC substrate 1, and (c) on the gate insulating film. The step (b) includes the step (d) forming a first insulating film 5 made of SiO ₂ doped with phosphorus on the SiC substrate 1, and (e) a first step. Forming a second insulating film 6 having a lower diffusion rate of phosphorus element than SiO ₂ and having a larger band gap than SiC on the first insulating film 5. Since the first insulating film 5 to which phosphorus is added in the step (d) is formed, the trap level generated between the SiC substrate and the SiC substrate is greatly reduced. Further, by forming the second insulating film in the step (e), it is possible to prevent the phosphorus in the first insulating film from diffusing, so that SiC having high dielectric strength, low leakage current, and stable threshold voltage can be obtained. It becomes a semiconductor device. Further, since the second insulating film 6 prevents moisture absorption of the first insulating film 5, the threshold voltage is stabilized.

  In the step (e), the SiON film is formed as the second insulating film 6 to prevent the phosphorus added to the first insulating film 5 from diffusing, so that a high dielectric strength is maintained, and a low leakage current is obtained. An SiC semiconductor device having a stable threshold voltage can be manufactured.

In the step (d), (g) a step of forming a SiO ₂ film on the SiC substrate 1 by thermal oxidation or CVD, and (h) after the step (g), the SiO ₂ film is converted to phosphoryl chloride. And a step of heat treatment in an atmosphere containing (POCl ₃ ), so that trap levels generated between the SiC layer and the SiC layer are significantly reduced.

  Alternatively, the step (d) includes (i) a step of ion-implanting a phosphorus element onto the SiC substrate 1 and (j) a step of thermally oxidizing the SiC substrate 1 after the step (i). Therefore, the trap level generated between the SiC layer and the SiC layer is greatly reduced.

Alternatively, in the step (d), (k) a step of forming a SiO ₂ film on the SiC substrate 1 by thermal oxidation or a CVD method, and (l) after the step (k), phosphorus is added to the SiO ₂ film. Since the step of ion-implanting the element and (m) the step of heat-treating the SiO ₂ film after the step (l) are provided, the trap level generated between the SiC layer and the SiC layer is greatly reduced.

  Alternatively, the step (d) includes (n) a step of depositing a poly-Si film doped with a phosphorus element on the SiC substrate 1, and (o) a step of thermally oxidizing the poly-Si film after the step (n). Therefore, the trap level generated between the SiC layer and the SiC layer is significantly reduced.

(Embodiment 2)
<Configuration>
FIG. 10 is a cross-sectional view showing a configuration of a MOSFET which is an SiC semiconductor device according to the second embodiment. In the first embodiment, the gate insulating film has a laminated structure of the SiO ₂ film 5 and the SiON film 6 to which phosphorus is added. In the _second embodiment, a non-doped SiO ₂ film 10 is further formed on the SiON film 6. These three layers constitute a gate insulating film. Since points other than this are the same as those of the first embodiment, description thereof is omitted.

<Manufacturing process>
A manufacturing process of the MOSFET according to the second embodiment will be described with reference to FIGS. The steps until the SiON film 6 is formed on the SiO ₂ film 5 in which phosphorus is added to the SiC substrate are the same as those in the first embodiment shown in FIGS.

An SiO ₂ film 10 is deposited on the upper surface of the SiON film 6 (FIG. 11). Next, the gate electrode 7 is formed on the SiO ₂ film 10 (FIG. 12). The formation position of the gate electrode 7 is the same as that of the first embodiment except that the SiO ₂ film 10 exists on the SiON film 6. The material of the gate electrode 7 is the same as that in the first embodiment.

Thereafter, as in the first embodiment, predetermined portions of the SiO ₂ film 10, the SiON film 6, and the SiO ₂ film 5 doped with phosphorus are removed to expose the surfaces of the source electrodes 4a and 4b (FIG. 13). Source electrodes 8a and 8b are formed on the exposed portions by film formation and patterning (FIG. 14).

  Thereafter, the drain electrode 9 is formed on the back surface of the SiC substrate 1, thereby forming the SiC-MOSFET having the element structure shown in FIG.

<Effect>
In the SiC semiconductor device of the present embodiment, the gate insulating film further includes the third insulating film 10 made of SiO ₂ formed on the second insulating film 6, so that the second insulating made of SiON having a small band gap width. The film thickness can be reduced, and the dielectric breakdown strength of the gate insulating film can be made closer to that when the gate insulating film is made of only the SiO ₂ film. Moreover, a desired threshold value can be obtained by adjusting the film thickness ratio between the second insulating film 6 and the third insulating film 10.

The manufacturing method of the SiC semiconductor device of the present embodiment includes the step of forming the third insulating film 10 made of SiO ₂ on the second insulating film 6, so that the dielectric breakdown strength of the gate insulating film is reduced to the SiO ₂ It can be approached when it consists of only _two films. Moreover, a desired threshold value can be obtained by adjusting the film thickness ratio between the second insulating film 6 and the third insulating film 10.

The present invention can be applied to an insulated gate transistor element such as a MOSFET or IGBT having a SiO ₂ film formed on a SiC substrate layer as a gate insulating film. The insulated gate transistor can also be applied to a lateral semiconductor element in which the source, gate and drain electrodes are formed on the same main surface. A power device having high mobility and operating at high speed This can be realized by the present invention. The effect of the present invention can also be applied to the reduction of the interface state at the element isolation interface by the shallow trench isolation (STI) method or the LOCOS method.

  1 SiC substrate, 2 drift layer, 3a, 3b base region, 4a, 4b source region, 5 first insulating film, 6 second insulating film, 7 gate electrode, 8a, 8b source electrode, 9 drain electrode, 10 third insulation film.

Claims (10)

A SiC substrate;
A gate insulating film formed on the SiC substrate;
A SiC semiconductor device comprising a gate electrode formed on the gate insulating film,
The gate insulating film is
A first insulating film made of SiO ₂ doped with phosphorus formed on the SiC substrate;
A second insulating film made of a material having a lower diffusion rate of phosphorus element than SiO ₂ and having a larger band gap than SiC, formed on the first insulating film;
SiC semiconductor device. The second insulating film is a SiON film;
The SiC semiconductor device according to claim 1. The gate insulating film further includes a third insulating film made of SiO ₂ formed on the second insulating film;
The SiC semiconductor device according to claim 1. (A) preparing a SiC substrate;
(B) forming a gate insulating film on the SiC substrate;
(C) forming a gate electrode on the gate insulating film,
The step (b)
(D) forming a first insulating film made of SiO ₂ doped with phosphorus on a SiC substrate;
(E) forming a second insulating film having a lower diffusion rate of phosphorus element than SiO ₂ and having a larger band gap than SiC on the first insulating film. The step (e) is a step of forming a SiON film as the second insulating film.
The manufacturing method of the SiC semiconductor device of Claim 4. (F) further comprising a step of forming a third insulating film made of SiO ₂ on the second insulating film;
A method for manufacturing an SiC semiconductor device according to claim 4 or 5. The step (d)
(G) forming a SiO ₂ film on the SiC substrate 1 by thermal oxidation or CVD;
(H) after the step (g), heat-treating the SiO ₂ film in an atmosphere containing phosphoryl chloride (POCl ₃ );
The manufacturing method of the SiC semiconductor device in any one of Claims 4-6 provided with these. The step (d)
(I) a step of ion-implanting a phosphorus element on the SiC substrate;
(J) The manufacturing method of the SiC semiconductor device in any one of Claims 4-6 provided with the process of thermally oxidizing the said SiC substrate after the said process (i). The step (d)
(K) forming a SiO ₂ film on the SiC substrate by thermal oxidation or CVD;
(L) a step of ion-implanting phosphorus element into the SiO ₂ film after the step (k);
(M) after said step (l), and a step of heat-treating the SiO ₂ film, a manufacturing method of the SiC semiconductor device according to any one of claims 4-6. The step (d)
(N) depositing a phosphorus element-doped poly-Si film on the SiC substrate 1;
(O) The manufacturing method of the SiC semiconductor device in any one of Claims 4-6 provided with the process of thermally oxidizing the said poly Si film | membrane after the said process (n).

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