JP2012151154A - Method for manufacturing component built-in wiring substrate - Google Patents

Abstract

To provide a method of manufacturing a wiring board with a built-in component, which can manufacture a wiring board with excellent connection reliability with a built-in component at a low cost.
After preparing a ceramic capacitor and a core substrate, an insulating layer is formed and one opening of an accommodation hole is formed by bonding a build-up material to the core back surface side of the core substrate. Block. By mounting the ceramic capacitor 101 on the insulating layer on the core back surface 13 side, the ceramic capacitor 101 is accommodated in the accommodation hole 90, and the gap between the inner wall surface 91 of the accommodation hole 90 and the ceramic capacitor 101 is accommodated by the resin filling portion 93. 92 is filled. The insulating layers formed on the core main surface 12 side and the core back surface 13 side are polished to expose the external electrodes 111, 112, 121, 122 of the ceramic capacitor 101. On the resin filling portion 93, the conductor layer 50 is formed by performing patterning after the entire surface is plated.
[Selection] Figure 11

Description

  The present invention relates to a method of manufacturing a component built-in wiring board in which a built-in component is housed in a housing hole of a core substrate.

  In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard. In a wiring board for mounting an IC chip constituting this type of package, it has been proposed to provide a capacitor (also referred to as a “capacitor”) in order to reduce switching noise of the IC chip and stabilize the power supply voltage. . For example, a component built-in wiring board in which a capacitor is embedded in a resin core board (for example, see Patent Document 1) has been proposed.

  One example of the conventional method for manufacturing the component built-in wiring board will be described below with reference to FIGS. First, a core substrate 204 made of a polymer material having an accommodation hole 203 that opens on both the core main surface 201 and the core back surface 202 is prepared. In addition, a capacitor 209 having a plurality of surface electrodes 207 and 208 on the capacitor main surface 205 and the capacitor back surface 206 is prepared. A protruding conductor 210 is formed on the surface electrode 207 on the capacitor main surface 205 side of the capacitor 209. Next, in the core substrate 204, a taping step of attaching an adhesive tape 211 (masking tape) to the core back surface 202 side is performed, and the opening of the housing hole 203 on the core back surface 202 side is sealed in advance. And the accommodation process which accommodates the capacitor | condenser 209 in the accommodation hole part 203 is performed, and the capacitor | condenser back surface 206 is affixed on the adhesive surface of the adhesive tape 211, and is temporarily fixed.

  Next, a resin insulating layer 212 is formed on the core main surface 201 and the capacitor main surface 205 (see FIG. 16). In addition, the gap between the inner wall surface of the accommodation hole 203 and the capacitor 209 is filled with a part of the resin insulating layer 212 to fix the capacitor 209. Thereafter, the adhesive tape 211 is peeled off. Then, the resin insulating layer 212 is polished to expose the surface of the protruding conductor 210 of the surface electrode 207 in the capacitor 209.

  Next, the resin insulating layer 213 is formed on the core main surface 201 and the capacitor main surface 205, and the resin insulating layer 214 is formed on the core back surface 202 and the capacitor back surface 206. Further, laser drilling is performed to form via holes 216 penetrating the resin insulating layers 213 and 214 at a plurality of locations, and the protruding conductors 210 and the surface electrodes 208 of the surface electrode 207 are exposed. Then, after performing electroless copper plating on the inner surfaces of the resin insulating layers 213 and 214 and the via hole 216, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Thereby, the conductor layer 215 is patterned on the resin insulating layers 213 and 214, and the via conductor 217 is formed inside each via hole 216 (see FIG. 17).

  Thereafter, the build-up layer is formed by alternately forming the resin insulating layer and the conductor layer on the resin insulating layers 213 and 214. As a result, a desired wiring board is obtained.

JP 2008-306173 A

  By the way, in the conventional manufacturing method described above, the adhesive tape 211 is required to temporarily fix the capacitor 209 in the accommodation hole 203. The adhesive tape 211 is unnecessary after the capacitor 209 is fixed, and is peeled off from the core substrate 204 and is discarded. Further, since the electrodes 207 and 208 of the capacitor 209 built in the core substrate 204 are electrically connected to the conductor layer 215 through the via conductors 217 formed in the resin insulating layers 213 and 214, wiring is performed. There is also a problem that the degree of freedom of the pattern is lost and the total number of the resin insulating layers 213 and 214 is increased. Further, there is a problem that the wiring board is warped or a wave is generated on the substrate surface due to the difference in the coefficient of thermal expansion (CTE) between the capacitor 209, the core substrate 204, and the embedded resin (resin insulating layer 212).

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a wiring board with a built-in component that can manufacture a wiring board with excellent connection reliability with a built-in component at a low cost. There is.

  And as means (means 1) for solving the above-mentioned problem, a built-in part having a first component main surface on which a plurality of first surface electrodes are arranged and a second component main surface on which a plurality of second surface electrodes are arranged. A preparation step of preparing a core substrate having a first main surface and a second main surface and having an accommodation hole portion that is open at the first main surface and the second main surface; After the preparation step, a build-up material mainly composed of a resin material is joined to the second main surface side of the core substrate to form a second main surface side insulating layer and one of the accommodation holes After the second main surface side insulating layer forming step for closing the opening of the substrate and the second main surface side insulating layer forming step, the housing part is mounted on the second main surface side insulating layer by mounting the built-in component. A housing step of housing the built-in component in the part, and the housing hole portion with a filled resin material after the housing step After the gap filling step for filling the gap between the inner wall surface and the built-in component, and after the housing step, the buildup material is joined to the first main surface side of the core substrate, whereby the first main surface side insulating layer The first main surface side insulating layer is formed after the first main surface side insulating layer forming step, and the first main surface side insulating layer forming step is performed to polish the first main surface side insulating layer. A double-side polishing step of exposing the plurality of first surface electrodes and polishing the second main surface side insulating layer to expose the plurality of second surface electrodes; and after the double-side polishing step, And a patterning step of forming a wiring layer by performing patterning after performing overall plating on the first main surface side insulating layer and the second main surface side insulating layer. There is.

  Therefore, according to the invention described in the means 1, in the housing step, the built-in component is temporarily fixed in the housing hole portion using the buildup material of the second main surface side insulating layer that remains as a part of the wiring board later. If it does in this way, since it is not necessary to fix a built-in component using a masking tape like the prior art, manufacturing cost can be held down. Further, in the double-side polishing step, the first main surface side insulating layer and the second main surface side insulating layer are polished, and the first surface electrode and the second surface electrode are exposed. And in a patterning process, a wiring layer can be directly connected to each electrode of a built-in component by forming a wiring layer. In this case, the degree of freedom of the wiring pattern is increased and the electrical connection to the built-in component can be favorably performed as compared with the case of connecting to each electrode by the via conductor as in the prior art. Further, in the case of polishing only one side as in the prior art, the core substrate may be warped due to the extension of the conductor layer on one side, but in the present invention, both sides are similarly polished. Warpage of the substrate due to elongation of the conductor layer on the main surface side and the second main surface side can be prevented.

  In the gap filling process, the inner wall surface of the accommodation hole is built in by flowing a part of the resin material constituting the first main surface side insulating layer and a part of the resin material constituting the second main surface side insulating layer. It is preferable to fill a gap with the part. In this way, when flowing the resin material of the insulating layer on both main surfaces of the first main surface and the second main surface, compared to the case of flowing the resin material of the insulating layer only on one main surface side, The gap can be filled reliably.

  The plurality of first surface electrodes and the plurality of second surface electrodes in the built-in component are preferably formed by forming protruding conductors on the conductor layer. In this way, when a thick projecting conductor is provided on each surface electrode, even if the built-in component is displaced in the thickness direction within the receiving hole, the misalignment is adjusted by cutting the projecting conductor in the polishing process. can do.

  As for the metal material which comprises a protruding conductor, copper, silver, iron, cobalt, nickel etc. are mentioned, for example. In particular, the protruding conductor is preferably formed mainly of copper. In this way, the resistance of the protruding conductor can be reduced and the conductivity of the protruding conductor can be improved as compared with the case where the protruding conductor is mainly formed of another material. In addition, since the protruding conductor is formed mainly of relatively soft copper, the protruding conductor can be easily polished.

  Examples of the method for forming the protruding conductor include a method of forming the protruding conductor by plating. When the protruding conductor is formed mainly of copper, the protruding conductor is preferably formed by copper plating. In this way, the conductivity of the protruding conductor is improved as compared with the case where the protruding conductor is formed of, for example, a conductive paste. Other methods of forming the protruding conductor include a method of forming a protruding conductor by printing a metal paste, a method of forming a protruding conductor by performing only a step of applying a metal foil, and a protruding conductor. For example, a method of forming a protruding conductor by applying a larger metal foil and then etching the metal foil.

  In the housing step, the built-in component may be mounted on the second main surface side insulating layer so that at least a part of the plurality of second surface electrodes is buried in the second main surface side insulating layer. If it does in this way, position shift of a built-in component in an accommodation hole part can be prevented certainly.

  It is preferable that the protruding conductor, the conductor layer formed on the protruding conductor through the patterning step, and the via conductor formed on the conductor layer are both made of copper. In this way, electrical connection between each surface electrode of the built-in component and the conductor layer on the wiring board side can be reliably performed.

  In the patterning step, it is preferable to form a conductor layer on the first main surface side insulating layer and the second main surface side insulating layer and covering a portion corresponding to the gap. In this case, the resin material that fills the gap expands due to heat applied during the manufacture of the substrate. However, the warping of the wiring substrate can be reliably suppressed by pressing the resin material with a conductor layer harder than the resin material.

  Examples of the built-in component include a chip capacitor and a ceramic capacitor. In addition, as a preferable ceramic capacitor, a dielectric layer, a plurality of internal electrodes stacked via the dielectric layer, a plurality of first surface electrodes and a plurality of electrodes connected to the plurality of internal electrodes and at both ends are provided. And a plurality of via conductors in the capacitor connected to the second surface electrode, and a plurality of via conductors in the capacitor are arranged in an array as a whole. With such a structure, the inductance of the capacitor can be reduced, and noise absorption and voltage stabilization can be achieved.

  As the dielectric layer of the ceramic capacitor, a sintered body of high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride, etc. is preferably used, and borosilicate glass or lead borosilicate glass. A sintered body of low-temperature fired ceramic such as glass ceramic to which an inorganic ceramic filler such as alumina is added is suitably used. In this case, it is also preferable to use a sintered body of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate depending on the application. When a dielectric ceramic sintered body is used, a capacitor having a large capacitance can be easily realized.

  Although it does not specifically limit as an internal electrode of a ceramic capacitor and a via conductor in a capacitor, For example, it is preferred that it is a metallized conductor. The metallized conductor is formed by applying a conductive paste containing metal powder by a conventionally well-known method, for example, a metallized printing method, followed by baking. When the metallized conductor and the ceramic dielectric layer are formed by the co-firing method, the metal powder in the metallized conductor needs to have a melting point higher than the firing temperature of the ceramic dielectric layer. For example, when the ceramic dielectric layer is made of a so-called high-temperature fired ceramic (for example, alumina), the metal powder in the metallized conductor includes nickel (Ni), tungsten (W), molybdenum (Mo), manganese (Mn), etc. And their alloys can be selected. When the ceramic dielectric layer is made of a so-called low-temperature fired ceramic (for example, glass ceramic), copper (Cu) or silver (Ag) or an alloy thereof can be selected as the metal powder in the metallized conductor.

  Specific examples of the core substrate include an EP resin (epoxy resin) substrate, a PI resin (polyimide resin) substrate, a BT resin (bismaleimide / triazine resin) substrate, and a PPE resin (polyphenylene ether resin) substrate. In addition, a substrate made of a composite material of these resins and organic fibers such as glass fibers (glass woven fabric or glass nonwoven fabric) or polyamide fibers may be used. Alternatively, a substrate made of a resin-resin composite material obtained by impregnating a thermosetting resin such as an epoxy resin with a three-dimensional network fluorine-based resin base material such as continuous porous PTFE may be used.

  The insulating layer can be appropriately selected in consideration of insulating properties, heat resistance, moisture resistance, and the like. Preferred examples of the insulating layer forming material include thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin, and thermoplastic resins such as polycarbonate resin, acrylic resin, polyacetal resin, and polypropylene resin. Can be mentioned. In addition, composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc. A resin-resin composite material impregnated with a thermosetting resin may be used.

1 is a schematic cross-sectional view showing a component built-in wiring board according to an embodiment of the present invention. The schematic sectional drawing which shows a ceramic capacitor. The top view which shows a ceramic capacitor. The expanded sectional view which shows the external electrode of a ceramic capacitor. Explanatory drawing which shows the manufacturing method of a component built-in wiring board. Explanatory drawing which shows the manufacturing method of a component built-in wiring board. Explanatory drawing which shows the manufacturing method of a component built-in wiring board. Explanatory drawing which shows the manufacturing method of a component built-in wiring board. Explanatory drawing which shows the manufacturing method of a component built-in wiring board. Explanatory drawing which shows the manufacturing method of a component built-in wiring board. Explanatory drawing which shows the manufacturing method of a component built-in wiring board. Explanatory drawing which shows the manufacturing method of a component built-in wiring board. Explanatory drawing which shows the manufacturing method of a component built-in wiring board. Explanatory drawing which shows the manufacturing method of a component built-in wiring board. Explanatory drawing which shows the manufacturing method of a component built-in wiring board. Explanatory drawing which shows the manufacturing method of the component built-in wiring board in a prior art. Explanatory drawing which shows the manufacturing method of the component built-in wiring board in a prior art.

  Hereinafter, an embodiment in which the present invention is embodied in a component built-in wiring board will be described in detail with reference to the drawings.

  As shown in FIG. 1, the component built-in wiring board 10 of the present embodiment is a wiring board for mounting an IC chip. The component built-in wiring board 10 includes a substantially rectangular core substrate 11, a first buildup layer 31 formed on the core main surface 12 (first main surface) of the core substrate 11, and a core back surface of the core substrate 11. 13 (second main surface) and a second buildup layer 32 formed on the second main surface.

  The first buildup layer 31 formed on the core main surface 12 of the core substrate 11 includes two resin interlayer insulating layers 33 and 35 made of a thermosetting resin (epoxy resin), a conductor layer 42 made of copper, It has the structure which laminated | stacked alternately. Terminal pads 44 are formed in an array at a plurality of locations on the surface of the second resin interlayer insulation layer 35. Further, the surface of the resin interlayer insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 having a rectangular flat plate shape.

  The region where each terminal pad 44 and each solder bump 45 is formed is an IC chip mounting region 23 on which the IC chip 21 can be mounted. Also, via conductors 43 are formed at a plurality of locations in the resin interlayer insulating layers 33 and 35. The via conductor 43 is electrically connected to the conductor layer 42 and the terminal pad 44.

  The second buildup layer 32 formed on the core back surface 13 of the core substrate 11 has substantially the same structure as the first buildup layer 31 described above. That is, the second buildup layer 32 has a structure in which two resin interlayer insulating layers 34 and 36 made of thermosetting resin (epoxy resin) and conductor layers 42 are alternately laminated. Via conductors 43 are formed at a plurality of locations in the first resin interlayer insulation layer 34, and the lower end of each via conductor 43 is a conductor layer 42 formed on the surface of the resin interlayer insulation layer 34. It is connected to the. Via conductors 43 are also formed at a plurality of positions in the second resin interlayer insulation layer 36, and the lower end of each via conductor 43 on the lower surface of the resin interlayer insulation layer 36 is interposed via via conductors 43. The BGA pads 48 electrically connected to the conductor layer 42 are formed in a lattice shape. The lower surface of the resin interlayer insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. A plurality of solder bumps 49 that can be electrically connected to a mother board (not shown) are disposed on the surface of the BGA pad 48. The wiring board 10 shown in FIG. 1 is mounted on a mother board (not shown) by each solder bump 49.

  The core substrate 11 of the present embodiment has a substantially rectangular plate shape in plan view of 25 mm length × 25 mm width × 0.9 mm thickness. The core substrate 11 is made of, for example, a resin insulating material (glass epoxy material) obtained by impregnating a glass cloth as a reinforcing material with an epoxy resin. In the core substrate 11, a plurality of through-hole conductors 16 are formed so as to penetrate the core main surface 12 and the core back surface 13. The through-hole conductor 16 connects and connects the core main surface 12 side and the core back surface 13 side of the core substrate 11. The inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin. Further, a conductor layer 41 made of copper is patterned on the core main surface 12 and the core back surface 13 of the core substrate 11, and each conductor layer 41 is electrically connected to the through-hole conductor 16. Furthermore, the core substrate 11 has one rectangular accommodation hole 90 in a plan view that opens at the center of the core main surface 12 and the center of the core back surface 13. That is, the accommodation hole 90 is a through hole. The accommodating hole 90 has chamfered portions with chamfer dimensions of 0.1 mm or more and 2.0 mm or less at the four corners.

  The ceramic capacitor 101 (built-in component) shown in FIGS. 2 and 3 is housed in the housing hole 90 in an embedded state. The ceramic capacitor 101 according to the present embodiment is a plate-like object having one capacitor main surface 102 (first component main surface), one capacitor back surface 103 (second component main surface), and four capacitor side surfaces 106. For example, it has a size of 12.0 mm long × 12.0 mm wide × 0.9 mm thick. The ceramic capacitor 101 is accommodated with the capacitor main surface 102 facing the same side as the core main surface 12 and the capacitor back surface 103 facing the same side as the core back surface 13. The ceramic capacitor 101 is disposed in a region immediately below the IC chip mounting region 23 in the core substrate 11. The area of the IC chip mounting region 23 (the area of the surface on which the surface connection terminals 22 are formed in the IC chip 21) is set to be smaller than the area of the capacitor main surface 102 of the ceramic capacitor 101. When viewed from the thickness direction of the ceramic capacitor 101, the IC chip mounting region 23 is located in the capacitor main surface 102 of the ceramic capacitor 101.

  As shown in FIG. 1, the gap 92 between the inner wall surface 91 of the accommodation hole 90 and the capacitor side surface 106 of the ceramic capacitor 101 is a resin made of a polymer material (in this embodiment, a thermosetting resin such as epoxy). It is filled with the filling part 93. The resin filling portion 93 has a function of fixing the ceramic capacitor 101 to the core substrate 11. Moreover, in order to relieve the thermal expansion difference with the ceramic capacitor 101, the resin filling part 93 may be added with ceramic powder such as silica. Moreover, in order to improve heat dissipation, metal powders, such as Cu, may be added. Ceramic capacitor 101 has a substantially square shape in plan view, and has chamfered portions with chamfering dimensions of 0.55 mm or more (in this embodiment, chamfering dimensions of 0.6 mm) at four corners. Accordingly, when the ceramic capacitor 101 is built in the wiring board 10 or when the resin filling portion 93 is deformed due to a temperature change, stress concentration on the corner portion of the ceramic capacitor 101 can be reduced. Can be prevented.

  As shown in FIGS. 1 to 3, the ceramic capacitor 101 of the present embodiment is a so-called via array type ceramic capacitor. The ceramic sintered body 104 constituting the ceramic capacitor 101 has a structure in which power supply internal electrode layers 141 (internal electrodes) and ground internal electrode layers 142 (internal electrodes) are alternately stacked via ceramic dielectric layers 105. have. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric between the power supply internal electrode layer 141 and the ground internal electrode layer 142. Each of the power supply internal electrode layer 141 and the ground internal electrode layer 142 is a layer formed mainly of nickel, and is disposed in every other layer in the ceramic sintered body 104.

  As shown in FIGS. 1 and 2, a large number of via holes 130 are formed in the ceramic sintered body 104. These via holes 130 penetrate the ceramic sintered body 104 in the thickness direction and are arranged in an array over the entire surface of the ceramic sintered body 104. In each via hole 130, a plurality of in-capacitor via conductors 131 and 132 that communicate between the capacitor main surface 102 and the capacitor back surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. In this embodiment, since the diameter of the via hole 130 is set to about 100 μm, the diameter of the via conductors 131 and 132 in the capacitor is also set to about 100 μm. Each power supply capacitor internal via conductor 131 passes through each power supply internal electrode layer 141 and electrically connects them to each other. Each ground capacitor via conductor 132 passes through each ground internal electrode layer 142 and electrically connects them to each other. Each power source capacitor via conductor 131 and each ground capacitor inner via conductor 132 are arranged in an array as a whole.

  2 and 3, on the capacitor main surface 102 of the ceramic sintered body 104, a plurality of main surface side power supply external electrodes 111 and a plurality of main surface side ground externals are provided as first surface electrodes. An electrode 112 is provided. Each of the external electrodes 111 and 112 has a substantially circular shape when viewed from a direction perpendicular to the capacitor main surface 102 (part thickness direction), and has a diameter of 300 μm (see FIG. 3). The main surface side power external electrode 111 is directly connected to the end surface of the plurality of power source capacitor internal via conductors 131 on the capacitor main surface 102 side, and the main surface side ground external electrode 112 is connected to a plurality of ground ground electrodes. The internal via conductor 132 is directly connected to the end surface of the capacitor main surface 102 side.

  Further, as shown in FIG. 2, a plurality of back-side power external electrodes 121 and a plurality of back-side ground external electrodes 122 are provided as second surface electrodes on the capacitor back surface 103 of the ceramic sintered body 104. It has been. Each of the external electrodes 121 and 122 has a substantially circular shape when viewed from a direction perpendicular to the capacitor back surface 103, and has a diameter of 300 μm. The back-side power external electrode 121 is directly connected to the end surface on the capacitor back surface 103 side of the plurality of power-source capacitor via conductors 131, and the back-side ground external electrode 122 is a plurality of ground-capacitor vias. The conductor 132 is directly connected to the end surface on the capacitor back surface 103 side. Therefore, the power supply external electrodes 111 and 121 are electrically connected to the power supply capacitor internal via conductor 131 and the power supply internal electrode layer 141, and the ground external electrodes 112 and 122 are connected to the ground capacitor internal via conductor 132 and the ground internal electrode. Conductive to layer 142.

  As shown in FIG. 4, the external electrodes 111, 112, 121, 122 are a metallized metal layer 151 mainly composed of nickel and a copper plating layer 152 (conductor layer) provided so as to cover the metal layer 151. And a protruding conductor 153 projecting on the copper plating layer 152. Each protruding conductor 153 is a cylindrical conductor (copper post) formed by copper plating. The diameter of each protruding conductor 153 is set to be smaller than the diameter (about 300 μm) of the external electrodes 111, 112, 121, 122 and larger than the diameter (about 100 μm) of the via conductors 131, 132 in the capacitor. In this embodiment, it is set to about 200 μm. Further, the height of the protruding conductor 153 is set to 50 μm or more and 200 μm or less.

  As shown in FIG. 1, in the component built-in wiring board 10, the protruding conductors 153 of the external electrodes 111 and 112 in the ceramic capacitor 101 are interposed via a conductor layer 50 (wiring layer) formed on the surface of the resin filling portion 93. And directly connected to the conductor layer 41 on the core substrate 11. The conductor layer 50 is formed so as to cover the resin filling portion 93 that fills the gap between the ceramic capacitor 101 and the core substrate 11.

  The protruding conductors 153 of the external electrodes 111, 112 on the capacitor main surface 102 side are via the conductor layers 41, 42, 50, via conductors 43, terminal pads 44, solder bumps 45, and surface connection terminals 22 of the IC chip 21. , And electrically connected to the IC chip 21. On the other hand, the protruding conductors 153 of the external electrodes 121 and 122 on the capacitor back surface 103 side are electrodes provided on a mother board (not shown) through the conductor layers 41, 42 and 50, the via conductors 43, the BGA pads 48 and the solder bumps 49. Is electrically connected.

  For example, when energization is performed from the mother board side through the external electrodes 121 and 122 and a voltage is applied between the power supply internal electrode layer 141 and the ground internal electrode layer 142, for example, positive charges accumulate in the power supply internal electrode layer 141. For example, negative charges accumulate in the ground internal electrode layer 142. In the ceramic capacitor 101, the via-conductor 131 for power supply capacitor and the via-conductor 132 for ground capacitor are alternately arranged adjacent to each other, and the via-conductor 131 for power-supply capacitor and the via-conductor 132 for ground capacitor are connected to each other. The directions of the flowing currents are set to be opposite to each other. Thereby, the inductance component is reduced.

  Next, a method for manufacturing the ceramic capacitor 101 of the present embodiment will be described.

  First, a green sheet of a dielectric material mainly composed of barium titanate is formed, and a nickel paste for internal electrode layers is screen-printed on the green sheet and dried. As a result, a power internal electrode portion that will later become the power internal electrode layer 141 and a ground internal electrode portion that will be the ground internal electrode layer 142 are formed. Next, the green sheets with the power supply internal electrode portions and the green sheets with the ground internal electrode portions are alternately stacked, and each green sheet is integrated by applying a pressing force in the sheet stacking direction. To form a green sheet laminate.

  Further, a number of via holes 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via hole 130 using a paste press-fitting and filling device (not shown). Next, a nickel paste for an electrode is printed on the upper surface of the green sheet laminate, and the metallized metal layer 151 of the external electrodes 111 and 112 is formed so as to cover the upper end surfaces of the respective conductor portions on the upper surface side of the green sheet laminate. To do. Also, a nickel paste for an electrode is printed on the lower surface of the green sheet laminate, and the metallized metal layer 151 of the external electrodes 121 and 122 is formed so as to cover the lower end surfaces of the respective conductor portions on the lower surface side of the green sheet laminate. .

  Thereafter, the green sheet laminate is dried to solidify each metallized metal layer 151 to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104. Next, on the capacitor main surface 102 and the capacitor back surface 103 of the obtained ceramic sintered body 104, copper plating is performed on each metallized metal layer 151 to be the external electrodes 111, 112, 121, 122, and each metallized A copper plating layer 152 (thickness: 15 μm) is formed on the metal layer 151.

  Further, a photoresist material having an opening (inner diameter 200 μm) at a predetermined position is laminated on the capacitor main surface 102 and the capacitor back surface 103 of the ceramic sintered body 104. These openings are formed by exposure and development, and a part of the surface of the external electrodes 111, 112, 121, 122 is exposed. Then, after performing electrolytic copper plating on the external electrodes 111, 112, 121, and 122 through the photoresist material, the photoresist material is removed. As a result, the protruding conductor 153 is formed on the external electrodes 111, 112, 121, 122, and the ceramic capacitor 101 is completed.

  Next, a method for manufacturing the component built-in wiring board 10 of the present embodiment will be described.

  First, a copper clad laminate having a copper foil (thickness of about 50 μm) attached to both surfaces of a base material is prepared. And a drilling process is performed using a drill machine, and the through-hole (illustration omitted) which penetrates the front and back of a copper clad laminated board is previously formed in the predetermined position. And the through-hole conductor 16 is formed in a through-hole by performing the electroless copper plating and the electrolytic copper plating with respect to the inner surface of the through-hole of a copper clad laminated board. Thereafter, the cavity of the through-hole conductor 16 is filled with an insulating resin material (epoxy resin) to form the closing body 17.

  Next, the copper-clad laminate with the through-hole conductors 16 is drilled using a router to form through holes that serve as the receiving hole portions 90 at predetermined positions, and an intermediate product of the core substrate 11 is obtained. (See FIG. 5). The intermediate product of the core substrate 11 is a multi-piece core substrate having a structure in which a plurality of regions to be the core substrate 11 are arranged vertically and horizontally along the plane direction.

  As described above, the core substrate 11 through which the accommodation hole 90 is formed is prepared, and the ceramic capacitor 101 as a built-in component is prepared (preparation process).

  After the preparatory step, as shown in FIG. 6, an insulating layer 161 (by attaching a sheet-like buildup material mainly composed of a thermosetting epoxy resin as a resin material to the core back surface 13 side of the core substrate 11. (Second main surface side insulating layer) is formed, and one opening of the accommodation hole 90 is closed by the insulating layer 161 (second main surface side insulating layer forming step). Here, the build-up material is heated to some extent to have a state of having an adhesive force on the surface.

  Thereafter, as shown in FIG. 7, the ceramic capacitor 101 is housed in the housing hole 90 by mounting the ceramic capacitor 101 on the insulating layer 161 (housing step). In the present embodiment, the ceramic capacitor 101 is mounted on the insulating layer 161 so that the leading end portions of the protruding conductors 153 in the external electrodes 121 and 122 are embedded in the insulating layer 161. As described above, the ceramic capacitor 101 is surely temporarily fixed by embedding the tip of the protruding conductor 153 in the insulating layer 161. Here, the tip of the protruding conductor 153 is embedded in the insulating layer 161, but the protruding conductor 153 is not necessarily embedded in the insulating layer 161. For example, the tip surface of the protruding conductor 153 may be brought into contact with the surface of the insulating layer 161 and the ceramic capacitor 101 may be temporarily fixed by the adhesive force of the insulating layer 161.

  Next, an insulating layer 162 that bonds a sheet-like build-up material mainly composed of a thermosetting epoxy resin as a resin material to the core main surface 12 side of the core substrate 11 and closes the opening above the accommodation hole 90 is formed. After the formation, it is heated under pressure with a vacuum press hot press (not shown) under vacuum. At this time, as shown in FIG. 8, the insulating layers 161 and 162 on the upper and lower surfaces are caused to flow, and a gap between the inner wall surface 91 of the accommodation hole 90 and the side surface 106 of the ceramic capacitor 101 is partly formed (resin filling portion 93). 92 is filled and the ceramic capacitor 101 is fixed to the core substrate 11 (gap filling step and first main surface side insulating layer forming step).

  Thereafter, the insulating layer 162 on the core main surface 12 side of the core substrate 11 is polished using, for example, a belt sander device to expose the protruding conductors 153 of the external electrodes 111 and 112 of the ceramic capacitor 101 (see FIG. 9). . Similarly, the insulating layer 161 on the core back surface 13 side of the core substrate 11 is polished to expose the protruding conductors 153 of the external electrodes 121 and 122 of the ceramic capacitor 101 (double-side polishing step). At this time, the insulating layers 161 and 162 are completely removed on the core main surface 12 and the core back surface 13 of the core substrate 11, and a part of the copper foil 163 on the substrate surface is polished, whereby the core substrate 11. The copper foil 163 is exposed.

  After the double-side polishing step, electroless copper plating and electrolytic copper plating are applied to the entire surface of the core main surface 12 and the core back surface 13 of the core substrate 11 in which the ceramic capacitor 101 is embedded in the accommodation hole 90 to form the entire plating layer 165. (See FIG. 10). After that, as shown in FIG. 11, patterning is performed by a subtractive method to form a conductor layer 50 (wiring layer) (patterning step). Specifically, a dry film is laminated on the surface of the core substrate 11 (entire plating layer 165), and an etching resist having a predetermined pattern is formed by exposing and developing the dry film. In this state, patterning by etching is performed on the entire surface plating layer 165 of the core main surface 12 and the core back surface 13 of the core substrate 11. As a result, the conductor layer 41 connected to the through-hole conductor 16 and the like is formed on the core main surface 12 and the core back surface 13 of the core substrate 11, and the protruding conductor 153 (external conductor) of the ceramic capacitor 101 is formed on the surface of the resin filling portion 93. A conductor layer 50 (wiring layer) connected to the electrodes 111, 112, 121, 122) is formed.

Then, the first buildup layer 31 is formed on the core main surface 12 and the second buildup layer 32 is formed on the core back surface 13 based on a conventionally known method. Specifically, on the core main surface 12 side and the core back surface 13 side of the core substrate 11, sheet-like resin interlayer insulating layers 33 and 34 made of a thermosetting resin such as epoxy are attached, and the resin interlayer insulating layer 33, 34 is cured (precured) to some extent (see FIG. 12). Then, via holes 167 are formed at predetermined positions of the resin interlayer insulating layers 33 and 34 by performing laser processing using, for example, an excimer laser, a UV laser, a CO ₂ laser, or the like (see FIG. 13). Next, a desmear process for removing smear in each via hole 167 is performed using an etching solution such as a potassium permanganate solution. As the desmear process, in addition to treatment with an etchant, for example it may perform processing of plasma ashing using O ₂ plasma.

  After the desmear process, via conductors 43 are formed in each via hole 167 by performing electroless copper plating and electrolytic copper plating according to a conventionally known method. Further, the conductor layer 42 is patterned on the resin interlayer insulating layers 33 and 34 by performing etching by a conventionally known method (for example, a semi-additive method) (see FIG. 14). The other resin interlayer insulation layers 35 and 36 and the pads 44 and 48 are also formed by the same method as the resin interlayer insulation layers 33 and 34 and the conductor layer 42 described above, and are formed on the resin interlayer insulation layers 33 and 34. Laminate.

  Next, solder resists 37 and 38 are formed by applying and curing a photosensitive epoxy resin on the resin interlayer insulation layers 35 and 36. Thereafter, exposure and development are performed with a predetermined mask placed, and the openings 40 and 46 are patterned in the solder resists 37 and 38 (see FIG. 15). Further, solder bumps 45 are formed on the terminal pads 44 and solder bumps 49 are formed on the BGA pads 48. In this state, it can be grasped that the product area to be the component built-in wiring board 10 is a multi-piece wiring board in which a plurality of product regions are arranged vertically and horizontally along the plane direction. Further, when the multi-piece wiring board is divided, a large number of component built-in wiring boards 10 (see FIG. 1), which are individual products, can be obtained simultaneously.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the present embodiment, in the housing step, the ceramic capacitor 101 is temporarily fixed in the housing hole 90 using a build-up material of the insulating layer 161 that will remain as a part of the wiring board 10 (resin filling portion 93) later. Has been. If it does in this way, since it is not necessary to fix the capacitor | condenser 101 using the adhesive tape 211 like a prior art, manufacturing cost can be held down. Further, in the double-side polishing step, the insulating layer 162 on the core main surface 12 side and the insulating layer 161 on the core back surface 13 side are polished, and the protruding conductors 153 of the external electrodes 111, 112, 121, 122 are exposed. In the patterning step, the wiring pattern of the conductor layer 50 can be directly connected to the external electrodes 111, 112, 121, 122 of the ceramic capacitor 101 by patterning the conductor layer 50. In this case, as compared with the case of connecting to each electrode 207, 208 by the via conductor 217 as in the prior art, the degree of freedom of the wiring pattern is increased and the electrical connection to the ceramic capacitor 101 can be performed well. It is possible to reduce the number of insulating layers in the buildup layers 31 and 32. Furthermore, when only one side is polished as in the prior art, the core substrate 204 may be warped due to the extension of the conductor layer on one side, but in the present invention, both sides are similarly polished. Warpage of the core substrate 11 due to elongation of the conductor layer (copper foil 163) on the main surface 12 side and the core back surface 13 side can be prevented.

  (2) In the gap filling process of the present embodiment, part of the resin material constituting the insulating layer 162 on the core main surface 12 side and part of the resin material constituting the insulating layer 161 on the core back surface 13 side are caused to flow. Thus, the gap 92 between the inner wall surface 91 of the accommodation hole 90 and the ceramic capacitor 101 is filled. In this case, the gap 92 can be reliably filled as compared with the case where the resin material of the insulating layer 212 only on the core main surface 201 side is made to flow as in the prior art.

  (3) In the case of the present embodiment, the plurality of external electrodes 111, 112, 121, 122 of the ceramic capacitor 101 are formed by forming protruding conductors 153 on the conductor layers (metallized metal layer 151 and copper plating layer 152). Become. As described above, when the protruding conductor 153 having a thickness is provided on each of the external electrodes 111, 112, 121, and 122, even if the ceramic capacitor 101 is displaced in the thickness direction in the accommodation hole 90, the protrusion is formed in the polishing process. The positional deviation can be adjusted by cutting the conductor 153.

  (4) In the housing step of the present embodiment, the ceramic capacitor 101 is placed on the insulating layer 161 so that the tips of the plurality of external electrodes 121 and 122 on the capacitor back surface 103 side are embedded in the insulating layer 161 on the core back surface 13 side. It is installed. In this way, it is possible to reliably prevent the displacement of the ceramic capacitor 101 in the accommodation hole 90.

  (5) In the present embodiment, the protruding conductor 153, the conductor layer 50 formed on the protruding conductor 153, and the via conductor 43 formed on the conductor layer 50 are both made of copper. In this case, electrical connection between each external electrode 111, 112, 121, 122 of the ceramic capacitor 101 and each conductor layer 41, 42, 50 can be reliably performed.

  (6) In the component built-in wiring board 10 of the present embodiment, the conductor layer 50 is formed so as to cover the portion corresponding to the gap 92 on the resin filling portion 93. In this way, in the component built-in wiring board 10, the resin filling portion 93 that fills the gap 92 expands due to heat applied at the time of manufacturing the substrate, but the resin filling portion 93 is pressed by the conductor layer 50 that is harder than the resin filling portion 93. In addition, it is possible to reliably suppress the warpage of the wiring substrate 10 and the wave of the substrate surface.

  (7) In the component built-in wiring board 10 of the present embodiment, a via array type ceramic capacitor 101 is housed in the housing hole 90 as a built-in component. In this ceramic capacitor 101, since the plurality of via conductors 131 and 132 are arranged in an array as a whole, the inductance of the ceramic capacitor 101 can be reduced, and high-speed power supply for noise absorption and power fluctuation smoothing can be achieved. Is possible.

  (8) In the component built-in wiring board 10 of the present embodiment, since the ceramic capacitor 101 is disposed immediately below the IC chip 21 mounted in the IC chip mounting region 23, the wiring connecting the ceramic capacitor 101 and the IC chip 21 And the increase of the inductance component of the wiring is prevented. Therefore, the switching noise of the IC chip 21 due to the ceramic capacitor 101 can be reliably reduced, and the power supply voltage can be reliably stabilized. In addition, since noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction.

  (9) In the component built-in wiring board 10 of the present embodiment, since the IC chip mounting area 23 is located in the area directly above the ceramic capacitor 101, the IC chip 21 mounted in the IC chip mounting area 23 is It is supported by a ceramic capacitor 101 having high rigidity and a small coefficient of thermal expansion. Therefore, in the IC chip mounting area 23, the first buildup layer 31 is not easily deformed, so that the IC chip 21 mounted in the IC chip mounting area 23 can be supported more stably. Therefore, it is possible to prevent the IC chip 21 from cracking and poor connection due to large thermal stress. Therefore, the IC chip 21 is considered to be a large IC chip of 10 mm square or more, which has a large stress (strain) due to a difference in thermal expansion and is greatly affected by thermal stress, and has a large calorific value and severe thermal shock during use. A low-k (low dielectric constant) IC chip can be used.

  In addition, you may change embodiment of this invention as follows.

  In the above embodiment, the gap filling process and the first main surface side insulating layer forming process are performed in the same process, but the present invention is not limited to this. For example, after the accommodating step, after performing the gap filling step of filling the gap 92 between the inner wall surface 91 of the accommodating hole 90 and the side surface 106 of the ceramic capacitor 101 with the filling resin material, the insulating layer is formed on the core main surface 12 side. The first main surface side insulating layer forming step of forming 162 and closing the opening above the accommodation hole 90 may be performed.

  In the ceramic capacitor 101 of the above embodiment, the circular external electrodes 111, 112, 121, 122 are provided, but the electrode shape may be changed to other shapes such as a substantially rectangular shape. . Further, dummy electrodes may be provided on the capacitor main surface 102 and the capacitor back surface 103 so as to surround the periphery of the external electrodes 111, 112, 121, and 122.

  In the above embodiment, the protruding conductors 153 constituting the external electrodes 111, 112, 121, and 122 have a cylindrical shape. However, the present invention is not limited to this, and other shapes such as a triangular prism shape and a quadrangular prism shape are possible. It may be a shape. Further, the protruding conductor 153 has a columnar shape in which the diameter of the top and the diameter of the bottom are equal, but may be a trapezoidal conductor having a different diameter from the top.

  In the above embodiment, the package form of the component built-in wiring board 10 is BGA (ball grid array). However, the package form is not limited to BGA, and is, for example, PGA (pin grid array) or LGA (land grid array). May be.

DESCRIPTION OF SYMBOLS 10 ... Component built-in wiring board 11 ... Core board 12 ... Core main surface as 1st main surface 13 ... Core back surface as 2nd main surface 50 ... Conductor layer which comprises a wiring layer 90 ... Accommodating hole part 91 ... Accommodating hole part The inner wall surface 92 ... the gap 101 ... the ceramic capacitor as a built-in component 102 ... the capacitor main surface as the first component main surface 103 ... the capacitor back surface as the second component main surface 105 ... the ceramic dielectric layer 111 as the dielectric layer ... Main surface side power external electrode 112 as first surface electrode 112. Main surface side ground external electrode 121 as first surface electrode 121. Back surface side external power electrode 122 as second surface electrode 122. Back side ground external electrode 131... Capacitor via conductor for power supply as via conductor in capacitor 132... Ground capacitor as via conductor in capacitor Internal via conductor 141... Internal electrode layer for power supply as internal electrode 142. Internal electrode layer for ground as internal electrode 151. Metallized metal layer constituting conductor layer 152. Copper plating layer constituting conductor layer 153. Conductor 161 ... Insulating layer as second main surface side insulating layer 162 ... Insulating layer as first main surface side insulating layer

Claims (7)

A built-in component having a first component main surface on which a plurality of first surface electrodes are arranged and a second component main surface on which a plurality of second surface electrodes are arranged is prepared, and the first main surface and the second main surface are prepared. A preparation step of preparing a core substrate having an accommodation hole portion that is open through the first main surface and the second main surface;
After the preparation step, a build-up material mainly composed of a resin material is joined to the second main surface side of the core substrate to form a second main surface side insulating layer and one of the accommodation holes. A second main surface side insulating layer forming step of closing the opening;
After the second main surface side insulating layer forming step, a housing step of housing the built-in component in the housing hole by mounting the built-in component on the second main surface side insulating layer;
After the housing step, a gap filling step of filling a gap between the inner wall surface of the housing hole and the built-in component with a filling resin material;
After the housing step, the buildup material is joined to the first main surface side of the core substrate, thereby forming a first main surface side insulating layer and closing the other opening of the housing hole. 1 main surface side insulating layer forming step;
After the first main surface side insulating layer forming step, the first main surface side insulating layer is polished to expose the plurality of first surface electrodes, and the second main surface side insulating layer is polished. A double-side polishing step for exposing the plurality of second surface electrodes;
And a patterning step of forming a wiring layer by performing patterning after performing plating on the first main surface side insulating layer and the second main surface side insulating layer after the double-side polishing step. A method of manufacturing a component built-in wiring board   In the gap filling step, the gap is filled by flowing part of the resin material constituting the first main surface side insulating layer and part of the resin material constituting the second main surface side insulating layer. The method of manufacturing a component built-in wiring board according to claim 1.   3. The component built-in wiring board according to claim 1, wherein the plurality of first surface electrodes and the plurality of second surface electrodes in the built-in component are formed by forming a protruding conductor on a conductor layer. Manufacturing method.   In the housing step, the built-in component is mounted on the second main surface side insulating layer so that at least a part of the plurality of second surface electrodes is embedded in the second main surface side insulating layer. The method for manufacturing a component built-in wiring board according to claim 3.   The said protruding conductor, the conductor layer formed on the said protruding conductor through the said patterning process, and the via conductor formed on the said conductor layer are both made of copper, The Claim 3 or 4 characterized by the above-mentioned. Method of manufacturing a component built-in wiring board.   2. The patterning step includes forming a conductor layer on the first main surface side insulating layer and the second main surface side insulating layer so as to cover a portion corresponding to the gap. 6. A method of manufacturing a component built-in wiring board according to any one of items 1 to 5. The built-in component is
A dielectric layer;
A plurality of internal electrodes stacked via the dielectric layers;
A plurality of via conductors in the capacitor connected to the plurality of internal electrodes and connected to the plurality of first surface electrodes and the plurality of second surface electrodes at both ends; 7. The method of manufacturing a component built-in wiring board according to claim 1, wherein the capacitor is a via array type capacitor arranged in an array as a whole.

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