JP2012141231A - Failure diagnosis system, semiconductor integrated circuit, and failure diagnosis method - Google Patents

Abstract

To diagnose a failure by identifying a signal causing a failure from a plurality of input signals using a fixed number of output terminals.
A first selection circuit that selects and outputs one of a first input test signal and a first expected value that is an expected value of the first input test signal; A first compression circuit having a first logic circuit that outputs a match determination result between the input test signal and the output signal from the first selection circuit to an output terminal; When the first output result from the output terminal when the input test signal is selected indicates an error, the first selection circuit is caused to select the first expected value, and the first output result indicates an error. As a result, when the second output result from the output terminal when the first expected value is selected by the first selection circuit indicates normal, the first input test signal is identified as an error, If the output result of 2 indicates an error, the second input test signal is identified as an error. And a 択制 control circuit.
[Selection] Figure 1

Description

  The present invention relates to a failure diagnosis system, a semiconductor integrated circuit, and a failure diagnosis method, and more particularly to a failure diagnosis system, a semiconductor integrated circuit, and a semiconductor integrated circuit for diagnosing a failure by identifying a signal causing a failure from a plurality of input signals. The present invention relates to a failure diagnosis method.

  The logic on one chip is increasing due to the high integration and large scale of LSI (Large Scale Integration). Along with this, in the field of design for testability (DFT: Design For Test), it is essential to apply a compressed scan test system for the purpose of reducing test costs.

  The compressed scan test system is a means for reducing the scan shift cycle by dividing the scan chain inside the LSI into a large number. In the compressed scan test system, simply increasing the number of divisions requires a large number of external observation terminals. Therefore, it is common to insert a decompressor (Decompressor) that expands scan data into an internal scan chain on the scan input data side, and a compressor (Compactor) that compresses scan test results on the output data side. This makes it possible to realize a compressed scan test without increasing the number of external observation terminals even when the number of internal chains becomes large.

  In the compressed scan test, the observation value of the internal scan chain is compressed by the compressor and observed at the external terminal, so it may be difficult to identify the scan FF that has observed the failure internally from the observation result at the external observation terminal. It is a problem. Therefore, it is necessary to identify which scan FF has observed the failure, and a technique capable of performing it in a short time.

  Japanese Patent Application Laid-Open No. 2004-151820 discloses a technique for preventing a failure response from being overlooked when a plurality of failures are observed inside an LSI in a compression scan test. By using the technique according to Patent Document 1, failure diagnosis can be performed when there is one failure.

In Patent Document 1, when there are p external observation terminals and q internal scan chains satisfying the following expression (1), p EXORs (or EXNORs) are mounted in the compressor. In this technique, each EXOR is connected so that the outputs (SO1 to SOq) of the internal scan chain are sparse with each other, thereby enabling failure diagnosis when the number of failures in the LSI is 1.
q ≦ 2 ^ p−1 (1)

  FIG. 9 is a block diagram showing a configuration of the compressor 900 according to Patent Document 1. As shown in FIG. The compressor 900 includes exclusive OR circuits EOR1 to EOR3. The compressor 900 inputs the seven scan chain outputs SO1 to SO7 received from the outside to the exclusive OR circuits EOR1 to EOR3 as shown in FIG. 9, and inputs the exclusive OR circuits EOR1 to EOR3. The respective output signals are output to the external observation terminals PO1 to PO3. As a result, when a failure is propagated from any one of the scan chain outputs SO1 to SO7, the combinations of responses of the external observation terminals PO1 to PO3 at that time are all different, so that the failure propagation path can be specified.

  FIG. 10 is a diagram for explaining the relationship of fault propagation according to Patent Document 1. In FIG. That is, when the output values of the external observation terminals (PO1, PO2, PO3) indicate (0, 0, 0), it can be specified that none of the scan chain outputs SO1 to SO7 has failed. Further, when the output value of the external observation terminal (PO1, PO2, PO3) indicates (1, 0, 0), it can be identified from the scan chain output SO1 that a failure has propagated. Similarly, when the output value of the external observation terminals (PO1, PO2, PO3) indicates (0, 1, 0), a failure has propagated from the scan chain output SO2, and the external observation terminals (PO1, PO2, PO3) When the output value of (1) indicates (1, 1, 0), a failure has propagated from the scan chain output SO3, and the output values of the external observation terminals (PO1, PO2, PO3) indicate (0, 0, 1). In this case, the failure is propagated from the scan chain output SO4, and if the output value of the external observation terminals (PO1, PO2, PO3) indicates (1, 0, 1), the failure is propagated from the scan chain output SO5. When the output values of the external observation terminals (PO1, PO2, PO3) indicate (0, 1, 1), a failure has propagated from the scan chain output SO6, and the external observation terminals (PO1, PO2, PO3) If the output value indicating the (1,1,1), it specified that the scan chain output SO7 failure has propagated. As described above, in Patent Document 1, since the response of the external observation terminal is uniquely determined according to the EXOR input signal value, the failure observation path can be specified.

  In Patent Document 2, two pairs of scan chains are constructed, and only one of them is always scan-tested. At that time, the expected value of the test target chain is stored in the other to create an external expected value. A technique that can facilitate the above is disclosed. Patent Document 3 discloses a technology that configures a Compactor that uses an error detection mechanism based on a Hamming code and that can identify a scan chain in which FAIL is propagated using the values of information bits and check bits. Yes. Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique that can implement a high-speed scan test even with an inexpensive tester without using a high-precision tester.

JP 2005-274500 A JP-A-10-111346 JP 2004-012420 A JP 2004-271438 A

  Patent Document 1 discloses that when only one failure is inherent in an LSI, p external observation terminals satisfying the above-described expression (1) with respect to the number of internal scan chains q, and an EXOR in the compressor. (Or EXNOR) is implemented, and fault diagnosis is made possible by making the inputs of each EXOR sparse. In the compressed scan test, the number of internal scan chains is increased as much as possible, and the scan chain length per one is shortened to reduce the test cycle.

  However, Patent Document 1 has a problem that the number of external observation terminals increases as the number of internal scan chains increases. For example, when q = 100, p is minimum “7”. In other words, seven external observation terminals are required. Further, when q = 200, p is minimum “8”. That is, eight external observation terminals are required. Further, when q = 400, p is minimum “9”. That is, nine external observation terminals are required. Depending on the circuit scale of the LSI targeted for failure diagnosis, it is necessary to replace a device such as a tester that performs failure diagnosis with a higher-function device. Further, in recent years, since LSIs are highly integrated and large-scale, the number of external observation terminals increases, making it difficult to deal with equipment for fault diagnosis.

  The technique according to Patent Document 2 is a technique for determining whether or not there is a defect in the target scan chain from the result of one external observation terminal. Therefore, in order to find out where the fault is in the internal scan chain, the two scan chains that are paired cannot be tested in parallel, so the test time becomes longer. Note that the technique according to Patent Document 3 requires a large number of external observation terminals as the number of internal scan chains increases, as in Patent Document 1. Further, the technique according to Patent Document 4 is not intended for the compression scan test.

  The failure diagnosis system according to the first aspect of the present invention selects and outputs either the first input test signal or the first expected value that is the expected value of the first input test signal. A first compression circuit comprising: a first selection circuit; a second input test signal; and a first logic circuit that outputs a match determination result of the output signal from the first selection circuit to an output terminal. And a selection control circuit that controls selection in the first selection circuit in accordance with an output result from the output terminal, wherein the selection control circuit is configured to output the first input by the first selection circuit. If the first output result from the output terminal when the test signal is selected indicates an error, the first selection circuit is caused to select the first expected value, and the first output result Indicates that an error has occurred by the first selection circuit. When the second output result from the output terminal when the first expected value is selected indicates normality, the first input test signal is identified as an error, and the second output result indicates an error. When indicated, the second input test signal is identified as an error.

  A semiconductor integrated circuit according to a second aspect of the present invention is a semiconductor integrated circuit used in the failure diagnosis system according to the first aspect, and includes a first input test signal and the first input test signal. Match determination result of the first selection circuit that selects and outputs one of the first expected values that are expected values, the second input test signal, and the output signal from the first selection circuit And a first logic circuit that outputs to the output terminal.

  The failure diagnosis method according to the third aspect of the present invention uses the first input test signal out of the first input test signal and the first expected value that is the expected value of the first input test signal. Select and output, and output a match determination result between the second input test signal and the selected first input test signal to the output terminal, and the first output result from the output terminal indicates an error If the first expected value is selected and the second output result from the output terminal when the first expected value is selected indicates normal, the first input test signal is An error is specified, and when the second output result indicates an error, the second input test signal is specified as an error.

  According to the first to third aspects of the present invention described above, when one of the first input test signal and the second input test signal is an error, the output result is output twice using one output terminal. By determining, a signal that is an error can be specified. That is, in the first determination, when the first selection circuit selects the first input test signal, the first compression circuit determines whether the first input test signal and the second input test signal match. I do. If the coincidence determination result (first output result) indicates an error, one of the signals is an error. Therefore, here, the first selection circuit replaces the first input test signal with the first expectation. Select a value. Therefore, in the second determination, the first compression circuit determines whether or not the first expected value matches the second input test signal. When the coincidence determination result (second output result) indicates normal, it indicates that both the first expected value and the second input test signal are normal. That is, the first input test signal and the first expected value are different from each other. Therefore, the selection control circuit specifies that the first input test signal is an error. On the contrary, when the second output result indicates an error, it indicates that either the first expected value or the second input test signal is an error. Here, since the first expected value is normal, the selection control circuit specifies that the second input test signal is an error.

  According to the present invention, there are provided a failure diagnosis system, a semiconductor integrated circuit, and a failure diagnosis method for diagnosing a failure by identifying a signal causing a failure from a plurality of input signals using a fixed number of output terminals. be able to.

It is a block diagram which shows the structure of the failure diagnosis system concerning Embodiment 1 of this invention. It is a flowchart which shows the flow of a process of the failure diagnosis method concerning Embodiment 1 of this invention. It is a block diagram which shows the structure of the failure diagnosis system concerning Embodiment 2 of this invention. It is a flowchart which shows the flow of a process of the failure diagnosis method concerning Embodiment 2 of this invention. It is a flowchart which shows the flow of a process of the failure diagnosis method concerning Embodiment 2 of this invention. It is a block diagram which shows the structure of the compression scan test system concerning Embodiment 3 of this invention. It is a flowchart which shows the flow of a failure diagnostic process of the compression scan test concerning Embodiment 3 of this invention. It is a flowchart which shows the flow of the failure location tracking process concerning Embodiment 3 of this invention. It is a block diagram which shows the structure of the compressor concerning related technology. It is a figure for demonstrating the relationship of the failure propagation concerning related technology.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description will be omitted as necessary for the sake of clarity.

<Embodiment 1 of the Invention>
FIG. 1 is a block diagram showing a configuration of a failure diagnosis system 101 according to the first embodiment of the present invention. The failure diagnosis system 101 is a system for diagnosing a failure by specifying which of the first input test signal SI1 and the second input test signal SI2 is a signal indicating an error based on the failure. . The first input test signal SI1 and the second input test signal SI2 may be signals generated in the failure diagnosis system 101 or signals input from the outside of the failure diagnosis system 101.

  For example, it is assumed that the failure diagnosis system 101 includes a failure diagnosis target circuit (including a plurality of logic circuits and flip-flops). A plurality of flip-flops in the failure diagnosis target circuit are connected in series for a scan test and output as a scan chain output signal. At this time, the first input test signal SI1 and the second input test signal SI2 may be output signals output as a result of a scan test for two scan chains. Alternatively, the first input test signal SI1 and the second input test signal SI2 may be signals that have passed through a predetermined circuit instead of the output signal itself from the scan chain.

  Further, the failure diagnosis system 101 can target an external circuit that outputs two signals as a failure diagnosis target. In this case, as the first input test signal SI1 and the second input test signal SI2, two output signals output as a result of a predetermined test in the external circuit may be used. Further, the first input test signal SI1 and the second input test signal SI2 may be signals indicating at least one of “HIGH” and “LOW” or “0” and “1”, for example. .

  The failure diagnosis system 101 includes a first compression circuit 10 and a selection control circuit 40. The first compression circuit 10 includes a first selection circuit 11, a first logic circuit 12, and an output terminal 13.

  The first selection circuit 11 selects and outputs either the first input test signal SI1 or the first expected value SE1 that is the expected value of the first input test signal SI1. The first logic circuit 12 outputs a match determination result between the second input test signal SI 2 and the output signal from the first selection circuit 11 to the output terminal 13. Here, the first logic circuit 12 determines whether or not the values of the two input signals match. Then, the first logic circuit 12 outputs the coincidence determination result to the output terminal 13 as one signal. The match determination result may be, for example, a value indicating normality when two signal values match, a value indicating an error when they do not match, or a reverse value in each case. The output terminal 13 is a terminal for outputting an output signal from the first logic circuit 12 to the selection control circuit 40.

  The selection control circuit 40 controls the selection in the first selection circuit 10 according to the output result from the output terminal 13. That is, the selection control circuit 40 performs the first selection when the first output result R1 from the output terminal 13 indicates an error when the first input test signal SI1 is selected by the first selection circuit 11. The circuit 11 is caused to select the first expected value SE1. The selection control circuit 40 then outputs the second output from the output terminal 13 when the first expected value SE1 is selected by the first selection circuit 11 in accordance with the first output result R1 indicating an error. When the result R2 indicates normality, the first input test signal SI1 is identified as an error. The selection control circuit 40 specifies the second input test signal SI2 as an error when the second output result R2 indicates an error.

  FIG. 2 is a flowchart showing the flow of processing of the failure diagnosis method according to the first embodiment of the present invention. First, the first selection circuit 11 selects the first input test signal SI1 (S11). Therefore, the first logic circuit 12 receives the first input test signal SI1 as an output signal from the first selection circuit 11. At the same time, the first logic circuit 12 receives the second input test signal SI2.

  Next, the first logic circuit 12 determines whether the first input test signal SI1 and the second input test signal SI2 match (S12). Then, the first logic circuit 12 outputs the coincidence determination result to the output terminal 13.

  Thereafter, the selection control circuit 40 receives a signal from the output terminal 13 as the first output result R1. Here, the selection control circuit 40 determines whether or not the first output result R1 is an error (S13). When it is determined that the first output result R1 is an error, the selection control circuit 40 instructs the first selection circuit 11 to select the first expected value SE1. Then, the first selection circuit 11 selects the first expected value SE1 (S14). Therefore, the first logic circuit 12 receives the first expected value SE1 as an output signal from the first selection circuit 11. At the same time, the first logic circuit 12 receives the second input test signal SI2. At this time, it is assumed that the second input test signal SI2 is not changed.

  Subsequently, the first logic circuit 12 performs matching determination between the first expected value SE1 and the second input test signal SI2, and outputs a matching determination result to the output terminal 13.

  Thereafter, the selection control circuit 40 receives a signal from the output terminal 13 as the second output result R2. Here, the selection control circuit 40 determines whether or not the second output result is normal (S15). When it is determined that the second output result R2 is normal, the selection control circuit 40 identifies the first input test signal SI1 as an error (S16). On the other hand, when it is determined in step S15 that the second output result R2 is an error, the selection control circuit 40 identifies the second input test signal SI2 as an error (S17).

  If it is determined in step S13 that the first output result R1 is not an error, that is, is normal, the selection control circuit 40 specifies that the first and second input test signals SI1 and SI2 are both normal ( S18).

  Thus, in Embodiment 1 of the present invention, when the first output result R1 is an error, either the first input test signal SI1 or the second input test signal SI2 is an error. It turns out. Therefore, under the control of the selection control circuit 40, the first selection circuit 11 causes the first expected value SE1 to be selected instead of the first input test signal SI1. As a result, it is assumed that one of the first logic circuit 12 when performing the coincidence determination of the two signals is normal. Therefore, if the second output result R2 is normal, it is determined that the second input test signal SI2 is also normal along with the first expected value SE1. Therefore, it can be specified that the first input test signal SI1 is an error. On the other hand, if the second output result R2 is an error, the first expected value SE1 is normal when either the first expected value SE1 or the second input test signal SI2 is an error. , It can be determined that the second input test signal SI2 is an error. For this reason, it is possible to perform fault diagnosis by specifying which of the two signals is an error using one output terminal 13.

<Embodiment 2 of the Invention>
Next, a second embodiment of the present invention in which improvements are made to the first embodiment of the present invention will be described. In the above-described failure diagnosis system 101 according to the first embodiment of the present invention, the two signals of the first input test signal SI1 and the second input test signal SI2 are targeted. In the second embodiment of the present invention, four signals are targeted. And the error in four signals is specified using one output terminal.

  FIG. 3 is a block diagram showing a configuration of the failure diagnosis system 102 according to the second exemplary embodiment of the present invention. The failure diagnosis system 102 according to the second exemplary embodiment of the present invention includes a second compression circuit 20 and a third compression circuit 30 that are equivalent to the first compression circuit 10 in the previous stage of the first compression circuit 10 described above. Are connected.

  The fault diagnosis system 102 has an error based on a fault, any one of four signals of the third input test signal SI3, the fourth input test signal SI4, the fifth input test signal SI5, and the sixth input test signal SI6. It is a system for diagnosing a failure by specifying whether the signal is a signal indicating the error. The third input test signal SI3, the fourth input test signal SI4, the fifth input test signal SI5, and the sixth input test signal SI6 are signals generated in the failure diagnosis system 102 or the failure diagnosis system 102. It may be a signal input from the outside. The third input test signal SI3, the fourth input test signal SI4, the fifth input test signal SI5, and the sixth input test signal SI6 are the first input test signal SI1 according to the first embodiment described above. Similarly, four output signals as a result of a scan test from a scan chain built in the failure diagnosis system 102 or four output signals output as a result of a predetermined test in an external circuit may be used. The failure diagnosis system 102 includes a first compression circuit 10, a second compression circuit 20, a third compression circuit 30, and a selection control circuit 40a. The first compression circuit 10 is the same as that shown in FIG.

  The second compression circuit 20 includes a second selection circuit 21 and a second logic circuit 22. The third compression circuit 30 includes a third selection circuit 31 and a third logic circuit 32. Note that the second selection circuit 21 and the third selection circuit 31 have the same functions as the first selection circuit 11. Further, the second logic circuit 22 and the third logic circuit 32 have functions equivalent to those of the first logic circuit 12.

  The second selection circuit 21 selects and outputs either the third input test signal SI3 or the second expected value SE2 that is the expected value of the third input test signal SI3. The second logic circuit 22 outputs the coincidence determination result between the fourth input test signal SI4 and the output signal from the second selection circuit 21 to the first compression circuit 10 as the first input test signal SI1. .

  The third selection circuit 31 selects and outputs either the fifth input test signal SI5 or the third expected value SE3 that is the expected value of the fifth input test signal SI5. The third logic circuit 32 outputs a match determination result between the sixth input test signal SI6 and the output signal from the third selection circuit 31 to the first compression circuit 10 as the second input test signal SI2. .

  The first selection circuit 11 receives the output signal from the second logic circuit 22 as the first input test signal SI1. The first logic circuit 12 receives the output signal from the third logic circuit 32 as the second input test signal SI2.

  The selection control circuit 40a performs a process equivalent to the selection control circuit 40 of FIG. Further, the selection control circuit 40a performs the following processing. When the first input test signal SI1 is identified as an error, the selection control circuit 40a causes the second selection circuit 21 to select the second expected value SE2. Then, the selection control circuit 40a receives the third output from the output terminal 13 when the second expected value SE1 is selected by the second selection circuit 21 when the first input test signal SI1 is specified as an error. When the output result R3 indicates normal, the third input test signal SI3 is identified as an error. The selection control circuit 40a identifies the fourth input test signal SI4 as an error when the third output result R3 indicates an error.

  Further, when the second input test signal SI2 is identified as an error, the selection control circuit 40a causes the third selection circuit 31 to select the third expected value SE3. Then, the selection control circuit 40a receives the fourth output from the output terminal 13 when the third expected value SE3 is selected by the third selection circuit 31 when the second input test signal SI2 is specified as an error. When the output result R4 indicates normal, the fifth input test signal SI5 is identified as an error. In addition, when the fourth output result R4 indicates an error, the selection control circuit 40a specifies the sixth input test signal SI6 as an error.

  4 and 5 are flowcharts showing the flow of processing of the failure diagnosis method according to the second embodiment of the present invention. First, the second selection circuit 21 selects the third input test signal SI3 (S21). Therefore, the second logic circuit 22 receives the third input test signal SI3 as an output signal from the second selection circuit 21. At the same time, the second logic circuit 22 receives the fourth input test signal SI4.

  Next, the second logic circuit 22 determines whether the third input test signal SI3 and the fourth input test signal SI4 match (S22). Then, the second logic circuit 22 outputs the coincidence determination result to the first selection circuit 11 as the first input test signal SI1.

  In parallel with step S21, the third selection circuit 31 selects the fifth input test signal SI5 (S23). Therefore, the third logic circuit 32 receives the fifth input test signal SI5 as an output signal from the third selection circuit 31. At the same time, the third logic circuit 32 receives the sixth input test signal SI6.

  Next, the third logic circuit 32 determines whether the fifth input test signal SI5 and the sixth input test signal SI6 match (S24). Then, the third logic circuit 32 outputs the coincidence determination result to the first logic circuit 12 as the second input test signal SI2.

  Subsequently, the first compression circuit 10 performs processing similarly to steps S11 and S12 of FIG. Then, the selection control circuit 40a determines whether or not the first output result R1 is an error (S13a). In step S13a, when it is determined that the first output result R1 is not an error, that is, normal, the selection control circuit 40a specifies that the third to sixth input test signals SI3 to SI6 are all normal ( S18a).

  If it is determined in step S13a that the first output result R1 is an error, the selection control circuit 40a instructs the first selection circuit 11 to select the first expected value SE1. Here, the first expected value SE1 is an expected value when both the third input test signal SI3 and the fourth input test signal SI4 are normal. Then, the first selection circuit 11 selects the first expected value SE1 (S14). Therefore, the first logic circuit 12 receives the first expected value SE1 as an output signal from the first selection circuit 11. At the same time, the first logic circuit 12 receives the second input test signal SI2. At this time, it is assumed that the match determination result between the second input test signal SI2, that is, the fifth input test signal SI5 and the sixth input test signal SI6, is not changed.

  Subsequently, the first logic circuit 12 performs matching determination between the first expected value SE1 and the second input test signal SI2, and outputs a matching determination result to the output terminal 13.

  Thereafter, the selection control circuit 40a receives a signal from the output terminal 13 as the second output result R2. Here, the selection control circuit 40a determines whether or not the second output result is normal (S15a). When it is determined that the second output result R2 is normal, the selection control circuit 40a identifies the first input test signal SI1 as an error (S16a). On the other hand, if it is determined in step S15a that the second output result R2 is an error, the selection control circuit 40a identifies the second input test signal SI2 as an error (S17a).

  After step S16a, the selection control circuit 40a instructs the second selection circuit 21 to select the second expected value SE2. Then, the second selection circuit 21 selects the second expected value SE2 (S25). Therefore, the second logic circuit 22 receives the second expected value SE2 as an output signal from the second selection circuit 21. At the same time, the second logic circuit 22 receives the fourth input test signal SI4. At this time, it is assumed that the fourth input test signal SI4 is not changed. Then, the second logic circuit 22 outputs the coincidence determination result of the second expected value SE2 and the fourth input test signal SI4 to the first selection circuit 11 as the first input test signal SI1.

  Subsequently, the selection control circuit 40a instructs the first selection circuit 11 to select the first input test signal SI1. Then, the first selection circuit 11 selects the first input test signal SI1 (S26). Thereafter, the first logic circuit 12 performs a match determination between the first input test signal SI1 and the second input test signal SI2, and outputs a match determination result to the output terminal 13.

  Thereafter, the selection control circuit 40a receives a signal from the output terminal 13 as the third output result R3. Here, the selection control circuit 40a determines whether or not the third output result R3 is normal (S27). When it is determined that the third output result R3 is normal, the selection control circuit 40a identifies the third input test signal SI3 as an error (S28). On the other hand, if it is determined in step S27 that the third output result R3 is an error, the selection control circuit 40a identifies the fourth input test signal SI4 as an error (S29).

  After step S17a, the selection control circuit 40a instructs the third selection circuit 31 to select the third expected value SE3. Then, the third selection circuit 31 selects the third expected value SE3 (S30). Therefore, the third logic circuit 32 receives the third expected value SE3 as an output signal from the third selection circuit 31. At the same time, the third logic circuit 32 receives the sixth input test signal SI6. At this time, it is assumed that the sixth input test signal SI6 is not changed. Then, the third logic circuit 32 outputs the coincidence determination result between the third expected value SE3 and the sixth input test signal SI6 to the first logic circuit 12 as the second input test signal SI2. Thereafter, the first logic circuit 12 performs a match determination between the first input test signal SI1 and the second input test signal SI2, and outputs a match determination result to the output terminal 13.

  Thereafter, the selection control circuit 40a receives a signal from the output terminal 13 as the fourth output result R4. Here, the selection control circuit 40a determines whether or not the fourth output result R4 is normal (S31). If it is determined that the fourth output result R4 is normal, the selection control circuit 40a identifies the fifth input test signal SI5 as an error (S32). On the other hand, if it is determined in step S31 that the fourth output result R4 is an error, the selection control circuit 40a identifies the sixth input test signal SI6 as an error (S33).

  As described above, in the second embodiment of the present invention, first, one of the two input signals to the first compression circuit 10 is selected by the selection control in the first selection circuit 11 closest to the output terminal 13 among the selection circuits. Determine if is an error. That is, the compression circuit that outputs the input signal on the side where the error is specified is specified. Then, it can be seen that one of the two input signals input to the specified compression circuit is an error. On the contrary, it is determined that the two input signals input to the other compression circuit for the first compression circuit 10 are normal.

  Then, the selection circuit included in the specified compression circuit is caused to select an expected value. As a result, according to the output result output from the output terminal 13, it is possible to specify which of the input signals input to the specified compression circuit is an error. For this reason, failure diagnosis can be performed by specifying which of the four signals is an error using one output terminal 13.

<Third Embodiment of the Invention>
FIG. 6 is a block diagram showing the configuration of the compressed scan test system 200 according to the third embodiment of the present invention. The compressed scan test system 200 includes a compressed scan test circuit 210 and a tester 220. The compressed scan test circuit 210 includes a scan chain 211, a compressor 212, an external observation terminal 213, an EXOR input expected value generation circuit 214, and a selector control circuit 215.

  The scan chain 211 outputs an output signal from each of the plurality of scan chains. In the scan chain, a plurality of flip-flops in an arbitrary circuit are connected in series for a scan test and output as a scan chain output signal. In FIG. 6, there are eight scan chain output signals, but the present invention is not limited to this.

  The compressor 212 receives a plurality of output signals from the scan chain 211, compresses these signals into one signal, and outputs it from the external observation terminal 213. The compressor 212 includes EXOR circuits 411, 412, 413, 414, 421, 422, and 431 and selectors 311, 312, 313, 314, 321, 322, and 331. The EXOR circuit performs an exclusive OR of two input signals and outputs the result. That is, each EXOR circuit compresses two input signals and outputs them as one signal. Each selector is connected to an expected value output from an EXOR input expected value generation circuit 214 described later, and selects one of two inputs based on a control signal from a selector control circuit 215 described later.

  Each EXOR circuit is configured in a tree shape from the external observation terminal 213 toward the scan chain 211. The output signal based on the scan chain 211 is connected to one input of each EXOR circuit, and the output signal of the selector is connected to the other input. Therefore, the EXOR circuits 411 to 414 directly connect the scan chain output signal to one input and connect the selectors 311 to 314 to the other input, respectively. Each of the selectors 311 to 314 connects a signal not connected to the EXOR circuits 411 to 414 among the scan chain output signals from the scan chain 211 to one input, and the EXOR input expected value generation circuit 214 to the other input. Connect the expected value output from.

  The EXOR circuit 421 connects the output signal from the EXOR circuit 411 to one input, and connects the selector 321 to the other input. The selector 321 connects the output signal from the EXOR circuit 412 to one input, and connects the signal output from the EXOR input expected value generation circuit 214 to the other input. The EXOR circuit 422 connects the output signal from the EXOR circuit 413 to one input, and connects the selector 322 to the other input. The selector 322 connects the output signal from the EXOR circuit 414 to one input, and connects the signal output from the EXOR input expected value generation circuit 214 to the other input.

  The EXOR circuit 431 connects the output signal from the EXOR circuit 421 to one input, and connects the selector 331 to the other input. That is, the EXOR circuit 431 can be said to input the first input test signal and the second input test signal, but the first input test signal and the second input test signal are used in the scan test. It can be said that the signal is based on outputs from different scan chains. The selector 331 connects the output signal from the EXOR circuit 422 to one input, and connects the signal output from the EXOR input expected value generation circuit 214 to the other input. Then, the EXOR circuit 431 outputs the result of the exclusive OR to the external observation terminal 213. Thereby, the tester 220 can observe the scan test results for the eight scan chain output signals from one external observation terminal 206.

  The selector control circuit 215 outputs a selection control signal for selecting a signal to each of the selectors 311 to 314, 321, 322, and 331. At this time, the selector control circuit 215 causes any one of the plurality of selectors to select the expected value signal from the EXOR input expected value generation circuit 214 at any time, and causes the other selectors to receive the expected value signal. A selection control signal is generated and output so as not to be selected. Note that the selector control circuit 215 generates a selection control signal based on a predetermined compression scan pattern.

  The EXOR input expected value generation circuit 214 is a circuit that generates an expected value of a signal connected to one input of the selector at an arbitrary time.

  The tester 220 is a device that controls a compression scan test for a predetermined circuit included in the compression scan test circuit 210. The tester 220 receives an output signal from the external observation terminal 213 and performs various controls on the scan chain 211, the EXOR input expected value generation circuit 214, and the selector control circuit 215. The tester 220 instructs a plurality of scan chains in the scan chain 211 to execute a compression scan test. Then, the tester 220 instructs the EXOR input expected value generation circuit 214 to generate an expected value according to the output result indicated by the output signal from the external observation terminal 213. Further, the tester 220 generates and outputs the above-described selection control signal to the selector control circuit 215 according to the output result. Further, the tester 220 instructs the scan chain 211 to execute the compression scan test again according to the output result. The tester 220 may be a general-purpose computer or a dedicated device, for example.

  FIG. 7 is a flowchart showing the flow of the failure diagnosis process of the compression scan test according to the third embodiment of the present invention. First, the compressed scan test circuit 210 controls all the selectors to select the scan chain input (S41). Specifically, the tester 220 designates a compressed scan pattern for all selectors to select the input of the scan chain to the selector control circuit 215. Then, the selector control circuit 215 causes the selectors 311 to 314 to select the scan chain output signal based on the compressed scan pattern, and causes the selectors 321, 322, and 331 to output the output signal from the preceding EXOR circuit. A selection control signal for selection is generated and output. Thereafter, the tester 220 instructs the scan chain 211 to execute a compression scan test.

  Next, the tester 220 determines whether or not the scan test result is normal (S42). Here, when it is determined that the scan test result is normal, the tester 220 diagnoses that there is no failure in the circuit related to the scan chain 211 (S43). Then, the compressed scan test system 200 ends the failure diagnosis process.

  If it is determined in step S42 that the scan test result is not normal, the tester 220 collects a FAIL address (S44). That is, the tester 220 extracts a FAIL time on the compressed scan pattern and determines a pattern address to be a failure diagnosis target. Then, based on the collected pattern address, the generated compressed scan pattern is sequentially updated according to the failure location tracking process (S45) shown in FIG. 8, and a rescan test is performed.

  FIG. 8 is a flowchart showing the flow of a failure location tracking process according to the third embodiment of the present invention. First, the tester 220 performs initial setting of variables N and M used when updating the compressed scan pattern (S51). Specifically, “N = 1” and “M = maximum number of EXOR stages in the compressor 212” are set. In the example of FIG. 6, “M = 3”.

  Next, the tester 220 determines whether or not “N = 1” (S52). When it is determined that “N = 1”, that is, when the scan test is the first time, only the selector 331 at the last stage selects an expected value (S53). That is, the tester 220 updates the compression scan pattern, and the selector control circuit 215 generates a selection control signal so that only the selector 331 connected to the EXOR circuit 431 directly connected to the external observation terminal 213 selects the expected value. ,Output.

  If it is determined in step S52 that “N = 1” is not satisfied, and if the scan test is the second or later, only the selector connected to the EXOR circuit on the side where the failure is specified in the immediately preceding scan test result is the expected value. Is selected (S54). That is, the tester 220 updates the compressed scan pattern, and the selector control circuit 215 generates and outputs a selection control signal so that only the corresponding selector selects an expected value.

  Thereafter, the tester 220 executes the compression scan test again. As a result, the tester 220 determines whether or not the rescan test result is normal (S55). When it is determined that the rescan test result is normal, the tester 220 identifies the input signal on the selector side that has selected the expected value as a failure (S56). For example, when the selector 331 has selected the expected value, it is determined that each scan chain output signal input to the EXOR circuit 421 is normal. In this case, one of the scan chain output signals input to the EXOR circuit 422 can be said to be an error.

  If it is determined in step S55 that the rescan test result is not normal, the tester 220 identifies an input signal on the non-selector side (non-selector side) that has selected the expected value as a failure (S57). For example, if the selector 331 has selected an expected value, it can be said that any of the scan chain output signals input to the EXOR circuit 421 is an error.

  Here, the tester 220 determines whether N is greater than M (S58). That is, it is determined whether N is equal to or less than the maximum number of EXOR stages in the compressor 212. When it is determined that N is equal to or less than M, the tester 220 adds 1 to N (S59). Thereafter, steps S52 to S58 are repeated until N exceeds M.

  If it is determined in step S58 that N is greater than M, the process proceeds to step S46 in FIG. Since the tree of all the EXOR circuits is traced from the external observation terminal 213 to reach the scan chain 211, the series of processing of the rescan test from the update of the compressed scan pattern is completed.

  Returning to FIG. The tester 220 identifies the flip-flop that has become FAIL (S46). That is, the scan chain flip-flop causing the scan test failure is identified. Thereby, the compression scan test system 200 ends the failure diagnosis process.

  For example, when N = 1, an error is determined in the first stage (EXOR circuit 431) in the tree structure of the EXOR circuit, and when N = 2, an error is determined in the second stage (EXOR circuit 421 or 422). When N = 3, it is possible to determine an error in the third bullet (EXOR circuits 411 to 414). Thereby, it is possible to specify which of the plurality of scan chain output signals is an error using the output result from one external observation terminal 213.

  In this way, it is possible to identify the scan chain that causes the compression scan test to fail based on the above-described diagnosis result. In addition, from the test cycle in which a failure is observed from the external observation terminal 213, it is possible to calculate the number of causes of the failure in the scan chain. Therefore, by combining these results, it is possible to identify the scan chain that causes the scan test to fail and the flip-flop that causes the scan test to fail.

  Here, Embodiment 3 of the present invention can be rephrased as follows. That is, Embodiment 3 of the present invention is a scan test circuit including a compressor between a plurality of scan chains, a scan output of the plurality of scan chains, and an external output pin. Here, the compressor has a plurality of EXORs arranged in a tree shape. One input of the EXOR has a selector for selecting either the output of the scan chain or the expected output value of the scan chain set to a certain value. In the scan test method using the scan test circuit, first, the selector performs a scan test in a state where all the selectors select the output of the scan chain. Next, when the result of the scan test is unsuccessful, the selector sequentially selects the output expected value of the scan chain from the last stage of the EXOR tree configuration of the compressor and performs the rescan test. The test result is observed for each rescan test. Thereby, it is confirmed which input of the selector has an error. Then, the rescan test is repeated up to the first stage of the tree structure so as to backtrace the input side where the error exists. Accordingly, it is possible to identify the scan chain that causes the scan test to fail without increasing the number of external terminals for observing the scan test result in the compression scan test.

  From the above, the effect of the third embodiment of the present invention is that failure diagnosis is not necessary in a compression scan system in which a compressor is configured by an exclusive OR circuit without requiring an increase in the number of external observation terminals due to the number of internal scan chains. Is that you can do that. The reason is that the expected value to be propagated is forcibly input to one input of any one EXOR circuit and the response of the external observation terminal is confirmed, so that the other input value of the EXOR circuit is normal. This is because it becomes possible to determine whether or not. Therefore, a failure can be diagnosed by specifying a signal that causes a failure from a plurality of input signals using a fixed number of output terminals.

<Other embodiments of the invention>
The first logic circuit according to the first and second embodiments of the present invention described above is preferably an EXOR circuit or an EXNOR circuit. A logic circuit that outputs other coincidence determination results may be used.

  Further, the EXOR circuit according to the third embodiment of the present invention may be an EXNOR circuit, and the selector may be a circuit corresponding to it.

  A plurality of terminal circuits corresponding to the first compression circuit 10 may be provided. Even in such a case, the compression circuits may be added in a tree form before each compression circuit.

  When the three input test signals are targeted, in the failure diagnosis system 102 according to the second embodiment of the present invention, either the second compression circuit 20 or the third compression circuit 30 may be used. . Alternatively, either the fourth input test signal SI4 or the sixth input test signal SI6 may be an expected value signal.

  Furthermore, the failure diagnosis system 102 according to the second exemplary embodiment of the present invention adds a compression circuit to the previous stage in accordance with an increase in the number of input signals, thereby allowing a plurality of signal errors at one output terminal. The location can be identified. That is, a compression circuit equivalent to the second compression circuit 20 is provided in the preceding stage of the third input test signal SI3, the fourth input test signal SI4, the fifth input test signal SI5, and the sixth input test signal SI6. What should I do?

  Further, in the failure diagnosis system 102 according to the second exemplary embodiment of the present invention, for example, when the second compression circuit 20 is used instead of the third compression circuit 30, a plurality of stages before the second compression circuit 20 are used. The same effect can be obtained by providing the compression circuit.

  In addition, although each compression circuit and selection control circuit in the failure diagnosis systems 101 and 102 according to the first and second embodiments of the present invention have been described as being hardware, the present invention is not limited to this. For example, various processes in the selection control circuit described above are implemented by a computer program, stored in a storage device mounted on a general-purpose computer, and read out from the storage device by a control unit such as a CPU and executed. It does not matter if it is realized. In that case, the computer program can also be used as a failure diagnosis tool. Further, the above-described selection control circuit may be realized by dividing into hardware and software as in the selector control circuit 215 and the tester 220 as shown in FIG.

  Note that the compressed scan test circuit 210 according to the third embodiment of the present invention may include a plurality of external observation terminals 213 and compress output signals from different scan chain groups. In that case, an EXOR circuit tree concept as shown in FIG. 6 may be provided for each external observation terminal.

  Furthermore, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention described above.

DESCRIPTION OF SYMBOLS 101 Failure diagnosis system 102 Failure diagnosis system 10 1st compression circuit 11 1st selection circuit 12 1st logic circuit 13 Output terminal 20 2nd compression circuit 21 2nd selection circuit 22 2nd logic circuit 30 3rd Compression circuit 31 third selection circuit 32 third logic circuit 40 selection control circuit 40a selection control circuit SI1 first input test signal SI2 second input test signal SI3 third input test signal SI4 fourth input test Signal SI5 5th input test signal SI6 6th input test signal SE1 1st expected value SE2 2nd expected value SE3 3rd expected value R1 1st output result R2 2nd output result R3 3rd output Result R4 Fourth output result 200 Compression scan test system 210 Compression scan test circuit 211 Scan chain 212 Compression 213 External observation terminal 214 EXOR input expected value generation circuit 215 Selector control circuit 220 Tester 311 Selector 312 Selector 313 Selector 314 Selector 321 Selector 322 Selector 331 Selector 411 EXOR circuit 412 EXOR circuit 413 EXOR circuit 414 EXOR circuit 421 EXR circuit 421 EXR circuit 421 431 EXOR circuit 900 Compressor EOR1 to EOR3 Exclusive OR circuit SO1 to SO7 Scan chain output PO1 to PO3 External observation terminal

Claims (14)

A first selection circuit that selects and outputs one of a first input test signal and a first expected value that is an expected value of the first input test signal;
A first compression circuit having a first logic circuit that outputs a match determination result between a second input test signal and an output signal from the first selection circuit to an output terminal;
A selection control circuit for controlling selection in the first selection circuit according to an output result from the output terminal,
The selection control circuit includes:
When the first output result from the output terminal when the first input test signal is selected by the first selection circuit indicates an error, the first selection circuit performs the first Select the expected value,
When the second output result from the output terminal indicates normal when the first expected value is selected by the first selection circuit as the first output result indicates an error, Identify the first input test signal as an error;
A fault diagnosis system, wherein when the second output result indicates an error, the second input test signal is identified as an error. A second selection circuit that selects and outputs either a third input test signal or a second expected value that is an expected value of the third input test signal;
A second logic circuit that outputs a match determination result between a fourth input test signal and an output signal from the second selection circuit to the first compression circuit as the first input test signal;
A second compression circuit having
The selection control circuit includes:
If the first input test signal is identified as an error, the second selection circuit further selects the second expected value;
When the third output result from the output terminal indicates normal when the second expected value is selected by the second selection circuit due to the first input test signal being identified as an error And identifying the third input test signal as an error,
The fault diagnosis system according to claim 1, wherein when the third output result indicates an error, the fourth input test signal is specified as an error. A third selection circuit that selects and outputs one of a fifth input test signal and a third expected value that is an expected value of the fifth input test signal;
A third logic circuit that outputs a match determination result between a sixth input test signal and an output signal from the third selection circuit as the second input test signal to the first compression circuit;
A third compression circuit having
The selection control circuit includes:
If the second input test signal is identified as an error, the third selection circuit is further configured to select the third expected value;
The fourth output result from the output terminal when the third expected value is selected by the third selection circuit when the second input test signal is specified as an error indicates normal And identifying the fifth input test signal as an error,
3. The fault diagnosis system according to claim 1, wherein when the fourth output result indicates an error, the sixth input test signal is identified as an error. 4.   The failure according to any one of claims 1 to 3, wherein the first input test signal and the second input test signal are signals based on outputs from different scan chains in a scan test. Diagnostic system.   5. The fault diagnosis system according to claim 1, wherein the first logic circuit is an EXOR circuit or an EXNOR circuit. 6. A semiconductor integrated circuit used in the fault diagnosis system according to any one of claims 1 to 5,
A first selection circuit that selects and outputs one of a first input test signal and a first expected value that is an expected value of the first input test signal;
A first logic circuit that outputs a match determination result between a second input test signal and an output signal from the first selection circuit to an output terminal;
A semiconductor integrated circuit comprising: a first compression circuit having: A second selection circuit that selects and outputs either a third input test signal or a second expected value that is an expected value of the third input test signal;
A second logic circuit that outputs a match determination result between a fourth input test signal and an output signal from the second selection circuit to the first compression circuit as the first input test signal;
The semiconductor integrated circuit according to claim 6, further comprising: a second compression circuit including: A third selection circuit that selects and outputs one of a fifth input test signal and a third expected value that is an expected value of the fifth input test signal;
A third logic circuit that outputs a match determination result between a sixth input test signal and an output signal from the third selection circuit as the second input test signal to the first compression circuit;
The semiconductor integrated circuit according to claim 6, further comprising a third compression circuit including   9. The device according to claim 6, wherein the first input test signal and the second input test signal are signals based on output signals from different scan chains in a scan test. Semiconductor integrated circuit.   The semiconductor integrated circuit according to claim 6, wherein the first logic circuit is an EXOR circuit or an EXNOR circuit. Selecting and outputting the first input test signal from the first input test signal and a first expected value that is an expected value of the first input test signal;
Outputting a match determination result between the second input test signal and the selected first input test signal to the output terminal;
If the first output result from the output terminal indicates an error, select the first expected value;
If the second output result from the output terminal when the first expected value is selected indicates normal, the first input test signal is identified as an error;
A failure diagnosis method for identifying the second input test signal as an error when the second output result indicates an error. Selecting and outputting the third input test signal out of the third input test signal and the second expected value that is the expected value of the third input test signal;
A match determination result between a fourth input test signal and the selected third input test signal is output as the first input test signal;
If the first input test signal is identified as an error, further select the second expected value;
If the third output result from the output terminal when the second expected value is selected indicates normal, the third input test signal is identified as an error;
12. The fault diagnosis method according to claim 11, wherein when the third output result indicates an error, the fourth input test signal is identified as an error. Selecting and outputting the fifth input test signal from the fifth input test signal and the third expected value which is the expected value of the fifth input test signal;
A match determination result between the sixth input test signal and the selected fifth input test signal is output as the second input test signal;
If the second input test signal is identified as an error, further select the third expected value;
If the fourth output result from the output terminal when the third expected value is selected indicates normal, the fifth input test signal is identified as an error;
The fault diagnosis method according to claim 11 or 12, wherein when the fourth output result indicates an error, the sixth input test signal is identified as an error.   The failure according to any one of claims 11 to 13, wherein the first input test signal and the second input test signal are signals based on outputs from different scan chains in a scan test. Diagnosis method.

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