JP2012039044A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a semiconductor device including a MOS field effect transistor having a high withstand voltage capable of reducing the element area and a method for manufacturing the same.
[Solution]
The semiconductor device 100 according to the present embodiment is provided on the semiconductor substrate 10 on the semiconductor substrate 10, the element isolation regions 14 a and 14 b provided on the semiconductor substrate 10, and the element region partitioned by the adjacent element isolation regions. A gate insulating film 12; a gate electrode 13 provided on the gate insulating film 12; source / drain diffusion regions 11a and 11b provided on a surface of an element region immediately below the gate electrode 13; and the source / drain diffusion regions. Contact plugs 15a and 15b provided on 11a and 11b, and the thickness of the gate insulating film 12 on the drain side is larger than the thickness of the gate insulating film 12 on the source side.
[Selection] Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device, for example, a semiconductor device including a high breakdown voltage MOS field effect transistor and a method for manufacturing the same.

  A semiconductor device, such as a NAND flash memory, includes a low breakdown voltage MOS field effect transistor that operates in a read mode and a high breakdown voltage MOS field effect transistor that operates in a program and erase mode.

  The high breakdown voltage MOS field effect transistor is driven at a higher voltage than the low breakdown voltage MOS field effect transistor. Accordingly, the high breakdown voltage MOS field effect transistor is designed differently from the low breakdown voltage MOS field effect transistor. For example, the gate insulation film of the high breakdown voltage MOS field effect transistor is the gate insulation of the low breakdown voltage MOS field effect transistor. It is formed thicker than the film.

US Patent Application Publication No. 2006/0138549

  The present invention provides a semiconductor device including a high-breakdown-voltage MOS field effect transistor capable of reducing the element area and a method for manufacturing the same.

  According to this embodiment, a semiconductor device includes a semiconductor substrate, an element isolation region provided in the semiconductor substrate, a gate insulating film provided on an element region partitioned by the adjacent element isolation region, A gate electrode provided on the gate insulating film; a source / drain diffusion region provided on the surface of the element region near the gate electrode; and a contact plug provided on the source / drain diffusion region. The film thickness on the drain side of the gate insulating film is thicker than the film thickness on the source side of the gate insulating film.

According to the present embodiment, a method for manufacturing a semiconductor device includes: (a) a step of forming an insulating film formed on the entire surface of a semiconductor substrate and having a partially raised portion; and (b) a conductive material on the insulating film. A step of forming a film; and (c) a step of covering a resist above the conductive film so as to straddle a part of the raised portion and a part of the insulating film excluding the raised portion. (D) removing the conductive film using the resist to form a gate electrode; and (e) a portion of the raised portion where the gate electrode is not formed on the raised portion. Removing the
And (f) forming a source / drain diffusion region on the surface of the semiconductor substrate in the vicinity immediately below the gate electrode.

Sectional drawing of the MOS field effect transistor in this embodiment. Sectional drawing of the MOS type field effect transistor in the modification 1 of this embodiment. Sectional drawing which shows the process of the manufacturing method of the semiconductor device in this embodiment. Sectional drawing which shows the process of the manufacturing method of the semiconductor device in this embodiment. Sectional drawing which shows the process of the manufacturing method of the semiconductor device in this embodiment. Sectional drawing which shows the process of the manufacturing method of the semiconductor device in the modification 2 of this embodiment.

  Hereinafter, one aspect of the present embodiment will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

(Embodiment)
[Configuration of semiconductor device]
The configuration of the semiconductor device of this embodiment will be described with reference to the cross-sectional view of FIG.

  As shown in FIG. 1, the semiconductor device 100 of this embodiment includes a semiconductor substrate 10, source / drain diffusion regions 11 a and 11 b provided on the surface of the semiconductor substrate 10, and a gate insulating film provided on the semiconductor substrate 10. 12, a gate electrode 13 provided on the gate insulating film 12, element isolation regions 14 a and 14 b, and contact plugs 16 a and 16 b provided on the source / drain diffusion regions 11 a and 11 b.

  The MOS field effect transistor in the semiconductor device 100 of this embodiment has a desired gate on an element region defined by element isolation regions (for example, STI (Shallow Trench Isolation) structures) 14a and 14b formed in the semiconductor substrate 10. The insulating film 12 and the gate electrode 13 are sequentially stacked.

  As shown in FIG. 1, the thickness of the gate insulating film 12 on the drain side is thicker than the thickness of the gate insulating film 12 on the source side. As shown in FIG. 1, the gate insulating film 12 includes a first portion having a substantially constant film thickness (for example, 6 nm to 10 nm) from the source side end of the gate insulating film 12 and a drain side end of the gate insulating film 12. The second portion is thicker than the first portion (for example, 20 nm to 40 nm), and the third portion connects the step between the first portion and the second portion. That is, the first partial upper surface and the second partial upper surface are flat, and the first partial upper surface is higher than the second partial upper surface.

  The gate electrode 13 is formed on the gate insulating film 12 with a substantially constant film thickness. For this reason, as shown in FIG. 1, the gate electrode 13 has a shape reflecting the third portion (step) of the gate insulating film 12.

  As shown in FIG. 1, the source / drain diffusion regions 11a and 11b of the present embodiment are formed on the surface of the semiconductor substrate 10 in the vicinity of the gate electrode 13 and have a DDD (Double Diffused Drain) structure. In this embodiment, the present invention is not limited to this DDD structure, and may be applied to, for example, an LDD (Lightly Doped Drain) structure, an LDMOS (Lateral Double diffused MOS) structure, or the like.

<Modification 1>
The gate electrode 13 of the present embodiment has a shape reflecting the third portion of the gate insulating film 12, but as shown in FIG. 2, the upper surface of the gate electrode 15 is flat as the semiconductor device 101 of the first modification. It is good also as the shape made into.

  The shape of the step (third portion) of the gate insulating film 12 is not reflected in, for example, the insulating film formed on the MOS field effect transistor of the first modification. Therefore, the lithography process margin is widened when the insulating film is formed into a desired pattern using an optical lithography technique.

[Method for Manufacturing Semiconductor Device]
As a method of manufacturing the semiconductor device of this embodiment, an example in which the above-described high breakdown voltage MOS field effect transistor and low breakdown voltage MOS field effect transistor are formed on the same semiconductor substrate is shown in the cross-sectional view of FIGS. This will be described with reference to the drawings.

First, as shown in FIG. 3A, an insulating film (hereinafter referred to as a sacrificial insulating film; for example, SiO ₂ ) 21a is formed on a semiconductor substrate 20a by, for example, a CVD (Chemical Vapor Deposition) method. Photoresist 22 is applied over the entire surface of the sacrificial insulating film 21a, and a low breakdown voltage MOS type field effect transistor formation planned region (shown in the figure shows a LV (Low Voltage) formation planned region) 200 by an optical lithography technique. A desired resist pattern is formed so as to cover a part of the separation formation scheduled region 201. That is, the photoresist 22 covers part of the element isolation formation planned region 201 on the region 200 side.

  Here, the gate insulating film of the low breakdown voltage MOS field effect transistor is thinner than the gate insulating film of the high breakdown voltage MOS field effect transistor described above, and is formed with a substantially constant film thickness of 6 nm to 10 nm on the entire surface. Is done.

  As shown in FIG. 3B, the sacrificial insulating film 21a and a part of the semiconductor substrate 20a are processed by dry etching (for example, RIE (Reactive Ion Etching)) using the photoresist 22 as a mask. For example, a semiconductor substrate 20b is formed in which the surface of a region where a high breakdown voltage MOS field effect transistor is to be formed (shown in the drawing is a region for forming HV (High Voltage)) 202 is lower by about 30 nm than the surface of the region 200.

  As shown in FIG. 3C, the photoresist 22 and the sacrificial insulating film 21b remaining in the step of FIG. 3B are removed, and an insulating film (hereinafter referred to as a first insulating film) is formed on the semiconductor substrate 20b by a CVD method. ) 23. The film thickness of the first insulating film 23 is, for example, 35 nm.

  As shown in FIG. 3D, a photoresist is applied to the entire surface of the first insulating film 23, and a photoresist 25 having a desired resist pattern is formed so as to cover a part of the region 202 by photolithography. To do. For example, as shown in FIG. 3D, the photoresist 25 is formed across the region 202 and the region 201.

  Then, using the photoresist 25 as a mask, the first insulating film 23 is processed by wet etching until the surface of the semiconductor substrate 20b is exposed. As a result, as shown in FIG. 3D, a tapered first insulating film 24 is formed after processing by wet etching.

  As shown in FIG. 4A, the photoresist 25 remaining in the step of FIG. 3D is removed, and an insulating film of the same type as the first insulating film 24 (on the semiconductor substrate 20b and the first insulating film 24). (Hereinafter referred to as a second insulating film) 26 is formed by a CVD method. The film thickness of the second insulating film 26 is thinner than the film thickness of the first insulating film 24, and is about 6 nm, for example. As a result, an insulating film having a partially raised portion can be formed.

  Next, a conductive film 27 a is formed on the second insulating film 26. The conductive film 27a serves as a gate electrode. Then, an insulating film (hereinafter referred to as a third insulating film; for example, SiN) 28 is formed on the entire surface of the conductive film 27a.

  As shown in FIG. 4B, the element isolation region 29 is formed in the element isolation formation planned region 201.

  As shown in FIG. 4C, the third insulating film 28 is removed, and the same type of insulating film as the first insulating film 24 (hereinafter referred to as a fourth insulating film) is formed on the conductive film 27a and the element isolation region 29. 30 is formed by a CVD method.

  As shown in FIG. 4D, a photoresist (not shown) is applied to the entire surface of the fourth insulating film 30, and in the region 202, the first insulating film 24 and the second insulating film 26 are applied by photolithography. A desired resist pattern is formed so as to cover a range across a part of the thick film laminated with a part of the second insulating film 26. For example, as shown in FIG. 4D, a photoresist is formed across a part of the thick film and a part of the second insulating film 26.

  On the other hand, in the region 200, a desired resist pattern is formed by photolithography to form a low breakdown voltage MOS field effect transistor.

  Using the resist patterns in the regions 200 and 202 as a mask, the fourth insulating film 30, the conductive film 27a, and the second insulating film 26 are processed by dry etching until the surface of the semiconductor substrate 20c is exposed. Thereby, gate electrodes 27b and 27c are formed.

  Next, an insulating film 31 (hereinafter referred to as a fifth insulating film) 31 of the same type as the first insulating film 24 is formed on the semiconductor substrate 20c, the gate electrodes 27b and 27c, the element isolation region 29, and the first insulating film 24 by the CVD method. Form.

  As shown in FIG. 5A, a photoresist is applied to the entire surface of the fifth insulating film 31, and the gate insulating film of the MOS field effect transistor having a high breakdown voltage among the first and second insulating films 24 and 26. A photoresist 33 having a desired resist pattern is formed so that the unused portion 32 can be removed.

  As shown in FIG. 5B, the fifth insulating film 31, the first and second insulating films 24 and 26, and a part of the element isolation region 29 are removed using the photoresist 33 as a mask. After the removal, the photoresist 33 is removed. Thereby, a gate insulating film is formed.

  Note that a resist pattern for removing only the first and second insulating films 24 and 26 of the portion 32 and the fifth insulating film 31 formed on the portion 32 may be formed.

  Then, ion implantation is performed using the gate insulating film and gate electrodes 27b and 27c formed in the step of FIG. 5B as masks to form source / drain regions.

  Thereby, a high breakdown voltage MOS field effect transistor and a low breakdown voltage MOS field effect transistor can be formed on the same semiconductor substrate.

  As a modification of the present embodiment, for example, the fifth insulating film 31 is removed, and an insulating film of the same type as the first insulating film 24 (hereinafter referred to as a sixth insulating film) is applied, and the gate insulating film and the gate electrode are applied. Side wall films may be formed on the side walls of 27b and 27c.

  Further, an insulating film (not shown) is formed on the high voltage MOS field effect transistor, and a desired opening (not shown) for forming a contact plug (not shown) is formed in this insulating film in the same manner as described above. And a material used for the contact plug is embedded in the opening to form the contact plug.

<Modification 2>
Next, a method of manufacturing a semiconductor device having a MOS field effect transistor having a planarized gate electrode upper surface as shown in FIG. 2 will be described with reference to FIG.

  The manufacturing method of the semiconductor device of Modification 2 is different from the manufacturing method of the semiconductor device of this embodiment in that a conductive film 27a is formed on the second insulating film 26 in FIG. 4A of the manufacturing process of this embodiment. After the formation, the surface of the conductive film 27a is planarized by CMP (Chemical Mechanical Polishing), and after the surface of the conductive film 27a is planarized, the third insulating film 28 is formed. This is different from the step of planarizing by CMP, and the other steps are the same as in this embodiment.

<Modification 3>
In the manufacturing method of the semiconductor device of this embodiment, wet etching is used to form the tapered first insulating film 24. However, dry etching may be used as in Modification 3.

  Thereby, the boundary between the first portion and the third portion in the gate insulating film of the semiconductor device can be made clearer, and the drive current can be controlled more easily.

[Effect of the embodiment]
As described above, the present embodiment provides a semiconductor device including a high-breakdown-voltage MOS field effect transistor capable of reducing the element area and a method for manufacturing the same. This will be specifically described below.

  Specifically, in the semiconductor device of this embodiment, the film thickness on the drain side of the gate insulating film is formed thicker than the film thickness on the source side of the gate insulating film.

  By increasing the thickness of the gate insulating film on the drain side to which a high voltage is applied, the MOS field effect transistor of the semiconductor device can have a high breakdown voltage. On the other hand, the drive current of the MOS field effect transistor of the semiconductor device can be improved by making the gate insulating film on the source side thinner than the drain side. For example, when the gate insulating film on the source side has the same thickness as the gate insulating film of a low breakdown voltage MOS field effect transistor, the MOS field effect transistor of this embodiment is a low breakdown voltage MOS field effect transistor. Can be controlled by a drive current equivalent to

  As a result, the operating speed of the MOS field effect transistor of the present embodiment can be improved to the operating speed of the low withstand voltage MOS field effect transistor.

  In the MOS field effect transistor of this embodiment, a high breakdown voltage is ensured by making the thickness of the gate insulating film on the drain side thicker than that on the source side. For this reason, a gate electrode is formed on a gate oxide film uniformly formed with a film thickness equivalent to that of a low breakdown voltage MOS field effect transistor, which is an example of a high breakdown voltage MOS field effect transistor, and an element isolation region The MOS field effect transistor according to the present embodiment can reduce the element area as compared with the field effect transistor in which the drain diffusion layer is formed across the gate electrode.

  A gate electrode is formed on a gate oxide film uniformly formed with a film thickness equivalent to that of a low breakdown voltage MOS field effect transistor, which is an example of a high breakdown voltage MOS field effect transistor, and straddles the element isolation region. It is a field effect transistor in which a drain diffusion layer is formed, and the MOS type field effect transistor of this embodiment is more than a case where a contact plug that penetrates the element isolation region and is electrically connected to the drain diffusion layer is formed. Can reduce the manufacturing process. This is because in the present embodiment, a process of forming a through hole in the element isolation region is not necessary.

  Furthermore, the MOS field effect transistor of this embodiment is a MOS field effect transistor that can cope with both a low breakdown voltage and a high breakdown voltage. Therefore, the MOS field effect transistor of this embodiment may be formed instead of separately forming the low breakdown voltage MOS field effect transistor and the high breakdown voltage MOS field effect transistor. In this case, the manufacturing process of the MOS field effect transistor of this embodiment is shorter than the manufacturing process of separately forming the low breakdown voltage MOS field effect transistor and the high breakdown voltage MOS field effect transistor, and the manufacturing process can be reduced. .

  The gate insulating film of the MOS field effect transistor of this embodiment has a substantially constant film thickness from the source side end of the gate insulating film. The drive current of the MOS field effect transistor of this embodiment varies depending on the width of the portion having the substantially constant film thickness. Therefore, the drive current can be controlled by controlling this width.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

10 20a 20b ... Semiconductor substrate 11a 11b 36 ... Source / drain diffusion region 12 34 35 ... Gate insulating film 13 15 27b 27c ... Gate electrode 14a 14b ... Element isolation region 16a 16b ... Contact plug 21a 21b ... Sacrificial insulating film 22 25 33 ... Photoresist 23 24 ... 1st insulating film 26 ... 2nd insulating film 27a ... Conductive film 28 ... 3rd insulating film 29 ... Element isolation region 30 ... 4th insulating film 31 ... 5th insulating film 32 ... High voltage MOS type electric field Part 37 not used as gate insulating film of effect transistor ... Sixth insulating film 100 101 ... Semiconductor device 200 ... LV formation planned region 201 ... Element isolation formation planned region 202 ... HV formation planned region

Claims (5)

A semiconductor substrate;
An element isolation region provided in the semiconductor substrate;
A gate insulating film provided on an element region partitioned by the adjacent element isolation region;
A gate electrode provided on the gate insulating film;
A source / drain diffusion region provided on the surface of the element region in the vicinity immediately below the gate electrode;
A contact plug provided on the source / drain diffusion region,
2. The semiconductor device according to claim 1, wherein a thickness of the gate insulating film on the drain side is larger than a thickness of the gate insulating film on the source side. The semiconductor device according to claim 1, wherein the gate insulating film has a substantially constant thickness from an end on the source side. The gate insulating film is
The first portion having a substantially constant film thickness from the end on the source side and the second portion having an upper surface higher than the top surface of the first portion and the substantially constant film thickness from the end on the drain side The semiconductor device according to claim 1, further comprising a third portion that connects the second portion and the third portion. (A) a step of forming an insulating film formed on the entire surface of the semiconductor substrate and having a partially raised portion;
(B) forming a conductive film on the insulating film;
(C) covering the resist over the conductive film so as to straddle a part of the raised part and a part of the insulating film excluding the raised part;
(D) removing the conductive film using the resist to form a gate electrode;
(E) removing the insulating film in a portion of the raised portion where a gate electrode is not formed on the raised portion;
(F) forming a source / drain diffusion region on the surface of the semiconductor substrate immediately under the gate electrode; and a method for manufacturing a semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 4, wherein dry etching is used when forming the raised portion in the step (a).

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