JP2012038994A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor device capable of forming a silicide layer having a large thickness and a uniform thickness while suppressing the occurrence of a short circuit between a gate electrode and a semiconductor substrate, and a method for manufacturing the same. The issue is to provide.
SOLUTION: Gate electrodes 61 and 62 provided on side surfaces 26a and 26b of a pillar 26 via a gate insulating film 27, a silicide layer 38 formed on an upper end 26-1 of the pillar 26, a gate electrode 61, 62, and is provided so as to surround the side surface of the pillar 26 and expose the side surface of the silicide layer 38, and to cover the side surface of the silicide layer 38, and on the upper end 26-1 of the pillar 26. A metal film 39 for silicidation of contained silicon; an upper impurity diffusion region 36 formed in the pillar 26 so as to contact the lower surface 38b of the silicide layer 38; and a capacitor 52 provided on the upper surface 38a of the silicide layer 38; Have.
[Selection] Figure 2B

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, semiconductor devices (specifically, semiconductor elements) have been miniaturized. Therefore, when a DRAM (Dynamic Random Access Memory) is used as a semiconductor device and a DRAM memory cell is miniaturized, a selection transistor and a capacitor constituting the memory cell are reduced, so that a sufficient capacity of the capacitor is ensured. Has become difficult.

  As one method for solving this problem, the capacitor is three-dimensionalized to increase the surface area of the electrodes constituting the capacitor, and the capacitor structure is shifted from the MIS (Metal Insulator Semiconductor) structure to the MIM (Metal Insulation Metal) structure. Has been done.

  In Patent Document 1, in order to reduce resistance between an MIM capacitor including a lower electrode, a capacitive insulating film, and an upper electrode, and a capacitive contact plug to which the MIM capacitor is connected, a lower electrode and a capacitive contact plug are provided. It is disclosed that a silicide layer is formed between the two.

Here, the method for forming the MIM capacitor and the silicide layer described in Patent Document 1 will be briefly described.
First, a capacitive contact plug made of an impurity-containing polycrystalline silicon film is formed which is electrically connected to an impurity diffusion region (source region) constituting the transistor.
Next, an interlayer insulating film is formed on the capacitor contact plug. Next, a cylinder hole reaching the upper surface of the capacitor contact plug is formed in the interlayer insulating film by anisotropic etching.

Next, a titanium (Ti) film covering the upper end surface of the capacitor contact plug exposed from the cylinder hole and the inner peripheral surface of the cylinder hole, and a titanium nitride (TiN) film covering the surface of the titanium (Ti) film are sequentially stacked. Thus, the lower electrode is formed.
At this time, a silicide layer is formed on the capacitive contact plug by reacting Ti contained in the titanium (Ti) film constituting the lower electrode with silicon contained in the capacitive contact plug.
Thereafter, a MIM capacitor is formed by sequentially forming a capacitive insulating film covering the surface of the lower electrode and an upper electrode covering the surface of the capacitive insulating film.

In Patent Documents 2 and 3, as a technique for miniaturizing a memory cell of a DRAM, a vertical transistor (also referred to as a “three-dimensional transistor”) in which a transistor is formed in a pillar extending perpendicularly to the main surface of a semiconductor substrate is disclosed. It is disclosed.
The vertical transistor described in Patent Document 3 is connected to an MIM capacitor disposed above the vertical transistor via a capacitive contact plug.
The vertical transistor having the above-described configuration has an advantage that the occupied area is small and a large drain current can be obtained by complete depletion, and a close-packed layout of 4F ² (F is the minimum processing dimension) can be realized. Is possible.

JP 2008-192650 A Japanese Patent Laid-Open No. 2008-300623 JP 2009-10366 A

When the DRAM cell is composed of the vertical transistor, the capacitor is formed so as to be in direct contact with the upper impurity diffusion region (source region) formed at the upper end of the pillar in order to ensure sufficient capacity.
In this case, in order to reduce the contact resistance between the lower electrode and the upper impurity diffusion region, the Ti film constituting the lower electrode and a part of the upper impurity diffusion region made of silicon are silicided to form a silicide layer. The capacitor and the upper impurity diffusion region are electrically connected to each other.

  By the way, when the semiconductor device is further miniaturized, the diameter of the cylinder hole is further reduced, so that the contact resistance between the capacitor and the upper impurity diffusion region is increased. Therefore, in order to suppress an increase in contact resistance, it is necessary to make the thickness of the silicide layer thicker than before.

  However, when a titanium (Ti) film is formed on the upper surface of the upper impurity diffusion region exposed from the bottom surface of the cylinder hole having a high aspect ratio (= cylinder hole depth / cylinder hole diameter), titanium (Ti) Variations in the thickness of the film increase, making it difficult to make the thickness of the silicide layers formed on the plurality of pillars uniform.

Therefore, when the thickness of the silicide layer is increased by promoting the growth of the silicide layer, in the pillar in which the silicide layer is formed thicker than other pillars, the distance between the gate electrode and the silicide layer is too close. The silicide layer reaches the gate insulating film formed on the side surface of the pillar, the gate insulating film is eroded and destroyed, and a short circuit occurs between the gate electrode and the semiconductor substrate.
Therefore, in the conventional method of forming a silicide layer by forming a lower electrode through a cylinder hole with a high aspect ratio, the occurrence of a short circuit between the gate electrode and the semiconductor substrate is suppressed, and the thickness is increased. In addition, it is difficult to form a silicide layer having a uniform thickness.

  According to one aspect of the present invention, a pillar provided on a semiconductor substrate containing silicon (Si) and using the semiconductor substrate as a base material, a silicide layer formed on an upper end of the pillar, and a side surface of the silicide layer are provided. A metal film for siliciding silicon (Si) contained at the upper end of the pillar and a side surface of the pillar located below the silicide layer via a gate insulating film is provided. A gate electrode; an insulating film that covers the gate electrode and surrounds a side surface of the pillar located below the silicide layer; and exposes the silicide layer and the metal film; and An upper impurity diffusion region disposed on the pillar and a capacitor provided on the upper surface of the silicide layer so as to be in contact with the lower surface. The semiconductor device is provided, wherein.

  According to the semiconductor device of the present invention, a pillar provided on a semiconductor substrate containing silicon (Si), a pillar using the semiconductor substrate as a base material, a silicide layer formed on an upper end of the pillar, and a side surface of the silicide layer are covered. A metal film for siliciding silicon (Si) included at the upper end of the pillar, a gate electrode provided on a side surface of the pillar located below the silicide layer via the gate insulating film, and a gate electrode And is disposed on the pillar so as to be in contact with the lower surface of the silicide layer and the insulating film exposing the silicide layer and the metal film, and surrounding the side surface of the pillar located below the silicide layer. By having the upper impurity diffusion region and the capacitor provided on the upper surface of the silicide layer, only the upper end of the pillar surrounded by the metal film is silicidized. Since it is possible to form a layer, a sufficient distance is ensured between the silicide layer and the gate electrode, and the occurrence of a short circuit between the gate electrode and the semiconductor substrate is suppressed, and the thickness is increased. A silicide layer having a uniform thickness can be provided.

1 is a plan view schematically showing a memory cell array provided in a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the memory cell array shown in FIG. 1 in the AA line direction. FIG. 2 is a cross-sectional view of the memory cell array shown in FIG. 1 in the BB line direction. FIG. 3B is a diagram (part 1) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, and a sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2A; FIG. 4B is a diagram (part 1) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, and a sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2B; FIG. 3B is a diagram (part 2) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, and a sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2A; FIG. 8B is a diagram (part 2) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, and a sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2B; FIG. 3D is a diagram (part 3) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2A; FIG. 8B is a diagram (No. 3) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, and a sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 4B is a diagram (part 4) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2A; FIG. 4D is a diagram (part 4) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2B; FIG. 8B is a diagram (part 5) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2A; FIG. 6B is a view (No. 5) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, and a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 6D is a diagram (No. 6) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2A; FIG. 6D is a view (No. 6) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 7B is a view (No. 7) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2A; FIG. 8B is a view (No. 7) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 8B is a view (No. 8) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2A; FIG. 8B is a view (No. 8) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 9B is a diagram (No. 9) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2A; FIG. 9D is a diagram (No. 9) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 10B is a view (No. 10) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2A; FIG. 10B is a view (No. 10) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, and a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 11B is a view (No. 11) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2A; FIG. 12B is a view (No. 11) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, and a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 12B is a view (No. 12) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, and a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2A; FIG. 12B is a view (No. 12) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, and a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 13B is a view (No. 13) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2A; FIG. 13B is a view (No. 13) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B;

  Embodiments to which the present invention is applied will be described below in detail with reference to the drawings. Note that the drawings used in the following description are for explaining the configuration of the embodiment of the present invention, and the size, thickness, dimensions, and the like of each part shown in the drawings are different from the dimensional relationship of an actual semiconductor device. There is.

(Embodiment)
FIG. 1 is a plan view schematically showing a memory cell array provided in a semiconductor device according to an embodiment of the present invention. 2A is a cross-sectional view of the memory cell array shown in FIG. 1 in the AA line direction, and FIG. 2B is a cross-sectional view of the memory cell array shown in FIG. 1 in the BB line direction.
In FIG. 1, the X direction indicates the extending direction of the word line 29, and the Y direction indicates the extending direction of the bit line 21 that intersects the word line 29. In FIG. 1, for convenience of explanation, among the components of the memory cell array 11 shown in FIGS. 2A and 2B, the bit line 21, the word line 29, the silicide layer 38, the metal film 39, and the other metal film 41, and Only the capacitor 52 is shown.
2A and 2B, the same components as those of the memory cell array 11 shown in FIG. 1, 2 </ b> A, and 2 </ b> B, a DRAM (Dynamic Random Access Memory) is taken as an example of the semiconductor device of this embodiment, and the following description is given.

  The semiconductor device 10 of this embodiment includes a memory cell region in which the memory cell array 11 shown in FIGS. 1, 2A, and 2B is formed, and a peripheral circuit (not shown) arranged around the memory cell region. And a peripheral circuit region to be formed. In the peripheral circuit region, peripheral circuit transistors (for example, planar transistors) (not shown) are formed.

Next, the configuration of the memory cell array 11 will be described with reference to FIGS. 1, 2A, and 2B.
The memory cell array 11 includes a semiconductor substrate 13, an element isolation region (not shown), a bit line forming groove 15, a first insulating film 16, a bit contact 18, a lower impurity diffusion region 19, and a bit line. 21, second insulating film 23, word line forming groove 25, pillar 26, gate insulating film 27, word line 29, first buried insulating film 31, groove 32, and liner film 33. The second buried insulating film 35, the upper impurity diffusion region 36, the recess 37, the silicide layer 38, the metal film 39, the other metal film 41, the first etching stopper film 46, and the first etching stopper film 46. The interlayer insulating film 47, the second etching stopper film 48, the support film 51, the capacitor 52, the third interlayer insulating film 53, the wiring 55, and the fourth interlayer insulating film 56 are included.

2A and 2B, the semiconductor substrate 13 is a substrate containing silicon (Si) and having impurities of a predetermined concentration. As the semiconductor substrate, for example, a p-type silicon substrate can be used. Hereinafter, a case where a p-type silicon substrate is used as the semiconductor substrate 13 will be described as an example.
The semiconductor substrate 13 includes an element isolation region (not shown) constituted by an element isolation groove (not shown) and an element isolation insulating film (not shown) that fills the element isolation groove, and the element isolation. And an element forming region formed inside the region and having a rectangular shape.
A silicon oxide film (SiO ₂ film) is used as the element isolation insulating film. The structure of the element isolation region is called STI (Shallow Trench Isolation). The element formation region is an active region that is insulated and isolated by an element isolation region.

Referring to FIG. 2A, the bit line forming groove 15 is formed in the semiconductor substrate 13. A plurality of bit line forming grooves 15 are arranged in the X direction so as to extend in the Y direction. A bit line 21 is formed at the bottom of the bit line forming groove 15.
The first insulating film 16 is formed on the inner surface of the bit line formation groove 15 corresponding to the formation region of the bit line 21 (specifically, a part of the side surface and the bottom surface of the bit line formation groove 15). Is provided. The first insulating film 16 has an opening 16A in which the bit contact 18 is formed. The opening 16A is formed so as to expose a part of the side surface of the pillar 26. As the first insulating film 16, a silicon oxide film (SiO ₂ film) can be used.

The bit contact 18 is provided so as to fill the opening 16 </ b> A formed in the first insulating film 16. As a material of the bit contact 18, for example, a polycrystalline silicon film containing an n-type impurity (for example, arsenic (As)) can be used.
The lower impurity diffusion region 19 is an impurity diffusion region containing an n-type impurity (for example, arsenic (As)), and functions as a drain region. The lower impurity diffusion region 19 is formed in the pillar 26 located below the upper impurity diffusion region 36 and is in contact with the bit contact 18. Lower impurity diffusion region 19 is electrically connected to bit line 21 via bit contact 18.

Referring to FIG. 2A, the bit line 21 (embedded bit line) is formed at the bottom of the bit line forming groove 15 via the first insulating film 16. That is, the bit line 21 is disposed below gate electrodes 61 and 62 described later in a state of being electrically insulated from the semiconductor substrate 13.
The upper surface 21a of the bit line 21 is a flat surface. The bit line 21 intersects with the word line 29 and extends in the Y direction. A plurality of bit lines 21 are arranged in the X direction (see FIG. 1). The bit line 21 is in contact with the bit contact 18 and is electrically connected to the lower impurity diffusion region 19 through the bit contact 18.
The bit line 21 is composed of a conductive film. As the conductive film constituting the bit line 21, for example, a laminated film in which a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film are sequentially laminated can be used.

Referring to FIG. 2A, the second insulating film 23 includes the upper surface 21a of the bit line 21 and the side surface of the bit line forming groove 15 located above the bit line 21 (in other words, the upper impurity diffusion region 36). The side surfaces 26c and 26d) of the pillar 26 including the side surfaces and the silicide layer 38d are formed so as to cover them. The upper surface 23 a of the second insulating film 23 is substantially flush with the lower surface 38 b of the silicide layer 38. For example, a SiON film can be used as the second insulating film 23.
2A and 2B, the word line forming groove 25 is formed in the semiconductor substrate 13 so as to intersect the bit line forming groove 15. The word line forming grooves 25 extend in the X direction, and a plurality of the word line forming grooves 25 are arranged in the Y direction.

2A and 2B, the pillar 26 is surrounded by the bit line forming groove 15 and the word line forming groove 25, and has a columnar shape. The pillar 26 uses a semiconductor substrate 13 containing silicon as a base material. A plurality of pillars 26 are processed by partially etching the main surface 13a of the semiconductor substrate 13 to process the bit line forming groove 15 and the word line forming groove 25. It is formed.
A silicide layer 38 is formed on the upper end 26-1 of the pillar 26, and an upper impurity diffusion region 36 that is in contact with the silicide layer 38 is formed below the silicide layer 38. A portion of the pillar 26 located below the upper impurity diffusion region 36 functions as a channel.

A vertical transistor 66 is formed by forming the lower impurity diffusion region 19, the upper impurity diffusion region 36, the gate insulating film 27, and a pair of gate electrodes 61 and 62 described later in the pillar 26. That is, in the memory cell array 11, a plurality of vertical transistors 66 are formed in a matrix.
The vertical transistor 66 has an advantage in that the occupied area is small and a large drain current can be obtained by complete depletion. Therefore, in the memory cell array 11, by providing a plurality of the vertical transistors 66, a close-packed layout of 4F ² (F is the minimum processing dimension) can be realized.

Referring to FIG. 2B, the gate insulating film 27 includes side surfaces 26a and 26b (including side surfaces of the upper impurity diffusion region 36 and side surface 38c of the silicide layer 38) of the plurality of pillars 26 arranged in the X direction, and word lines. It is formed so as to cover the bottom surface 25 a of the forming groove 25.
Examples of the gate insulating film 27 include a single-layer silicon oxide film (SiO ₂ film), a film obtained by nitriding a silicon oxide film (SiON film), a stacked silicon oxide film (SiO ₂ film), and a silicon oxide film (SiO ₂ ). A laminated film in which a silicon nitride film (SiN film) is laminated on ( _two films) can be used.

Referring to FIG. 1, the word line 29 includes a pair of gate electrodes 61 and 62, an electrode end connection portion 63, and a connection portion 65.
1 and 2B, the gate electrode 61 extends in the X direction, and is provided on the side surfaces 26a of the plurality of pillars 26 located below the silicide layer 38 via the gate insulating film 27. It has been. The gate electrode 62 extends in the X direction, and is provided on the side surfaces 26 b of the plurality of pillars 26 located below the silicide layer 38 with the gate insulating film 27 interposed therebetween. The gate electrode 62 is disposed to face the gate electrode 61 with the gate insulating film 27 and the plurality of pillars 26 interposed therebetween.
Referring to FIG. 1, the electrode end connection portions 63 are provided at both ends of the gate electrodes 61 and 62, respectively, and are configured integrally with the end portions of the gate electrodes 61 and 62.

Referring to FIGS. 1 and 2A, the connection portion 65 is provided in the bit line forming groove 15 located between the gate electrodes 61 and 62 via the second insulating film 23. One end of the connecting portion 65 is configured integrally with the gate electrode 61, and the other end of the connecting portion 65 is configured integrally with the gate electrode 62. The connection portion 65 is a member for reducing the difference in electrical resistance of the word line 29 in the X direction.
The word line 29 is composed of a conductive film. As the conductive film constituting the word line 29, for example, a stacked film in which a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film are sequentially stacked can be used.

Referring to FIG. 2A, the first buried insulating film 31 fills the bit line forming groove 15 so as to cover the upper surface of the connecting portion 65. The upper surface 31 a of the first buried insulating film 31 is a flat surface and is flush with the lower surface 38 b of the silicide layer 38. In other words, the upper surface 31a of the first buried insulating film 31 is disposed at a position lower than a main surface 13a of the semiconductor substrate 13 (an upper end surface 26-1e of the pillar 26 shown in FIGS. 4A and 4B described later). .
As the first buried insulating film 31, for example, an insulating film having excellent filling characteristics and a dense film quality may be used. Specifically, for example, a silicon oxide film (SiO ₂ film) formed by HDP (High Density Plasma) method may be used as the first buried insulating film 31.

  Referring to FIG. 2B, the groove 32 extends in the X direction and is formed in the word line forming groove 25. The width of the groove 32 in the Y direction is narrower than the width of the word line forming groove 25 in the Y direction. The groove 32 is embedded in the word line forming groove 25, and a conductive film (not shown) serving as a base material of the word line 29 is separated into two to form a pair of gate electrodes 61 and 62. This is a separation groove. Therefore, the depth of the groove 32 is formed so as to be deeper than the depth of the word line forming groove 25 so that the conductive film as the base material of the word line 29 can be reliably separated into two.

Referring to FIG. 2B, the liner film 33 is provided in the word line forming groove 25 and formed in a sidewall shape on the gate electrodes 61 and 62. The liner film 33 is an insulating film. As the liner film 33, for example, a SiON film can be used. The upper surface 33 a of the liner film 33 is a flat surface and is flush with the lower surface 38 b of the silicide layer 38.
Referring to FIG. 2B, the second buried insulating film 35 is provided so as to fill the trench 32. The upper surface 35 a of the second buried insulating film 35 is a flat surface and is flush with the lower surface 38 b of the silicide layer 38.
In the present embodiment, the insulating film that covers the gate electrodes 61 and 62 and surrounds the side surface of the pillar 26 located below the silicide layer 38 and exposes the silicide layer 38 and the metal film 39. Is composed of a first buried insulating film 31, a liner film 33, and a second buried insulating film 35.

Referring to FIGS. 2A and 2B, the upper impurity diffusion region 36 is formed on the pillar 26 and is in contact with the lower surface 38 b of the silicide layer 38. Thereby, the upper impurity diffusion region 36 is electrically connected to the silicide layer 38.
The upper impurity diffusion region 36 is an impurity diffusion region containing an n-type impurity (for example, arsenic (As)), and functions as a source region.
The vertical transistor 66 (also referred to as “three-dimensional transistor”) in the present embodiment includes a pillar 26, a bit contact 18, a lower impurity diffusion region 19, a gate insulating film 27, gate electrodes 61 and 62, and upper impurities. The diffusion region 36 is formed.

  Referring to FIG. 2A and FIG. 2B, the recess 37 includes the upper surface 23a of the second insulating film 23, the upper surface 31a of the first embedded insulating film 31, the upper surface 33a of the liner film 33, and the like. The upper surface 35 a of the second buried insulating film 35 is formed below the main surface 13 a of the semiconductor substrate 13. The bottom surface of the recess 37 is a flat surface. The upper surface 23 a of the second insulating film 23, the upper surface 31 a of the first embedded insulating film 31, the upper surface 33 a of the liner film 33, and the second embedded insulating film 35. It is comprised by the upper surface 35a.

The recess 37 is a groove for disposing the metal film 39, the other metal film 41, and the first etching stopper film 46, and is formed so as to expose the side surfaces 38c and 38d of the silicide layer 38.
When actually forming a memory cell, as shown in FIGS. 4A and 4B, which will be described later, the concave portion 37 has side surfaces 26-1a of the upper ends 26-1 of the plurality of pillars 26 on which the metal films 39 are formed. 26-1b, 26-1c, and 26-1d are formed to be exposed. The metal film 39 is a film for forming the silicide layer 38 on the upper ends 26-1 of the plurality of pillars 26.
The side surface 26-1a is a part of the side surface 26a of the pillar 26, and the side surface 26-1b is a part of the side surface 26b of the pillar 26. The side surface 26-1c is a part of the side surface 26c of the pillar 26, and the side surface 26-1d is a part of the side surface 26d of the pillar 26.

Thus, by providing the recessed part 37 which exposes the side surfaces 26-1a, 26-1b, 26-1c, 26-1d of the upper ends 26-1 of the plurality of pillars 26 on which the metal films 39 are formed, By changing the depth, the thickness of the silicide layer 38 can be easily controlled, and variations in the thickness of the silicide layers 38 formed on the plurality of pillars 26 can be reduced.
The depth of the concave portion 37 when the main surface 13a of the semiconductor substrate 13 is used as a reference can be set to 50 nm, for example.

Referring to FIGS. 2A and 2B, the silicide layer 38 is formed on the upper end 26-1 of the pillar 26 exposed from the recess 37 and surrounded by the metal film 39.
The upper surface 38 a of the silicide layer 38 is substantially flush with the main surface 13 a of the semiconductor substrate 13 and is in contact with the lower electrode 71 serving as the capacitor 52. Further, the lower surface 38 b of the silicide layer 38 is in contact with the upper impurity diffusion region 36. Thereby, the silicide layer 38 electrically connects the lower electrode 71 of the capacitor 52 and the upper impurity diffusion region 36.
The silicide layer 38 is a layer for reducing the contact resistance between the capacitor 52 and the upper impurity diffusion region 36.

The silicide layer 38 is formed by reacting silicon contained in the upper end 26-1 of the pillar 26 with a metal described later contained in the metal film 39, whereby the upper end 26-1 of the pillar 26 is silicided.
As the silicide layer 38, a titanium silicide layer (specifically, a TiSi ₂ layer or the like), a cobalt silicide layer, or the like can be used.

As the silicide layer 38, a TiSi ₂ layer may be used. The TiSi ₂ layer has the lowest electrical resistance among the silicide layers, and is stable even when a natural oxide film (silicon oxide film (SiO ₂ film)) is formed on the surface of the polycrystalline silicon and the upper impurity diffusion region. This is because the phase reaction proceeds (Ti reacts by reducing the silicon oxide film).
The thickness of the silicide layer 38 is equal to the depth value of the recess 37, and can be set to, for example, 50 nm.

Referring to FIGS. 2A and 2B, the metal film 39 is provided on the inner wall of the recess 37, and a first metal film 67 and a second metal film 68 are sequentially stacked. .
The first metal film 67 covers the upper surface 23a of the second insulating film 23, the upper surface 31a of the first buried insulating film 31, and the upper surface 33a of the liner film 33 so as to cover the side surfaces 38c and 38d of the silicide layer 38. Has been placed.
The upper surface 67 a of the first metal film 67 is substantially flush with the upper surface 38 a of the silicide layer 38. The upper surface 67 a of the first metal film 67 is in contact with the lower electrode 71 of the capacitor 52. Thereby, the first metal film 67 is electrically connected to the lower electrode 71.

  The first metal film 67 is a film containing a metal that forms the silicide layer 38 by reacting with silicon contained in the upper end 26-1 of the pillar 26. That is, the first metal film 67 is formed by silicidizing the upper end 26-1 of the pillar 26 by heat during the formation of the first metal film 67, thereby forming the silicide layer 38 on the upper end 26-1 of the pillar 26. It is a film for forming. Therefore, the silicide layer 38 is formed only in a portion surrounded by the first metal film 67. The first metal film 67 can be formed by a CVD method.

  As described above, the concave portion 37 exposing the upper end 26-1 of the pillar 26 is provided, and the first metal film 67 containing a metal that reacts with silicon is formed so as to cover the side surface of the upper end 26-1 of the pillar 26. Accordingly, the silicide layer 38 can be formed only in the region surrounded by the first metal film 67. As a result, a sufficient distance is ensured between the silicide layer 38 and the gate electrodes 61 and 62 to suppress occurrence of a short circuit between the gate electrodes 61 and 62 and the semiconductor substrate 13, and the thickness is increased. In addition, the silicide layer 38 having a uniform thickness can be provided, and variations in the thickness of the silicide layers 38 formed on the plurality of pillars 26 can be reduced.

As the first metal film 67, for example, a titanium (Ti) film, a cobalt (Co) film, or the like can be used. When a titanium (Ti) film is used as the first metal film 67, a TiSi ₂ layer can be formed as the silicide layer 38.
When a titanium (Ti) film is used as the first metal film 67, the thickness of the first metal film 67 in the direction orthogonal to the side surfaces 38c and 38d of the silicide layer 38 can be set to 7 nm, for example. .

  The second metal film 68 is provided on the upper surface 31 a of the first buried insulating film 31 and the upper surface 33 a of the liner film 33 so as to cover the outer peripheral side surface 67 b of the first metal film 67. The upper surface 68 a of the second metal film 68 is in contact with the lower electrode 71. As a result, the second metal film 68 is electrically connected to the lower electrode 71.

The second metal film 68 is preferably a film that can improve the adhesion between the first metal film 67 and the other metal film 41. As the second metal film 68, for example, a titanium nitride (TiN) film or a laminated film in which a titanium (Ti) film and a titanium nitride (TiN) film are sequentially laminated can be used.
When a titanium nitride (TiN) film is used as the second metal film 68, the thickness of the second metal film 68 in the direction orthogonal to the side surfaces 38c and 38d of the silicide layer 38 is, for example, 5 nm. it can.
As shown in FIG. 1, the metal film 39 configured as described above has a shape surrounding a silicide layer 38 formed on the pillar 26.
In this embodiment, as an example, a case where a titanium (Ti) film is used as the first metal film 67 and a titanium nitride (TiN) film is used as the second metal film 68 is described as an example. Will be explained.

2A and 2B, another metal film 41 is formed on the upper surface 31a of the first buried insulating film 31 and the upper surface 33a of the liner film 33 so as to cover the outer peripheral side surface 68b of the second metal film 68. Is provided.
The other metal film 41 is disposed in the recess 37 together with the metal film 39. The other metal film 41 is a film having a lower resistance value than the metal film 39. The upper surface of the other metal film 41 is in contact with the lower electrode 71. Thereby, the other metal film 41 is electrically connected to the lower electrode 71.

As the other metal film 41, for example, a tungsten (W) film can be used. When a tungsten (W) film is used as the other metal film 41, the thickness of the other metal film 41 in the direction orthogonal to the side surfaces 38c and 38d of the silicide layer 38 can be set to 10 nm, for example.
As shown in FIG. 1, the other metal film 41 configured as described above has a shape surrounding a silicide layer 38 formed on the pillar 26 with a metal film 39 interposed therebetween.

2A and 2B, the first etching stopper film 46 includes an upper surface 38a of the silicide layer 38, an upper surface 67a of the first metal film 67, an upper surface 68a of the second metal film 68, and other metals. The upper surface 41a of the film 41 is formed so as to cover a surface that is not in contact with the lower electrode 71 and to bury the concave portion 37 in which the metal film 39 and the other metal film 41 are formed. Thereby, the first etching stopper film 46 covers the outer peripheral side surface 41 b of the other metal film 41. The upper surface of the first etching stopper film 46 is a flat surface.
A silicon nitride film (SiN film) is used as the first etching stopper film 46. In this case, the thickness of the first etching stopper film 46 can be set to, for example, 50 nm.
The first interlayer insulating film 47 is provided on the first etching stopper film 46. A silicon oxide film (SiO ₂ film) is used as the first interlayer insulating film 47. In this case, the thickness of the first interlayer insulating film 47 can be set to 400 nm, for example.

  The second etching stopper film 48 is provided on the first interlayer insulating film 47. A silicon nitride film (SiN film) is used as the second etching stopper film 48. In this case, the thickness of the second etching stopper film 48 can be set to, for example, 50 nm.

The support film 51 is disposed above the second etching stopper film 48. As the support film 51, a silicon nitride film (SiN film) is used. The support film 51 is in contact with the outer peripheral side surface 57a on the upper end side of a plurality of lower electrodes 71 described later. As a result, the support film 51 connects the plurality of lower electrodes 71.
As shown in FIG. 2B, the support film 51 has a through-hole 76 formed therein. The through portion 76 is an inlet for an etching solution for removing a second interlayer insulating film 78 shown in FIGS. 11A and 11B described later by wet etching. In the semiconductor device 10, the second interlayer insulating film 78 is formed in a peripheral circuit region (not shown).

By removing the second interlayer insulating film 78, a space 77 is formed between the second etching stopper film 48 and the support film 51. The distance between the support film 51 and the second etching stopper film 48 is equal to the thickness of the second interlayer insulating film 78 shown in FIGS. 11A and 11B, and can be, for example, 900 nm.
Further, the thickness of the support film 51 can be set to 100 μm, for example. In FIG. 2B, only one through portion 76 is shown, but actually, a plurality of through portions 76 are formed in the support film 51.

The capacitors 52 are MIM capacitors, and one capacitor 52 is provided for each of the plurality of pillars 26. That is, the memory cell array 11 has a plurality of capacitors 52.
The capacitor 52 includes one lower electrode 71, a capacitor insulating film 72 (in other words, a capacitor insulating film common to the plurality of lower electrodes 71) formed so as to extend over the plurality of lower electrodes 71, and a capacitor insulating film. And an upper electrode 73 covering the surface of 72 (in other words, an upper electrode common to the plurality of lower electrodes 71).
The lower electrode 71 has a crown shape. The lower electrode 71 is connected to the other lower electrode 71 by the support film 51. A metal film is used as the lower electrode 71. Specifically, as the lower electrode 71, for example, a laminated film in which a titanium (Ti) film and a titanium nitride (TiN) film are sequentially laminated may be used. The bottom of the lower electrode 71 is connected to the upper surface 39 a of the metal film 39.

  Thus, by connecting the bottom part of the lower electrode 71 made of a metal film and the metal film 39, the bottom part of the lower electrode 71 is connected to the outer peripheral part of the silicide layer 38 and the metal film 39. The contact resistance between the capacitor 52 and the upper impurity diffusion region 36 can be reduced as compared with the case where the bottom portion of the capacitor contacts only the center of the upper surface 38 a of the silicide layer 38.

The bottom of the lower electrode 71 is connected to the upper surface 41 a of another metal film 41 disposed so as to cover the outer peripheral side surface 68 b of the second metal film 68.
In this way, the upper surface 41a of the other metal film 41, which is disposed so as to cover the outer peripheral side surface 68b of the second metal film 68 and has a lower resistance value than the metal film 39, and the bottom of the lower electrode 71 made of the metal film are formed. By connecting, the contact resistance between the capacitor 52 and the upper impurity diffusion region 36 can be further reduced.

The capacitor insulating film 72 includes inner surfaces of the plurality of lower electrodes 71, outer peripheral side surfaces 71 a of the plurality of lower electrodes 71 positioned between the second etching stopper film 48 and the support film 51, and upper surfaces of the second etching stopper film 48. 48 a, the upper surface 51 a and the lower surface 51 b of the support film 51, and the side surface of the support film 51 constituting the through portion 76.
As the capacitor insulating film 72, for example, a laminated film in which an aluminum oxide film (Al ₂ O ₃ film) and a zirconium oxide film (ZrO ₂ film) are sequentially laminated can be used.

The upper electrode 73 is provided so as to cover the surface of the capacitive insulating film 72, and fills the plurality of lower electrodes 71, the through portions 76, and the spaces 77 through the capacitive insulating film 72.
The upper surface 73a of the upper electrode 73 is a flat surface. As the upper electrode 73, a metal film such as a ruthenium (Ru) film, a tungsten (W) film, a titanium nitride (TiN) film, a polycrystalline silicon film, or the like can be used.

The third interlayer insulating film 53 is provided on the upper surface 73 a of the upper electrode 73. As the third interlayer insulating film 53, for example, a silicon oxide film (SiO ₂ film) can be used.
The wiring 55 is provided on the third interlayer insulating film 53. The wiring 55 is electrically connected to the upper electrode 73 disposed in the lower layer.
The fourth interlayer insulating film 56 is provided on the third interlayer insulating film 53 so as to cover the wiring 55. As the fourth interlayer insulating film 56, for example, a silicon oxide film (SiO ₂ film) can be used.

  According to the semiconductor device of the present embodiment, the gate electrodes 61 and 62 provided on the side surfaces 26 a and 26 b of the pillar 26 and the silicide layer formed on the upper end 26-1 of the pillar 26 via the gate insulating film 27. 38 and the gate electrodes 61 and 62, and is disposed so as to surround the side surfaces 26a, 26b, 26c, and 26d of the pillar 26 and exposes the side surfaces 38c and 38d of the silicide layer 38 (specifically, An insulating film composed of the second insulating film 23, the first buried insulating film 31, and the liner film 33) and the side surfaces 38 c and 38 d of the silicide layer 38, and the upper end 26-of the pillar 26 1 is an upper impurity diffusion region formed in the pillar 26 so as to be in contact with the metal film 39 for siliciding silicon contained in 1 and the lower surface 38b of the silicide layer 38. 36 and the capacitor 52 provided on the upper surface 38a of the silicide layer 38, the silicide layer 38 can be formed only in the portion surrounded by the metal film 39. Therefore, the silicide layer 38 and the gate are formed. The distance between the electrodes 61 and 62 is sufficiently secured to suppress the occurrence of a short circuit between the gate electrodes 61 and 62 and the semiconductor substrate 13, and the thickness is increased to be uniform. A silicide layer 38 may be provided.

  Thereby, even when the diameter of the cylinder hole is small, the contact resistance between the lower electrode 52 and the upper impurity diffusion region 36 can be reduced.

3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, and 11A 11B, FIG. 12A, FIG. 12B, FIG. 13A, FIG. 13B, FIG. 14A, FIG. 14B, FIG. 15A, and FIG. 15B show the manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment of the present invention. FIG.
3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A are cuts of the memory cell array 11 shown in FIG. 2A. It is sectional drawing corresponding to a surface.

3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, and 15B show the memory cell array 11 shown in FIG. 2B. It is sectional drawing corresponding to a cut surface.
3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, and 11A 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, and 15B, the same components as those in the memory cell array 11 shown in FIGS. 2A and 2 are denoted by the same reference numerals. .

  Next, FIGS. 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, and 10B. 11A, 11B, 12A, 12B, 13A, 13B, 4A, 14B, 15A, and 15B, the semiconductor device 10 according to the embodiment of the present invention (specifically Next, a method for manufacturing the memory cell array 11) will be described.

First, in the process shown in FIGS. 3A and 3B, an element isolation trench (not shown) is formed in a semiconductor substrate 13 containing silicon (Si), and then the element isolation insulating film is embedded. By forming (silicon oxide film (SiO ₂ film)), an element isolation region (not shown) is formed. Thus, an element formation region (active region) disposed inside the element isolation region is formed.
As the semiconductor substrate 13, for example, a p-type silicon substrate can be used. Hereinafter, a case where a p-type silicon substrate is used as the semiconductor substrate 13 will be described as an example.

  Next, a hard mask (not shown) made of a silicon nitride film is formed on the main surface 13a of the semiconductor substrate 13 by photolithography and dry etching. Next, the main surface 13a of the semiconductor substrate 13 is partially etched by dry etching using the hard mask (not shown) as a mask, thereby forming a plurality of bit line forming grooves 15 extending in the Y direction. To do. Next, the first insulating film 16 is formed so as to cover the surface corresponding to the formation region of the bit line 21 among the inner surfaces of the plurality of bit line forming grooves 15. At this stage, the opening 16 </ b> A is not formed in the first insulating film 16.

  Next, a polycrystalline silicon film (not shown) containing arsenic (As) so as to bury the bit line forming groove 15 at a position lower than the formation region of the opening 16A through the first insulating film 16. ). Next, a portion of the first insulating film 16 corresponding to the formation region of the bit contact 18 is selectively etched to form an opening 16A that exposes the semiconductor substrate 13.

Next, a plurality of bit line forming grooves are formed by growing a polycrystalline silicon film (not shown) containing arsenic (As) on a polycrystalline silicon film (not shown) containing arsenic (As). 15 is embedded.
Next, the polycrystalline silicon film (not shown) containing arsenic (As) formed in the plurality of trenches 15 for bit line formation is removed by etch back, and arsenic (As) is contained only in the opening 16A. By leaving the polycrystalline silicon film (not shown), a bit contact 18 made of a polycrystalline silicon film (not shown) containing arsenic (As) is formed in the opening 16A.

Next, a conductive film serving as a base material of the bit line 21 is formed by an CVD method in an atmosphere heated to a predetermined temperature (for example, 650 ° C.). Specifically, a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film are sequentially stacked as a conductive film that becomes a base material of the bit line 21.
At this time, arsenic (As) contained in the bit contact 18 is thermally diffused into the semiconductor substrate 13 corresponding to the formation region of the pillar 26 due to heat at the time of forming the conductive film. As a result, the lower impurity diffusion region 19 is formed in a portion corresponding to the side wall of the pillar 26.
Next, the conductive film is etched back to leave the conductive film at the bottom of the bit line forming groove 15, thereby forming the bit line 21 extending in the Y direction.

Next, a second insulation that covers the upper surface 21a of the bit line 21 and the side surface of the bit line forming groove 15 positioned above the bit line 21 (in other words, part of the side surfaces 26c and 26d of the plurality of pillars 26). A film 23 is formed. For example, a SiON film can be used as the second insulating film 23.
Next, a coating type silicon oxide film (SiO ₂ film) (not shown) is applied by SOG (Spin On Glass) method so as to fill the bit line forming groove 15, and then the coating type silicon oxide film By etching back the (SiO ₂ film), the coating-type silicon oxide film (SiO ₂ film) remains only in the bit line forming groove 15 corresponding to the formation region of the connection portion 65.
Then, by HDP (High Density Plasma) method, by forming a silicon oxide film of coating type silicon oxide film to be buried bit lines forming grooves 15 located (SiO ₂ film) on (SiO ₂ film), a One buried insulating film 31 is formed.

Next, the main surface 13a of the semiconductor substrate 13 is partially etched to form a plurality of word line forming grooves 25 that intersect the bit line forming grooves 15 and extend in the X direction. The word line forming groove 25 is formed by the same method as the bit line forming groove 15 described above. At this time, the word line forming groove 25 is formed so as to completely expose a coating type silicon oxide film (not shown) formed by the SOG method.
As a result, a plurality of pillars 26 made of the semiconductor substrate 13 containing silicon and surrounded by the bit line forming grooves 15 and the word line forming grooves 25 are formed. In other words, the pillars 26 are formed by partially etching the main surface 13 a of the semiconductor substrate 13.

  Next, a coating type silicon oxide film (not shown) is selectively removed by wet etching. Thereafter, a gate insulating film 27 is formed to cover the inner surface of the word line forming groove 25 (specifically, the bottom surface 25a of the word line forming groove 25 and the side surfaces 26a and 26b of the plurality of pillars 26).

Examples of the gate insulating film 27 include a single-layer silicon oxide film (SiO ₂ film), a film obtained by nitriding a silicon oxide film (SiON film), a stacked silicon oxide film (SiO ₂ film), and a silicon oxide film (SiO ₂ ). A laminated film in which a silicon nitride film (SiN film) is laminated on ( _two films) can be used.

Next, a conductive film serving as a base material of the word line 29 is formed by CVD so as to fill the bit line forming groove 15 and the word line forming groove 25 corresponding to the formation region of the connection portion 65.
Specifically, by sequentially forming a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film, the titanium (Ti) film, the titanium nitride (TiN) film, and the tungsten ( W) A conductive film made of a film is formed.
As a result, a plurality of connection portions 65 made of the conductive film are formed in the bit line forming groove 15. At this time, an electrode end connection portion 63 (see FIG. 1) not shown is also formed at the same time.
Next, the conductive film formed in the word line formation groove 25 is etched back, and the thickness of the conductive film remaining in the word line formation groove 25 is set to a predetermined thickness. The conductive film remaining in the word line forming trench 25 serves as a base material for the pair of gate electrodes 61 and 62.

Next, a groove 32 having a width smaller than that of the word line forming groove 25 and extending in the X direction and dividing the conductive film remaining in the word line forming groove 25 into two in the word line forming groove 25. Form.
As a result, gate electrodes 61 are formed on the side surfaces 26 a of the plurality of pillars 26 via the gate insulating film 27, and gate electrodes 62 are formed on the side surfaces 26 b of the plurality of pillars 26 via the gate insulating film 27. The
That is, at this stage, the word line 29 including the electrode end connection portion 63, the connection portion 65, and the pair of gate electrodes 61 and 62 extending in the X direction is formed.

Next, the liner film 33 is formed on the gate electrodes 61 and 62 so as to be in contact with the gate insulating film 27. As the liner film 33, for example, a SiON film can be used.
Next, the word line forming trench 25 and the trench 32 are filled with the second buried insulating film 35. As the second buried insulating film 35, a coated silicon oxide film (SiO ₂ film) formed by the SOG method may be used.
Next, a hard mask (mask used when forming the bit line forming groove 15) (not shown) is removed. Thereby, the upper end surfaces of the plurality of pillars 26 (main surface 13a of the semiconductor substrate 13) are exposed.

Next, arsenic (As) is doped as n-type impurities on the upper end surfaces 26-1e of the plurality of pillars 26 (the main surface 13a of the semiconductor substrate 13), and then, thermal diffusion of the arsenic (As) is performed. An upper impurity diffusion region 36 is formed in the upper part of the pillar 26 (including the upper end 26-1 of the pillar 26).
At this stage, an upper impurity diffusion region 36 is also formed at the upper end 26-1 of the pillar 26. In the process shown in FIGS. 5A and 5B described later, a silicide layer 38 is formed, thereby forming FIG. An upper impurity diffusion region 36 shown in FIG. 2B is formed.

Thereafter, portions of the insulating film (specifically, the first buried insulating film 31, the liner film 33, and the second buried insulating film 35) protruding from the upper end surfaces 26-1e of the plurality of pillars 26 are polished. As shown in FIGS. 3A and 3B, a structure with a flattened upper surface is formed.
As a result, the side surfaces 26a, 26b, 26c, and 26d of the pillar are surrounded by the gate insulating film 27 and the insulating films that cover the gate electrodes 61 and 62 (in this case, the second insulating film 23 and the first buried insulating layer). Film 31, liner film 33, and second buried insulating film 35).

4A and 4B, the second insulating film 23, the first embedded insulating film 31, the liner film 33, the insulating film made of the second embedded insulating film 35, and the gate insulating film 27 are formed. Etching back forms the recesses 37 that expose the side surfaces 26-1a, 26-1b, 26-1c, 26-1d of the upper ends 26-1 of the plurality of pillars 26 in which the upper impurity diffusion regions 36 are formed.
At this time, the bottom surface of the recess 37 constituted by the upper surface 23 a of the second insulating film 23, the upper surface 31 a of the first buried insulating film 31, the upper surface 33 a of the liner film 33, and the upper surface 35 a of the second buried insulating film 35. However, etch back is performed so that a flat surface is obtained.

The recess 37 is formed so that the depth C of the recess 37 is equal to the desired thickness of the silicide layer 38. In this way, by setting the depth of the recess 37, it is possible to accurately form the metal film 39 (film that forms the silicide layer 38 by reacting with silicon) in the region where the silicide layer 38 is to be formed. As a result, the thickness of the silicide layer 38 can be easily controlled, and variations in the thickness of the silicide layers 38 formed on the plurality of pillars 26 can be reduced.
The depth C of the concave portion 37 with respect to the main surface 13a of the semiconductor substrate 13 can be set to, for example, 50 nm.

5A and 5B, the side surfaces 26-1a, 26-1b, 26-1c, 26-1d and the upper end surface 26-1e of the upper end 26-1 of the pillar 26 shown in FIGS. 4A and 4B are formed. A metal film 39 made of the first and second metal films 68 and 68 is formed so as to cover the metal contained in the first metal film 67 and the silicon contained in the upper end 26-1 of the pillar 26. By reacting, a silicide layer 38 is formed on the upper end 26-1 of the pillar 26 surrounded by the first metal film 67 in the upper impurity diffusion region 36 shown in FIGS. 4A and 4B.
As a result, the lower surface 38 b of the silicide layer 38 is in contact with the upper impurity diffusion region 36. That is, the silicide layer 38 and the upper impurity diffusion region 36 are electrically connected.

Specifically, in an atmosphere heated to a predetermined temperature (for example, 650 ° C.) by a CVD method, the side surfaces 26-1a, 26-1b, 26-1b of the upper end 26-1 of the pillar 26 shown in FIGS. 4A and 4B, 26-1c and 26-1d and the upper end surface 26-1e are covered with a titanium (Ti) film (for example, a thickness of 7 nm) as the first metal film 67, and a titanium (Ti) film is formed. By reacting titanium (Ti) contained in the titanium (Ti) film with silicon (Si) contained in the upper end 26-1 of the pillar 26 by heat at the time of film formation, the upper end 26-1 of the pillar 26 is caused to react. A TiSi ₂ layer is formed as the silicide layer 38.

At this time, the first metal film 67 is formed on the entire top surface of the structure shown in FIGS. 4A and 4B. In other words, the first metal film 67 is also formed on the bottom surface of the recess 37.
In practice, most of the portion of the titanium (Ti) film that is in contact with the upper end 26-1 of the pillar 26 is silicided to form a TiSi ₂ layer.
Further, by forming the silicide layer 38, the vertical transistor including the bit contact 18, the lower impurity diffusion region 19, the gate insulating film 27, the gate electrodes 61 and 62, and the upper impurity diffusion region 36 in the plurality of pillars 26. 66 (also referred to as “three-dimensional transistor”) is formed.

  As described above, the insulating films (second insulating film 23, first buried insulating film) that surround the gate electrodes 61 and 62 while surrounding the side surfaces 26a, 26b, 26c, and 26d of the pillar 26 with the gate insulating film 27 interposed therebetween. 31, the liner film 33, and the second buried insulating film 35), and then the gate insulating film 27 and the insulating film are etched back to form the pillar in which the upper impurity diffusion region 36 is formed. 26, the side surfaces 26-1a, 26-1b, 26-1c, and 26-1d of the upper end 26-1 are exposed, and then the side surfaces 26-1a, 26-1b, 26-1c, and the upper end 26-1 of the pillar 26 are exposed. A metal film 39 is formed so as to cover 26-1d and the upper end surface 26-1e, and a metal (for example, titanium (Ti)) included in the metal film 39 is reacted with silicon included in the upper end of the pillar 26. In the upper impurity diffusion region 36, only the upper end 26-1 of the pillar 26 surrounded by the metal film 39 is formed by forming the silicide layer 38 on the upper end 26-1 of the pillar 26 surrounded by the metal film 39. Since the silicide layer 38 can be formed on the gate electrode 61, a sufficient distance between the silicide layer 38 and the gate electrodes 61 and 62 can be secured to prevent a short circuit between the gate electrodes 61 and 62 and the semiconductor substrate 13. It is possible to form the silicide layer 38 having a large thickness and a uniform thickness while suppressing the generation.

Further, as the silicide layer 38, a TiSi ₂ layer having a resistance lower than that of other silicide layers (for example, WSi ₂ layer) is formed, so that the contact resistance is reduced as compared with the case where other silicide layers are used. Can be lowered.
Note that a cobalt (Co) film may be formed as the first metal film 67 instead of the titanium (Ti) film. In this case, a cobalt silicide layer is formed as the silicide layer 38.

Next, after forming the first metal film 67 and the silicide layer 38, a second metal film 68 covering the surface of the first metal film 67 is formed. Specifically, a titanium nitride (TiN) film (for example, a thickness of 5 nm) is formed as the second metal film 68 by a CVD method.
Note that a stacked film in which a titanium (Ti) film and a titanium nitride (TiN) film are sequentially stacked may be formed as the second metal film 68 instead of the titanium nitride (TiN) film.

  6A and 6B, another metal having a lower resistance value than that of the metal film 39 so as to cover the surface of the metal film 39 (specifically, the surface 68a of the second metal film 68). A film 41 is formed. Specifically, a tungsten (W) film (for example, a thickness of 10 nm) is formed as the other metal film 41 by the CVD method.

Next, in the process shown in FIGS. 7A and 7B, the metal film 39 and the other metal film 41 shown in FIGS. 6A and 6B are etched back to form the upper surface 38a of the silicide layer 38 and the bottom surface of the recess 37. By selectively removing the metal film 39 and the other metal film 41, the metal film 39 and the other metal film 41 are left so as to cover the side surfaces 38c and 38d of the silicide layer 38.
As a result, the metal film 39 and the other metal film 41 having the sidewall shape and surrounding the side surfaces 38c and 38d of the silicide layer 38 (the metal film 39 and the other metal film 41 shown in FIGS. 2A and 2B described above). ) Is formed.

By the etch back, the upper surface 39a of the metal film 39 (the upper surfaces 67a and 68a of the first and second metal films 68 and 68) and the upper surface 41a of the other metal film 41 after the etch back are the upper surface 38a of the silicide layer 38. It becomes flush with.
Next, a planar transistor (not shown) is formed as a peripheral circuit transistor in a peripheral circuit region (not shown) by a known method.

  Next, the upper surface 38a of the silicide layer 38, the upper surface 67a of the first metal film 67, the upper surface 68a of the second metal film 68, and the upper surface 41a of the other metal film 41 are covered, and the metal film 39 and the other metal film are covered. A first etching stopper film 46 is formed so as to fill the recess 37 in which 41 is formed. As a result, the outer peripheral side surface 41 b of the other metal film 41 is covered with the first etching stopper film 46. The first etching stopper film 46 is formed by depositing a silicon nitride film (SiN film) having a thickness of 50 nm.

  The first etching stopper film 46 is formed by anisotropic etching (specifically, dry etching), a second etching stopper film 48, first and second interlayer insulating films 47 and 78, which are interlayer insulating films, And it functions as an etching stopper film when the cylinder hole 79 (see FIGS. 9A and 9B) penetrating the support film 51 is formed.

  8A and 8B, the first interlayer insulating film 47 and the second etching stopper film 48 (etching stopper film) are formed on the first etching stopper film 46 shown in FIGS. 7A and 7B. Then, the second interlayer insulating film 78 and the support film 51 are sequentially formed.

Specifically, for example, a silicon oxide film (SiO ₂ film) having a thickness of 400 nm as the first interlayer insulating film 47, and a silicon nitride film (SiN film) having a thickness of 50 nm as the second etching stopper film 48, A silicon oxide film (SiO ₂ film) having a thickness of 900 nm is formed as the second interlayer insulating film 78 and a silicon nitride film (SiN film) having a thickness of 100 nm is sequentially formed as the support film 51.

  The second etching stopper film 48 is formed when the second interlayer insulating film 78 formed in the memory cell region is removed by wet etching in the process shown in FIGS. 12A and 12B described later. It has a function of preventing the structure (for example, the first interlayer insulating film 47 and the vertical transistor 66) disposed below 48 from being etched. That is, the second etching stopper film 48 functions as a stopper film at the time of wet etching.

Further, the second etching stopper film 48 connects the lower portions of the plurality of lower electrodes 71, so that the second interlayer insulating film 78 formed in the memory cell region in the process shown in FIGS. 12A and 12B described later. When the is removed, the plurality of lower electrodes 71 are connected.
In addition, the through-hole 76 shown in FIG. 2B described above is not yet formed in the support film 51 at this stage. That is, the support film 51 shown in FIGS. 8A and 8B is a film that is not patterned.

  Next, in the process shown in FIGS. 9A and 9B, the support film 51, the second interlayer insulating film 78, the second etching stopper film 48, and the first film are formed by anisotropic etching (specifically, dry etching). By etching the interlayer insulating film 47 and the first etching stopper film 46, the cylinder hole 79 exposing the upper surface 36a of the upper impurity diffusion region 36, the upper surface 39a of the metal film 39, and the upper surfaces 41a of the other metal films 41 is exposed. Form.

  Specifically, an opening (not shown) that exposes the upper surface 51a of the support film 51 corresponding to the formation region of the cylinder hole 79 on the upper surface 44a of the support film 51 shown in FIGS. 8A and 8B by photolithography. A photoresist (not shown) having is formed.

Next, as a first step, a second etching stopper film 48 made of a support film 51 and a silicon nitride film (SiN film), and first and second interlayer insulating films 47 made of a silicon oxide film (SiO ₂ film). The first and second interlayer insulating films 47 and 78, the support film 51, and the second etching stopper film 48 are dry-etched using the same etching conditions. A first hole (through the first interlayer insulating film 47 and the second etching stopper film 48 and having a bottom surface located between the second etching stopper film 48 and the first etching stopper film 46 ( A plurality of (not shown) are formed. The first hole is a hole that becomes a part of the cylinder hole 79.

Next, as a second step, there is a selection ratio with respect to the conditions for selectively etching the first interlayer insulating film 47 made of the silicon oxide film (SiO ₂ film) (in other words, the silicon nitride film (SiN film)). The first interlayer insulating film 47 is dry etched until the upper surface of the first etching stopper film 46 is exposed.
Thereby, a formation region of a first hole (not shown) and a plurality of second holes (not shown) formed below the first hole and deeper than the first hole are formed. To do.

  Next, as a third step, the upper surface 36 a of the upper impurity diffusion region 36 and the upper surface 39 a of the metal film 39 are used under the condition of selectively etching the first etching stopper film 46 made of a silicon nitride film (SiN film). The first etching stopper film 46 is dry-etched until the upper surface 41a of the other metal film 41 is exposed.

Thereby, a formation region of a second hole (not shown) and a plurality of cylinder holes 79 formed below the second hole and deeper than the second hole are formed.
The cylinder hole 79 is a hole in which the lower electrode 71 is formed, and is formed so as to expose the upper surface 36 a of the upper impurity diffusion region 36, the upper surface 39 a of the metal film 39, and the upper surfaces 41 a of the other metal films 41. Thereafter, the photoresist (not shown) is removed.

The thickness of the first etching stopper film 46 is 50 nm, the thickness of the first interlayer insulating film 47 is 400 nm, the thickness of the second etching stopper film 48 is 50 nm, and the thickness of the second interlayer insulating film 78 is When the thickness of the support film 51 is 900 nm and the diameter R of the cylinder hole 79 can be set to 60 nm, for example. In this case, the depth D of the cylinder hole 79 can be 1500 nm.
When the cylinder hole 79 is formed, a guard wall groove (not shown) having a ring shape surrounding the memory cell region is formed. The guard wall groove is formed so as to penetrate at least the support film 51, the second interlayer insulating film 78, and the second etching stopper film 48.

  Next, in the process shown in FIGS. 10A and 10B, the inner surface of the cylinder hole 79 is covered and the lower electrode 71 made of a metal film is formed with a crown shape. Thereby, the bottom of the lower electrode 71 is connected to the upper surface 36 a of the upper impurity diffusion region 36, the upper surface 39 a of the metal film 39, and the upper surfaces 41 a of the other metal films 41. Accordingly, the lower electrode 71 is electrically connected to the upper impurity diffusion region 36, the metal film 39, and the other metal film 41.

Thus, by connecting the bottom of the lower electrode 71 made of a metal film and the upper surface 39a of the metal film 39, the bottom of the lower electrode 71 is connected to the outer periphery of the silicide layer 38 and the metal film 39. Compared with the case where the bottom of the lower electrode 71 is in contact with only the center of the upper surface 38a of the silicide layer 38, the contact resistance between the capacitor 52 and the upper impurity diffusion region 36 can be reduced.
Further, the contact resistance between the capacitor 52 and the upper impurity diffusion region 36 is obtained by connecting the bottom of the lower electrode 71 made of a metal film and the upper surface 41a of another metal film 41 having a resistance value lower than that of the metal film 39. Can be further reduced.

  Specifically, the lower electrode 71 includes a titanium (Ti) film covering the inner surface of the cylinder hole 79 and a surface of the titanium (Ti) film from the upper surface side of the structure shown in FIGS. 9A and 9B by CVD. A covering titanium nitride (TiN) film is sequentially formed. Next, the plurality of cylinder holes 71 formed with the titanium (Ti) film and the titanium nitride (TiN) film are filled with a photoresist, and then the support film 51 is formed by anisotropic etching (specifically, dry etching). A plurality of lower electrodes 71 are formed by removing unnecessary titanium (Ti) films and titanium nitride (TiN) films formed on the upper surface 51a. Thereafter, the photoresist is removed.

10A and 10B, a titanium (Ti) film and a titanium nitride (TiN) film are formed on the inner surface of the guard wall groove (not shown), and the guard wall groove (not shown) is formed. The titanium (Ti) film and the titanium nitride (TiN) film are left on the inner surface. The titanium (Ti) film and titanium nitride (TiN) film formed in the guard wall groove (not shown) function as a guard wall (not shown).
In the step shown in FIGS. 12A and 12B, which will be described later, the guard wall is formed by removing the second interlayer insulating film 78 formed in the memory cell region with an etching solution when the second interlayer insulating film 78 formed in the peripheral circuit region is removed. It has a function of preventing the etching solution from reaching the interlayer insulating film 78.

  Next, in the step shown in FIGS. 11A and 11B, a through-hole 76 exposing the second interlayer insulating film 78 formed below the support film 51 is formed in the support film 51 shown in FIGS. 10A and 10B. Thus, the support film 51 shown in FIG. 2B is formed in contact with the outer peripheral surfaces 71 a at the upper ends of the plurality of lower electrodes 71 and connecting the plurality of lower electrodes 71.

Specifically, the through portion 76 is an opening that exposes the upper surface 51a of the support film 51 corresponding to the formation region of the through portion 76 on the upper surface 51a of the support film 51 illustrated in FIGS. 10A and 10B by photolithography. A photoresist (not shown) having (not shown) is formed, and then the upper surface of the second interlayer insulating film 78 is formed by anisotropic etching (specifically, dry etching) using the photoresist as a mask. The support film 51 is etched until it is exposed. Thereafter, the photoresist (not shown) is removed.
In FIG. 11A and FIG. 11B, only one through-hole 76 is shown, but in the process shown in FIGS. 11A and 12B, a plurality of through-holes 76 are actually formed.

Next, in the process shown in FIGS. 12A and 12B, wet that can selectively etch the second interlayer insulating film 78 on the second interlayer insulating film 78 formed in the memory cell region through the through portion 76. By supplying the etching solution, the second interlayer insulating film 78 surrounded by the guard wall (not shown) is selectively removed. Thereby, a space 77 is formed between the second etching stopper film 48 and the support film 51.
As the wet etching solution, an etching solution for selectively etching a silicon oxide film (SiO ₂ film) (in other words, an etching solution having a selection ratio with respect to the second etching stopper film 48 and the support film 51) is used. . Specifically, for example, hydrofluoric acid (HF) is used as the wet etching solution.

The space 77 includes an upper surface 48 a of the second etching stopper film 48, a lower surface 51 b of the support film 51, and outer peripheral side surfaces 71 a of the plurality of lower electrodes 71 positioned between the second etching stopper film 48 and the support film 51. And an inner wall of a guard wall (not shown) is formed to be exposed.
At this time, since the stopper film 23 prevents the wet etching solution from penetrating into the lower layer of the memory cell region 11, the first interlayer insulating film 47, the already formed transistor (for example, the vertical transistor 66), etc. Will not be damaged.

Next, in the process shown in FIGS. 13A and 13B, the space 77 is partitioned from the upper surface side of the structure shown in FIGS. 12A and 12B by the ALD (Atomic Layer Deposition) method through the penetrating portion 76. A capacitor insulating film 72 covering the surface to be formed is formed.
As a result, the capacitive insulating film 72 includes a plurality of upper surfaces 48 a of the second etching stopper film 48, upper and lower surfaces 51 a and 51 b of the support film 51, and a plurality of portions located between the second etching stopper film 48 and the support film 51. The lower electrode 71 is formed to cover the outer peripheral side surface 71a.
As the capacitor insulating film 72, for example, a laminated film made of an aluminum oxide film (Al ₂ O ₃ film) and a zirconium oxide film (ZrO ₂ film) can be used.

14A and 14B, from the upper surface side of the structure shown in FIGS. 13A and 13B, the surface of the capacitive insulating film 72 is covered by the CVD method through the penetrating portion 76, and the space 77 is formed. A conductive film to be filled is formed.
The conductive film is a film that becomes a base material of the upper electrode 73, and for example, a metal film such as a ruthenium (Ru) film, a tungsten (W) film, a titanium nitride (TiN) film, or a polycrystalline silicon film is used. be able to.

Next, the conductive film is polished by a CMP (Chemical Mechanical Polishing) method to form the upper electrode 73 made of the conductive film and having a flat upper surface 73a.
As a result, a capacitor 52 (MIM capacitor) including the lower electrode 71, the capacitor insulating film 72, and the upper electrode 73 is formed on the upper impurity diffusion region 36. The capacitor 52 is electrically connected to the upper impurity diffusion region 36, the metal film 39, and the other metal film 41.

  Further, a space exposing the upper surface 48 a of the second etching stopper film 48, the lower surface 51 b of the support film 51, and the outer peripheral side surfaces 71 a of the plurality of lower electrodes 71 between the second etching stopper film 48 and the support film 51. 77, and then a capacitor insulating film 72 is formed to cover the surface defining the space 77, and then an upper electrode 73 that fills the space 77 is formed on the surface of the capacitor insulating film 72. Can be increased.

15A and 15B, a third interlayer insulating film 53 is formed on the upper surface 73a of the upper electrode 73. The third interlayer insulating film 53 can be formed by a CVD method. As the third interlayer insulating film 53, a silicon oxide film (SiO ₂ film) is used.

Next, a wiring 55 that is electrically connected to the upper electrode 73 is formed on the third interlayer insulating film 53 by a known method. Next, a fourth interlayer insulating film 56 is formed on the third interlayer insulating film 53 so as to cover the wiring 55. The fourth interlayer insulating film 56 can be formed by a CVD method. As the fourth interlayer insulating film 56, a silicon oxide film (SiO ₂ film) is used. Thereby, the semiconductor device 10 of the present embodiment is manufactured.

  According to the semiconductor device manufacturing method of the present embodiment, the upper impurity diffusion region 36 is formed on the pillar 26 including the upper end 26-1 of the pillar 26, and then the pillar 26 is formed via the gate insulating film 27. An insulating film that surrounds the side surfaces 26a, 26b, 26c, and 26d and covers the gate electrodes 61 and 62 (specifically, the second insulating film 23, the first buried insulating film 31, the liner film 33, and the second film) (Insulating film composed of the buried insulating film 35) is formed, and then the gate insulating film 27 and the insulating film are etched back, whereby the side surfaces 26-1a, 26-1b, 26 of the upper end 26-1 of the pillar 26 are obtained. -1c, 26-1d are exposed, and then a metal film 39 is formed to cover the side surfaces 26-1a, 26-1b, 26-1c, 26-1d and the upper end surface 26-1e of the upper end 26-1 of the pillar 26. do it, By reacting a metal (for example, titanium (Ti)) contained in the metal film 39 with silicon (Si) contained in the upper end 26-1 of the pillar 26, the upper end 26- of the pillar 26 surrounded by the metal film 39 is reacted. 1 is formed, and the metal film 39 formed on the upper surface 38a of the silicide layer 38 is selectively removed. Thereafter, the metal film 39 is left only on the side surfaces 38c and 38d of the silicide layer 38. Next, the capacitor 52 is formed on the silicide layer 38 so as to be in contact with the upper surface 39a of the metal film 39 remaining on the upper surface 38a of the silicide layer 38 and the side surfaces 38c and 38d of the silicide layer 38, thereby being surrounded by the metal film 39. Since the silicide layer 38 can be formed only on the upper end 26-1 of the pillar 26, the distance between the silicide layer 38 and the gate electrodes 61 and 62 is reduced. The sufficiently secured, on which suppresses the occurrence of short circuit between the gate electrodes 61 and 62 and the semiconductor substrate 13, thick thick, and can form a uniform thickness and silicide layer 38.

  Thereby, even when the diameter of the cylinder hole is small, the contact resistance between the lower electrode 52 and the upper impurity diffusion region 36 can be reduced.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

For example, in the present embodiment, the case where the upper surface 39a of the metal film 39 and the upper surface 41a of the other metal film 41 are connected to the bottom of the lower electrode 71 has been described as an example, but at least the metal film 39 is configured. It is only necessary that the upper surface 67a of the first metal film 67 to be connected to the bottom of the lower electrode 71.
In the present embodiment, the case where another metal film 41 is provided has been described as an example. However, when the area of the upper surface 39a of the metal film 39 is sufficiently large (between the capacitor 52 and the upper impurity diffusion region 36). When the contact resistance between them can be sufficiently reduced), it is not necessary to provide another metal film 41.

  The present invention is applicable to a semiconductor device and a manufacturing method thereof.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 11 ... Memory cell array, 13 ... Semiconductor substrate, 13a ... Main surface, 15 ... Bit line formation groove, 16 ... First insulating film, 16A ... Opening, 18 ... Bit contact, 19 ... Lower impurity Diffusion region, 21... Bit line, 21a, 23a, 31a, 33a, 35a, 38a, 39a, 41a, 51a, 67a, 68a, 73a ... upper surface, 23 ... second insulating film, 25 ... word line forming groove, 25a ... bottom surface, 26 ... pillar, 26-1 ... upper end, 26a, 26b, 26c, 26d, 26-1a, 26-1b, 26-1c, 26-1d, 38c, 38d ... side surface, 26-1e ... upper end surface 27 ... Gate insulating film, 29 ... Word line, 31 ... First buried insulating film, 32 ... Groove, 33 ... Liner film, 35 ... Second buried insulating film, 36 ... Upper impurity diffusion region, 37 ... Recess 38 ... Silicide layer, 38b, 51b ... Lower surface, 39 ... Metal film, 41 ... Other metal films, 41b, 67b, 68b ... Outer side surface, 46 ... First etching stopper film, 47 ... First interlayer insulating film 48 ... second etching stopper film, 51 ... support film, 52 ... capacitor, 53 ... third interlayer insulating film, 55 ... wiring, 56 ... fourth interlayer insulating film, 61, 62 ... gate electrode, 63 ... Electrode end connection part, 65 ... connection part, 66 ... vertical transistor, 67 ... first metal film, 68 ... second metal film, 68a ... surface, 71 ... lower electrode, 71a ... outer peripheral side surface, 72 ... capacitive insulation Membrane, 73 ... upper electrode, 76 ... penetration, 77 ... space, 78 ... second interlayer insulating film, 79 ... cylinder hole, C, D ... depth, R ... diameter

Claims (17)

Pillars provided on a semiconductor substrate containing silicon (Si) and using the semiconductor substrate as a base material;
A silicide layer formed on an upper end of the pillar;
A metal film provided so as to cover a side surface of the silicide layer and silicidating silicon (Si) included in an upper end of the pillar;
A gate electrode provided on a side surface of the pillar located below the silicide layer via a gate insulating film;
An insulating film that covers the gate electrode and surrounds the side surface of the pillar located below the silicide layer and exposes the silicide layer and the metal film;
An upper impurity diffusion region disposed in the pillar so as to be in contact with the lower surface of the silicide layer;
A capacitor provided on the upper surface of the silicide layer;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the lower electrode serving as the capacitor is in contact with the upper surface of the silicide layer and the upper surface of the metal film. The metal film includes a titanium (Ti) film covering a side surface of the silicide layer,
The semiconductor device according to claim 1, wherein the silicide layer is a TiSi ₂ layer.   4. The semiconductor device according to claim 3, wherein the metal film has a titanium nitride (TiN) film covering an outer peripheral side surface of the titanium (Ti) film.   5. The device according to claim 2, further comprising: another metal film having a lower resistance value than the metal film, provided to cover an outer peripheral side surface of the metal film, and having an upper surface in contact with the lower electrode. A semiconductor device according to any one of the above.   6. The semiconductor device according to claim 5, wherein the other metal film is a tungsten (W) film.   A bit provided in the semiconductor substrate so as to be positioned below the gate electrode, electrically insulated from the semiconductor substrate, and extending in a direction intersecting with the extending direction of the gate electrode 7. The semiconductor device according to claim 1, further comprising a line.   8. The semiconductor device according to claim 7, further comprising a lower impurity diffusion region formed in a portion of the pillar located below the upper impurity diffusion region and electrically connected to the bit line. Forming a pillar by partially etching a semiconductor substrate containing silicon (Si);
Forming a gate electrode on a side surface of the pillar via a gate insulating film;
Forming an upper impurity diffusion region on an upper portion of the pillar including an upper end of the pillar;
Forming an insulating film that surrounds the side surface of the pillar through the gate insulating film and covers the gate electrode;
Etching back the gate insulating film and the insulating film to expose the upper side surface of the pillar in which the upper impurity diffusion region is formed among the side surfaces of the pillar;
By forming a metal film so as to cover the upper side surface of the pillar and the upper end surface of the pillar, the metal contained in the metal film reacts with silicon (Si) contained in the upper end of the pillar, A step of forming a silicide layer in a portion surrounded by the metal film in the upper impurity diffusion region;
Selectively removing the metal film formed on the upper surface of the silicide layer to leave the metal film only on the side surface of the silicide layer;
Forming a capacitor in contact with the upper surface of the silicide layer and the upper surface of the metal film remaining on the side surface of the silicide layer on the silicide layer;
A method for manufacturing a semiconductor device, comprising: With a CVD (Chemical Vapor Deposition) method, a titanium (Ti) film to be the metal film is formed so as to cover the side surface of the upper end of the pillar, and by the heat at the time of forming the titanium (Ti) film, The TiSi ₂ layer is formed as the silicide layer by reacting titanium (Ti) contained in the titanium (Ti) film with the silicon (Si) contained in the upper end of the pillar. 10. A method for manufacturing a semiconductor device according to 9. Before selectively removing the metal film, having a step of forming another metal film having a lower resistance than the metal film so as to cover the surface of the metal film;
When the metal film is selectively removed, the other metal film formed on the upper end surface of the pillar is selectively removed through the metal film, thereby forming a side surface of the silicide layer. 11. The method of manufacturing a semiconductor device according to claim 9, wherein the other metal film is left on the metal film. Forming an interlayer insulating film covering the upper surface of the silicide layer, the upper surface of the metal film, and the upper surface of the other metal film;
Forming a cylinder hole exposing the upper surface of the upper impurity diffusion region, the upper surface of the metal film, and the upper surface of the other metal film in the interlayer insulating film;
The method for manufacturing a semiconductor device according to claim 11, further comprising: forming a lower electrode to be the capacitor so as to cover an inner surface of the cylinder hole. In the step of forming the pillar, a plurality of the pillars are formed,
One lower electrode is formed for each of the plurality of pillars,
Forming an etching stopper film connecting the plurality of lower electrodes in the interlayer insulating film;
Forming a support film connecting upper ends of the plurality of lower electrodes on the interlayer insulating film,
13. The method of manufacturing a semiconductor device according to claim 12, wherein the cylinder hole is formed so as to penetrate the etching stopper film and the support film. After forming the lower electrode, the support film is formed with a penetrating portion that penetrates the support film,
The interlayer insulating film disposed between the support film and the etching stopper film is selectively removed by introducing an etching solution having a low etching rate for the etching stopper film and the support film from the through portion. 14. The method for manufacturing a semiconductor device according to claim 13, wherein a space exposing the upper surface of the etching stopper film, the lower surface of the support film, and the outer peripheral side surfaces of the plurality of lower electrodes is formed.   A capacitor insulating film to be the capacitor is formed so as to cover the inner surface of the lower electrode, the upper and lower surfaces of the support film, the outer peripheral side surface of the lower electrode exposed by the space, and the upper surface of the etching stopper film. The method of manufacturing a semiconductor device according to claim 14.   16. The method of manufacturing a semiconductor device according to claim 15, wherein an upper electrode serving as the capacitor is formed so as to cover the surface of the capacitive insulating film and fill the space. Forming a lower impurity diffusion region in a portion of the pillar located below the upper impurity diffusion region;
A bit line extending in a direction intersecting with the extending direction of the gate electrode and electrically connected to the lower impurity diffusion region is formed on the semiconductor substrate located below the gate electrode. Process,
The method of manufacturing a semiconductor device according to claim 9, further comprising:

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