JP2012038260A - Bus transfer system - Google Patents

Description

  The present invention relates to a bus transfer system in which a plurality of functional modules transfer data via a system bus.

  In industrial systems such as FA (factory automation) and PLC (programmable controller), a plurality of CPU modules and a plurality of input / output modules as shown in FIGS. 4 and 5 are connected to the system bus 01. There is known a bus transfer system for exchanging data between modules via the system bus.

Japanese Patent Laid-Open No. 9-73430

  For example, as an example of the data transfer method in the above-described bus transfer system, there is a parallel data transfer method. However, the parallel data transfer method has a limit in the data transfer speed, and the serial data transfer can be performed faster than the parallel data transfer. There is a tendency to adopt a data transfer method.

  However, the conventional bus transfer system described above uses a single protocol (data exchange method in a transfer cycle) negotiated in the system, so that each module transfers data, so different protocols (for example, Even if another module using the serial transfer system is mounted on the system bus, it is not compatible and data transfer is not possible.

For this reason, there is a problem that flexibility and expandability due to the expansion of the system are poor, and the improvement of the system performance is reached.
By the way, in general, a control device such as a PLC is mounted with a module for realizing a predetermined function in a bus connector 11 (slot) arranged on the system bus 01 as shown in FIG. In some cases, the module is not mounted on all of the bus connectors 11 and is shipped with an unmounted portion remaining.

  In a control system including a PLC, it is desired to extend a system life cycle by extending a system by incorporating new functions while inheriting existing functions. Therefore, in the future, it is expected that a module adopting the serial data transfer system will be mounted in the surplus slot and the control system will be expanded using the minimum necessary resources.

  The present invention has been made in consideration of such circumstances, and the purpose of the present invention is to realize different data transfer protocols on the same system bus, and to facilitate flexibility and expandability by adding a system. An object of the present invention is to provide a bus transfer system using a plurality of protocols.

As a method for solving the above problems, the present invention is configured as follows.
The invention according to claim 1 is a bus transfer system in which a plurality of stations transfer data via a system bus, the access cycle of the system bus, the arbitration cycle for determining the access right of the system bus, and the access that has acquired the access right It is divided into a transfer cycle in which the right acquisition station transfers data, and each of the plurality of stations determines the access right by a common arbitration protocol in the arbitration cycle, and the access right acquisition station that has acquired the access right through this arbitration protocol is: In the transfer cycle, data is transferred by a data transfer protocol defined in a group including predetermined stations including its own station.

  According to a second aspect of the present invention, in the bus transfer system according to the first aspect, the group is configured by a parallel transfer group configured by stations that perform parallel transfer or a serial transfer group configured by stations that perform serial transfer.

  The invention according to claim 3 is the bus transfer system according to claim 2, wherein the system bus has an address bus, and the serial transfer group includes a master station that has obtained the bus access right in the arbitration cycle, and the master station. The master station outputs address data to the address bus, designates the slave station, transmits a packet to the slave station, and transfers the data.

According to a fourth aspect of the present invention, in the bus transfer system according to the third aspect, the packet is configured not to include an address portion for designating a slave station.
According to a fifth aspect of the present invention, in the bus transfer system according to the second aspect, the signal line of the system bus used for the serial transfer is constituted by a part of the signal line of the system bus used for the parallel transfer. .

  According to the present invention, some signal lines of the conventional system bus have a plurality of functions so that a plurality of bus transfer protocols can coexist, thereby improving the performance of the bus transfer system and improving the life cycle. Can be extended.

Time chart showing data transfer according to the bus transfer system of the present invention 1 is an external view showing the configuration of a PLC that employs the bus transfer system of the present invention. The figure which shows the flow of the data on the system bus | bath which concerns on FIG. External view showing a typical PLC configuration example The figure which shows the flow of the data on the system bus | bath which concerns on FIG.

In the following drawings, the same reference numerals denote the same or corresponding parts.
FIG. 2 is an external view of a PLC adopting an example of the bus transfer system according to the present invention.
Reference numeral 10 denotes a base board on which the CPU module 20 (21, 22,... 2m), the memory module 30, and the input / output module 40 (41, 22,... 4n) are mounted. Reference numeral 11 denotes a bus connector provided on the base board 10 for connecting each of the modules 20, 30 and 40 to the base board 10.

  A system bus 01A for transferring data by these modules includes an arbitration bus 1, an address bus 2, a data bus 3, and a control bus 4A. In the control bus 4A, the read signal line RD * also serves as a serial data signal line S1 described later, and the write signal line WT * also serves as a serial data signal line S2 described later.

  FIG. 3 is a conceptual diagram showing the flow of transfer data on the system bus 01A. The CPU module 21 performs parallel data transfer with the memory module 30 and the input / output module 41 using the data bus 3. The CPU module 2m performs serial data transfer with the input / output module 4n using the serial data signals S1 and S2. Note that FIG. 3 does not show all the modules shown in FIG.

  FIG. 1 is a time chart when a master module such as the CPU module 20 accesses a slave module such as the memory module 30 and the input / output module 40 as shown in FIG. The CPU module 20 is configured to control a device by executing a user application at predetermined intervals while communicating with a slave module via the system bus 01A.

  In FIG. 1, Tarb is an arbitration cycle, Ttrf is a transfer cycle, and BSK is a bus clock. ARB * (* indicates a negative logic signal) is an arbitration start signal indicating the start of arbitration, ARBid * is an arbitration ID bus signal indicating a priority for acquiring a bus access right, and BSY * is a predetermined value. This is a busy signal indicating that the other module is using the bus. AD is an address bus (address bus signal), and DT is a data bus (data bus signal). RD * is a read signal and WT * is a write signal. Note that the read signal RD * also serves as a serial data signal S1 described later, and the write signal WT * also serves as a serial data signal S2 described later. RDY * is a ready signal indicating that data is ready for the data bus DT.

  The CPU module 21 has an arbitration ID of “1” (referred to as M1), the CPU module 22 has an arbitration ID of “2” (referred to as M2), and the CPU module 2m has an arbitration ID of “m” (referred to as an arbitration ID). (Referred to as Mm).

The arbitration ID has a higher priority when the numerical value is smaller. In this example, the CPU module 21 having the arbitration ID “M1” can obtain the bus access right with the highest priority.
First, read access from time t11 to t14 will be described. This read access is an example in which the CPU module 21 transfers data using the parallel data transfer protocol when accessing the input / output module 41.

  When detecting that the busy signal BSY * has become inactive, the CPU module 20 activates the arbitration start signal ARB * and outputs the arbitration ID. The CPU module 20 can read the arbitration ID output on the bus, and when the value has a higher priority than the arbitration ID of the own module, the CPU module 20 lowers the output of the arbitration ID of the own module. In this way, the master module with the lower priority lowers the arbitration ID, so that the arbitration ID of the master module with the highest priority remains on the bus. In this case, the CPU module 21 that has output the arbitration ID 'M1' at the fourth clock from the start of arbitration has acquired the bus access right. Note that four clocks are required from the start of arbitration to acquisition of the bus access right. This is in consideration of lime lag until the output signal of the CPU module whose arbitration ID is lowered is disabled.

  The CPU module 21 that has acquired the bus access right in this way activates the busy signal BSY * and enters the transfer cycle. In this transfer cycle Ttrf, the CPU module 21 outputs the address “0x1000” for designating the input / output module 41 that performs parallel transfer as the address signal AD, and activates the read signal RD *. When the input / output module 41 detects that the address matches that of its own module, it outputs data as the data signal DT and activates the ready signal RDY *. When the ready signal RDY * becomes active, the CPU module 21 takes in the data output as the data signal DT, deactivates the busy signal BSY *, and ends the parallel data transfer cycle.

  Next, the bus access period from time t21 to t24 will be described. Here, an example in which the CPU module 2m and the input / output module 4n perform serial data transfer by setting the read signal line RD * to the serial data signal line S1 and the write signal line WT * to the serial data signal line S2, respectively. Show.

  In the arbitration cycle Tarb from time t21 to t22, the CPU module 2m has obtained the bus access right. The CPU module 2m which has obtained the bus access right immediately sets the busy signal BSY * to active "L", and enters the serial data transfer cycle Ttrf.

At this time t22, the CPU module 2m continues to output “0xF000” as the address signal AD in order to designate the input / output module 4n.
The input / output module 4n designated by the address “0xF000” enters a preparation state for serial data transfer.

The CPU module 2m continues to transmit a command for read access or write access to the input / output module 4n.
In response to this command, data is transferred from the input / output module 4n to the CPU module 2m for read access and from the CPU module 2m to the input / output module 4n for write access.

  Then, at the time t23, the receiving-side module that has received the terminal part of the serial data transfer message outputs the ready signal RDY *. The CPU module 2m sets the busy signal BSY * to inactive “H” at time t24. In this way, the serial data transfer cycle Ttrf ends.

  In the bus transfer system including a plurality of data transfer protocols according to the present invention, the address space using the conventional parallel transfer protocol is assigned from 0x0000 to 0xEFFF, and the address space using the serial transfer protocol as a new protocol is changed from 0xF000. It is assigned to 0xFFFF. That is, the address space is divided into two and the transfer protocol to be used is divided.

  As described above, the present invention divides the system bus access cycle into an arbitration cycle for determining the access right of the system bus and a transfer cycle for transferring data by the station that has acquired the bus access right. In the arbitration cycle, the bus access right is determined by a common arbitration protocol for the master module that requests bus access. In the subsequent transfer cycle, parallel transfer is performed between modules that transfer data using the parallel transfer method, and serial transfer is performed between modules that transfer data using the serial transfer method.

  In serial transfer, the master module that has obtained the bus access right in the arbitration cycle outputs address data to the address bus, designates a slave module as a transmission destination, and transmits a packet toward the slave station. Therefore, this packet does not require an address (header) for designating the slave module. The amount of data handled by slave modules such as I / O modules is often only from a few bytes to a few tens of bytes, and since it is relatively small, transferring data while reducing the packet header dramatically increases the transfer efficiency of control data. It can be improved and further speedup can be expected.

01A System bus 1 Arbitration bus 2 Address bus 3 Data bus 4A Control bus ARB * Arbitration start signal line or arbitration start signal ARBid * Arbitration ID bus or arbitration ID bus signal BSY * Busy signal line or busy signal AD Address signal DT Data signal RD * Read signal line or read signal WT * Write signal line or write signal S1, S2 Serial data signal line or serial data signal RDY * Ready signal line or ready signal 10 Base board 11 Bus connector 20 (21 , 22,..., 2m) CPU module 30 Memory module 40 (41, 42,..., 4n) Input / output module

Claims (5)

In a bus transfer system in which multiple stations transfer data via the system bus,
The access cycle of the system bus is divided into an arbitration cycle for determining the access right of the system bus and a transfer cycle in which the access right acquisition station that has acquired the access right transfers data,
Each of the plurality of stations determines the access right by a common arbitration protocol in the arbitration cycle,
The access right acquiring station that has acquired the access right through the arbitration protocol transfers data using a data transfer protocol within a group including a plurality of predetermined stations including the own station in the transfer cycle. Bus transfer system. The bus transfer system according to claim 1, wherein
2. The bus transfer system according to claim 1, wherein the group is a parallel transfer group composed of stations that perform parallel transfer or a serial transfer group composed of stations that perform serial transfer. The bus transfer system according to claim 2,
The system bus has an address bus;
The serial transfer group is composed of a master station that has obtained a bus access right in the arbitration cycle, and a slave station that exchanges data with the master station.
The bus transfer system, wherein the master station outputs address data to the address bus to designate the slave station, and transmits a packet by transmitting a packet to the slave station. In the bus transfer system according to claim 3,
The bus transfer system, wherein the packet does not include an address part for designating the slave station. The bus transfer system according to claim 2,
The bus transfer system, wherein the signal line of the system bus used in the serial transfer is a part of the signal line of the system bus used in the parallel transfer.