JP2012033692A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

A mounting failure of a semiconductor device is suppressed.
A BGA (semiconductor device) 1 includes a semiconductor chip 2 having a surface 2a and an electrode pad (bonding pad) 2c formed on the surface 2a, and solder electrically connected to the electrode pad 2c of the semiconductor chip 2. Ball 10. The solder ball 10 includes a plurality of core balls 11 and a solder material 12 that covers the plurality of core balls 11. As a result, when the BGA 1 is mounted on the mounting board, the core ball 11 can be prevented from becoming a hindrance factor for the solder ball 10 to be deformed and submerged, so that mounting failure of the BGA 1 can be suppressed.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and relates to a technique effective when applied to a semiconductor device including a solder ball as an external terminal.

  Japanese Patent Laying-Open No. 2006-66865 (Patent Document 1) describes mounting a ball made of copper on a land via cream solder as a protruding electrode that is an external terminal of an electronic component.

  JP 2004-342959 A (Patent Document 2) discloses a ball (a copper core ball, a resin core) in which a core member is covered with a solder member on each of a semiconductor package (semiconductor device) and a substrate on which the semiconductor package is mounted. Balls) are formed and the balls are integrated by reflow.

Japanese Patent Laid-Open No. 2006-66865 JP 2004-342959 A

  There is a technique in which a solder ball made of a solder material formed in a ball shape is used as an external terminal of a semiconductor device. Further, there is a technique of using a solder ball having a core ball as a solder ball that is an external terminal. A solder ball with a core ball is advantageous in several respects compared to a solder ball without a core ball.

  For example, in the case of a solder ball in which a core ball mainly made of resin is covered with a solder material, the stress applied to the solder ball can be relieved by causing the core ball to function as a stress relieving member. This is advantageous in that the reliability of the electrical connection of the solder balls can be improved or the product life can be extended.

  In addition, for example, in the case of a solder ball in which a core ball made of a metal material having a higher electric conductivity than the solder material or a material having a higher heat transfer coefficient than the solder material is covered with the solder material, the electric resistance of the solder ball is reduced, the current This is advantageous in terms of measures against electromigration associated with an increase in density or improvement in heat dissipation.

  Therefore, the inventor of the present application has studied a technique of using a solder ball that covers a core ball with a solder material as an external terminal of a semiconductor device, and has found the following problems. That is, it has been found that mounting defects of the semiconductor device are likely to occur.

  For example, in a BGA (Ball Grid Allay) type semiconductor device in which a plurality of solder balls are arranged on a mounting surface of a wiring board, the tip height of the solder ball varies due to warping of the wiring board. If the solder ball does not have a core ball, the solder ball deforms and sinks in the reflow process for joining the terminal formed on the mounting board and the solder ball. Can be joined.

  However, when each solder ball has one core ball as in Patent Document 1 and Patent Document 2, the core ball included in the solder ball inhibits the above-described sinking and Bonding failure occurs in the solder ball of the part.

  The present invention has been made in view of the above problems, and an object thereof is to provide a technique for suppressing a mounting failure of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, a semiconductor device according to one embodiment of the present invention includes a semiconductor chip having a front surface, a bonding pad formed on the front surface, a back surface opposite to the front surface, and the bonding pad of the semiconductor chip. Solder balls to be connected. The solder balls include a plurality of core balls and a solder material that covers the plurality of core balls.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to one embodiment of the present invention, a mounting failure of a semiconductor device can be suppressed.

It is a top view which shows the internal structure of the surface side of the semiconductor device which is one embodiment of this invention. FIG. 2 is a plan view showing a structure on the back side of the semiconductor device shown in FIG. 1. It is sectional drawing along the AA line of FIG. It is an expanded sectional view of the B section of FIG. It is an expanded sectional view which shows the state which has arrange | positioned the cream solder on the several terminal of the mounting board | substrate which mounts the semiconductor device shown in FIG. 6 is an explanation schematically showing a state in which the semiconductor device shown in FIG. 3 is arranged on the mounting substrate shown in FIG. 5 and heat treatment is started. It is description which shows typically the state which the cream solder and solder ball shown in FIG. 6 integrated. It is explanatory drawing which shows the assembly flow of the semiconductor device which is one embodiment of this invention. It is a top view which shows the whole structure of the wiring board prepared by the board | substrate preparation process shown in FIG. FIG. 10 is an enlarged plan view showing a state in which a semiconductor chip is mounted on the wiring board shown in FIG. 9. It is an expanded sectional view along CC line of FIG. It is an enlarged plan view which shows the state which electrically connected the semiconductor chip and wiring board shown in FIG. 10 by wire bonding. It is an expanded sectional view which shows the state which electrically connected the semiconductor chip and wiring board shown in FIG. 11 by wire bonding. It is an expanded sectional view which shows the state which clamped the wiring board shown in FIG. 13 with a shaping die, and supplied sealing resin in the cavity. It is a top view which shows the state which took out the wiring board in which sealing resin was formed from the shaping die shown in FIG. It is sectional drawing along the DD line of FIG. FIG. 17 is an enlarged cross-sectional view illustrating a state in which a plurality of solder balls serving as external electrodes (external connection terminals) of the semiconductor device are formed (joined) on the lower surface of the wiring board illustrated in FIG. 16. FIG. 17 is an enlarged cross-sectional view showing a step of arranging a bonding material on the lower surface side of the wiring board shown in FIG. 16. FIG. 19 is an enlarged cross-sectional view showing a state where a plurality of solder balls are arranged on each land shown in FIG. 18. It is an expanded sectional view of the E section of FIG. FIG. 20 is an enlarged cross-sectional view showing a state where the mask shown in FIG. 19 is removed and then reversed and heat is applied to the solder balls. It is an expanded sectional view of the F section of FIG. It is an expanded sectional view which shows the state which cut | disconnected the wiring board shown in FIG. 17 with the dicing blade. It is explanatory drawing which shows typically the electrical test contained in the test | inspection process shown in FIG. FIG. 20 is an enlarged cross-sectional view illustrating a ball mounting process (solder ball arrangement process) according to an embodiment which is a modified example of FIG. 19, and a state in which a plurality of solder balls are arranged on the land illustrated in FIG. 18. It is an expanded sectional view of the G section of FIG. FIG. 26 is an enlarged cross-sectional view showing a state where the mask shown in FIG. 25 is reversed after being removed and heat is applied to the solder balls. It is an expanded sectional view which shows the modification of the core ball | bowl shown in FIG. It is an expanded sectional view which shows the internal structure of the solder ball which is other embodiment of this invention. FIG. 21 is an enlarged sectional view showing a modified example of the solder ball arrangement step shown in FIG. 20. FIG. 21 is an enlarged cross-sectional view showing another modification of the solder ball arrangement step shown in FIG. 20. FIG. 21 is an enlarged cross-sectional view showing another modification of the solder ball arrangement step shown in FIG. 20. It is a top view which shows the whole structure of the semiconductor device which is other embodiment of this invention. It is an expanded sectional view along the HH line of FIG. It is explanatory drawing which shows the assembly flow of the manufacturing method of the semiconductor device which is other embodiment of this invention. FIG. 36 is a plan view showing a plane on the main surface side of the semiconductor wafer prepared in the semiconductor wafer preparation step shown in FIG. 35; FIG. 37 is an enlarged cross-sectional view showing a partial cross-sectional structure of the semiconductor wafer shown in FIG. 36. FIG. 38 is an enlarged cross-sectional view showing a state where a rewiring layer is formed on the semiconductor wafer shown in FIG. 37. FIG. 39 is an enlarged cross-sectional view showing a first insulating film forming step in the step of forming the rewiring layer shown in FIG. 38. It is an expanded sectional view which shows a seed layer formation process among the processes which form the rewiring layer shown in FIG. FIG. 39 is an enlarged cross-sectional view showing a first resist film forming step in the step of forming the rewiring layer shown in FIG. 38. It is an expanded sectional view which shows a rewiring formation process among the processes which form the rewiring layer shown in FIG. It is an expanded sectional view which shows a seed layer removal process among the processes of forming the rewiring layer shown in FIG. FIG. 39 is an enlarged cross-sectional view showing a second insulating film forming step in the step of forming the rewiring layer shown in FIG. 38. FIG. 39 is an enlarged cross-sectional view showing a step of grinding the semiconductor wafer shown in FIG. 38. It is an expanded sectional view which shows the state which joined the solder ball to the land part shown in FIG. FIG. 35 is an enlarged cross-sectional view showing a modification of the semiconductor device shown in FIG. 34. FIG. 48 is an enlarged cross-sectional view showing a first resist film forming step in the step of forming the rewiring layer shown in FIG. 47. FIG. 48 is an enlarged cross-sectional view showing a rewiring forming step among the steps of forming the rewiring layer shown in FIG. 47. FIG. 48 is an enlarged cross-sectional view showing a second resist film forming step in the step of forming the rewiring layer shown in FIG. 47. FIG. 48 is an enlarged cross-sectional view showing a land portion forming step among the steps of forming the rewiring layer shown in FIG. 47. FIG. 48 is an enlarged cross-sectional view showing a second insulating film forming step in the step of forming the rewiring layer shown in FIG. 47. FIG. 35 is an enlarged cross-sectional view showing a modification of the semiconductor device shown in FIG. 34. It is explanatory drawing which shows the comparative example of FIG. It is explanatory drawing which shows the comparative example of FIG.

(Description format, basic terms, usage in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included. Moreover, even if it says gold plating, Cu layer, nickel / plating, etc., unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.

  In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  Moreover, in each figure of embodiment, the same or similar part is shown with the same or similar symbol or reference number, and description is not repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, hatching or a dot pattern may be added in order to clearly indicate that it is not a void or to clearly indicate the boundary of a region.

(Embodiment 1)
In the present embodiment, as an example of a semiconductor device, the present invention was specifically applied to a BGA type semiconductor device in which a plurality of solder balls are arranged on the back surface (mounting surface) side of a wiring board. The embodiment will be described.

<Overall structure of semiconductor device>
1 is a plan view showing an internal structure on the front surface side of a semiconductor device according to one embodiment of the present invention, FIG. 2 is a plan view showing a structure on the back surface side of the semiconductor device shown in FIG. 1, and FIG. It is sectional drawing along the AA of. FIG. 1 shows a state where the sealing resin 6 shown in FIG. 3 is removed. In FIGS. 1 and 2, the number of terminals of the semiconductor chip and the interposer substrate is reduced for easy viewing.

  1 to 3, a BGA 1 includes a surface (main surface, first main surface) 2a, a plurality of electrode pads (bonding pads, chip electrodes) 2c formed on the surface 2a, and a back surface opposite to the surface 2a. The semiconductor chip 2 having (main surface, second main surface) 2b is provided. Further, the BGA 1 has a plurality of solder balls 10 that are electrically connected to the plurality of electrode pads 2 c of the semiconductor chip 2.

  The electrical connection structure between the electrode pad 2c and the solder ball 10 in the present embodiment will be described below in detail with reference to FIG. The BGA 1 includes an upper surface (surface, chip mounting surface) 3a, a plurality of bonding leads 3c formed on the upper surface 3a, a lower surface (back surface, mounting surface) 3b opposite to the upper surface 3a, and a plurality of surfaces formed on the lower surface 3b. It has an interposer substrate (wiring substrate) 3 having lands (bump lands) 3d. The plurality of bonding leads 3c and the plurality of lands 3d are electrically connected via a plurality of wirings 3e included in the interposer substrate 3, respectively. Solder balls 10 that are external terminals of the BGA 1 are joined and electrically connected to the lands 3d. The BGA 1 has a plurality of wires (conductive members) 4 that electrically connect the plurality of electrode pads 2 c of the semiconductor chip 2 and the plurality of bonding leads 3 c of the interposer substrate 3, respectively. That is, the plurality of electrode pads 2 c and the plurality of solder balls 10 are electrically connected through the plurality of wires 4.

  Next, the semiconductor chip 2 will be described. The planar shape of the semiconductor chip 2 is, for example, a quadrangle as shown in FIG. A plurality of electrode pads 2c are formed on the surface 2a of the semiconductor chip 2, and in the present embodiment, the plurality of electrode pads 2c are formed along each side of the surface 2a. Although not shown, a plurality of semiconductor elements (circuit elements) are provided on the surface of the semiconductor chip 2 (specifically, a semiconductor element forming region provided on the upper surface of the base material (semiconductor substrate) of the semiconductor chip 2). The plurality of electrode pads 2c are formed by wiring (not shown) formed in a wiring layer disposed inside the semiconductor chip 2 (specifically, between the surface 2a and a semiconductor element formation region not shown). And is electrically connected to the semiconductor element. The semiconductor chip 2 (specifically, the base material of the semiconductor chip 2) is made of, for example, silicon (Si). In addition, an insulating film is formed on the surface 2a to cover the base material and wiring of the semiconductor chip 2, and each surface of the plurality of electrode pads 2c is formed from the insulating film in the opening formed in the insulating film. Exposed. The electrode pad 2c is made of metal, and in the present embodiment, is made of, for example, aluminum (Al). Further, a plating film is formed on the surface of the electrode pad 2c. In the present embodiment, for example, a multilayer structure in which a gold (Au) film is formed via a nickel (Ni) film is used. By covering the surface of the electrode pad 2c with a nickel film, corrosion (contamination) of the electrode pad 2c can be suppressed.

  Next, the interposer substrate 3 on which the semiconductor chip 2 is mounted will be described. As shown in FIG. 3, the interposer substrate 3 includes, for example, an epoxy resin material, or a core layer (core insulating layer) 3h made of a prepreg in which glass fiber or carbon fiber is impregnated with resin, and the upper surface side of the core layer. And a wiring layer formed on the lower surface side. The number of wiring layers is not limited to the two-layer structure shown in FIG. 3, and a wiring layer and an insulating layer can be repeatedly stacked to form a multi-layer structure. A two-layer structure in which one wiring layer is formed above and below the layer 3h will be described. A plurality of wirings 3e are formed in the wiring layer on the upper surface 3a side and the wiring layer on the lower surface 3b side, respectively. A plurality of wirings 3e on the upper surface 3a side are electrically connected to a plurality of bonding leads 3c. The plurality of wirings 3e on the lower surface 3b side are electrically connected to the plurality of lands 3d. The plurality of wirings 3e on the upper surface 3a side and the plurality of wirings 3e on the lower surface 3b side are electrically connected via a plurality of wirings (via wirings) 3e which are interlayer conductive paths formed so as to penetrate the core layer 3h. Has been.

  As shown in FIG. 1, the upper surface 3a of the interposer substrate 3 has a quadrangular planar shape. A plurality of bonding leads 3 c formed on the upper surface 3 a of the interposer substrate 3 are arranged around the semiconductor chip 2 along each side of the semiconductor chip 2. On the other hand, as shown in FIG. 2, the lower surface 3b of the interposer substrate 3 has a quadrangular planar shape. The plurality of lands 3d formed on the lower surface 3b of the interposer substrate 3 are arranged in a matrix (matrix). A solder ball 10 is bonded to each land 3d. That is, the BGA 1 is a so-called area array type semiconductor device in which the solder balls 10 (lands 3 d) as external connection terminals are arranged in a matrix on the lower surface 3 b of the interposer substrate 3. In such an area array type semiconductor device, the mounting surface side of the wiring board can be effectively used as an arrangement space for external terminals, so that an increase in the mounting area of the semiconductor device is suppressed even if the number of external terminals increases. It is preferable in that it can be performed. That is, a semiconductor device in which the number of external terminals increases with higher functionality and higher integration can be mounted in a space-saving manner. Although FIG. 2 shows an example of the number of 96 external terminals, the number of terminals and the layout are not limited to this. The detailed structure of the solder ball 10 will be described later.

  As shown in FIG. 3, the interposer substrate 3 has a solder resist film (insulating film) 3f formed on the upper surface 3a and a solder resist film (insulating film) 3g formed on the lower surface 3b. The solder resist film 3f is formed so as to cover the upper surface 3a side of the core layer (core insulating layer) 3h and the wiring 3e formed on the upper surface 3a. The bonding lead 3c is formed in the opening formed in the solder resist film 3f. The solder resist film 3f is exposed. The solder resist film 3g is formed so as to cover the wiring 3e formed on the lower surface 3b side of the core layer (core insulating layer) 3h, and the lands 3d are formed in a plurality of openings formed in the solder resist film 3g. The solder resist film 3g is exposed.

  Next, other structures of the BGA 1 will be described. As shown in FIG. 3, the semiconductor chip 2 is bonded and fixed to the upper surface 3 a of the interposer substrate 3 through an adhesive (die bond material) 5 with the back surface 2 b and the upper surface 3 a facing each other. That is, it is mounted by a so-called face-up mounting method. A plurality of electrode pads 2c formed on the surface 2a of the semiconductor chip 2 are connected to a plurality of bonding leads 3c arranged around the semiconductor chip 2 on the upper surface 3a of the interposer substrate 3 and a plurality of wires (conductive members). ) 4 are electrically connected to each other. The wire 4 is made of, for example, gold (Au) or copper (Cu), and a part (for example, one end) of the wire 4 is bonded to the electrode pad 2c, and the other part (for example, the other end) is bonded. Bonded to the bonding region of the lead 3c. Further, a sealing body (sealing resin) 6 is formed on the upper surface 3a side of the interposer substrate 3, and the semiconductor chip 2, the plurality of wires 4, and the bonding leads 3c are sealed (resin-sealed) with the sealing resin 6. Has been stopped). The sealing resin 6 is formed by adding a filler such as silica to an epoxy resin, for example, and protects the surface 2a of the semiconductor chip 2 and the wire 4 by resin sealing.

  1 to 3 show an example in which one semiconductor chip 2 is mounted on the interposer substrate 3 by a so-called face-up mounting method as an example of the BGA type semiconductor device. The mounting method is not limited to this. For example, a plurality of semiconductor chips can be stacked or arranged side by side. Further, for example, the semiconductor chip 2 can be mounted by a so-called face-down mounting (flip chip connection) method in which the surface 2a of the semiconductor chip 2 is mounted facing the upper surface 3a of the interposer substrate 3. In this case, the semiconductor chip 2 is formed on the surface of the electrode pad 2c via a bump electrode (projection electrode) made of, for example, gold (Au), for example, the upper surface 3a of the interposer substrate 3 (specifically, the semiconductor chip 2). It is electrically connected to a terminal (bonding lead) formed in a region facing the electrode pad 2c.

<Detailed structure around solder balls>
Next, the structure around the solder ball 10 shown in FIG. 3 will be described. 4 is an enlarged cross-sectional view of a portion B in FIG.

  As shown in FIG. 4, the BGA 1 of the present embodiment has a part (exposed portion) of the land 3d to which the solder ball 10 is joined from the solder resist film 3g in the opening 3k formed in the solder resist film 3g. Is exposed to a so-called SMD (Solder Mask Defined) structure land 3d. The structure of the land 3d in the present embodiment is not limited to this SMD structure, but the so-called NSMD (Non Solder Mask Defined) in which the surface and side surfaces of the land 3d to which the solder ball 10 is bonded are exposed from the solder resist film 3g. ) Structure land may be used. The land 3d is made of, for example, a copper (Cu) film 3d1, and a plating film 3d2 is laminated on the surface thereof. In the plating film 3d2, for example, a nickel (Ni) film and a gold (Au) film are sequentially laminated on the surface of the copper film 3d1. The plating film 3d2 of the present embodiment is not limited to this, and platinum (Pd) may be disposed between the nickel (Ni) film and the gold (Au) film. Specifically, the plating film 3d2 is laminated on the surface of the exposed portion of the copper film 3d1. The openings 3k are formed in a circular shape in plan view, and the arrangement pitch (center-to-center distance) between adjacent openings 3k (lands 3d) is, for example, 400 μm. Further, the opening diameter of the opening 3k is, for example, 220 μm.

  A solder ball 10 having a diameter of, for example, 250 μm is bonded to the exposed portion of the land 3d (specifically, the surface of the plating film 3d2). The diameter of the solder ball 10 is defined as follows. That is, the solder ball 10 is formed in a substantially spherical shape due to the surface tension of the solder material 12, but strictly speaking, as shown in FIG. 4, a part on the land 3d side is embedded in the opening 3k. Therefore, it is not a true sphere. Therefore, in the present application, as shown in FIG. 4, the largest width among the widths along the lower surface 3 b of the interposer substrate 3 is defined as the diameter W <b> 1 of the solder ball 10.

  Each solder ball 10 includes a plurality of core balls 11 and a solder material 12 covering the core balls 11. In the present embodiment, each solder ball 10 includes two core balls 11. The solder material 12 is made of so-called lead-free solder that does not substantially contain lead (Pb). For example, only the tin (Sn), tin-bismuth (Sn-Bi), tin-silver (Sn-Ag), Tin-copper-silver (Sn-Cu-Ag), tin-copper-silver-nickel (Sn-Cu-Ag-Ni), or the like. In this embodiment, the solder material 12 made of tin-copper-silver (Sn-Cu-Ag) is used. Here, the lead-free solder means a lead (Pb) content of 0.1 wt% or less, and this content is defined as a standard of the RoHs (Restriction of Hazardous Substances) directive.

  The plurality of core balls 11 includes a core material 11a made of resin and a metal film 11b formed on the surface of the core material 11a. The core material 11a is formed in a spherical shape, and is coated with a metal film 11b so as to cover the surface thereof. In the present embodiment, for example, the diameter of the core material 11a is about 70 μm to 80 μm, and the thickness of the metal film 11b coated around the core material is about 10 μm. That is, in the present embodiment, the diameter W2 of each of the core balls 11 is smaller than the radius (half of the diameter W1) of the solder ball 10 and is, for example, about 90 μm to 100 μm.

  As the resin material constituting the core material 11a, a commercially available material can be appropriately used as the core material disposed in the solder ball. In the present embodiment, after mounting the BGA 1 on a mounting substrate (not shown), a resin having a lower Young's modulus than the solder material 12 from the viewpoint of relaxing stress applied to the solder balls 10 by, for example, a temperature cycle. Material is used. Thereby, since the destruction tolerance of the solder ball 10 after mounting can be improved, the electrical connection reliability of the solder ball 10 can be improved. Alternatively, the product life of the BGA 1 can be extended by improving the temperature cycle resistance.

  In addition, the metal film 11b covering the core material 11a is used to improve the adhesion between the core ball 11 and the solder material 12, or to suppress an increase in electrical resistance and a decrease in heat dissipation of the solder ball 10 by the core material 11a made of resin. Formed from. In the present embodiment, the metal film 11b is mainly made of copper (Cu). Further, from the viewpoint of improving the adhesion between the copper film and the core material 11a, a nickel film thinner than the copper film is formed between the copper film and the core material 11a. Further, from the viewpoint of suppressing diffusion to copper at the contact interface with the solder material 12, a nickel film thinner than the copper film is formed outside the copper film. That is, the metal film 11b of the present embodiment is a laminated film in which, for example, a nickel film, a copper film, and a nickel film are laminated so as to cover the surface of the core material 11a.

<Semiconductor device mounting process>
Next, a process for mounting the BGA 1 of the present embodiment on the mounting substrate will be described. FIG. 5 is an enlarged cross-sectional view showing a state in which cream solder is disposed on a plurality of terminals of a mounting board on which the semiconductor device shown in FIG. 3 is mounted, and FIG. 6 shows the semiconductor shown in FIG. 3 on the mounting board shown in FIG. It is description which shows typically the state which has arrange | positioned an apparatus and started the heat processing. FIG. 7 is an explanatory view schematically showing a state where the cream solder and the solder ball shown in FIG. 6 are integrated. 54 is an explanatory diagram showing a comparative example of FIG. 6, and FIG. 55 is an explanatory diagram showing a comparative example of FIG.

  The mounting board 20 (see FIG. 5) on which the BGA 1 shown in FIG. 3 is mounted has a plurality of terminals (lands, mounting board terminals) 21 exposed on the mounting surface 20a, as shown in FIG. In the mounting process of mounting the BGA 1 (see FIG. 3) on the mounting substrate 20, a plurality of solder balls 10 (see FIG. 3) and a plurality of terminals 21 of the mounting substrate 20 are joined to each other to be electrically connected. To do. That is, the solder ball 10 shown in FIG. 3 is a mounting external terminal for joining with the mounting board terminal of the mounting board.

  The outline of the mounting process will be described below. In the mounting process, first, cream solder 22 is disposed on the plurality of terminals 21 as a bonding material for bonding the solder balls 10 (see FIG. 3) and the terminals 21 shown in FIG. The cream solder 22 is a paste containing metal particles (solder component) and a flux component, and is a bonding material for bonding the solder ball 10 (see FIG. 3) and the terminal 21. Flux is an organic compound that improves the bonding characteristics between solders or between solder and other metal materials. For example, it has a function of removing a metal oxide film to be bonded and preventing reoxidation of the metal surface, or a function of improving the surface activity of the solder, and can improve the wettability (bonding characteristics) of the solder. . As such a bonding material, in addition to the cream solder 22 including the solder component and the flux component, a flux material not including the solder component can be used as in the present embodiment. A so-called welcome solder mounting method in which cream solder is arranged and mounted on the terminal 21 will be described. The method of disposing the cream solder 22 on each of the plurality of terminals 21 is not particularly limited. For example, a method of applying by a printing method such as a screen printing method, a dispensing method of applying the cream solder 22 from a nozzle (not shown), Alternatively, a transfer system that transfers the cream solder 22 onto the terminal 21 using a transfer jig or the like can be used.

  Next, as shown in FIG. 6, after the BGA 1 is disposed on the mounting substrate 20, the mounting substrate 20 and the BGA 1 are subjected to heat treatment as a reflow process. In this step, the plurality of solder balls 10 of the BGA 1 and the plurality of terminals 21 of the mounting substrate 20 are arranged to face each other. When the cream solder 22 is heated, the flux component activates the surface of the terminal 21 and the surface of the solder ball 10 (region in contact with the flux component). Further, when the solder components of the cream solder 22 and the solder balls 10 are heated to such a degree that they melt, the solder balls 10 are deformed and sink, and all the solder balls 10 and the cream solder 22 are integrated. The solder material 23 (see FIG. 7) is formed, and the land 3d (see FIG. 3) of the BGA 1 and the terminal 21 of the mounting substrate 20 are joined and electrically connected via the solder material 23.

  Here, the case where the mounting process described above is applied to BGA 100 which is a comparative example of the present embodiment shown in FIGS. 54 and 55 will be described. The differences between the BGA 100 of the comparative example shown in FIGS. 54 and 55 and the BGA 1 of the present embodiment shown in FIG. 3 are the number of core balls arranged in the solder balls and the external dimensions. The point is similar. In the BGA 100 shown in FIGS. 54 and 55, each solder ball 101 has one core ball 102 therein. As with the core ball 11 shown in FIG. 4, the core ball 102 is formed with a metal film such as a copper film around the core material. However, the diameter of the core material is larger than the core material 11a shown in FIG. This is because, after the BGA 100 is mounted on the mounting substrate 20, for example, the stress applied to the solder ball 101 is relaxed by a temperature cycle. For example, in order to obtain the same stress relaxation effect as the two core balls 11 of the present embodiment shown in FIG. 4, the volume of the core ball 102 (see FIG. 54) needs to be increased, and the diameter is , About 20 μm to 25 μm larger than the core ball 11 shown in FIG.

  Even when the BGA 100 having the core ball 102 having a large diameter is used, each solder ball 101 can be joined to the terminal 21 as long as the apexes of the solder balls 101 are aligned. However, as shown in FIGS. 6 and 54, in a BGA type semiconductor device in which a semiconductor chip is mounted on a wiring board, such as the BGA 1 of the present embodiment or the BGA 100 of the comparative example, the wiring board is warped. easy. If it demonstrates in detail using FIG. 3, BGA1 will be comprised by the various member from which a linear expansion coefficient differs, such as a metal material, a resin material, or a semiconductor material. In particular, the linear expansion coefficient of the interposer substrate 3 shown in FIG. 3 is greatly different from that of the semiconductor chip 2 and the sealing resin 6 that seals the semiconductor chip 2. For this reason, the heat treatment in each process of manufacturing the BGA 1 may cause the BGA 1 to warp, and the flatness of the lower surface 3b may deteriorate. As a result, the positions of the vertices of the plurality of solder balls 10 vary, and the coplanarity (the uniformity of the flatness of the vertices of the terminals with respect to the mounting surface is defined by the difference in distance from the mounting surface to the vertices of each terminal. (The difference becomes larger). For the same reason, the coplanarity also decreases in the BGA 100 shown in FIG.

  For this reason, as shown in FIGS. 54 and 55, in the mounting process in which the BGA 100 having the core ball 102 having a large diameter is mounted on the mounting substrate 20, the following mounting defects occur. That is, as shown in FIG. 54, in the reflow process in which the mounting substrate 20 and the BGA 100 are heated, the amount of the solder material 12 disposed on the cream solder 22 side is smaller than that of the core ball 102. The amount of solder material 12 to be reduced is reduced. Further, the amount of sinking when the solder ball 101 is deformed and sinks is hindered by the core ball 102 having a large diameter, and is therefore smaller than that of the present embodiment. As a result, as shown in FIG. 54, the solder balls 101 that are far from the terminals 21 (for example, the solder balls 101 at both ends shown in FIG. 54) do not contact the cream solder 22, or the contact area becomes extremely small. If the solder ball 101 and the cream solder 22 do not contact each other, the solder ball 101 cannot be joined, resulting in poor joining (electrical connection failure). Further, when the contact area between the solder ball 101 and the cream solder 22 is small, the surface of the solder ball 101 cannot be sufficiently activated, and the solder components of the solder ball 101 and the cream solder 22 are not as shown in FIG. It becomes a state of poor wetting without being integrated. For this reason, the electrical connection reliability between the BGA 100 and the mounting substrate 20 is lowered.

  Further, as described in Patent Document 2, in a mounting method in which solder balls each having a single core ball are bonded to both a semiconductor device and a mounting substrate, and each solder ball is melted and bonded, a substantially spherical solder ball is used. Since it is necessary to contact each other, it is difficult to sufficiently activate the surface of each solder ball. For this reason, the solder component of each solder ball is not integrated, resulting in a poor wetting state. For this reason, the electrical connection reliability between the BGA 100 and the mounting substrate 20 is lowered.

<Preferred Embodiment of Solder Ball>
Next, based on the above-described problems, typical effects obtained by the configuration of the BGA 1 of the present embodiment shown in FIG. 4 and preferred embodiments will be described.

  First, the BGA 1 has a core ball 11 including a core material 11 a made of resin inside the solder ball 10. For this reason, as shown in FIG. 7, after mounting on the mounting substrate 20, the stress applied to the solder material 23 can be relieved by the core material 11a as a stress relieving member.

  Further, the BGA 1 has a plurality of core balls 11 inside the solder balls 10. For this reason, even if the diameter W2 of each core ball 11 is reduced as compared with a semiconductor device having one core ball in a solder ball, an equivalent stress relaxation effect can be obtained. And in BGA1, since the diameter W2 of the some core ball | bowl 11 can be made small, as shown in FIG. 6, the sinking amount of the softened solder ball | bowl 10 can be increased in a mounting process. For this reason, it is possible to suppress mounting failures such as the above-described bonding failure and wetting failure.

  Moreover, as shown in FIG. 4, it is preferable that the diameter W2 of each of the plurality of core balls 11 arranged in each solder ball 10 is uniform. For example, when the two core balls 11 are included in the solder ball 10 as in the present embodiment, it is preferable that the diameters W2 of the two core balls are approximately the same. By setting the diameters W2 of the two core balls 11 to be approximately the same, the amount of subsidence in the mounting process described above can be reliably increased. The fact that the diameters W2 of the plurality of core balls 11 are the same means that the diameters W2 are the same, and the allowable error can be defined in relation to the coplanarity of the BGA1. That is, when the positions of the apexes of the plurality of solder balls are varied in the height direction, it is preferable that the error of the diameter W2 of each core ball 11 is smaller than the largest difference in height. However, it is more preferable that the diameters W2 of the plurality of core balls 11 have the same length from the viewpoint of surely increasing the amount of sinking in the mounting process described above and maximizing the stress relaxation effect.

  Further, it is preferable that the diameter W2 of each of the plurality of core balls 11 is smaller than the radius of the solder ball 10. Thereby, for example, as in the present embodiment, when two core balls 11 are included in the solder ball 10, the entire surface of each core ball 11 can be covered with the solder material 12. Then, by covering the entire surface of each core ball 11 with the solder material 12, it is possible to suppress problems that occur when the core ball 11 is exposed from the solder material 12. For example, when a part of the core ball 11 is exposed in the vicinity of the apex of the solder ball 10, the solder material 12 is not sufficiently activated in the mounting process described above, which causes a wetting defect. be able to. Further, for example, when a part of the core ball 11 is exposed, surface oxidation proceeds from the exposed metal film 11b, which can be suppressed. As a modification of the present embodiment, for example, three solder balls 11 can be included in each solder ball 10. In this case, the diameter W2 of the core ball 11 is equal to the diameter W1 of the solder ball 10. It is preferable to make it smaller than 1/3.

  Further, it is preferable that the core balls 11 are arranged in the solder balls 10 so as to be close to the land 3d as shown in FIG. In other words, the center of each of the plurality of core balls 11 is preferably disposed on the land 3d side with respect to the center of the solder ball 10 (the center of the diameter W1). Thereby, in the mounting process described above, the amount of the solder material 12 arranged on the cream solder 22 (see FIG. 6) side relative to the core ball 11 can be increased, so that the sinking amount can be increased. Further, by increasing the amount of the solder material 12 disposed on the cream solder 22 (see FIG. 6) side than the core ball 11, the solder material 12 that comes into contact with the flux component of the cream solder 22 is increased, so that the wettability is increased. Can be improved. A method of placing the core ball 11 close to the land 3d in the solder ball 10 will be described later.

  Further, from the viewpoint of controlling the amount of the core material 11 a in each solder ball 10, each of the plurality of solder balls 10 preferably includes the same number of core balls 11. By controlling the amount of the core material 11a in each solder ball 10, the stress applied to the solder material 23 (see FIG. 7) after mounting can be surely alleviated. A method of making the number of core balls 11 included in each solder ball 10 equal will be described later.

  In this embodiment, an example in which two core balls 11 are included in each solder ball 10 has been described. However, the number of core balls 11 may be larger. However, when the number of the core balls 11 is increased, the diameter W2 of each core ball 11 is reduced, so that the stress relaxation effect is reduced. Therefore, the number of core balls 11 arranged in each solder ball 10 is particularly preferably two or three.

  Further, in the present embodiment, an example in which all the solder balls 10 have the core ball 11 has been described. However, among the plurality of lands 3d arranged on the lower surface 3b of the interposer substrate 3, the corner or the outermost The solder ball 10 having the core ball 11 may be used only for the solder ball bonded to the outer peripheral land. Thereby, the electrical characteristics can be improved while realizing the stress relaxation effect at the corners or the outermost periphery of the lower surface 3b of the interposer substrate 3 where the mounting stress is particularly likely to be applied.

<Manufacturing process of semiconductor device>
Next, a manufacturing process of the BGA 1 shown in FIGS. 1 to 4 will be described. The BGA 1 in the present embodiment is manufactured along the assembly flow shown in FIG. FIG. 8 is an explanatory diagram showing an assembly flow of the semiconductor device of the present embodiment. Details of each step will be described below with reference to FIGS.

1. Substrate Preparation Step First, as a substrate preparation step (S1) shown in FIG. 8, a wiring substrate 25 as shown in FIG. 9 is prepared. FIG. 9 is a plan view showing the entire structure of the wiring board prepared in the board preparation step shown in FIG.

  As shown in FIG. 9, the wiring board 25 prepared in this step includes a plurality of device regions 25a inside a frame portion (frame body) 25b. Specifically, a plurality of device regions 25a are arranged in a matrix. The number of device regions 25a is not limited to the mode shown in FIG. 9, but the wiring substrate 25 of the present embodiment has, for example, 16 device regions arranged in a matrix (2 rows × 8 columns in FIG. 9). 25a. That is, the wiring board 25 is a so-called multi-piece board having a plurality of device regions 25a.

  Each device region 25a corresponds to the interposer substrate 3 shown in FIG. Each device region 25a includes an upper surface (front surface, chip mounting surface) 3a shown in FIG. 3, a plurality of bonding leads 3c formed on the upper surface 3a, a lower surface (back surface, mounting surface) 3b opposite to the upper surface 3a, and a lower surface It has a plurality of lands (bump lands) 3d formed in 3b. The plurality of bonding leads 3c and the plurality of lands 3d are electrically connected via a plurality of wirings 3e included in the interposer substrate 3, respectively. The interposer substrate 3 has a solder resist film (insulating film) 3f formed on the upper surface 3a and a solder resist film (insulating film) 3g formed on the lower surface 3b. The solder resist film 3f is formed so as to cover the upper surface 3a side of the core layer (core insulating layer) 3h and the wiring 3e formed on the upper surface 3a. The bonding lead 3c is formed in the opening formed in the solder resist film 3f. The solder resist film 3f is exposed. The solder resist film 3g is formed so as to cover the wiring 3e formed on the lower surface 3b side of the core layer (core insulating layer) 3h, and the lands 3d are formed in a plurality of openings formed in the solder resist film 3g. The solder resist film 3g is exposed.

  Further, around each device region 25a, a dicing region (dicing line), which is a planned region for cutting the wiring board 25 in the singulation process (S7) shown in FIG. 8, is arranged. As shown in FIG. 9, the dicing area 25c is arranged so as to surround each device area 25a between the adjacent device areas 25a and between the frame portion 25b and the device area 25a.

2. Semiconductor Chip Preparation Step As the semiconductor chip preparation step (S2) shown in FIG. 8, the semiconductor chip 2 shown in FIG. 1 is prepared. In this step, for example, a semiconductor wafer made of a plurality of semiconductor elements and a wiring layer electrically connected thereto is prepared on the main surface side of a semiconductor wafer made of silicon (not shown). Thereafter, a dicing blade is run along the dicing line of the semiconductor wafer (not shown) to cut the semiconductor wafer to obtain a plurality of semiconductor chips 2 shown in FIG.

3. Die Bonding Step Next, the die bonding step (S3) shown in FIG. 8 will be described. 10 is an enlarged plan view showing a state in which a semiconductor chip is mounted on the wiring board shown in FIG. 9, and FIG. 11 is an enlarged cross-sectional view taken along the line CC in FIG.

  In this step, the semiconductor chip 2 is mounted (adhered) on a chip mounting region disposed on the upper surface 3a of each device region 25a of the wiring board 25. As shown in FIG. 11, in the present embodiment, the semiconductor chip 2 is mounted on the wiring substrate 25 via an adhesive (die bonding material) 5 so that the back surface 2 b of the semiconductor chip 2 faces the upper surface 3 a of the wiring substrate 25. (Face-up mounting). In the present embodiment, for example, an adhesive material 5 which is a tape material (film material) provided with an adhesive layer on both surfaces is attached in advance to the back surface 2b of the semiconductor chip 2, and the semiconductor chip 2 is bonded via the tape material. To do. Thereafter, for example, the thermosetting resin component contained in the adhesive 5 is thermoset and firmly fixed. The adhesive material 5 is not limited to a tape material. For example, the semiconductor chip 2 is mounted via a paste-like adhesive material 5 that is an epoxy thermosetting resin, and the semiconductor chip 2 is thermally cured to be bonded. You can also

4). Wire Bonding Step Next, the wire bonding step (S4) shown in FIG. 8 will be described. 12 is an enlarged plan view showing a state in which the semiconductor chip and the wiring board shown in FIG. 10 are electrically connected by wire bonding, and FIG. 13 is an electrical drawing of the semiconductor chip and the wiring board shown in FIG. 11 by wire bonding. It is an expanded sectional view which shows the state connected to.

  In this step, as shown in FIGS. 12 and 13, the wiring substrate 25 and the semiconductor chip 2 are electrically connected to each other via a plurality of wires (conductive members) 4. Specifically, a plurality of electrode pads 2c formed on the surface 2a of the semiconductor chip 2, a plurality of bonding leads 3c formed on the upper surface 3a side of the wiring substrate 25 and exposed from the solder resist film 3f, and a plurality of wires 4 are connected. Electrically connected to each other. In the present embodiment, wire bonding is performed by a so-called positive bonding method in which the electrode pad 2c of the semiconductor chip 2 is the first bond side and the bonding lead 3c of the wiring board 25 is the second bond side, and the electrode pad 2c and the bonding are performed. The lead 3c is electrically connected. In the present embodiment, the wire 4 is supplied by a so-called nail head bonding method in which the wire 4 is supplied through a capillary (not shown) and the wire 4 is bonded by using both ultrasonic waves and thermocompression bonding. ing.

  The conductive member that electrically connects the wiring substrate 25 and the semiconductor chip 2 is not limited to the wire 4. For example, a plate-shaped metal member can be used. For example, when using a so-called face-down mounting method (flip chip connection method) in which the front surface 2a side of the semiconductor chip 2 is mounted facing the upper surface 3a of the wiring substrate 25, for example, gold (Au A bump electrode can be used.

5. Sealing Step Next, the sealing step (S5) shown in FIG. 8 will be described. In the present embodiment, as an example of a sealing process, a manufacturing method called MAP (Mold Allay Process) in which a plurality of product forming regions are collectively covered with one cavity of a molding die and resin-sealed is described. To do. FIG. 14 is an enlarged cross-sectional view showing a state in which the wiring board shown in FIG. 13 is clamped with a molding die and a sealing resin is supplied into the cavity. 15 is a plan view showing a state in which the wiring board on which the sealing resin is formed is taken out from the molding die shown in FIG. 14, and FIG. 16 is a cross-sectional view taken along the line DD in FIG. .

  In this step, first, a molding die 30 shown in FIG. 14 is prepared (die preparation step). The molding die 30 includes a lower die (die surface) 31a, and an upper die (die) 31 having a cavity (recessed portion, hollow portion) 31b formed on the lower surface 31a, and a lower surface (die) of the upper die 31. A lower mold (mold) 32 having an upper surface (mold surface) 32 a facing the mold surface 31 a is provided. Next, the wiring board 25 is placed on the lower mold 32 of the molding die 30 (board placement step). Here, in the present embodiment, as shown in FIG. 14, a plurality of device regions 25a are arranged in one cavity 31b. Next, the distance between the upper mold 31 and the lower mold 32 is reduced, and the wiring board 25 is clamped with the upper mold 31 and the lower mold 32 (clamping process). As a result, in the clamp region around the cavity 31b, the upper mold 31 (the lower surface 31a of the upper mold 31) and the upper surface 3a of the wiring board 25 are in close contact. Further, the lower mold 32 (the upper surface 32a of the lower mold 32) and the lower surface 3b of the wiring substrate 25 are in close contact with each other. In addition, in order to improve the adhesiveness in a clamping process, the film which consists of soft resins, such as a polyimide resin, for example can be affixed on the lower surface 31a side of the upper metal mold 31, and it can also contact | adhere through this film. In this case, the film and the sealing resin 6 can be easily peeled off in a substrate take-out process described later.

  Next, the sealing resin 6a is supplied into the cavity 31b and cured to form the sealing resin (sealing body) 6 (sealing body forming step). In this step, a resin tablet (not shown) disposed in the pot portion (not shown) of the molding die 30 is heated and softened, and the sealing resin 6a is inserted into the cavity 31b from the gate portion (not shown). Is formed by a transfer mold method. By this step, the semiconductor chip 2 and the plurality of wires 4 mounted on the upper surface 3a side of the wiring substrate 25 are sealed with the sealing resin 6a. At this time, the bonding lead 3c of the wiring board 25 is also sealed. Thereafter, by heating the inside of the cavity 31b, the sealing resin 6a is heat-cured (temporarily cured) to form the sealing resin 6.

  Next, as shown in FIGS. 15 and 16, the wiring substrate 25 on which the sealing resin 6 is formed is taken out from the molding die 30 used in the sealing body forming step (substrate taking out step). In this step, the upper mold 31 and the lower mold 32 are separated to take out the wiring board 25. Next, the wiring board 25 shown in FIGS. 15 and 16 is transferred to a baking furnace (not shown), and the wiring board 25 is heat-treated again. The sealing resin 6a heated in the molding die 30 is in a so-called temporary curing state in which more than half (for example, about 70%) of the curing component in the resin is cured. In this temporarily cured state, not all of the cured components in the resin are cured, but more than half of the cured components are cured, and at this point, the semiconductor chip 2 and the wires 4 are sealed. . However, since it is preferable to completely cure all the curing components from the viewpoint of strength stability of the sealing resin 6, so-called main curing, in which the temporarily cured sealing resin 6 is heated again in the baking step. I do. As described above, the step of curing the sealing resin 6a is divided into two times, so that the next wiring substrate 25 to be transported to the molding die 30 can be quickly subjected to the sealing step. For this reason, manufacturing efficiency can be improved.

  By performing the above-described sealing step, as shown in FIG. 15, a collective sealing body 6 b that seals the plurality of device regions 25 a is formed.

6). Ball Mounting Step Next, the ball mounting step (S6) shown in FIG. 8 will be described. FIG. 17 is an enlarged cross-sectional view showing a state in which a plurality of solder balls serving as external electrodes (external connection terminals) of the semiconductor device are formed (joined) on the lower surface of the wiring board shown in FIG. Hereinafter, the process of forming the plurality of solder balls 10 shown in FIG. 17 will be described in detail.

  In this ball mounting process, first, as shown in FIG. 18, a flux material 35, which is a bonding material, is disposed on the surfaces (exposed surfaces) of a plurality of lands 3d formed on the lower surface 3b of the wiring board 25 (bonding). Material placement process). FIG. 18 is an enlarged cross-sectional view showing a step of arranging the bonding material on the lower surface side of the wiring board shown in FIG. At this time, the flux material 35 is disposed with the lower surface 3b of the wiring board 25 facing upward. In other words, the flux material 35 is disposed on the plurality of lands 3d of the wiring board 25 from above. As the bonding material, in addition to the flux material 35 shown in FIG. 18, cream solder can be used as described in the mounting process of the semiconductor device described above. However, when cream solder containing a solder component is used as the bonding material, the size of the solder balls 10 shown in FIG. 17 may vary due to variations in the amount of cream solder applied. For this reason, it is preferable to use the flux material 35 from the viewpoint of aligning the sizes of the solder balls 10. As the method for arranging the bonding material, a printing method or a transfer method can be used as described in the mounting process of the semiconductor device, but in FIG. 18, an example of applying (arranging) by the screen printing method. Show. That is, the screen mask 36 is disposed on the lower surface 3 b of the wiring board 25. Through holes 36 a are formed in the screen mask 36 at positions facing the plurality of lands 3 d of the wiring substrate 25. Then, from the back surface side of the screen mask 36 (the surface opposite to the surface facing the lower surface 3b of the wiring board 25), the flux material 35, which is a paste-like bonding material, is placed in the plurality of through holes 36a using the squeegee 37. Place it embedded in. Subsequently, if the screen mask 36 is removed, the flux material 35 as a bonding material can be disposed on the surfaces (exposed surfaces) of the plurality of lands 3d formed on the lower surface 3b of the wiring board 25.

  Next, as shown in FIGS. 19 and 20, a plurality of solder balls 15 are arranged on the plurality of lands 3d via the flux material 35, respectively (solder ball arranging step). 19 is an enlarged cross-sectional view showing a state in which a plurality of solder balls are arranged on the land shown in FIG. 18, and FIG. 20 is an enlarged cross-sectional view of a portion E in FIG. In the present embodiment, as shown in FIG. 19, two solder balls 15 are arranged on each land 3d. Each of the plurality of solder balls 15 includes one core ball 11 and a solder material 16 that covers the core ball 11. Then, the plurality of solder balls 15 are melted in a reflow process described later, and the solder material 16 is integrated, whereby the solder balls 10 shown in FIG. 4 are formed.

  Here, the method of arranging the solder balls 15 is performed as follows, for example. First, a mask (solder ball placement mask) 40 shown in FIGS. 19 and 20 is prepared and placed on the lower surface 3 b of the wiring board 25. In the mask 40, a plurality of through holes 40 a are formed on a plurality of lands 3 d formed on the lower surface 3 b of the wiring substrate 25. The diameter of the through hole 40a is slightly larger than the diameter of the solder ball 15. For example, in the present embodiment, the diameter of the solder ball 15 is 150 μm, whereas the diameter of the through hole 40a is 151 μm to 160 μm. Degree. The solder balls 15 can be placed one by one into the plurality of through holes 40a of the mask 40. At this time, the solder balls 15 are arranged with the lower surface 3b of the wiring board 25 facing upward. In other words, the plurality of solder balls 15 are disposed on the plurality of lands 3d (on the flux material 35) of the wiring board 25 from above. For this reason, the solder balls 15 disposed in the through holes 40a are fixed in close contact with the paste-like flux material 35, respectively. Specifically, when the solder balls 15 and the flux material 35 are in close contact, the plurality of solder balls 15 are fixed to each of the flux materials 35 by the adhesive component contained in the flux material 35. In addition, as shown in FIG. 20, a part of each solder ball 15 can be firmly fixed by being brought into close contact with the flux material 35. For this reason, it is preferable to press the plurality of solder balls 15 arranged in the through hole 40 a toward the flux material 35 with a pressing jig (not shown).

  Further, as described above, from the viewpoint of making the number of the core balls 11 in the plurality of solder balls 10 shown in FIG. 4 equal, in the solder ball arranging step, there is surely one in the through hole 40a of the mask 40. It is preferable to arrange the solder balls 15 one by one. Therefore, as shown in FIG. 20, when the diameters of the solder balls 15 are larger than the radius of the opening diameter of the through hole 40a and smaller than the diameter of the opening diameter of the through hole 40a, one through hole 40a is formed. This is preferable in that it is possible to suppress a plurality of solder balls 15 from being disposed therein. As shown in FIG. 20, the depth of the through hole 40a is set so that the solder ball 15 is positioned in the through hole 40a. In other words, a part of the solder ball 15 is formed on the back surface of the mask 40 (the lower surface 3b of the wiring board 25). It is preferable that the plurality of solder balls 15 are prevented from being disposed in one through hole 40a. For example, when a plurality of solder balls 15 are arranged in one through hole 40 a, at least a part of the extra solder balls 15 protrudes from the back surface of the mask 40. At this time, after the solder balls 15 are arranged, a rubbing jig such as a brush (not shown) is rubbed against the back surface of the mask 40 (the surface opposite to the surface facing the lower surface 3b of the wiring board 25). This is preferable in that unnecessary solder balls 15 (solder balls 15 protruding from the back surface of the mask 40) can be removed. Further, after the solder balls 15 are arranged, a rubbing jig such as a brush (not shown) is rubbed against the back side of the mask 40, as shown in FIG. It is also preferable from the viewpoint of close contact so as to bite into 35.

  Further, in the reflow process described below, from the viewpoint of reliably joining the solder material 16 of the solder ball 15 and the land 3d shown in FIG. 20, the center of each of the plurality of solder balls 15 is exposed in the plan view. It is preferable to arrange so as to be located in the opening 3k. In the present embodiment, for example, the opening diameter of the opening 3k is, for example, 220 μm. In order to fit the center of the two solder balls 15 in each opening 3k, the diameter of the solder ball 15 is The thickness is preferably less than 220 μm. However, in the present embodiment, as described above, since the through holes 40a for arranging one solder ball 15 are formed in the mask 40, a space is required between the adjacent solder balls 15. For this reason, in the present embodiment, the diameter of the solder ball 15 can be surely accommodated in the opening 3k even if the space between the adjacent solder balls 15 and the error in processing accuracy of the solder ball 15 are taken into consideration. Is about 150 μm.

  When the flux material 35 is used as the bonding material as in the present embodiment, the center of each of the plurality of solder balls 15 is positioned within the opening 3k where the land 3d is exposed as described above. It is preferable to arrange. However, as described in the semiconductor device mounting process described above, when cream solder containing a solder component and a flux component is used as a bonding material, the center of each of the plurality of solder balls 15 is an opening through which the land 3d is exposed. It can also be arranged so as to be located outside the portion 3k. This is because the core ball 11 is strongly drawn toward the center of the opening 3k by the solder component contained in the cream solder and the surface tension of the solder material 16 contained in the solder ball 15. Therefore, in this case, the diameter of the solder ball 15 can be further increased.

  Next, after removing the masks shown in FIGS. 19 and 20, the wiring board 25 is turned upside down as shown in FIG. 21, and heat is applied to the plurality of solder balls 15 (reflow process). FIG. 21 is an enlarged cross-sectional view showing a state where the mask shown in FIG. 19 is removed and then reversed and heat is applied to the solder balls. FIG. 22 is an enlarged cross-sectional view of a portion F in FIG. In this step, for example, the wiring board 25 in which a plurality of solder balls 15 are fixed to the flux material 35 is placed in a reflow furnace (not shown), and the inside of the reflow furnace is heated to about 260 ° C., for example. When the surface of the solder material 16 of the solder ball 15 and the surface of the land 3d shown in FIG. 20 are sufficiently activated by the flux component contained in the flux material 35, the solder material 16 included in each of the plurality of solder balls 15 is obtained. They are integrated and joined to the land 3d. That is, the solder ball 10 shown in FIGS. 17 and 22 is formed. The core balls 11 respectively possessed by the solder balls 15 (see FIG. 20) are covered with the solder material 12 and enclosed in the solder balls 10 as shown in FIG.

  Here, in this embodiment, as shown in FIG. 21, the solder balls 15 are heated and integrated with the lower surface 3b of the wiring board 25 on which the plurality of lands 3d are formed facing downward. In other words, the plurality of solder balls 15 are integrated in a state where the plurality of solder balls 15 are arranged below the plurality of lands 3d. By performing the reflow process with the lower surface 3b of the wiring board 25 facing downward in this way, the plurality of core balls 11 are arranged close to the land 3d side in the solder ball 10 as shown in FIG. Can do. That is, the center of each of the plurality of core balls 11 can be disposed on the land 3 d side with respect to the center of the solder ball 10.

  The reason will be described in detail below. When the solder ball 15 shown in FIG. 21 is heated in the reflow process, the solder material 16 (see FIG. 20) contained in the solder ball 15 is softened or melted. At this time, the flux component contained in the flux material 35 melts and activates the surface of the solder material 16 and the surface of the land 3d. However, the solder ball 15 is held by the adhesive component contained in the flux material 35 and is lowered downward. It can prevent falling. When the surface of the solder material 16 and the surface of the land 3d are sufficiently activated and the fluidity of the solder material 16 increases, the solder material 16 is integrated and joined to the land 3d as shown in FIG. 12 In the present embodiment, as shown in FIG. 20, since the centers of the plurality of solder balls 15 are arranged so as to be located in the opening 3k where the land 3d is exposed, the solder material 16 and the land 3d are arranged. The distance can be reduced. For this reason, the solder material 16 of the solder ball 15 and the land 3d can be reliably joined.

  The heated solder material 12 has higher fluidity than the solder material 16 before heating, and is deformed into a substantially spherical shape as shown in FIG. 22 due to the surface tension of the solder material 12. Then, the plurality of core balls 11 inside the solder material 12 move within the solder material 12. Here, the core material 11a included in the core ball 11 is made of resin and not only has a specific gravity smaller than that of the solder material 12, but also is affected by convection of the molten solder. In the material 12, it moves upward. As a result, the plurality of core balls 11 can be arranged close to the land 3d side in the solder ball 10. Further, due to the surface tension of the solder material 12, the plurality of core balls 11 are pushed toward the center of the land 3d. As a result, the surface of the core ball 11 is not exposed from the solder material 12 and is covered with the solder material 12. In the case where cream solder including a solder component and a flux component is used as the bonding material shown in FIG. 20, similarly, a plurality of core balls 11 are arranged close to the land 3 d side in the solder ball 10. can do.

  As described above, according to the present embodiment, as shown in FIG. 20, the masks 40 each having the plurality of through holes 40a are disposed on the plurality of lands 3d, and each of the plurality of through holes 40a is arranged. Further, by arranging the solder balls 15 one by one, the number of core balls 11 included in each solder ball 10 shown in FIG. 22 can be made equal.

  Further, according to the present embodiment, by performing the reflow process with the lower surface 3b of the wiring board 25 facing downward, the plurality of core balls 11 are placed in the land 3d in the solder ball 10, as shown in FIG. Can be placed close to the side.

  Next, as shown in FIG. 22, the wiring board 25 in which the solder balls 10 are respectively formed on the plurality of lands 3d is cleaned (cleaning step). In this step, the residue (flux residue) of the flux material 35 (see FIG. 20) attached to the wiring board 25 is removed. As a cleaning method, for example, a high-pressure cleaning method in which a pressurized flux cleaning liquid (liquid) is sprayed toward the wiring board 25 can be employed.

7). Individualization Step Next, the individualization step (S7) shown in FIG. 8 will be described. FIG. 23 is an enlarged cross-sectional view showing a state in which the wiring board shown in FIG. 17 is cut with a dicing blade.

  In this step, as shown in FIG. 23, a dicing blade (rotating blade) 41 is run along a dicing area (dicing line) 25c to cut (divide) the wiring substrate 25 and the collective sealing body 6b. The area 25a is divided into individual pieces. Thereby, the plurality of device regions 25a are separated from the adjacent device region 25a and the frame portion 25b, respectively, and a plurality of BGAs 1 are acquired.

8). Inspection Step Next, the inspection step (S8) shown in FIG. 8 will be described. FIG. 24 is an explanatory view schematically showing an electrical test included in the inspection process shown in FIG.

  This process includes an appearance inspection and an electrical test of the BGA 1. Here, in the electrical test, for example, as shown in FIG. 24, probe pins (contact terminals) 43 that are electrically connected to the electrical test circuit 42a of the inspection apparatus 42 are solder balls that are external terminals of the BGA 1. 10 is contacted to conduct a continuity test, an electrical property confirmation test, and the like. Here, when the core ball 11 is included in the solder ball 10 as in the present embodiment, when some of the probe pins 43 come into contact with the core ball 11, Since the difference in electrical resistance increases between the two, correct test results cannot be obtained, causing contact failure.

  However, according to the present embodiment, as shown in FIG. 22, since the plurality of core balls 11 are arranged close to the land 3d side, each probe pin 43 can be reliably brought into contact with the solder material 12. it can. That is, contact failure can be prevented.

  Through the above steps, the BGA 1 shown in FIG. 1 is completed. Thereafter, it is shipped or mounted on the mounting board 20 shown in FIG.

(Embodiment 2)
Next, another embodiment for manufacturing the BGA 1 described in the first embodiment will be described. In the present embodiment, the description will focus on the differences from the semiconductor device manufacturing method described in the first embodiment, and the description of the common parts will be omitted. The drawings necessary for explaining the differences from the first embodiment are also shown, and the drawings described in the first embodiment will be cited as necessary. The manufacturing method of the semiconductor device of the second embodiment is the same as the manufacturing method of the semiconductor device described in the first embodiment, except that a solder ball in which a plurality of core balls are included in advance is mounted in the ball mounting process. It is the same.

  FIG. 25 shows a ball mounting step (solder ball placement step) of the present embodiment, which is a modification of FIG. 19, and is an enlarged cross-sectional view showing a state in which a plurality of solder balls are placed on the lands shown in FIG. is there. FIG. 26 is an enlarged cross-sectional view of a portion G in FIG.

  In the present embodiment, before the solder ball placement step described in the first embodiment, a solder ball 10 including a plurality of core balls 11 and a solder material 12 covering the periphery of the plurality of core balls 11 is prepared in advance. (Solder ball preparation process). Then, as shown in FIGS. 25 and 26, the solder balls 10 are arranged on the lands 3d from above the lands 3d via the flux material 35 (solder ball arrangement step).

  The solder ball 10 including the plurality of core balls 11 can be formed, for example, by applying the technique described in the first embodiment. That is, a plurality of core balls 11 are joined by, for example, solder, and then the joined member is used as a base, and the surface (outer periphery) of this member is grown by a solder plating method, so that FIG. 25 and FIG. A solder ball 10 including a plurality of core balls 11 shown and a solder material 12 covering the periphery of the plurality of core balls 11 is obtained.

  In the present embodiment, since one solder ball 10 is arranged on each of the plurality of lands 3d in the solder ball arrangement step, the mask (solder ball arrangement mask) 45 shown in FIGS. The number and arrangement of through holes are different from those of the mask 40 described in the first embodiment. That is, in the mask 45, one through hole 45a is formed on each of the plurality of lands 3d formed on the lower surface 3b of the wiring board 25. The diameter of the through hole 45a is slightly larger than the diameter of the solder ball 10. For example, in this embodiment, the diameter of the solder ball 10 is about 250 μm, whereas the diameter of the through hole 45a is 265 μm to It is about 280 μm. This is smaller than the sum of the opening diameters of the two through holes 40a described in the first embodiment. In other words, according to the present embodiment, since one solder ball 10 is disposed on each of the plurality of lands 3d, the adjacent lands 3d are compared with the solder ball placement step described in the first embodiment. The distance between the solder balls 10 arranged on the top can be increased. For this reason, even when the arrangement pitch of the adjacent lands 3d is narrow, the bridge between the solder balls 10 can be suppressed. However, in the present embodiment, since the solder ball forming step is added as compared with the first embodiment, from the viewpoint of improving the manufacturing efficiency, the method for manufacturing the semiconductor device described in the first embodiment Is preferred.

  Also, in the solder ball arrangement step of the second embodiment, as in the first embodiment, the solder ball 10 arranged in the through hole 45a and the flux material 35 are in close contact with each other, so that the solder ball is included in the flux material 35. A plurality of solder balls 10 are fixed to each flux material 35 by the adhesive component. Further, a part of the solder ball 10 can be firmly fixed by being in close contact with the flux material 35. For this reason, it is preferable to press the plurality of solder balls 10 disposed in the through hole 45a toward the flux material 35 with a pressing jig (not shown).

  Further, from the viewpoint of making the number of core balls 11 in the plurality of solder balls 10 shown in FIG. 4 equal, in this solder ball arranging step, the solder balls 10 are surely placed one by one in the through holes 45a of the mask 45. It is preferable to arrange. Therefore, when the diameters of the solder balls 10 are larger than the radius of the opening diameter of the through-hole 45a and smaller than the diameter of the opening diameter of the through-hole 45a, a plurality of solder balls are placed in one through-hole 45a. It is preferable at the point which can suppress that 10 is arrange | positioned. Further, the depth of the through hole 45a is set so that the solder ball 10 is located in the through hole 45a, in other words, a part of the solder ball 10 is opposite to the back surface of the mask 45 (the surface opposite to the lower surface 3b of the wiring board 25). It is preferable to prevent the plurality of solder balls 10 from being disposed in one through hole 45a. Further, after the solder ball 10 is disposed, a rubbing jig such as a brush (not shown) is rubbed against the back surface of the mask 45 (the surface opposite to the surface facing the lower surface 3b of the wiring board 25). This is preferable in that the solder ball 10 can be removed. That is, it is also preferable from the viewpoint that a part of each solder ball 10 is in close contact with the flux material 35.

  Next, after removing the masks shown in FIGS. 25 and 26, the wiring substrate 25 is turned upside down as shown in FIG. 27, and heat is applied to the plurality of solder balls 10 (reflow process). FIG. 27 is an enlarged cross-sectional view showing a state where the mask shown in FIG.

  In this step, for example, the wiring board 25 in which the solder balls 10 are fixed to the flux material 35 is placed in a reflow furnace (not shown), and the inside of the reflow furnace is heated to about 260 ° C., for example. When the surface of the solder material 12 of the solder ball 10 and the surface of the land 3d are sufficiently activated by the flux component contained in the flux material 35, as shown in FIGS. Joined to 3d.

  By the way, in the present embodiment, the solder ball 10 including a plurality of core balls 11 is formed in advance and disposed on the flux material 35. Therefore, as shown in FIG. 25 and FIG. The position of each core ball 11 in is random. That is, the core ball 11 approaching the land 3d side and the core ball 11 approaching the side far from the land 3d are mixed.

  Therefore, also in the second embodiment, as in the first embodiment, in the reflow process, as shown in FIG. 27, the lower surface 3b of the wiring board 25 on which the plurality of lands 3d are formed faces downward. The solder ball 10 is heated. In other words, the solder balls 10 are joined to the lands 3d in a state where the plurality of solder balls 10 are disposed below the plurality of lands 3d. In this way, by performing the reflow process with the lower surface 3b of the wiring board 25 facing downward, the plurality of core balls 11 inside the heated solder material 12 move within the solder material 12. Here, the core material 11a included in the core ball 11 is made of resin and not only has a specific gravity smaller than that of the solder material 12, but also is affected by convection of the molten solder. In the material 12, it moves upward. As a result, as shown in FIG. 22, the plurality of core balls 11 can be arranged close to the land 3 d in the solder ball 10. That is, the center of each of the plurality of core balls 11 can be disposed on the land 3 d side with respect to the center of the solder ball 10.

  The semiconductor device and the manufacturing method thereof according to the present embodiment are the same as the semiconductor device and the manufacturing method thereof described in the first embodiment except for the differences described above. Therefore, although the overlapping description is omitted, the invention described in the first embodiment can be applied except for the above differences.

(Embodiment 3)
Next, a modification of the core ball 11 described in the first embodiment will be described. Note that in this embodiment, differences from the semiconductor device described in Embodiment 1 will be mainly described, and description of common portions will be omitted. The drawings necessary for explaining the differences from the first embodiment are also shown, and the drawings described in the first embodiment will be cited as necessary. FIG. 28 is an enlarged sectional view showing a modification of the core ball shown in FIG.

  The difference between the core ball 46 shown in FIG. 28 and the core ball 11 shown in FIG. 4 is that the core material 46a is made of metal. Specifically, the core material 46a of the present embodiment is made of, for example, copper (Cu). Further, a metal film 46b covering the surface of the core material 46a is formed around the core material 46a, as in the first embodiment. The metal film 46b is made of, for example, nickel (Ni) from the viewpoint of suppressing the dissolution of copper at the contact interface with the solder material 12. The metal film 46b does not necessarily have to be formed on the surface (periphery) of the core material 46a.

  Copper constituting the core material 46 a has higher electrical conductivity than the solder material 12. For this reason, the core ball 46 including the core material 46 a is included in the solder ball 10, whereby the electrical resistance of the solder ball 10 can be reduced. That is, the electrical characteristics of the BGA 1 can be improved. Further, copper constituting the core material 46 a has a higher heat transfer coefficient than the solder material 12. For this reason, when the core ball 46 including the core material 46 a is included in the solder ball 10, the heat transfer coefficient of the solder ball 10 can be improved. That is, the heat dissipation characteristics of the BGA 1 can be improved. It is also effective as a countermeasure against electromigration accompanying an increase in current density.

  Here, even when the core ball 102 shown in FIG. 54 and FIG. 55 described in the first embodiment has a core material made of metal, the semiconductor device mounting process of the first embodiment is performed. The described problem occurs. Therefore, the core material 11a, the metal film 11b, and the core ball 11 described in the first embodiment are replaced with the core material 46a, the metal film 46b, and the core ball 46 according to the present embodiment, so that The effect described in the first embodiment is obtained. In addition, the core material 11a, the metal film 11b, and the core ball 11 described in the second embodiment are applied in place of the core material 46a, the metal film 46b, and the core ball 46 of the present embodiment. The effect described in the second embodiment is obtained.

  In the first and second embodiments, in the reflow process of the ball mounting process, the solder ball 15 or the solder ball 10 is heated with the lower surface 3b of the wiring board 25 facing downward. It has been explained that the core ball 11 can move within the solder material 12 and be moved toward the land 3d. Also in the present embodiment, if the specific gravity of the core material 46a is smaller than that of the solder material 12, the solder ball 15 or the solder ball 10 is heated with the lower surface 3b of the wiring board 25 facing downward. As shown in FIG. 28, the plurality of core balls 46 can be arranged so that the centers thereof are located on the land 3 d side with respect to the centers of the solder balls 10. For example, in the present embodiment, the core material 46 a made of copper (Cu) has a specific gravity smaller than that of the solder material 12. However, since the specific gravity difference with the solder material 12 is smaller than in the case of the core material 11a made of resin, the time required for the core ball 46 to move in the solder material 12 becomes longer. Further, when the core material 46a has a specific gravity greater than that of the solder material 12 and is not affected by the convection of the molten solder, the wiring board 25 is opposite to the first embodiment and the second embodiment. The solder ball 15 or the solder ball 10 is heated with the lower surface 3b facing upward. As a result, the plurality of core balls 46 can be arranged so that the centers thereof are located closer to the land 3 d than the centers of the solder balls 10.

(Embodiment 4)
Next, a modified example of the solder ball 10 described in the first embodiment will be described. In the present embodiment, the description will focus on the differences from the semiconductor device manufacturing method described in the first embodiment, and the description of the common parts will be omitted. The drawings necessary for explaining the differences from the first embodiment are also shown, and the drawings described in the first embodiment will be cited as necessary. FIG. 29 is an enlarged cross-sectional view showing the internal structure of a solder ball, which is a modified example of the first embodiment. FIG. 30 is an enlarged sectional view showing a modified example of the solder ball arranging step shown in FIG. 31 and 32 are enlarged cross-sectional views showing another modification of the solder ball arrangement step shown in FIG. FIG. 29 is a cross-sectional view showing a state cut in a direction parallel to the lower surface of the wiring board on which the solder balls are mounted.

  The difference between the solder ball 47 shown in FIG. 29 and the solder ball 10 of the first embodiment shown in FIG. 4, for example, is as follows. First, the first difference is that the solder ball 47 has a plurality of core balls 11 and 46 having different diameters. In other words, the solder ball 47 includes the core ball 11 having a diameter W2 and the core ball 46 having a diameter W3 smaller than the diameter W2. The second difference is that the solder ball 47 has core balls 11 and 46 made of different materials. For example, in the embodiment, the solder ball 47 includes the core ball 11 having the core material 11a made of resin and the core ball 46 having the core material 46a made of metal (for example, copper). The third difference is that the solder ball 47 has three core balls.

  As described above, the embodiment in which the plurality of core balls 11 and 46 having different diameters are arranged in one solder ball 47 has a configuration in which the core balls 11 and 46 made of different materials are mixed as in the present embodiment. When applied, it is particularly effective. For example, in the present embodiment, the diameter W2 of the core ball 11 having the core material 11a made of resin is larger than the diameter W3 of the core ball 46 having the core material 46a made of metal (for example, copper). Thereby, the stress relaxation effect demonstrated in the said Embodiment 1 is acquired by the core ball 11 with a large diameter. In addition, by arranging the core ball 46 having a small diameter, it is possible to suppress an increase in the electrical resistance of the solder ball 47 or a decrease in the heat dissipation characteristics.

  Here, from the viewpoint of improving the stress relaxation effect, it is preferable to increase the diameter of the core material 11a made of resin. On the other hand, from the viewpoint of suppressing an increase in electric resistance or a decrease in heat dissipation characteristics, the cross-sectional area of the electric or heat transfer path may be increased. Accordingly, the diameter W3 of the core ball 46 may be small as long as the core ball 46 is disposed around the core ball 11 in a cross section perpendicular to the direction of transmission of electricity and heat. The solder ball 47 of the present embodiment is manufactured using any of the manufacturing methods described in the first to third embodiments. For this reason, each of the core balls 11 and 46 moves toward the land 3d side in the reflow process described in the first to third embodiments. As a result, in the cross section in the direction perpendicular to the thickness direction of the BGA 1 (for example, the direction along the lower surface 3b of the interposer substrate 3 shown in FIG. 3), the core as shown in FIG. The core ball 46 is disposed around the ball 11. That is, the stress relaxation effect can be improved, and an increase in electrical resistance or a decrease in heat dissipation characteristics can be suppressed.

  As a method for forming the solder ball 47 of the present embodiment, when the ball mounting process described in the first embodiment is applied and applied, for example, the following is performed. That is, as shown in FIG. 30, a plurality of through holes 48a and 48b having different opening diameters are formed using a mask 48 formed on each land 3d. The diameters of the solder balls 15 forming the solder balls 47 are also different depending on the diameters of the core balls 11 and 46 to be included. That is, the diameter of the solder ball 15 enclosing the core ball 11 is larger than the diameter of the solder ball 15 enclosing the core ball 46. In the solder ball arrangement step, the larger solder ball 15 (the solder ball 15 containing the core ball 11) is first arranged in the through hole 48a having a large opening diameter. Here, the opening diameter of the through-hole 48b is smaller than the diameter of the solder ball 15 in which the core ball 11 is contained, and can thereby be selectively disposed in the through-hole 48a. Subsequently, the smaller solder ball 15 (the solder ball 15 containing the core ball 46) is disposed in the through hole 48b having an opening diameter smaller than that of the through hole 48a. At this time, since the solder ball 15 in which the core ball 11 is included is already disposed in the through hole 48a, the solder ball 15 in which the core ball 46 is included can be disposed in the through hole 48b. That is, the solder balls 15 having different constituent materials can be selectively mixed. Since FIG. 30 is a partially enlarged view of one cross section, one through hole 48a and one through hole 48b are shown corresponding to one land 3d. However, although not shown, another through hole 48b is formed in another cross section. That is, one through hole 48a and two through holes 48b are formed corresponding to one land 3d. Accordingly, as shown in FIG. 29, one core ball 11 and two core balls 46 can be included in one solder ball 47.

  Similarly to the first embodiment, when the diameters of the solder ball 15 containing the core ball 11 and the solder ball 15 containing the core ball 46 are made equal, for example, as shown in FIGS. In this case, the solder balls 15 having different constituent materials are sequentially sucked and transported by using the suction jig 49, and can be selectively mixed. First, as shown in FIG. 31, the plurality of solder balls 15 each containing the core ball 46 are sucked and held by the plurality of suction ports 49 a formed in the suction jig 49. And after conveying on the through-hole 40a among the several through-holes formed on the land 3d, the adsorption | suction force is released | released and it arrange | positions in the through-hole 40a. Subsequently, as shown in FIG. 32, the plurality of solder balls 15 each containing the core ball 11 are sucked and held by the plurality of suction ports 49 a formed in the suction jig 49. And after conveying on the through-hole 40b arrange | positioned next to the through-hole 40a among the several through-holes formed on the land 3d, the adsorption | suction force is released | released and it arrange | positions in the through-hole 40b. Thus, a plurality of solder balls 15 having different constituent materials can be selectively mounted on one land 3d. In the case of the method using the suction jig 49 shown in FIGS. 31 and 32, the placement position of the solder ball 15 can be positioned by the suction jig, so that it can be placed without using the mask 40. However, from the viewpoint of preventing the solder ball 15 from rolling after the suction release, it is preferable to use the mask 40 as a guide as shown in FIGS.

  The manufacturing method of the semiconductor device of the present embodiment is the same as the semiconductor device and the manufacturing method thereof described in the first to third embodiments except for the differences described above. Therefore, although the overlapping description is omitted, the invention described in the first to third embodiments can be applied except for the above differences.

  In the present embodiment, the solder ball 47 has a first configuration in which a plurality of core balls 11 and 46 having different diameters are used, and the solder ball 47 has the core balls 11 and 46 made of different materials. Although the example which combined the 2nd structure of having was demonstrated, these can also be applied independently. For example, in the first embodiment, the solder ball 10 may have a plurality of core balls 11 having different diameters. Further, for example, in the first embodiment, the solder ball 10 may have a structure in which the diameters are uniform and the core balls 11 and 46 made of different materials are included.

(Embodiment 5)
Next, an embodiment in which the solder ball 10 described in the first embodiment is applied to a package of a different type from the BGA 1 will be described. Specifically, in the present embodiment, an embodiment in which the structure and the forming method of the solder ball 10 described in the first embodiment is applied to a so-called WPP (Wafer Process Package) type semiconductor device will be described. WPP is a semiconductor package to which a rewiring technique is applied in which a rewiring layer is formed on a semiconductor chip and external terminals are formed at positions different from the positions of electrode pads in plan view. In WPP, since the process of forming the rewiring layer is performed before the semiconductor wafer is separated into pieces, a fine processing technique for forming a semiconductor element or the like can be applied. For this reason, as in the first embodiment, the semiconductor chip is mounted on the wiring board, and these are further advantageous in terms of reduction in the planar area and reduction in thickness as compared with the semiconductor package in which these are electrically connected. It is. Such a semiconductor device is called WPP or WL-CSP (Wafer Level Chip Scale Package) because a rewiring layer is formed before the semiconductor wafer is separated. Note that in this embodiment, differences from the semiconductor device described in Embodiment 1 or 2 and the manufacturing method thereof are mainly described, and description of common portions is omitted. The drawings also show the drawings necessary for explaining the differences from the first embodiment or the second embodiment, and the drawings described in the first embodiment or the second embodiment as necessary. Will be explained with reference to.

<Structure of semiconductor device>
FIG. 33 is a plan view showing the entire structure of the semiconductor device of the present embodiment, and FIG. 34 is an enlarged cross-sectional view taken along the line HH in FIG. In FIG. 33, the number of terminals of the semiconductor chip and the WPP is reduced for easy viewing.

  The WPP 51, which is a semiconductor device of the present embodiment, has a semiconductor chip 2 having a surface 2a, a plurality of electrode pads (bonding pads) 2c formed on the surface 2a, and a back surface 2b located on the opposite side of the surface 2a. is doing. As shown in FIG. 34, the semiconductor chip 2 has a semiconductor substrate 2d, which is a base material made of, for example, silicon (Si), and a semiconductor element formation region 2e is disposed on the main surface 2da of the semiconductor substrate 2d. A plurality of semiconductor elements such as transistors and diodes are formed in the element formation region 2e. These semiconductor elements are each electrically connected to a plurality of electrode pads 2c via wiring layers (first wiring layer, chip wiring layer) 2f formed on the main surface 2da. Specifically, the semiconductor element includes a plurality of internal wirings (internal wirings) 2ga formed in the wiring layer 2f and a plurality of surface wirings (wirings, top layer wiring) 2gb formed in the uppermost layer of the wiring layer. The electrode pad 2c is electrically connected. The electrode pad 2c is formed integrally with the surface wiring 2gb. The wiring 2ga is an embedded wiring made of, for example, copper (Cu), and after a groove or hole is formed in the insulating layer 2h formed in the wiring layer 2f, a conductive metal material such as copper is embedded in the groove or hole. The wiring is formed by polishing the surface, so-called damascene technology. The insulating layer 2h is an inorganic insulating layer made of a semiconductor compound such as silicon oxide (SiOC) containing carbon or tetraethylorthosilicate (TEOS). In addition, the wiring 2ga is electrically connected to a plurality of semiconductor elements to form an integrated circuit, but is stacked in a plurality of layers via a plurality of insulating layers 2h in order to secure a routing space for this wiring path. . The uppermost layer of the wiring layer 2f is formed with an electrode pad 2c and a surface wiring 2gb which are integrally formed with the electrode pad 2c and electrically connect the plurality of electrode pads 2c and the semiconductor element via the wiring 2ga. Yes. The electrode pad 2c and the surface wiring 2gb are made of, for example, aluminum (Al), and are covered with an insulating layer 2k serving as a passivation film for protecting the surface 2a. The insulating layer 2k is an inorganic insulating layer made of a semiconductor compound such as silicon oxide (SiO) or silicon nitride (SiN), as with the insulating layer 2h, from the viewpoint of improving the adhesion with the insulating layer 2h. is there. Further, in order to use the electrode pad 2c as an external terminal of the semiconductor chip 2, an opening is formed in the insulating layer 2k on the surface 2a of the electrode pad 2c, and the electrode pad 2c is exposed from the insulating layer 2k in the opening. ing.

  The WPP 51 has a rewiring layer (wiring layer, second wiring layer) 53 formed on the surface 2 a of the semiconductor chip 2. The redistribution layer 53 has a lower surface (main surface, back surface) 53b facing the surface 2a of the semiconductor chip 2 and an upper surface (main surface, surface) 53a opposite to the lower surface 53b. A plurality of land portions (bump lands) 53c are formed on the upper surface 53a, and a plurality of electrode pads 2c of the semiconductor chip 2 are respectively connected via a plurality of wirings (redistribution) 53d formed in the redistribution layer 53. Electrically connected. The solder balls 10 described in the first embodiment are joined to each land portion 53c. That is, in this embodiment, the solder ball 10 is an external terminal of the WPP 51. The WPP 51 changes the planar position of the solder ball 10 serving as an external terminal to a position different from the electrode pad 2c by forming the rewiring layer 53 on the electrode pad 2c. Since the position of the solder ball 10 can be made to correspond to the arrangement of the terminal of the mounting board on which the WPP 51 is mounted (see, for example, the terminal 21 of the mounting board 20 shown in FIG. 5), the terminal of the mounting board via the solder ball 10 Can be connected with. In other words, the mounting height can be reduced because it can be mounted on the mounting substrate without using the interposer substrate 3 described in the first embodiment. Since the WPP 51 forms the rewiring layer 53 on the semiconductor chip 2, the planar dimension thereof can be the same as the planar dimension of the surface 2 a of the semiconductor chip 2. Therefore, the mounting area can be reduced as compared with the BGA 1 described in the first embodiment.

  The rewiring layer 53 of the present embodiment is configured as follows, for example. That is, an insulating film (organic insulating film) 53e made of an organic compound such as polyimide resin is formed on the insulating layer 2k. On the insulating film 53e, for example, a wiring 53d made of a conductive metal material in which a nickel film is laminated on copper is formed in a predetermined pattern. Here, the insulating film 53e is formed between the wiring 53d and the insulating layer 2k because, for example, a parasitic capacitance is formed between the wiring 53d and the semiconductor element or the wiring 2ga formed on the surface 2a of the semiconductor chip 2. This is to prevent or suppress noise and other causes of characteristic degradation. Therefore, the insulating film 53e is preferably made of a material having a low dielectric constant. Therefore, in the present embodiment, as the insulating film 53e, polyimide resin, benzo-cyclobutene (BCB) film, or poly-benzo, which is an organic insulating film having a lower dielectric constant than the insulating layers 2h and 2k, which are inorganic insulating layers, are used. -Oxazole (PBO) or the like is used. From the viewpoint of preventing or suppressing the formation of parasitic capacitance, the insulating film 53e is preferably as thick as possible. For example, in the present embodiment, the insulating film 53e is thicker than the insulating layer 2k disposed in the lower layer. Further, in order to electrically connect the wiring 53d and the electrode pad 2c, at least a part of the electrode pad 2c is exposed from the insulating film 53e. An insulating film (organic insulating film) 53f made of an organic compound such as polyimide resin is formed on the wiring 53d. The insulating film 53f is formed as a protective film that protects the wiring 53d from oxidation, corrosion, migration, short circuit, or damage. In addition, it is preferable to use a material having low elasticity from the viewpoint of absorbing and relaxing the stress applied to the solder ball 10 which is an external terminal after the WPP 51 is mounted on the mounting substrate. Therefore, in the present embodiment, polyimide resin that is an organic insulating film having lower elasticity than the insulating layers 2h and 2k that are inorganic insulating layers is used as the insulating film 53f. An opening is formed in part of the region of the insulating film 53f that overlaps the wiring 53d, and the land 53c is exposed from the insulating film 53f in the opening. Solder balls 10 serving as external terminals of the WPP 51 are joined to the land portion 53c. That is, the wiring 53d functions as a lead wiring that changes the planar position of the external terminal of the WPP 51 to a position different from the electrode pad 2c. The wiring 53d includes a bonding portion bonded to the electrode pad 2c, a land portion 53c bonded to the solder ball 10, and an extending portion extending from the bonding portion to the land portion 53c. 53c is formed with a width wider than the extending portion from the viewpoint of ensuring a wide bonding area with the electrode pad 2c and the solder ball 10 to be bonded, and improving the bonding reliability.

  Here, since the WPP type semiconductor device is mainly composed of a semiconductor material such as silicon, if the thickness of the semiconductor substrate is sufficiently thick, compared with the interposer substrate 3 described in the first embodiment. Warpage is unlikely to occur. However, in the structure in which one side (surface 2a side) of the semiconductor chip 2 is covered with an insulating film 53f such as polyimide resin as in the WPP 51 of the present embodiment, the linear expansion coefficient between the insulating film 53f and the semiconductor chip 2 Due to the difference, warping occurs. In particular, when the back surface 2b side of the semiconductor chip 2 is ground to reduce the thickness, the rigidity of the semiconductor chip 2 is reduced, and thus warpage is likely to occur. For this reason, similarly to the BGA 1 described in the first embodiment, it is necessary to suppress mounting defects caused by warpage in the WPP 51 as well.

  Therefore, in the present embodiment, the solder ball 10 having the plurality of core balls 11 is bonded to the land portion 53c from the viewpoint of suppressing the mounting failure described in the first embodiment. As a result, the WPP 51 of the present embodiment can obtain the effects described in the first embodiment. As for the structure of the solder ball 10 and its periphery, the interposer substrate 3 is redistributed layer 53, the lower surface 3b is the upper surface 53a, the land 3d is the land portion 53c, and the solder resist film 3g is insulated as described in the first embodiment. The description can be omitted because it can be applied in place of the film 53f.

<Manufacturing process of semiconductor device>
Next, a method for manufacturing the WPP 51 will be briefly described focusing on differences from the method for manufacturing the BGA 1 described in the first embodiment. FIG. 35 is an explanatory diagram showing an assembly flow of the semiconductor device manufacturing method of the present embodiment. As shown in FIG. 35, the semiconductor device of the present embodiment includes a semiconductor wafer preparation process, a rewiring layer forming process, a back surface grinding process, a ball mounting process, a singulation process, and an inspection process.

1. Semiconductor Wafer Preparation Step First, in the semiconductor wafer preparation step, a wafer (semiconductor wafer) 55 shown in FIGS. 36 and 37 is prepared. FIG. 36 is a plan view showing a plane on the main surface side of the semiconductor wafer prepared in the semiconductor wafer preparation step of the present embodiment. FIG. 37 is an enlarged sectional view showing a sectional structure of a part of the semiconductor wafer shown in FIG. The wafer 55 has a substantially circular planar shape, and has a front surface 2a and a back surface 55b (see FIG. 37) located on the opposite side of the front surface 2a. The surface 2a of the wafer 55 corresponds to the surface 2a of the semiconductor chip 2 shown in FIG. The wafer 55 has a plurality of device regions 55a, and each device region 55a corresponds to the WPP 51 shown in FIG. Therefore, in the plurality of device regions 55a shown in FIG. 36, the semiconductor element, the wiring layer 2f, the surface wiring 2gb, and the electrode pad (bonding pad) 2c included in the semiconductor chip 2 described with reference to FIGS. 33 and 34, respectively. Is formed. As shown in FIG. 36, a dicing region 55c is formed between adjacent device regions 55a among the plurality of device regions 55a. The dicing area 55c is formed in a lattice shape and partitions the surface 2a of the wafer 55 into a plurality of device areas 55a.

  The wafer 55 shown in FIG. 37 is formed as follows, for example. First, a semiconductor substrate 2d that is a substantially circular wafer (for example, a silicon wafer) serving as a base material is prepared, and a plurality of semiconductor elements are formed in the semiconductor element formation region 2e of the main surface 2da. Next, a wiring layer 2f is formed on the main surface 2da, and the plurality of wirings 2ga and the plurality of semiconductor elements are electrically connected. Next, the surface wiring 2gb and the electrode pad 2c are formed on the upper surface of the wiring layer 2f. Since the surface wiring 2gb is formed integrally with the electrode pad 2c and is electrically connected to the plurality of wirings 2ga drawn to the upper surface of the wiring layer 2f, the plurality of electrode pads 2c and the plurality of semiconductor elements are It is electrically connected in the process. Next, an insulating layer 2k is formed on the wiring layer 2f, and after covering the wiring layer 2f, an opening is formed by an etching method, and a part of the electrode pad 2c is exposed from the insulating layer 2k.

2. Rewiring Layer Formation Step Next, as shown in FIG. 38, a rewiring layer 53 is formed on the wafer 55. FIG. 38 is an enlarged cross-sectional view showing a state in which a rewiring layer is formed on the semiconductor wafer shown in FIG. FIGS. 39 to 44 are explanatory diagrams showing details of the process of forming the rewiring layer shown in FIG.

  First, as shown in FIG. 39, an insulating film (organic insulating film) 53e made of an organic compound such as polyimide resin is formed on the surface 2a of the wafer 55 (first insulating film forming step). Thereafter, an opening is formed in the insulating film 53e on the electrode pad 2c to expose the electrode pad 2c (electrode pad exposing step). Next, as shown in FIG. 40, a conductor film 53s to be a seed layer is formed on the insulating film 53e and the exposed surface of the electrode pad 2c by, for example, a sputtering method (seed layer forming step). The conductor film 53s is made of, for example, chromium (Cr) and constitutes a part of the wiring 53d shown in FIG. Next, as shown in FIG. 41, a resist film (plating resist film) 54 is disposed on the conductor film 53s and then patterned (first resist film forming step). In the patterning of the resist film 54, patterning is performed so as to remove the region for forming the wiring 53d shown in FIG. Next, as shown in FIG. 42, a wiring 53d is formed by electrolytic plating in the presence of the resist film 54. In the present embodiment, for example, an electrolytic plating film of a copper (Cu) film and a nickel (Ni) film is sequentially formed (rewiring forming step). By this step, the wiring 53d (including the land portion 53c) is formed. Next, as shown in FIG. 43, the unnecessary conductor film 53s other than the region where the resist film 54 (see FIG. 42) and the wiring 53d are formed is removed (seed layer removing step). Next, as shown in FIG. 44, for example, an insulating film (organic insulating film) 53f made of an organic compound such as polyimide resin is formed (second insulating film forming step). Thereafter, as shown in FIG. 38, an opening is formed in the insulating film 53f on the land portion 53c, and the land portion 53c is exposed from the insulating film 53f (land portion exposing step). Through the above steps, a rewiring layer 53 shown in FIG. 38 is formed.

3. Back Surface Grinding Process Next, in the back surface grinding process, the back surface 55b (see FIG. 38) of the wafer 55 is ground. FIG. 45 is an enlarged cross-sectional view showing a step of grinding the semiconductor wafer shown in FIG. In this step, the back surface side is ground until the thickness of the wafer 55 reaches the thickness of the WPP 51 shown in FIG. 34 (up to the position of the back surface 2b shown in FIG. 45).

  As a method for reducing the thickness of the WPP 51, a method in which the thickness of a wafer (a silicon wafer in the present embodiment) serving as a base material is previously reduced is also conceivable. However, in this case, if it is made extremely thin, in each process of forming a semiconductor element or the like on the wafer as a base material, the handling property is lowered, and the wafer is damaged. Therefore, in the present embodiment, in each process until the rewiring layer 53 is formed on the surface 2a side of the wafer 55, the wafer having the first thickness that can prevent the handling property from being deteriorated is processed. Then, the back surface 55b side is ground to a second thickness that is thinner than the first thickness. This makes it possible to reduce the thickness of the obtained WPP 51 while preventing breakage of the wafer during the manufacturing process.

  The grinding method in this step is not particularly limited. For example, the back surface 55b (see FIG. 38) of the wafer 55 can be ground using a grinding member such as a grindstone (not shown). Further, in order to prevent residues and the like during grinding from remaining on the back surface 2b (see FIG. 45) of the wafer 55 after grinding, for example, polishing (polishing) is performed on the back surface 2b using abrasive particles (not shown). It is preferable to perform processing. In this step, it is preferable to perform grinding with a protective tape (protective sheet; not shown) covering the surface 2a side of the wafer 55, that is, the surface on which the rewiring layer 53 is formed. This is to protect the surface 2a side from damage due to application of external force during the grinding process.

4). Ball Mounting Step Next, in the ball mounting step, as shown in FIG. 46, the solder balls 10 to be bonded to the land portions 53c are formed. 46 is an enlarged cross-sectional view showing a state where solder balls are joined to the land portion shown in FIG.

  In this step, the solder ball 10 can be formed by applying the ball mounting step described in the first embodiment or the second embodiment. When the ball mounting process described in the first embodiment is applied, first, a plurality of solder balls are disposed on the land portion 53c from above the land portion 53c via a bonding material (flux material or cream solder). 15 (see FIG. 20) is arranged. Next, as a reflow process, heat is applied to the plurality of solder balls 15, the plurality of solder balls 15 are integrated, and joined to the land portion 53 c to form the solder balls 10. When the ball mounting process described in the second embodiment is applied, first, solder balls 10 (see FIG. 26) having a plurality of core balls 11 (see FIG. 26) are formed in advance. Next, the solder ball 10 is disposed on the land portion 53c from above the land portion 53c via a bonding material (flux material or cream solder). Next, as a reflow process, heat is applied to the solder balls 10 to join the land portions 53c. As shown in FIG. 46, in the reflow process, the solder ball 15 or the solder ball 10 is heated with the surface 2a of the semiconductor wafer (in other words, the upper surface 53a of the rewiring layer 53) facing downward. In other words, the solder ball 15 or the solder ball 10 is heated in a state where it is disposed below the land portion 53c. As a result, the core ball 11 having a specific gravity lighter than that of the solder material 12 moves in the solder material 12, so that the plurality of core balls 11 can be arranged close to the land portion 53c in the solder ball 10. . This step can also be performed before the above-described back grinding step. However, when the diameter of the solder ball 10 is large in the back grinding step, a high level of technology is required. It is preferable to carry out later.

5. Individualization Step Next, in the individualization step, the wafer 55 is divided along the dicing area 55c shown in FIG. 36, and is divided into individual device areas 55a to obtain a plurality of WPPs 51 shown in FIG. In the present embodiment, for example, in the present embodiment, the dicing region 55 c is cut using a cutting jig (rotary blade) such as a dicing blade and separated into a plurality of WPPs 51.

6). Inspection Process Next, in the inspection process, an appearance inspection and an electrical test of the WPP 51 are performed. Since the electrical test method included in this step is the same as the inspection step described in the first embodiment, a duplicate description is omitted.

  Through the above steps, the WPP 51 shown in FIG. 33 is completed. Thereafter, it is shipped or mounted on the mounting board 20 shown in FIG.

<Modification>
Incidentally, as a modification of the WPP 51 described in the present embodiment, as shown in FIG. 47, the land portion 57 can also be applied to the WPP 56 protruding from the upper surface 53a of the insulating film 53f. FIG. 47 is an enlarged cross-sectional view showing a modification of the semiconductor device shown in FIG. The land portion 57 shown in FIG. 47 is a conductor in which, for example, a copper (Cu) layer and a nickel (Ni) layer are sequentially laminated, and is formed in a columnar shape (post shape). The lower surface 57b side of the land portion 57 is electrically connected to the wiring (rewiring) 53d of the rewiring layer 53, and the upper surface 57a side protrudes above the upper surface 53a of the insulating film 53f. In other words, a part of the side surface 57c of the land portion 57 is exposed from the insulating film 53f.

  Thus, by projecting the upper surface 57a of the land portion 57 on the upper surface 53a of the insulating film 53f, in the mounting process of mounting the WPP 56 on the mounting substrate, the upper surface 53a of the insulating film 53f and the mounting surface of the mounting substrate A clearance can be secured between them. Further, by exposing a part of the side surface 57c of the land portion 57 from the insulating film 53f and bonding the solder material 12 of the solder ball 10 to the side surface 57c, the bonding area of the solder material 12 is increased. For this reason, the bonding strength between the solder ball 10 and the land portion 57 can be improved.

  Here, as shown in FIG. 47, the land portion 57 of the present embodiment has a shape in which the central portion 57d of the upper surface 57a is recessed with respect to the peripheral portion 57e. In other words, the central portion 57d of the upper surface 57a is a stepped portion that is lower than the peripheral portion 57e. The height difference between the central portion 57d and the peripheral portion 57e of the upper surface 57a is, for example, about 8 μm. Further, the outer dimension of the peripheral portion 57e is, for example, a circle having a diameter of about 220 μm, and the outer dimension of the central portion 57d is a circle having a diameter of about 200 μm. As described above, by providing the stepped portion on the upper surface 57a of the land portion 57, the solder ball 15 or the solder ball 10 can be stably disposed in the above-described ball mounting process. When the stepped portion is provided on the upper surface 57a of the land portion 57 as in the present embodiment, the solder ball 15 or the solder ball 10 is disposed so that the center of the solder ball 10 is disposed in the stepped portion in the ball mounting process. This is because the position of the ball 15 or the solder ball 10 is stabilized. In particular, when a flux material is used as a bonding material for bonding the solder ball 10 and the land portion 57, when the reflow process is performed in a state where the position of the solder ball is shifted in the solder ball placement process, it is compared with the case where cream solder is used. As a result, poor solder ball bonding is likely to occur. Therefore, this modification is particularly effective when applied to a flux material that does not contain a solder component as the bonding material.

  Next, a difference between the land portion 57 formation method and the rewiring forming process described with reference to FIGS. 39 to 44 will be described. 48 to 52 are explanatory views showing details of a process of forming the rewiring layer shown in FIG.

  In the method for manufacturing WPP 56 shown in FIG. 47, in the first resist film forming step of the rewiring layer forming step described above, as shown in FIG. 48, a part of a planned region for forming wiring 53d (see FIG. 47) (see FIG. 47). Patterning is performed so as to leave the resist film 58 in a region where a land portion 57 is to be formed as shown in 47 (first resist film forming step). Next, as shown in FIG. 49, a wiring 53d is formed by electrolytic plating in the presence of the resist films 54 and 58 (rewiring forming step). At this time, since an electrolytic plating film is not formed in the region where the resist film 58 is disposed, the conductor film 53s is exposed from the wiring 53d immediately below the resist film 58. Next, the resist films 54 and 58 shown in FIG. 49 are removed (first resist film removing step). Next, as shown in FIG. 50, a resist film (plating resist film, second resist film) 59 is disposed on the wiring 53d and then patterned (second resist film forming step). In the patterning of the resist film 59, patterning is performed so as to remove a region where the land portion 57 shown in FIG. 47 is to be formed. Specifically, the opening 59a is formed inside the wiring 53d so that the conductor film 53s is exposed and a part of the surrounding wiring 53d is exposed from the resist film 59. Next, as shown in FIG. 51, the land portion 57 is formed (land portion forming step). In the present embodiment, for example, an electrolytic plating film of a copper (Cu) film and a nickel (Ni) film is sequentially formed. When a metal film is formed on the opening 59a of the resist film 59 by electrolytic plating, a land portion 57 is formed following the shape of the bottom surface of the opening 59a. In the present embodiment, since the opening 59a is formed in the second resist film forming step so that a part of the wiring 53d is exposed from the resist film 59, the wiring 53d and the wiring 53d are formed on the bottom surface of the opening 59a. A step of the conductor film 53s is formed. For this reason, the upper surface 57a of the land portion 57 formed in this step has a shape in which the central portion 57d of the upper surface 57a is recessed with respect to the peripheral edge portion 57e. Next, the unnecessary conductor film 53s other than the region where the resist film 59, the wiring 53d, and the land portion 57 shown in FIG. 51 are formed is removed (seed layer removing step). Next, as shown in FIG. 52, an insulating film (organic insulating film) 53f made of an organic compound such as polyimide resin is formed so as to cover the wiring 53d (second insulating film forming step). In this step, the insulating film 53f is formed thinner than the land portion 57 so that a part of the side surface 57c of the land portion 57 is exposed. Through the above steps, the rewiring layer 53 in which the side surface 57c of the land portion 57 is exposed from the insulating film 53f can be formed.

  The semiconductor device manufacturing method of the present embodiment is the same as the semiconductor device and the manufacturing method thereof described in the first to fourth embodiments except for the differences described above. Therefore, although the overlapping description is omitted, the invention described in the first to fourth embodiments can be applied except for the above differences.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the rewiring layer 53 described in the fifth embodiment is not formed, and the semiconductor device 60 is applied to the solder ball 10 bonded to the electrode pad (bonding pad) 2c of the semiconductor chip 2 as shown in FIG. can do. FIG. 53 is an enlarged cross-sectional view showing a modification of the semiconductor device shown in FIG. In the method of manufacturing the semiconductor device 60, for example, in the method of manufacturing the WPP 51 described in the fifth embodiment, the land portion 53c is replaced with the electrode pad 2c, and the upper surface 53a of the redistribution layer 53 is replaced with the surface 2a of the semiconductor wafer. Can be applied. Further, for example, the solder ball 10 shown in FIG. 53 can be replaced with the solder ball 10 or the solder ball 47 described in the second to third embodiments. The semiconductor device 60 shown in FIG. 53 is mounted directly on a mounting substrate, for example, a plurality of semiconductor chips are stacked, and the plurality of semiconductor chips are electrically connected to each other via solder balls. It can be used as a semiconductor chip incorporated in a semiconductor device having a chip-on-chip structure.

  Further, for example, as a modification of the semiconductor device 60 shown in FIG. 53, an underbump metal film (underbump conductor film) is interposed between the solder ball 10 and the electrode pad 2c, and the above-described under bump metal film is formed on the underbump metal film. It can also be applied to the semiconductor device to which the solder ball 10 or the solder ball 47 described in the first to third embodiments is joined. Thus, the structure in which the under bump metal film is formed on the electrode pad 2c and the under bump metal film is formed can be considered as a modification of the WPP 51 described in the fifth embodiment. That is, in the fifth embodiment, the rewiring layer 53 is formed on the electrode pad 2c, so that the planar position of the solder ball 10 serving as the external terminal is changed to a position different from the electrode pad 2c. However, as a modified example, a WPP having a structure in which the solder ball 10 is connected via the under bump metal film directly above the electrode pad 2c may be used.

  The present invention is applicable to a semiconductor device provided with solder balls as external terminals.

1 BGA (semiconductor device)
2 Semiconductor chip 2a Front surface 2b Back surface 2c Electrode pad (bonding pad)
2d Semiconductor substrate 2da Main surface 2e Semiconductor element formation region 2f Wiring layer 2ga Wiring (internal wiring)
2gb surface wiring 2h, 2k insulating layer 3 interposer substrate (wiring substrate)
3a Upper surface 3b Lower surface 3c Bonding lead 3d Land (bump land)
3d1 Copper film 3d2 Plating film 3e Wiring 3f, 3g Solder resist film 3h Core layer 3k Opening 4 Wire (conductive member)
5 Adhesive Material 6 Sealing Resin 6a Sealing Resin 6b Collective Sealing Body 10 Solder Ball 11 Core Ball 11a Core Material 11b Metal Film 12 Solder Material 15 Solder Ball 16 Solder Material 20 Mounting Board 20a Mounting Surface 21 Terminal 22 Cream Solder 23 Solder material 25 Wiring board 25a Device region 25b Frame portion 25c Dicing region 30 Molding die 31 Upper die 31a Lower surface 31b Cavity 32 Lower die 32a Upper surface 35 Flux material 36 Screen mask 36a Through hole 37 Squeegee 40 Mask 40a, 40b Through hole 41 Dicing blade (Rotating blade)
42 Inspection Device 42a Electrical Test Circuit 43 Probe Pin 45 Mask 45a Through Hole 46 Core Ball 46a Core Material 46b Metal Film 47 Solder Ball 48 Mask 48a, 48b Through Hole 49 Suction Jig 49a Suction Port 51, 56 WPP (Semiconductor Device) )
53 Rewiring layer 53a Upper surface 53b Lower surface 53c Land part (bump land)
53d Wiring (rewiring)
53e, 53f Insulating film (organic insulating film)
53s Conductor film (seed layer)
54 Resist film 55 Wafer 55a Device region 55b Back surface 55c Dicing region 57 Land (bump land)
57a Upper surface 57b Lower surface 57c Side surface 57d Center portion 57e Peripheral portion 58, 59 Resist film 59a Opening portion 60 Semiconductor device 101 Solder ball 102 Core balls W1, W2, W3 Diameter

Claims (20)

A semiconductor chip having a front surface, a bonding pad formed on the front surface, and a back surface opposite to the front surface;
A solder ball electrically connected to the bonding pad of the semiconductor chip;
Including
The solder ball has a plurality of core balls and a solder material covering the plurality of core balls. In claim 1,
Each of the plurality of core balls has a uniform diameter. In claim 2,
Each of the plurality of core balls has a diameter smaller than a radius of the solder ball. In claim 3,
The solder ball is bonded to the bonding pad or a bump land electrically connected to the bonding pad,
The center of each of the plurality of core balls is arranged closer to the bonding pad or the bump land than the center of the solder ball. In claim 4,
Each of the plurality of solder balls includes the same number of the core balls. In claim 1,
The semiconductor device includes:
A wiring substrate having an upper surface, a plurality of bonding leads formed on the upper surface, a lower surface opposite to the upper surface, and a plurality of bump lands formed on the lower surface;
The semiconductor chip mounted on the upper surface of the wiring board, having the surface, the plurality of bonding pads formed on the surface, and the back surface opposite to the surface;
A plurality of conductive members that electrically connect the plurality of bonding pads of the semiconductor chip and the plurality of bonding leads of the wiring substrate;
A plurality of the solder balls formed on the plurality of bump lands;
Including
Each of the plurality of solder balls includes the plurality of core balls and the solder material covering the plurality of core balls. In claim 1,
The semiconductor device includes:
The semiconductor chip;
A lower surface formed on the surface of the semiconductor chip and facing the surface of the semiconductor chip, an upper surface opposite to the lower surface, and electrically formed with the plurality of bonding pads of the semiconductor chip formed on the upper surface A redistribution layer having a plurality of bump lands connected thereto;
A plurality of the solder balls formed on the plurality of bump lands;
Including
Each of the plurality of solder balls includes the plurality of core balls and the solder material covering the plurality of core balls. In claim 1,
The plurality of core balls include a core material made of resin,
A semiconductor device comprising a metal film formed on a surface of the core material. In claim 1,
The plurality of core balls are composed of only a core material made of metal, or the core material made of the metal and a metal film formed on the surface of the core material. In claim 1,
The plurality of core balls include a first core material made of resin, a first core ball made of a metal film formed on the surface of the first core material, and a second core made of a second core material made of metal. A semiconductor device including a ball. A method for manufacturing a semiconductor device comprising the following steps:
(A) preparing a semiconductor chip having a surface, a bonding pad formed on the surface, and a back surface opposite to the surface;
(B) A plurality of first solder balls via a bonding material from above the bonding pad or bump land electrically connected to the bonding pad, on the bonding pad or on the bump land. Placing
(C) After the step (b), heat is applied to the plurality of first solder balls so that the plurality of first solder balls are integrated and bonded to the bonding pad or the bump land. 2 forming solder balls;
here,
Each of the plurality of first solder balls arranged in the step (b) has one core ball and a solder material covering the core ball,
The second solder ball formed in the step (c) has a plurality of the core balls and the solder material covering the plurality of core balls. In claim 11,
A plurality of the bonding pads are formed on the surface of the semiconductor chip prepared in the step (a),
The core material each of the plurality of core balls has a lighter specific gravity than the solder material,
In the step (c),
The plurality of first solder balls in a state where the plurality of first solder balls are disposed below the plurality of bonding pads or the plurality of bump lands electrically connected to the plurality of bonding pads. A method for manufacturing a semiconductor device, comprising: In claim 12,
In the step (b),
A mask in which a plurality of through holes are formed is disposed on the plurality of bonding pads or the plurality of bump lands, and one first solder ball is placed in each of the plurality of through holes. A method for manufacturing a semiconductor device, comprising: disposing the semiconductor device. In claim 13,
A method of manufacturing a semiconductor device, wherein the plurality of first solder balls have the same diameter. In claim 11,
Each of the plurality of core balls has a diameter smaller than a radius of the second solder ball. In claim 11,
A method for manufacturing a semiconductor device, further comprising the following steps:
(A1) Before the step (b), a wiring board having an upper surface, a plurality of bonding leads formed on the upper surface, a lower surface opposite to the upper surface, and a plurality of the bump lands formed on the lower surface Preparing the step;
(A2) After the step (a) and the step (a1) and before the step (b), the semiconductor chip having a plurality of the bonding pads formed on the surface is formed on the wiring board. Mounting on the top surface;
(A3) After the step (a2) and before the step (b), the plurality of bonding pads of the semiconductor chip and the plurality of bonding leads of the wiring substrate are replaced with a plurality of conductive members. Via each of them electrically connected;
here,
In the step (b), the plurality of first solder balls are disposed on each of the plurality of bump lands with the lower surface of the wiring board facing upward.
In the step (c), heat is applied to the plurality of first solder balls in a state where the lower surface of the wiring board faces downward, and the plurality of first solder balls are integrated to form the plurality of bumps. A plurality of the second solder balls to be bonded to each of the lands are formed. A method for manufacturing a semiconductor device comprising the following steps:
(A) preparing a semiconductor chip having a surface, a bonding pad formed on the surface, and a back surface opposite to the surface;
(B) A step of placing solder balls on the bonding pads or the bump lands from above the bonding pads or the bump lands electrically connected to the bonding pads via a bonding material. ;
(C) After the step (b), heat is applied to the solder balls to join the bonding pads or the bump lands;
here,
The solder ball includes a plurality of core balls and a solder material that covers the plurality of core balls. In claim 17,
A plurality of the bonding pads are formed on the surface of the semiconductor chip prepared in the step (a),
The core material each of the plurality of core balls has a lighter specific gravity than the solder material,
In the step (c),
The plurality of solder balls are disposed below the plurality of bonding pads or the plurality of bump lands electrically connected to the plurality of bonding pads. A method for manufacturing a semiconductor device, comprising bonding to a bonding pad or the plurality of bump lands. In claim 17,
A diameter of each of the plurality of core balls is smaller than a radius of the solder ball. In claim 17,
A method for manufacturing a semiconductor device, further comprising the following steps:
(A1) Before the step (b), a wiring board having an upper surface, a plurality of bonding leads formed on the upper surface, a lower surface opposite to the upper surface, and a plurality of the bump lands formed on the lower surface Preparing the step;
(A2) After the step (a) and the step (a1) and before the step (b), the semiconductor chip having a plurality of the bonding pads formed on the surface is formed on the wiring board. Mounting on the top surface;
(A3) After the step (a2) and before the step (b), the plurality of bonding pads of the semiconductor chip and the plurality of bonding leads of the wiring substrate are replaced with a plurality of conductive members. Via each of them electrically connected;
here,
In the step (b), with the lower surface of the wiring board facing upward, the solder balls are disposed on each of the plurality of bump lands,
In the step (c), heat is applied to the solder balls in a state where the lower surface of the wiring board is directed downward to join each of the plurality of bump lands.

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