JP2012033580A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

To improve metallization in a via hole formed in a substrate.
A method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device including a substrate made of SiC, and etching the back surface of the substrate using an etching gas containing fluorocarbon and a mask. The first step of forming the first region 22 having a tapered shape in which the opening area gradually decreases from the back surface to the front surface of the substrate 10, and then the first step using the etching gas containing sulfur fluoride and the mask 14. A second step of forming the second region 24 by etching the inside of the region 22, and the inclination angle of the inner wall surface of the second region 24 with respect to the surface of the substrate 10 is It is characterized by being larger than the inclination angle of the inner wall surface.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

A semiconductor device using silicon carbide (SiC) as a substrate material is known. For example, a high-power high electron mobility transistor (HEMT) can be formed by stacking a nitride-based semiconductor layer (for example, a GaN-based semiconductor layer) on a substrate. Since the SiC substrate is harder than a normal silicon substrate, via holes (through holes) are formed in the SiC substrate by, for example, reactive ion etching (RIE) dry etching. For example, SF ₆ can be used as an etching gas (see, for example, Patent Document 1).

JP 2005-322811 A

  When forming a via hole in a substrate, under the conventional etching conditions, the inner wall surface of the via hole becomes a shape perpendicular to the substrate surface. As a result, metallization applied to the inside of the via hole is deteriorated, and disconnection may occur between the wiring on the substrate surface. Such a phenomenon is more likely to occur as the aspect ratio of the via hole becomes higher (as the area of the opening of the via hole becomes smaller).

The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device capable of improving metallization in a via hole formed in a substrate and a method for manufacturing the same.

  The manufacturing method of the present semiconductor device is a manufacturing method of a semiconductor device including a substrate made of SiC, and etches the back surface of the substrate using an etching gas containing fluorocarbon and a mask, from the back surface of the substrate. A first step of forming a first region having a tapered shape with an opening area gradually decreasing toward the surface, and then etching the inside of the first region using an etching gas containing sulfur fluoride and the mask; A second step of forming a second region, wherein an inclination angle of the inner wall surface of the second region with respect to the surface of the substrate is larger than an inclination angle of the inner wall surface of the first region with respect to the surface of the substrate. Features.

  In the above configuration, the first step includes inductively coupled plasma (ICP) type dry etching using the carbon fluoride as an etching gas, and the etching conditions include a gas flow rate of carbon fluoride = 10 to 10%. 200 sccm, the gas pressure is Press = 0.1 to 10.0 Pa, the inductively coupled plasma power is ICP = 100 to 5000 W, the bias power is Bias = 10 to 1000 W, and the second step is an etching gas. Including the inductively coupled plasma type dry etching using the sulfur fluoride or a mixed gas of the sulfur fluoride and oxygen, the etching conditions in the case of using the sulfur fluoride include a gas flow rate of sulfur fluoride = 10 to 200 sccm, Etching pressure is Press = 0.1-10.0Pa, inductive coupling The etching conditions when the plasma power is ICP = 100 to 5000 W, the bias power is Bias = 10 to 1000 W, or a mixed gas of sulfur fluoride and oxygen is used, the gas flow rate is sulfur fluoride / oxygen = 10 ˜200 sccm / 1 to 150 sccm, etching pressure is Press = 0.1 to 10.0 Pa, inductively coupled plasma power is ICP = 100 to 5000 W, and bias power is Bias = 10 to 1000 W. Can do.

  In the above configuration, the mask may include Ni.

  In the above configuration, the opening width of the mask may be larger than the opening width of the second region.

  The method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device including a substrate made of SiC, and etches the back surface of the substrate using an etching gas containing fluorocarbon and oxygen and a metal mask. Forming a first region having a tapered shape with an opening area gradually decreasing from the back surface to the front surface and a second region obtained by etching the inside of the first region, and the second region with respect to the surface of the substrate. The inclination angle of the inner wall surface of the region is larger than the inclination angle of the inner wall surface of the first region with respect to the surface of the substrate.

  In the above structure, the step of forming the first region and the second region includes inductively coupled plasma type dry etching using a mixed gas of fluorocarbon and oxygen as an etching gas, and the etching conditions include a gas flow rate, Carbon fluoride / oxygen = 10 to 200 sccm / 1 to 150 sccm, gas pressure is Press = 0.1 to 10.0 Pa, inductively coupled plasma power is ICP = 100 to 5000 W, bias power is Bias = 10 to 1000 W, It can be set as the structure which is.

  The said structure WHEREIN: The said metal mask can be set as the structure containing Ni.

  In the above configuration, the opening width of the mask may be larger than the opening width of the second region.

  The said structure WHEREIN: It can be set as the structure which has the process of forming a metal layer in the inner surface of the back surface of the said board | substrate, the said 1st area | region, and the said 2nd area | region.

  In the above configuration, the step of forming the metal layer includes a step of forming a seed layer by sputtering film formation on a back surface of the substrate, an inner wall surface of the first region and the second region, and a plating layer on the seed layer. The process of forming can be made.

  According to the present invention, metallization in a via hole formed in a substrate can be improved.

FIG. 1 is a diagram illustrating a configuration of a semiconductor device according to a comparative example. FIG. 2 is a diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 3 is a diagram illustrating the configuration of the semiconductor device according to the first embodiment.

(Comparative example)
First, a semiconductor device according to a comparative example will be described.

  FIG. 1A is a diagram illustrating a configuration of a semiconductor device 80 according to a comparative example. A nitride semiconductor layer 12 is formed on the surface of the substrate 10 made of SiC. A via hole 20 penetrating the substrate 10 and the nitride semiconductor layer 12 is provided, and a via pad 40 is provided in the opening of the via hole 20 on the surface of the nitride semiconductor layer 12. In the following description, of the two main surfaces of the substrate 10, the main surface on the side where the nitride semiconductor layer 12 is provided is referred to as the front surface, and the opposite main surface is referred to as the back surface. The thickness A of the substrate 10 can be set to 100 μm, for example, and the diameter B of the opening of the via hole 20 can be set to 50 μm, for example.

The via hole 20 is formed, for example, by RIE dry etching using SF ₆ (sulfur fluoride) as an etching gas. At this time, the cross-sectional shape of the via hole 20 is such that the inner wall surface is perpendicular to the surface of the substrate 10.

  FIG. 1B shows an example in which the metal layer 30 is formed by metallizing the back surface of the substrate 10 and the inner wall surface of the via hole 20. The metal layer 30 electrically connects the front surface and the back surface of the substrate 10. However, as described above, when the inner wall surface of the via hole 20 is perpendicular to the surface of the substrate 10, the metallization in the via hole 20 is deteriorated, and disconnection may occur (for example, reference numeral 50 in the drawing). (Refer to the section indicated by).

  FIG. 2 is a diagram illustrating the method for manufacturing the semiconductor device 100 according to the first embodiment. As shown in FIG. 2A, a nitride semiconductor layer 12 is formed on the surface of a substrate 10 made of SiC. The nitride semiconductor layer 12 includes, for example, a 300 nm buffer layer made of AlN, a 1000 nm channel layer (electron transit layer) made of i-GaN, a 20 nm electron supply layer made of n-AlGaN, and It has a structure in which 5 nm cap layers made of n-GaN are sequentially stacked. As the nitride semiconductor layer 12, GaN, AlN, InN, InGaN, AlGaN, InAlN, InAlGaN, or the like can be used. A via pad 40 is provided in a region where a via hole is to be formed on the surface of the nitride semiconductor layer 12. For the via pad 40, for example, a stacked body of Ni and Au can be used.

First, as shown in FIG. 2A, a Ni metal mask 14 is formed on the back surface of the substrate 10 (NiCr may be used in addition to Ni). Next, as shown in FIG. 2B, a first step of via etching is performed. As an etching method, dry etching using an ICP method is employed, and CF ₄ (fluorocarbon) is used as an etching gas. In the following description, the gas pressure during etching is represented by Press, the antenna power of inductively coupled plasma is represented by ICP, and the bias power is represented by Bias. Etching conditions are CF ₄ = 100 sccm (gas flow rate), Press = 5.0 Pa, ICP / Bias = 2000/500 W. By this step, a recess (the first region 22 of the via hole) is formed on the back surface of the substrate 10. The first region 22 has an opening on the back surface of the substrate 10 and has a tapered shape in which the opening cross-sectional area gradually decreases from the back surface to the surface of the substrate 10.

Next, as shown in FIG. 2C, a second step of via etching is performed. Etching is continued by the ICP method, and SF ₆ is used as an etching gas. The etching conditions are SF ₆ = 100 sccm, Press = 5.0 Pa, ICP / Bias = 2000/500 W. By this step, the second region 24 of the via hole is formed. The second region 24 is open to the first region 22 and the surface of the substrate 10 and reaches the via pad 40. The inclination angle of the inner wall surface of the second region 24 is larger than that of the first region 22. In this embodiment, the cross-sectional shape of the second region 24 is such that the inner wall surface is substantially perpendicular to the surface of the substrate 10, but the inner wall surface of the second region 24 may not be perpendicular.

  The via hole 20 is formed in the substrate 10 through the above steps. The shape of the via hole 20 is such that the opening on the back surface is the widest, the opening cross-sectional area gradually decreases in a tapered shape, and the opening cross-sectional area becomes almost constant from the middle.

  Next, as shown in FIG. 2D, the metal mask 14 is removed. Finally, as shown in FIG. 2E, a metal layer 30 is formed on the back surface of the substrate 10 and inside the via hole 20. For example, the metal layer 30 is formed by first forming a seed layer 32 made of Ti and Au by sputtering, and then forming a plating layer 34 made of Au by plating. Metal layer 30 is electrically connected to via pad 40.

  FIG. 3 is a diagram illustrating the configuration of the semiconductor device 100 according to the first embodiment. FIG. 3A shows a state before metallization, and FIG. 3B shows a state after metallization. As shown in FIG. 3A, the thickness A of the substrate 10 can be 100 μm, the diameter B of the opening in the first region 22 can be 100 μm, and the diameter C of the opening in the second region 24 can be 50 μm. The dimension of each part is not limited to this. Further, as shown in FIG. 3B, since the shape of the via hole 20 is a funnel shape and a tapered portion is formed in the first region 22, the seed layer 32 is easily attached by sputtering film formation, and plating is performed. The thickness of the layer 30 can be easily increased. As a result, the metallization of the metal layer 30 (seed layer 32 and plating layer 34) is better than the comparative example.

In the semiconductor device according to the first embodiment, the substrate 10 made of SiC is formed by performing ICP-type dry etching in which the etching gas is CF ₄ in the first step and the etching gas is SF ₆ in the second step. It is possible to form a via hole 20 having a shape of a funnel. C-based residues (mixtures and compounds of C, Si, Ni) generated during etching using CF ₄ have a high deposit growth rate and a high selectivity with SiC. For this reason, it is considered that the etching proceeds obliquely with the growth of the deposit, and a tapered via hole (first region 22) is formed. Further, after the first region 22 is formed, by performing etching with SF ₆ , a via hole (second region 24) having a substantially vertical cross-sectional shape is formed, and the beer-shaped via hole 20 is formed together with the first region 22. Can be formed.

By making the via hole 20 into the shape of a wax, the metallization in the via hole 20 can be improved. Further, since the opening on the front surface is smaller than the opening on the back surface of the substrate 10, the opening size for vias on the front surface side can be reduced. In addition, when the semiconductor device 100 is die-attached to a package or the like, the inclination of the via hole 20 on the back side of the substrate 10 is smaller than 90 °, thereby reducing stress concentration at the end of the via hole 20 due to thermal expansion of the package. can do. Further, by using the etching with CF ₄ and the etching with SF ₆ together, the time required for forming the via hole 20 can be shortened as compared with the case where the etching is performed only with CF ₄ .

  In the first embodiment, the ICP dry etching is used as an etching method. However, other methods may be used as long as the dry etching using a fluorocarbon plasma and a metal mask. However, according to the ICP method, since the plasma power and the bias power can be controlled independently, etching in a high-density plasma and low bias environment becomes possible. Further, etching at a low pressure (for example, Press ≦ 10 Pa) can be performed. As a result, deposition of deposits on the side walls of the via holes is promoted, so that a tapered cross section can be formed. Further, in the ICP method, since the distance between the plasma and the wafer (substrate 10) can be reduced, it is possible to suppress the etching from stopping halfway. From the above, the ICP dry etching is suitable for forming the funnel-shaped via hole 20. Also, the deposit speed and tilt angle can be easily adjusted.

The etching conditions shown in Example 1 are merely examples, and the present invention is not limited to the above form. For example, in the second step, not only SF ₆ but also a mixed gas of SF ₆ and O ₂ may be used. In this case, the etching rate is improved as compared with the case where only SF ₆ is used. Preferred etching conditions are shown below.

In the first step shown in FIG. _{2 (b), CF 4 =} 10~200sccm, Press = 0.1~10.0Pa, it is preferable that the ICP / Bias = 100~5000W / 10~1000W. Further, CF ₄ = 50 to 150 sccm, Press = 3.0 to 7.0 Pa, ICP / Bias = 1500 to 3000 W / 300 to 700 W are more preferable.

In a second step shown in FIG. _{2 (c), SF 6 =} 10~200sccm, Press = 0.1~10.0Pa, is preferably ICP / Bias = 100~5000W / 10~1000W. _{Further, SF 6 = 70~100sccm, Press =} 3.0~7.0Pa, further preferably ICP / Bias = 1500~3000W / 300~700W.

Further, in the second step shown in FIG. _{2 (c), SF 6 /} O 2 = 10~200sccm / 1~150sccm, Press = 0.1~10.0Pa, in ICP / Bias = 100~5000W / 10~1000W Preferably there is. Further, SF ₆ / O ₂ = 70 to 100 sccm / 0 to 30 sccm, Press = 3.0 to 7.0 Pa, ICP / Bias = 1500 to 3000 W / 300 to 700 W are more preferable.

  In the first embodiment, Ni is used as the metal mask 14 at the time of etching, but Cu, Al, Cr, or the like can also be used. However, by using Ni as the metal mask 14 (so that Ni is included in the deposit), the surface of the tapered portion of the via hole 20 becomes smooth, so that a better via shape can be obtained.

In Example 1, CF ₄ is used as the etching gas in the first step, but another fluorocarbon-based gas (for example, C ₂ F ₈ ) may be used instead of CF ₄ . Further, other sulfur fluoride-based gas may be used instead of SF ₆ used as the etching gas in the second step.

  Example 2 is an example in which a funnel-shaped via hole is formed in one step. The configuration of the semiconductor device according to the second embodiment is the same as that of the first embodiment (FIG. 3), and the description thereof is omitted.

The manufacturing method of the semiconductor device according to the second embodiment is the same as that of the first embodiment (FIG. 2A) until the metal mask 14 is first formed on the back surface of the substrate 10. Next, ICP dry etching is performed in the same manner as in Example 1. In Example 2, a mixed gas of CF ₄ and O ₂ is used as an etching gas. Etching conditions are CF ₄ / O ₂ = 90/10 sccm, Press = 5.0 Pa, and ICP / Bias = 2000/500 W. Further, Ni is used for the metal mask 14.

Etching with a mixed gas of CF ₄ and O ₂ has a higher etching rate than when CF ₄ gas is used alone. In the initial stage of etching, the etching proceeds in a tapered shape as in the first embodiment, and the first region 22 is formed (FIG. 2B). As the etching becomes deeper, the amount of Ni scattered from the metal mask 14 decreases. When the etching rate in the depth direction of the substrate becomes higher than the deposition rate of the deposit, the etching proceeds in a substantially vertical direction, and the second region 24 having a large inclination angle of the inner wall surface is formed (FIG. 2C). )). Through the above steps, a solder-like via hole 20 is formed in the substrate 10.

  After the formation of the via hole, the removal of the metal mask 14 (FIG. 2D) and the formation of the metal layer 30 (FIG. 2E) are performed as in the first embodiment. Thereby, the semiconductor device 100 according to the second embodiment is completed.

  According to the second embodiment, similarly to the first embodiment, the metallization in the via hole 20 can be improved. Further, by forming the via hole 20 in one step, the number of steps can be reduced as compared with the first embodiment.

  The etching conditions shown in Example 2 are merely examples, and the etching conditions are not limited to the above-described embodiment, but preferable etching conditions are shown below.

Etching conditions are preferably CF ₄ / O ₂ = 10 to 200 sccm / 1 to 150 sccm, Press = 0.1 to 10.0 Pa, and ICP / Bias = 100 to 5000 W / 10 to 1000 W. Further, CF ₄ / O ₂ = 70 to 100 sccm / 1 to 30 sccm, Press = 3.0 to 7.0 Pa, ICP / Bias = 1500 to 3000 W / 300 to 700 W are more preferable.

In addition, as to the type of etching gas, the etching method, and the material of the metal mask 14, other methods shown in the first embodiment may be used. However, as described in the first embodiment, it is preferable that the etching gas is CF ₄ , the etching method is ICP, and the material of the metal mask 14 is Ni.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Substrate 12 Nitride semiconductor layer 20 Via hole 22 1st area | region 24 2nd area | region 30 Metal layer 32 Seed layer 34 Plating layer 40 Via pad

Claims (10)

A method for manufacturing a semiconductor device including a substrate made of SiC,
A first step of etching the back surface of the substrate using an etching gas containing fluorocarbon and a mask to form a first region having a tapered shape in which an opening area gradually decreases from the back surface to the surface of the substrate;
A second step of forming a second region by etching the inside of the first region using an etching gas containing sulfur fluoride and the mask;
The method of manufacturing a semiconductor device, wherein an inclination angle of an inner wall surface of the second region with respect to a surface of the substrate is larger than an inclination angle of an inner wall surface of the first region with respect to the surface of the substrate. The first step includes inductively coupled plasma type dry etching using the carbon fluoride as an etching gas, and the etching conditions are:
The gas flow rate is fluorocarbon = 10 to 200 sccm,
Gas pressure is Press = 0.1-10.0 Pa,
Inductively coupled plasma power is ICP = 100 to 5000 W,
The bias power is Bias = 10 to 1000 W,
The second step includes inductively coupled plasma type dry etching using the sulfur fluoride or a mixed gas of sulfur fluoride and oxygen as an etching gas, and the etching conditions in the case of using the sulfur fluoride include:
The gas flow rate is sulfur fluoride = 10 to 200 sccm,
The pressure of etching is Press = 0.1-10.0 Pa,
Inductively coupled plasma power is ICP = 100 to 5000 W,
The bias power is Bias = 10 to 1000 W,
Alternatively, the etching conditions when using a mixed gas of sulfur fluoride and oxygen are:
The gas flow rate is sulfur fluoride / oxygen = 10 to 200 sccm / 1 to 150 sccm,
The pressure of etching is Press = 0.1-10.0 Pa,
Inductively coupled plasma power is ICP = 100 to 5000 W,
Bias power is Bias = 10 to 1000 W,
The method of manufacturing a semiconductor device according to claim 1, wherein:   The method of manufacturing a semiconductor device according to claim 1, wherein the mask contains Ni.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the opening width of the mask is larger than the opening width of the second region. A method for manufacturing a semiconductor device including a substrate made of SiC,
Etching the back surface of the substrate using an etching gas containing fluorocarbon and oxygen and a metal mask, and a first region and a first region having a tapered shape in which an opening area gradually decreases from the back surface to the surface of the substrate Forming a second region etched inside, and
The method of manufacturing a semiconductor device, wherein an inclination angle of an inner wall surface of the second region with respect to a surface of the substrate is larger than an inclination angle of an inner wall surface of the first region with respect to the surface of the substrate. The step of forming the first region and the second region includes inductively coupled plasma type dry etching using a mixed gas of carbon fluoride and oxygen as an etching gas.
Gas flow rate is carbon fluoride / oxygen = 10 to 200 sccm / 1 to 150 sccm,
Gas pressure is Press = 0.1-10.0 Pa,
Inductively coupled plasma power is ICP = 100 to 5000 W,
Bias power is Bias = 10 to 1000 W,
The method of manufacturing a semiconductor device according to claim 5, wherein:   6. The method of manufacturing a semiconductor device according to claim 5, wherein the metal mask contains Ni.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the opening width of the mask is larger than the opening width of the second region.   6. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a metal layer on an inner wall surface of the back surface of the substrate, the first region, and the second region. The step of forming the metal layer includes
Forming a seed layer on the inner surface of the back surface of the substrate, the first region and the second region by sputtering, and
The method of manufacturing a semiconductor device according to claim 9, further comprising: forming a plating layer on the seed layer.

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