JP2012023320A - Thin film transistor, display device using the same, and method for manufacturing thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor which suppresses OFF-state current and secures ON-state current.SOLUTION: A thin film transistor includes a substrate 10, a gate electrode 11 and a gate insulator 12 which are formed above the substrate, a channel layer 13 placed through the gate insulator, a buffer layer 14 connected to the channel layer, a first contact layer 15a (15b) connected to the buffer layer and to which impurities are added, a second contact layer 16a (16b) connected to the first contact layer and having impurity density which is higher than the first contact layer, and a source electrode 17S and a drain electrode 17D which are connected with the second contact layer. The carrier movement path between the source electrode and the drain electrode includes a first path in which carriers move through the channel layer, the buffer layer, the first contact layer and the second contact layer and a second path in which the carriers move through the channel layer and the second contact layer.

Description

  The present invention relates to a thin film transistor, a display device using the same, and a method for manufacturing the thin film transistor, and more particularly, to a thin film transistor suitable for driving a display element in a current driven display element such as an organic EL element.

  2. Description of the Related Art Conventionally, FPD (Flat Panel Display) has been actively developed, and display devices using an organic EL (Electro Luminescence) element or an LCD (Liquid Crystal Display) element are known.

  In recent years, organic EL display devices using current-driven organic EL elements have attracted attention as next-generation display devices. In particular, in an active matrix driving type organic EL display device, a field effect transistor is used. As one of the field effect transistors, a thin film transistor in which a semiconductor layer provided over a substrate having an insulating surface serves as a channel formation region. (TFT: Thin Film Transistor) is known.

  As a thin film transistor used in an active matrix driving type organic EL display device, at least a switching transistor for controlling driving timing such as on / off of the organic EL element, and driving for controlling the light emission amount of the organic EL element. A transistor is required. Each of these thin film transistors preferably has excellent transistor characteristics, and various studies have been made.

  For example, for a switching transistor, it is necessary to further reduce the off current and reduce the variation in both the on current and the off current. In addition, for the drive transistor, it is necessary to further improve the on-current and reduce the variation of the on-current.

  Therefore, conventionally, a technique using a microcrystalline silicon layer as a channel layer of a thin film transistor has been proposed. By using a microcrystalline silicon layer for the channel layer in this manner, carrier mobility in the channel layer can be increased, so that high on-state current can be ensured.

  In addition, in a thin film transistor, a technique of using a silicon layer containing a low-concentration impurity as a contact layer between a source or drain electrode and a channel layer has been proposed. Thus, off current can be suppressed by using a low-concentration impurity layer as the contact layer.

  As described above, a conventional technique for improving transistor characteristics has been proposed. For example, Patent Document 1 discloses a first technique including a low concentration impurity as a contact layer (drain layer or source layer) on a channel layer. A thin film transistor using a stack of one silicon layer and a second silicon layer containing a high concentration of impurities is disclosed.

  Patent Document 2 discloses a thin film transistor that uses a laminated structure of a polycrystalline silicon film and a hydrogenated amorphous silicon film as a channel layer, and further uses an impurity-added silicon film as a contact layer.

JP 2008-258345 A JP 2005-057056 A

  However, the thin film transistor disclosed in Patent Document 1 can secure an on-current, but there is a problem that an off-current is not sufficiently suppressed.

  In the thin film transistor disclosed in Patent Document 2, the off-state current can be suppressed by the hydrogenated amorphous silicon film. However, there is a problem that the on-state cannot be secured and the on-state characteristics deteriorate.

  SUMMARY An advantage of some aspects of the invention is to provide a thin film transistor, a display device, and a method of manufacturing the thin film transistor that can suppress the off current and ensure the on current.

  In order to solve the above problems, one embodiment of a thin film transistor according to the present invention is a substrate, a gate electrode and a gate insulating film formed over the substrate, and the gate electrode facing the gate electrode. A channel layer arranged as described above, a buffer layer connected to the channel layer, a first contact layer connected to the buffer layer and doped with a predetermined impurity, connected to the first contact layer, A carrier contact path between the source electrode and the drain electrode, the second contact layer having a higher impurity concentration than the first contact layer; and a source electrode and a drain electrode connected to the second contact layer. Includes a first path passing through the channel layer, the buffer layer, the first contact layer, and the second contact layer, and the channel layer and It is intended to include a second path via the serial second contact layer.

  Thereby, an off current or an on current flows along the first path or the second path.

  Furthermore, in one embodiment of the thin film transistor according to the present invention, the channel layer is preferably a crystalline silicon film.

  Furthermore, in one embodiment of the thin film transistor according to the present invention, the buffer layer is preferably an amorphous silicon film.

  Furthermore, in one aspect of the thin film transistor according to the present invention, in the first path, the carriers are the channel layer, the buffer layer, the first contact layer, and the second contact layer in this order. Alternatively, it is preferable that the carriers move in the reverse order, and in the second path, the carriers move through the channel layer and the second contact layer in this order or in the reverse order.

  Furthermore, in one embodiment of the thin film transistor according to the present invention, it is preferable to have a first interface between the first contact layer and the second contact layer.

  Furthermore, in one aspect of the thin film transistor according to the present invention, it is preferable that the first interface is substantially parallel to the main surface of the substrate.

  Furthermore, in one embodiment of the thin film transistor according to the present invention, it is preferable to have a second interface between the channel layer and the second contact layer.

  Furthermore, in one aspect of the thin film transistor according to the present invention, it is preferable that the second interface is substantially perpendicular to the main surface of the substrate.

  Furthermore, in one aspect of the thin film transistor according to the present invention, it is preferable that the second interface is substantially parallel to the main surface of the substrate.

  Furthermore, in one embodiment of the thin film transistor according to the present invention, it is preferable to have a third interface between the buffer layer and the second contact layer.

  Furthermore, in one aspect of the thin film transistor according to the present invention, the thin film transistor has a contact hole penetrating the buffer layer and the first contact layer, and the second contact layer is connected to the channel layer through the contact hole. Preferably it is.

  Furthermore, in one embodiment of the thin film transistor according to the present invention, it is preferable that at least the gate electrode, the gate insulating film, the channel layer, and the buffer layer are formed in this order on the substrate.

  Furthermore, one embodiment of the thin film transistor according to the present invention preferably includes a channel protective layer formed on the channel layer or the buffer layer.

  Furthermore, in one embodiment of the thin film transistor according to the present invention, a distance of a separation portion between the source electrode and the drain electrode that are separated from each other in a cut section when the thin film transistor is cut in a direction perpendicular to the substrate is Lch. When the length of the gate electrode is Lgm, it is preferable that Lgm> Lch.

  Furthermore, in one embodiment of the thin film transistor according to the present invention, it is preferable that Lgm <Lsi where the length of the channel layer is Lsi.

  Furthermore, in one embodiment of the thin film transistor according to the present invention, it is preferable to have a fourth interface between the source electrode or the drain electrode and the second contact layer.

  Furthermore, in one embodiment of the thin film transistor according to the present invention, a distance of a separation portion between the source electrode and the drain electrode that are separated from each other in a cut section when the thin film transistor is cut in a direction perpendicular to the substrate is Lch. When the length of the gate electrode is Lgm, it is preferable that Lgm <Lch.

  Furthermore, in one embodiment of the thin film transistor according to the present invention, it is preferable that at least the channel layer, the gate insulating film, and the gate electrode are formed in this order on the substrate.

  Furthermore, in one embodiment of the thin film transistor according to the present invention, it is preferable that the buffer layer is formed between the channel layer and the gate insulating film.

  In one embodiment of the method for manufacturing a thin film transistor according to the present invention, a substrate, a gate electrode and a gate insulating film formed above the substrate, and the gate electrode are disposed so as to face the gate electrode. A channel layer, a buffer layer connected to the channel layer, a first contact layer connected to the buffer layer and doped with a predetermined impurity, connected to the first contact layer, and the first contact A method of manufacturing a thin film transistor, comprising: a second contact layer having a higher impurity concentration than the layer; and a source electrode and a drain electrode connected to the second contact layer, wherein the buffer layer and the first contact layer are continuously formed. Forming a film and etching the buffer layer and the first contact layer in the same pattern; and the second contact layer and the source It is intended to include a step of etching the electrode and the drain electrode in the same pattern.

  One embodiment of a display device according to the present invention includes the above thin film transistor and a display element connected to the thin film transistor.

  According to the thin film transistor and the manufacturing method thereof according to the present invention, it is possible to suppress the leakage current at the time of off while maintaining the driving current at the time of on, and to improve the rising of the current.

  In addition, according to the display device of the present invention, since the thin film transistor having excellent electrical characteristics is provided, a high-performance display device can be realized.

Sectional drawing which shows the structure of the thin-film transistor concerning the 1st Embodiment of this invention. Plan view of the thin film transistor according to the first embodiment of the present invention (plan view of FIG. 1A) The figure which shows the current-voltage (Id-Vg) characteristic of the thin-film transistor which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the structure of the thin-film transistor concerning the comparative example 1 Sectional drawing which shows the structure of the thin-film transistor concerning the comparative example 2 The figure which shows the current-voltage (Id-Vd) characteristic in the thin-film transistor which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process (gate metal film formation process) of the thin-film transistor which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process (gate electrode patterning process) of the thin-film transistor which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process (gate insulating film formation process) of the thin-film transistor which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process (film formation process for channel layers) of the thin-film transistor which concerns on the 1st Embodiment of this invention Sectional drawing which shows the manufacturing process (film | membrane formation process for buffer layers) of the thin-film transistor which concerns on the 1st Embodiment of this invention Sectional drawing which shows the manufacturing process (film | membrane formation process for 1st contact layers) of the thin-film transistor which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process (channel part island formation process) of the thin-film transistor which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process (film | membrane formation process for 2nd contact layers) of the thin-film transistor which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process (source-drain metal film formation process) of the thin-film transistor which concerns on the 1st Embodiment of this invention Sectional drawing which shows the manufacturing process (source electrode and drain electrode patterning process) of the thin-film transistor which concerns on the 1st Embodiment of this invention Sectional drawing which shows the manufacturing process (2nd contact layer formation process) of the thin-film transistor which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process (passivation film formation process) of the thin-film transistor which concerns on the 1st Embodiment of this invention Sectional drawing which shows the structure of the thin-film transistor which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the structure of the thin-film transistor which concerns on the 3rd Embodiment of this invention. The top view of the thin-film transistor which concerns on the 3rd Embodiment of this invention (plan view of FIG. 7A) Sectional drawing which shows the structure of the thin-film transistor which concerns on the 4th Embodiment of this invention. Sectional drawing which shows the structure of the thin-film transistor which concerns on the 5th Embodiment of this invention. Sectional drawing which shows the structure of the thin-film transistor concerning the 6th Embodiment of this invention. Sectional drawing which shows the structure of the thin-film transistor which concerns on the other example of the 6th Embodiment of this invention. Sectional drawing which shows the structure of the thin-film transistor which concerns on the 7th Embodiment of this invention Sectional drawing which shows the structure of the thin-film transistor which concerns on the 8th Embodiment of this invention. Partially cutaway perspective view of an organic EL display device according to a ninth embodiment of the present invention 1 is a circuit diagram of a pixel using a thin film transistor according to any one of the first to eighth embodiments of the present invention. Sectional drawing of one pixel of the organic electroluminescence display at the time of using the thin-film transistor which concerns on the 1st Embodiment of this invention as a drive transistor FIG. 17 is an external view of a television set including a display device according to an embodiment of the present invention.

  Hereinafter, a thin film transistor, a manufacturing method thereof, and a display device according to embodiments of the present invention will be described with reference to the drawings. Each figure is a schematic diagram for explanation, and the film thickness, the ratio of the size of each part, and the like are not necessarily strict.

(First embodiment)
First, a thin film transistor according to a first embodiment of the present invention will be described with reference to FIGS. 1A and 1B. FIG. 1A is a cross-sectional view showing a configuration of a thin film transistor according to the first embodiment of the present invention. FIG. 1B is a plan view of the thin film transistor according to the first embodiment of the present invention shown in FIG. 1A.

  As shown in FIGS. 1A and 1B, a thin film transistor 1 according to the first embodiment of the present invention is a bottom-gate n-type thin film transistor, and includes a substrate 10 and a gate electrode 11 formed on the substrate 10. A gate insulating film 12 formed on the gate electrode 11, a channel layer 13 disposed so as to face the gate electrode through the gate insulating film 12, a buffer layer 14 connected to the channel layer 13, A pair of first contact layers 15a and 15b connected to the buffer layer 14, a pair of second contact layers 16a and 16b formed on the pair of first contact layers 15a and 15b, and a pair of second contact layers 16a And a source electrode 17S and a drain electrode 17D formed on 16b.

  The substrate 10 is an insulating substrate made of a glass substrate made of a glass material such as quartz glass. Although not shown, an underlayer made of an insulating film such as a silicon nitride film (SiN) is formed on the surface of the substrate 10 in order to prevent impurities such as sodium and phosphorus contained in the substrate from entering the semiconductor film. A coat film may be formed.

  The gate electrode 11 is an electrode made of, for example, molybdenum (Mo) and patterned in a strip shape. The gate electrode 11 may be a metal other than molybdenum (Mo), and may be made of, for example, molybdenum tungsten (MoW). In addition, as a material of the gate electrode 11, when the manufacturing process of the thin film transistor 1 includes a heating step, it is preferable that the material is a refractory metal material which is hardly changed by heat. In this embodiment, molybdenum (Mo) having a thickness of about 100 nm is used as the gate electrode 11.

The gate insulating film 12 is formed on the gate electrode 11 so as to cover the gate electrode 11. As a material of the gate insulating film 12, for example, silicon dioxide (SiO ₂ ) can be used. In addition, the material of the gate insulating film 12 can be composed of a silicon nitride film (SiN), a silicon oxynitride film, or a laminated film thereof.

  In this embodiment, since a crystalline semiconductor film is used as the channel layer formed on the gate insulating film 12, silicon dioxide is preferably used as the gate insulating film 12. By using silicon dioxide as the gate insulating film 12, the interface state with the channel layer can be made favorable, and good threshold voltage characteristics in the TFT can be maintained. In the present embodiment, silicon dioxide having a film thickness of about 200 nm is used as the gate insulating film 12.

  The channel layer 13 is patterned in an island shape on the gate insulating film 12 above the gate electrode 11. The channel layer 13 can be composed of a crystalline semiconductor film, which can increase the on-current of the TFT.

  As the channel layer 13, a crystalline silicon film containing crystalline silicon can be used. The crystalline silicon film can be composed of microcrystalline silicon or polycrystalline silicon. Crystalline silicon can be formed by crystallizing amorphous silicon (amorphous silicon) by heat treatment such as annealing. In this embodiment, a crystalline silicon film having a thickness of about 30 nm is used as the channel layer 13. In this embodiment, the crystal grain size in the crystalline silicon film is 1 μm or less. The channel layer 13 may be a mixed crystal of an amorphous structure and a crystalline structure.

  The buffer layer 14 is stacked on the channel layer 13 and is patterned in an island shape. The buffer layer 14 is patterned in an island shape simultaneously with the channel layer 13. The buffer layer 14 preferably has a larger band gap than the channel layer 13 and functions as a leak path when off. As the buffer layer 14, for example, an amorphous semiconductor film such as amorphous silicon (amorphous silicon) can be used. In this embodiment, a hydrogenated amorphous silicon film having a thickness of about 70 nm is used as the buffer layer 14.

The buffer layer 14 is an undoped layer, and no intentional addition of impurities is performed. However, it is conceivable that impurities are unintentionally mixed in the hydrogenated amorphous silicon film during the manufacturing process. Therefore, the impurity concentration in the hydrogenated amorphous silicon film that is the buffer layer 14 is preferably 1 × 10 ¹⁸ / cm ³ or less. Furthermore, the buffer layer 14 preferably has an impurity concentration as low as possible. Therefore, the impurity concentration of the buffer layer 14 is more preferably 1 × 10 ¹⁷ / cm ³ or less. Note that a high impurity concentration in the hydrogenated amorphous silicon film serving as the buffer layer 14 is not preferable because off current (Ioff) increases.

The pair of first contact layers 15 a and 15 b are composed of an amorphous silicon film (n ⁻ Si) containing impurities at a low concentration, and are formed on the buffer layer 14 so as to be separated from each other. The pair of first contact layers 15 a and 15 b are formed in contact with the buffer layer 14. The first contact layers 15a and 15b can be formed, for example, by adding an n-type impurity such as phosphorus (P) at a low concentration to amorphous silicon having a thickness of about 20 nm.

In the present embodiment, the impurity concentration of the first contact layers 15a and 15b may be an impurity whose concentration is one digit or more lower than that of the second contact layers 16a and 16b. Specifically, the concentration of impurities in the first contact layers 15a and 15b is preferably 5 × 10 ²⁰ / cm ³ or less, particularly 1 × 10 ¹⁹ / cm ³ or more and 1 × 10 ²⁰ / cm ³ or less. It is preferable that Thus, by setting the impurity concentration of the first contact layers 15a and 15b, the electric field concentration at the interface with the second contact layers 16a and 16b can be reduced.

  The n-type impurity in the first contact layers 15a and 15b is not limited to phosphorus, and may be a group V element other than phosphorus. Moreover, it is not limited to n-type impurities, and for example, p-type impurities containing Group III elements such as boron (B) may be used. In the present embodiment, it is not necessary to form another film between the buffer layer 14 and the first contact layers 15a and 15b, and the first contact layers 15a and 15b are continuously formed on the buffer layer 14. It is preferable to do. As a result, it is possible to prevent a natural oxide film from being formed between the buffer layer 14 and the first contact layers 15a and 15b.

The pair of second contact layers 16a and 16b is composed of an amorphous silicon film (n ⁺ Si) containing impurities at a high concentration, and is formed on the first contact layers 15a and 15b. Further, the second contact layer 16a and the second contact layer 16b are formed apart from each other. In the present embodiment, the second contact layers 16a and 16b can be formed, for example, by adding an n-type impurity such as phosphorus (P) at a high concentration to amorphous silicon having a thickness of about 20 nm. .

  Further, the second contact layers 16a and 16b in the present embodiment are formed so as to cover the side surfaces of the channel layer 13 and the buffer layer 14, and the gate insulating film 12 is formed from the upper surfaces of the first contact layers 15a and 15b. It is formed so as to cover the region between the upper surface of the substrate. That is, the pair of second contact layers 16a and 16b is in contact with the first contact layers 15a and 15b, and is also in contact with the channel layer 13 and the buffer layer 14.

  Thus, in the present embodiment, the first interface, which is the interface between the second contact layer 16a (16b) and the first contact layer 15a (15b), and the second contact layer 16a (16b) and the channel layer 13 A second interface which is an interface; a third interface which is an interface between the second contact layer 16a (16b) and the buffer layer 14; and an interface between the second contact layer 16a (16b) and the source electrode 17S or the drain electrode 17D. A fourth interface. In the present embodiment, as shown in FIG. 1A, the first interface and the fourth interface are substantially perpendicular to the main surface of the substrate 10 and substantially horizontal to the main surface of the substrate 10. A horizontal plane exists, and only a vertical plane that is substantially perpendicular to the main surface of the substrate 10 exists at the second interface and the third interface.

In the present embodiment, the impurity concentration of the second contact layers 16a and 16b may be an impurity having a concentration higher by one digit or more than that of the first contact layers 15a and 15b. Specifically, the impurity concentration in the second contact layers 16a and 16b is preferably 1 × 10 ²¹ / cm ³ or more and 1 × 10 ²² / cm ³ or less. This concentration is generally a concentration that can be easily realized when a high-concentration impurity is introduced into a silicon film.

  Further, the n-type impurity in the second contact layers 16a and 16b is not limited to phosphorus, and may be a group V element other than phosphorus. Moreover, it is not limited to n-type impurities, and for example, p-type impurities containing Group III elements such as boron (B) may be used.

  The source electrode 17S and the drain electrode 17D are formed on the second contact layers 16a and 16b, respectively, and are patterned so as to be separated from each other. The source electrode 17S and the drain electrode 17D are in ohmic contact with the second contact layers 16a and 16b, and are formed so that the side surfaces thereof coincide with the second contact layers 16a and 16b.

  The source electrode 17S and the drain electrode 17D have a single layer structure or a multilayer structure such as a conductive material and an alloy, respectively. For example, titanium (Ti) tantalum (Ta), molybdenum (Mo), tungsten (W), aluminum (Al ), A single layer made of a metal such as copper (Cu) or a laminated film made of two or more materials is formed so as to have a film thickness of about 50 to 1000 nm. As a method for forming the source electrode 17S and the drain electrode 17D, for example, a sputtering method is used. In this embodiment, as the source electrode 17S and the drain electrode 17D, a three-layer metal layer made of Mo / Al / Mo is formed with a film thickness of 50 nm / 300 nm / 50 nm.

  As described above, in the thin film transistor 1 according to the first embodiment of the present invention, the side surface of the channel layer 13 and the side surface of the buffer layer 14 are covered with the second contact layers 16a and 16b with high concentration impurities. The layer 14 is electrically connected to the source electrode 17S and the drain electrode 17D through the second contact layers 16a and 16b. Further, the upper surface of the buffer layer 14 is covered with the first contact layers 15a and 15b of low-concentration impurities, and the upper surface of the buffer layer 14 is connected to the second contact layers 16a and 16b via the first contact layers 15a and 15b. Electrically connected.

  In the thin film transistor 1 in this embodiment, an ohmic contact layer is formed between the channel layer 13 and the source electrode 17S or the drain electrode 17D. In the present embodiment, the ohmic contact layers are the first contact layers 15 a and 15 b, the second contact layers 16 a and 16 b, or the buffer layer 14.

  With this configuration, as a carrier movement path through which carriers flow between the source electrode 17S and the drain electrode 17D, the channel layer 13, the buffer layer 14, the first contact layer 15a (15b), and the second contact layer 16a (16b) are provided. Thus, there is a first path Ch1 through which carriers move, and a second path Ch2 through which carriers move through the channel layer 13 and the second contact layer 16a (16b).

  More specifically, in the thin film transistor 1 according to the present embodiment, the movement of carriers in the off state is governed by the first path Ch1, and the off-current flows along the first path Ch1, and in the on state, In the carrier movement, the second path Ch2 is dominant, and the on-current flows along the second path Ch2. That is, the carrier at the time of OFF is between the drain electrode 17D and the source electrode 17S along the first path Ch1, the second contact layer 16b, the first contact layer 15b, the buffer layer 14, the channel layer 13, and the buffer layer. 14, the first contact layer 15a and the second contact layer 16a move in this order. On-state carriers move from the source electrode 17S to the drain electrode 17D in the order of the second contact layer 16a, the channel layer 13, and the second contact layer 16b along the second path Ch2. As described above, in the thin film transistor according to the present embodiment, the carrier moves along different paths between the off time and the on time.

  As a result, it is possible to suppress the leakage current at the time of turning off while maintaining the TFT driving current at the time of turning on, so that a thin film transistor with a good current rising can be realized.

  Next, electrical characteristics of the thin film transistor 1 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a diagram showing current-voltage (Id-Vg) characteristics of the thin film transistor according to the first embodiment of the present invention. In FIG. 2, “present invention” indicates the characteristics of the thin film transistor 1 according to the first embodiment of the present invention, and “comparative example 1” and “comparative example 2” refer to comparative example 1 and The characteristic of the thin-film transistors 100 and 200 concerning the comparative example 2 is shown. In FIG. 2, the horizontal axis indicates the voltage value Vg [V] of the gate voltage at the gate electrode, and the vertical axis indicates the current value Id [A] of the drain current.

  Here, the structure of the thin film transistors 100 and 200 according to Comparative Example 1 and Comparative Example 2 will be described with reference to FIGS. 3A and 3B. 3A is a cross-sectional view illustrating the configuration of the thin film transistor according to Comparative Example 1, and FIG. 3B is a cross-sectional view illustrating the configuration of the thin film transistor according to Comparative Example 2.

  As shown in FIG. 3A, a thin film transistor 100 according to Comparative Example 1 includes a gate electrode 111, a gate insulating film 112, a channel layer 113 made of a crystalline silicon film, a first contact layer 115a with a low concentration impurity, and a substrate 110. 115b, second contact layers 116a and 116b of a high concentration impurity layer, a source electrode 117S and a drain electrode 117D are stacked.

  As shown in FIG. 3B, a thin film transistor 200 according to Comparative Example 2 includes a gate electrode 211, a gate insulating film 212, a channel layer 213 made of a crystalline silicon film, and a buffer layer made of amorphous silicon on a substrate 210. 214, low concentration impurity first contact layers 215a and 215b, high concentration impurity layers second contact layers 216a and 216b, a source electrode 217S and a drain electrode 217D are stacked. However, unlike the first embodiment of the present invention, the second contact layers 216a and 216b of the high concentration impurity layer are formed only on the upper surfaces of the first contact layers 215a and 215b.

  As shown in FIG. 2, the thin film transistor 100 according to Comparative Example 1 (“Comparative Example 1”) has a high gate voltage (Vg) at the time of ON (ON) and a high on-current (Id). It can be seen that the gate voltage (Vg) at the time of OFF) is high and the on-current (Id) is also high. On the other hand, the thin film transistor 200 according to Comparative Example 2 (“Comparative Example 2”) has a low gate voltage (Vg) in the off state and a low on current (Id), but also has a low gate voltage (Vg) in the on state. It can be seen that the on-current (Id) is also low.

  On the other hand, the thin film transistor 1 according to the first embodiment of the present invention (“present invention”) is compared with the thin film transistor 100 according to comparative example 1 (“comparative example 1”) in the off-state gate voltage (Vg). ) Is low, indicating that the off-state current is low. Furthermore, the thin film transistor 1 according to the first embodiment of the present invention (“present invention”) has a gate voltage (Vg) at the time of ON as compared with the thin film transistor 200 according to comparative example 2 (“comparative example 2”). It can be seen that the on-current is also high.

  As described above, the thin film transistor 1 (“the present invention”) according to the first embodiment of the present invention has excellent current-voltage characteristics such as high on-current and low off-current.

  Next, the current-voltage (Id-Vd) characteristics of the thin film transistor according to the first embodiment of the present invention will be described with reference to FIG. FIG. 4 is a diagram showing current-voltage (Id-Vd) characteristics in the thin film transistor according to the first embodiment of the present invention. In FIG. 4, “present invention”, “comparative example 1”, and “comparative example 2” are the same as the thin film transistors described in FIG. In FIG. 4, the horizontal axis indicates the drain voltage value Vd [V], and the vertical axis indicates the drain current value Id [A].

  Here, as for the Id-Vd characteristic, it is assumed that the slope in the linear region of each thin film transistor in the graph shown in FIG. 4 is seen. In this case, the linear region is a region where the voltage (Vd) between the source electrode and the drain electrode is low, and is a region having a predetermined inclination. On the other hand, the saturation region is a region where the voltage between the source electrode and the drain electrode is high and has no inclination.

  The larger the Id gradient in the linear region, the lower the on-time resistance (Ron resistance), and the smaller the Id gradient in the linear region, the higher the Ron resistance. Furthermore, a low Ron resistance indicates that the current rise in the linear region is good. On the contrary, the good rise of current in the linear region indicates that the Ron resistance is low.

  As shown in FIG. 4, the thin film transistor 1 (“present invention”) according to the first embodiment of the present invention has an Id in the linear region as compared with the thin film transistor 200 according to the comparative example 2 (“comparative example 2”). It can be seen that the rise of is good. That is, it can be seen that the slope in the linear region is larger in the present invention than in Comparative Example 2. Therefore, it can be seen that the Ron resistance of the present invention is lower than that of Comparative Example 2.

  As described above, as a result of consideration based on the result of the electrical characteristics of the thin film transistor 1 according to the first embodiment of the present invention shown in FIGS. 2 and 4, the following knowledge has been obtained.

  In the saturation region where the voltage (Vd) between the source electrode and the drain electrode is high, that is, when the carrier electrode is off, carriers mainly move along a path with a short separation distance between the source electrode 17S and the drain electrode 17D. Conceivable. Therefore, in the thin film transistor 1 according to the present embodiment, it is considered that carriers are mainly moved along the first path Ch1 in FIG. In this case, in the first path Ch1, the second contact layers 16a and 16b and the first contact layers 15a and 15b have different impurity concentrations by one digit or more, so that the concentration of charges in the source / drain electric field can be reduced. The off-current when the gate voltage is OFF can be suppressed.

  Further, the lifetime of the thin film transistor can be extended by preventing the concentration of charges in the source / drain electric field. Furthermore, in this embodiment, since the amorphous silicon buffer layer 14 is formed on the crystalline silicon channel layer 13, the junction interface between the channel layer 13 and the buffer layer 14 can be satisfactorily formed. it can. Thereby, the leakage current at the junction interface can also be suppressed.

  On the other hand, in the linear region where the voltage (Vd) between the source electrode and the drain electrode is low, that is, in the on state, carriers mainly flow along a path with higher carrier mobility. Therefore, in the thin film transistor 1 according to the present embodiment, it is considered that carriers are mainly moved along the second path Ch2 in FIG. In this case, in the second path Ch2, there are only the channel layer 13 and the second contact layers 16a and 16b with high concentration impurities between the source electrode 17S and the drain electrode 17D, and the second path Ch2 is made of amorphous silicon which has a high resistance component. There is no buffer layer 14 configured. As a result, the thin film transistor 1 according to this embodiment has a good current rise in the linear region.

  As described above, according to the thin film transistor according to the first embodiment of the present invention, it is possible to suppress the leakage current at the time of OFF while maintaining the TFT drive current at the time of ON, and the current rise is good. A thin film transistor can be realized.

  In this embodiment, as shown in FIG. 1A, the length (Lgm) of the gate electrode 11 is longer than the distance (Lch) between the source electrode 17S and the drain electrode 17D, and the length of the channel layer 13 is further increased. It is preferable that the length be longer than (Lsi).

  As a result, the electric field from the gate electrode 11 is applied to a region where the second contact layers 16a and 16b are in direct contact with the channel layer 13 in the linear region of the graph shown in FIG. As a result, the Ron resistance can be effectively reduced. In addition, since the switching transistor in the display device preferably has a small Ron resistance, a thin film transistor suitable for the switching transistor can be realized with the above structure. In particular, in an organic EL display device, it is conceivable that the switching cycle is shortened. Therefore, an organic EL display device having excellent display performance can be realized by using a thin film transistor having a small Ron resistance.

  Next, a method for manufacturing the thin film transistor 1 according to the first embodiment of the present invention will be described with reference to FIGS. 5A to 5L are cross-sectional views showing the respective steps in the method of manufacturing a thin film transistor according to the first embodiment of the present invention.

  First, as shown in FIG. 5A, a gate metal film 11M made of molybdenum or the like is formed with a film thickness of about 100 nm on a substrate 10 made of an insulating glass substrate by sputtering. Note that an undercoat film may be formed on the substrate 10 before forming the gate metal film 11M.

  Next, the gate metal film 11M is patterned by performing photolithography and wet etching on the gate metal film 11M to form a gate electrode 11 having a predetermined shape as shown in FIG. 5B.

  Next, as shown in FIG. 5C, a gate insulating film 12 made of a silicon oxide film is formed on the substrate 10 to a thickness of about 200 nm so as to cover the gate electrode 11 by plasma CVD.

  Next, as shown in FIG. 5D, a channel layer film 13F made of crystalline silicon is formed on the gate insulating film 12 to a thickness of about 30 nm. The channel layer film 13F made of crystalline silicon is formed by directly forming microcrystalline silicon by a CVD method, or by applying heat treatment with a laser or a lamp after forming amorphous silicon by plasma CVD. It can be formed by crystallization.

  Next, as shown in FIG. 5E, a buffer layer film 14F made of a hydrogenated amorphous silicon film is formed to a thickness of about 20 nm so as to cover the channel layer film 13F by plasma CVD.

  Next, as shown in FIG. 5F, the first contact layer film 15F made of amorphous silicon in which phosphorus is added at a low concentration as an n-type impurity so as to cover the buffer layer film 14F by plasma CVD. Is deposited.

In the present embodiment, the first contact layer film 15F is formed continuously with the buffer layer film 14F. In this case, for example, monosilane (SiH ₄ ) and hydrogen (H ₂ ) are used as the film forming gas, and phosphine (PH ₃ ) can be used to dope phosphorus as an n-type impurity.

  Note that, even when continuous film formation of the buffer layer film 14F and the first contact layer film 15F is performed using the same apparatus, the first contact is formed using different film formation chambers. The impurity concentration of the layer film 15F is easy to control. However, in this case, when moving the film forming chamber, it is preferable that the film is transferred to another chamber in a vacuum so that the buffer layer film 14F is not oxidized. Even when the film is formed in the same film formation chamber, the impurity concentration to be added can be controlled by appropriately adjusting the gas flow rate, pressure, discharge power, or the like. After the formation of the buffer layer film 14F, the substrate after film formation is temporarily evacuated from the film formation chamber to another vacuum space. A method of forming a film after the substrate is transferred into the film chamber is also possible.

  Next, as shown in FIG. 5G, the laminated channel layer film 13F, buffer layer film 14F, and first contact layer film 15F are selectively patterned simultaneously by performing photolithography and wet etching. Thus, the channel layer 13 and the buffer layer 14 patterned in an island shape can be formed. The first contact layer film 15F is also patterned in the same shape as the channel layer 13 and the buffer layer.

  Next, as shown in FIG. 5H, phosphorus is used as an n-type impurity in a high concentration so as to cover the island-shaped stacked structure of the channel layer 13, the buffer layer 14, and the first contact layer film 15F by plasma CVD. A second contact layer film 16F made of the added amorphous silicon is formed.

  In the present embodiment, the silicon film to which the impurity that is the first contact layer film 15F and the second contact layer film 16F is added is formed by the CVD method, but the impurity is added by the ion implantation method. A silicon film can also be formed. The ion implantation method is a method of forming an impurity region having a concentration gradient by introducing an impurity only into a silicon film to which an impurity is added after forming a silicon film without containing an n-type impurity. Further, unlike the CVD method, the ion implantation method does not require concentration management or management of impurity contamination in the CVD apparatus. However, in consideration of the manufacturing equipment cost, the CVD method that does not require an ion implanter is preferable.

  Next, as shown in FIG. 5I, a source / drain metal film 17M is formed on the second contact layer film 16F by sputtering. In the present embodiment, as the source / drain metal film 17M, a three-layer metal layer made of Mo / Al / Mo is formed with a film thickness of 50 nm / 300 nm / 50 nm.

  Next, as shown in FIG. 5J, by performing photolithography and wet etching, the source / drain metal film 17M is patterned to form the source electrode 17S and the drain electrode 17D separately. The source / drain metal film 17M can be etched by wet etching using a mixed acid composed of phosphoric acid, nitric acid and acetic acid, for example. As a result, the second contact layer film 16F is exposed.

  Next, as shown in FIG. 5K, the second contact layer film 16F and the first contact layer film 15F are patterned by etching to form a pair of second contact layers 16a and 16b having a predetermined shape, and a pair of The first contact layers 15a and 15b are formed separately. At this time, the pair of second contact layers 16a and 16b are patterned so that the side surfaces thereof coincide with the source electrode 17S and the drain electrode 17D. Further, as shown in FIG. 5K, the second contact layers 16a and 16b are formed so as to cover the upper surfaces of the first contact layers 15a and 15b, the side surfaces of the buffer layer 14, and the side surfaces of the channel layer 13.

The etching of the second contact layer film 16F and the first contact layer film 15F can be performed, for example, by dry etching using a gas such as fluorine-based CHF ₃ . At this time, since the buffer layer 14 and the channel layer 13 are also films made of silicon, the buffer layer 14 and the channel layer 13 may be dry-etched. For this reason, it is preferable to strictly manage the power, pressure, gas flow rate, etching time, etc. during dry etching.

  In this embodiment, as shown in FIG. 5K, the buffer layer 14 is left in the contact layer isolation region on the channel layer 13, and a part of the upper surface of the buffer layer 14 is dry-etched. This structure takes into account etching damage to the channel layer 13. However, although not shown, the buffer layer 14 in the contact layer isolation region on the channel layer 13 is completely removed, and etching damage on the channel layer 13 is caused by performing heating or hydrogenation treatment in a later process. A recovery method may be used. Examples of methods for recovering etching damage include hydrogen plasma treatment, heat treatment under a hydrogen atmosphere, or heat treatment under a low oxygen condition or in a vacuum atmosphere.

  Thereby, the thin film transistor 1 according to the first embodiment of the present invention can be manufactured.

Thereafter, as shown in FIG. 5L, a passivation film 18 made of, for example, a silicon nitride film (SiN ₂ ) may be formed to a thickness of 400 nm so as to cover the entire surface of the substrate 10. Although not shown in the drawing, subsequently, by performing photolithography and wet etching, a step of simultaneously forming contact holes to the source electrode 17S, the drain electrode 17D, and the gate electrode 11 in the passivation film 18 is performed. The source electrode 17S, the drain electrode 17D, and the gate electrode 11 are connected to the wiring electrode in the device.

(Second Embodiment)
Next, a thin film transistor 2 according to a second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view showing a configuration of a thin film transistor according to the second embodiment of the present invention.

  The thin film transistor according to the second embodiment of the present invention shown in FIG. 6 has the same basic configuration as the thin film transistor 1 according to the first embodiment of the present invention shown in FIG. 1A. Therefore, in FIG. 6, the same components as those shown in FIG. 1A are denoted by the same reference numerals, and the description thereof is omitted.

  The thin film transistor 2 according to the second embodiment of the present invention shown in FIG. 6 is different from the thin film transistor 1 according to the first embodiment of the present invention shown in FIG. 1A in the configuration of the channel layer.

  That is, as shown in FIG. 6, in the thin film transistor 2 according to the second embodiment of the present invention, the length (Lsi) of the channel layer 23 and the length of the buffer layer 14 are different. 14 is not etched at the same time. In the present embodiment, the length (Lsi) of the channel layer 23 is configured to be longer than the length (Lgm) of the gate electrode 11.

  Further, the side surface of the channel layer 23 is configured to coincide with the side surfaces of the second contact layers 16a and 16b, and the channel layer 23 and the second contact layers 16a and 16b are in contact with each other as compared with the first embodiment. The area that has become larger. Further, the region where the channel layer 23 and the second contact layers 16a and 16b are in contact is only the stacking direction (substrate vertical direction) of the channel layer 23 and the second contact layers 16a and 16b.

  Also in this embodiment, the first interface which is the interface between the second contact layer 16a (16b) and the first contact layer 15a (15b), and the interface between the second contact layer 16a (16b) and the channel layer 23. A second interface, a third interface which is an interface between the second contact layer 16a (16b) and the buffer layer 14, and a fourth interface which is an interface between the second contact layer 16a (16b) and the source electrode 17S or the drain electrode 17D. And an interface. However, in the present embodiment, unlike the first embodiment, as shown in FIG. 6, the first interface and the fourth interface have a vertical plane substantially perpendicular to the main surface of the substrate 10 and the substrate 10. A horizontal plane that is substantially horizontal to the main surface of the substrate 10, only a horizontal plane that is substantially horizontal to the main surface of the substrate 10 is present at the second interface, and the main surface of the substrate 10 is present at the third interface. There is only a vertical plane that is substantially perpendicular to it.

  As described above, in the thin film transistor 2 according to the second embodiment of the present invention, as in the first embodiment, the carrier movement path through which carriers flow between the source electrode 17S and the drain electrode 17D is as shown in FIG. 1A. The first route Ch1 and the second route Ch2 exist. The carrier movement at the off time is dominated by the first path Ch1, and the off current flows along the first path Ch1, and the carrier movement at the on time is dominated by the second path Ch2. Thus, the on-current flows along the second path Ch2.

  That is, the carrier at the time of OFF is between the drain electrode 17D and the source electrode 17S along the first path Ch1, the second contact layer 16b, the first contact layer 15b, the buffer layer 14, the channel layer 23, the buffer layer. 14, the first contact layer 15a and the second contact layer 16a move in this order. On-state carriers move from the source electrode 17S to the drain electrode 17D in the order of the second contact layer 16a, the channel layer 23, and the second contact layer 16b along the second path Ch2.

  Thereby, also in the second embodiment, it is possible to suppress the leakage current at the time of turning off while maintaining the TFT driving current at the time of turning on, so that a thin film transistor having a good current rising can be realized.

  In the thin film transistor 1 according to the first embodiment shown in FIG. 1A, the second contact layers 16a and 16b with high concentration impurities are disposed between the gate electrode 11 and the source electrode 17S (or the drain electrode 17D) in the substrate vertical direction. And a region where only the gate insulating film 12 is formed. On the other hand, in the thin film transistor 2 according to this embodiment shown in FIG. 6, the second contact layers 16a and 16b with high concentration impurities are disposed between the gate electrode 11 and the source electrode 17S (or the drain electrode 17D) in the substrate vertical direction. And only the gate insulating film 12 are removed, and the second contact layers 16a and 16b of at least high-concentration impurities are provided between the gate electrode 11 and the source electrode 17S (or the drain electrode 17D) in the substrate vertical direction. The channel layer 23 and the gate insulating film 12 are formed.

  That is, in the present embodiment, the interface between the channel layer 23 and the second contact layers 16a and 16b is formed only along the horizontal direction of the substrate, and the channel layer 13 and the second contact are formed as in the first embodiment. There is no region where the interface with the layers 16a and 16b is formed along the direction perpendicular to the substrate. That is, in the present embodiment, there is no interface between the channel layer 23 and the second contact layers 16a and 16b in the substrate vertical direction on the side surface portion of the channel layer 23.

  With this configuration, the parasitic capacitance (Cgd or Cgs) between the gate electrode 11 and the source electrode 17S (or the drain electrode 17D) can be reduced. Therefore, by using the thin film transistor 2 according to the present embodiment as a switching transistor of a pixel in the display device, it is possible to prevent a jump voltage from being generated through the parasitic capacitance when the gate electrode 11 is turned from ON to OFF. be able to.

  Furthermore, the thin film transistor 2 according to the present embodiment has a film thickness between the gate electrode 11 and the source electrode 17S (or the drain electrode 17D) as much as the channel layer 23 compared to the thin film transistor 1 according to the first embodiment. Since it is thick, short circuit defects are less likely to occur.

  Next, a method for manufacturing the thin film transistor 2 according to the second embodiment of the present invention will be described with reference to FIGS. 6A to 6L with reference to FIGS. The manufacturing method of the thin film transistor 2 according to the second embodiment of the present invention is common in many steps to the manufacturing method of the thin film transistor 1 according to the first embodiment of the present invention. Therefore, it demonstrates centering on a different point from the manufacturing method which concerns on 1st Embodiment.

  The difference between the manufacturing method according to the present embodiment and the manufacturing method according to the first embodiment is that in the first embodiment, three layers of a channel layer 13, a buffer layer 14, and first contact layers 15a and 15b are provided. In contrast to the etching and patterning performed simultaneously, in the second embodiment, only the two layers of the channel layer 23 and the first contact layers 15a and 15b are simultaneously etched and patterned.

  The other steps are basically the same as those in the first embodiment, and will be described with reference to the manufacturing method according to the first embodiment and FIGS. 5A to 5L.

  First, the gate electrode 11 is patterned on the substrate 10 by a method similar to the method described in FIGS. 5A to 5D (FIGS. 5A and 5B), and then the gate insulating film 12 is formed so as to cover the gate electrode 11. Then, a channel layer film made of crystalline silicon is formed on the gate insulating film 12 (FIG. 5D).

  Next, in the first embodiment, the buffer layer film is subsequently formed. In this embodiment, however, the channel layer film is subjected to photolithography and wet etching before the buffer layer film is formed. As a result, a channel layer 23 having a predetermined shape is formed by patterning as shown in FIG.

  Next, a buffer layer film 14F made of hydrogenated amorphous silicon is formed so as to cover the channel layer 23 by a method similar to the method described in FIGS. 5E and 5F (FIG. 5E). Then, a first contact layer film 15F made of amorphous silicon to which phosphorus is added at a low concentration as an n-type impurity is formed (FIG. 5F).

  Next, in the same manner as described in FIG. 5G, by performing photolithography and wet etching, the buffer layer film 14F and the first contact layer film 15F are selectively patterned simultaneously to form islands. The patterned buffer layer 14 and first contact layer film 15F can be formed.

  Next, in the same manner as described in FIGS. 5H and 5I, phosphorus is added as a n-type impurity at a high concentration so as to cover the channel layer 23, the buffer layer 14, and the first contact layer film 15F. A second contact layer film 16F made of amorphous silicon is formed (FIG. 5H), and a source / drain metal film 17M is formed on the second contact layer film 16F (FIG. 5I).

  Next, in the same manner as the method described in FIGS. 5J and 5K, the source / drain metal film 17M is patterned to separate and form the source electrode 17S and the drain electrode 17D (FIG. 5J), and then the second contact layer film. A pair of second contact layers 16a and 16b having a predetermined shape and a pair of first contact layers 15a and 15b are separately formed by patterning 16F and the first contact layer film 15F.

  Thereby, the thin film transistor 2 according to the second embodiment of the present invention can be manufactured.

(Third embodiment)
Next, a thin film transistor 3 according to a third embodiment of the present invention will be described with reference to FIGS. 7A and 7B. FIG. 7A is a cross-sectional view showing a configuration of a thin film transistor according to a third embodiment of the present invention. FIG. 7B is a plan view of the thin film transistor according to the third embodiment of the present invention shown in FIG. 7A.

  The thin film transistor 3 according to the third embodiment of the present invention shown in FIGS. 7A and 7B has the same basic configuration as the thin film transistor 2 according to the second embodiment of the present invention shown in FIG. In FIG. 7B, the same components as those shown in FIG.

  The thin film transistor 3 according to the third embodiment of the present invention shown in FIGS. 7A and 7B is different from the thin film transistor 2 according to the second embodiment of the present invention shown in FIG. The buffer layer 34, the pair of first contact layers 15a and 15b, and the pair of second contact layers 36a and 36b.

  As shown in FIG. 7A, the thin film transistor 3 according to the third embodiment of the present invention includes a buffer layer 34, a pair of first contact layers 15a and 15b, and a pair of second contact layers on the channel layer 23. 36a and 36b are formed. A source electrode 17S and a drain electrode 17D are formed on the pair of second contact layers 36a and 36b.

  In the present embodiment, a contact hole 38 penetrating the first contact layer 15b and the buffer layer 34 is formed, and the second contact layers 36a and 36b of high concentration impurities and the channel layer are formed through the contact hole 38. 23 is directly connected. In the present embodiment, unlike the second embodiment, the second contact layers 36 a and 36 b and the channel layer 23 are directly connected only via the contact hole 38.

  In the present embodiment, the shape of the contact hole 38 in plan view is rectangular as shown in FIG. 7B, but may be other shapes such as a circle. Further, although only one contact hole 38 is formed, a plurality of contact holes 38 may be formed. Further, although the contact hole 38 is formed only on the source electrode 17S side, it may be formed only on the drain electrode 17D side, or on both the source electrode 17S side and the drain electrode 17D side. However, since the electric field concentrates on the drain electrode 17D side, it is preferably formed at least on the drain electrode 17D side.

  In the present embodiment, the first interface (side surface of the contact hole 38) that is the interface between the second contact layer 36b and the first contact layer 15b, and the first interface that is the interface between the second contact layer 36b and the channel layer 23 are used. Two interfaces (the bottom surface of the contact hole 38), a third interface (a side surface of the contact hole 38) that is an interface between the second contact layer 36b and the buffer layer 34, a second contact layer 36a (36b), and the source electrode 17S. Or it has the 4th interface which is an interface with drain electrode 17D. In the present embodiment, as shown in FIG. 7A, the first interface and the third interface have only a vertical surface substantially perpendicular to the main surface of the substrate 10 and the second interface has a substrate. There are only parallel planes substantially parallel to the main surface of the substrate 10, and the fourth interface has a vertical surface substantially perpendicular to the main surface of the substrate 10 and a parallel surface substantially parallel to the main surface of the substrate 10 And exist.

  As described above, in the thin film transistor 3 according to the third embodiment of the present invention, as in the first and second embodiments, the carrier movement path through which carriers flow between the source electrode 17S and the drain electrode 17D is off. There is a first path that becomes dominant and a second path that becomes dominant when turned on. When the carrier is off, the first path is dominant and the off current flows along the first path. When the carrier is on, the second path is dominant and the carrier is on. Will flow along the second path.

  Thereby, also in the third embodiment, it is possible to suppress the leakage current at the time of turning off while maintaining the TFT driving current at the time of turning on, so that a thin film transistor with a good current rising can be realized.

  Furthermore, in the present embodiment, due to the configuration described above, the interface portion between the channel layer 23 and the second contact layer 36a or 36b is less than in the first embodiment and the second embodiment. That is, in this embodiment, the channel layer 23 and the second contact layer 36b are in contact only via the contact hole 38, and the area where the channel layer 23 and the second contact layer 36a or 36b are in contact is small.

  Therefore, the smaller the interface portion between the channel layer 23 and the second contact layer 36a or 36b, the larger the Ron resistance and the more the off current can be reduced. Therefore, the thin film transistor 3 according to the present embodiment can further reduce the off-current as compared with the second embodiment.

  Further, the thin film transistor 3 according to the present embodiment has a larger film thickness between the gate electrode 11 and the source electrode 17S (or the drain electrode 17D) than the thin film transistors 1 and 2 according to the first and second embodiments. Therefore, the occurrence of short-circuit failure can be further reduced as compared with the first and second embodiments.

  Note that the manufacturing method of the thin film transistor 3 according to this embodiment is different from the second embodiment only in the mask pattern, and the thin film transistor 3 according to this embodiment is different from the manufacturing method of the thin film transistor 2 according to the second embodiment. It can be manufactured by a similar method.

(Fourth embodiment)
Next, a thin film transistor 4 according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a cross-sectional view showing a configuration of a thin film transistor according to the fourth embodiment of the present invention.

  The thin film transistor 4 according to the fourth embodiment of the present invention shown in FIG. 8 has the same basic configuration as the thin film transistor according to the first embodiment of the present invention shown in FIG. 1A. The same components as those shown are denoted by the same reference numerals.

  The thin film transistor 4 according to the fourth embodiment of the present invention shown in FIG. 8 is different from the thin film transistor 1 according to the first embodiment of the present invention shown in FIG. 1A in that the thin film transistor 4 according to this embodiment is a channel protective layer. It is a point equipped with.

  That is, in the thin film transistor 4 according to the fourth embodiment of the present invention, the channel protective layer 48 is formed on the channel layer 13, and the buffer layers 44 a and 44 b are formed so as to cover both ends of the channel protective layer 48. Is formed. In the present embodiment, the buffer layer on the channel layer 13 is a buffer layer 44a and 44b separated by removing the channel portion of the TFT. Therefore, it is considered that the buffer layers 44a and 44b are more dominant in the function as the contact layer than in the function as the channel layer of the TFT.

  As the channel protective layer 48, an insulating film made of a nitride film such as a silicon nitride film is used. The channel protective layer 48 is formed by patterning the buffer layer 44a (44b), the first contact layer 15a (15b), and the second contact layer 16a (16b) formed after the channel protective layer 48 by etching or the like. It functions as an etching stopper layer for the channel portion. Thus, by forming the channel protective layer 48, it is possible to prevent the channel layer 13 from being damaged by etching. Therefore, forming the channel protective layer 48 has an advantage that the etching damage is not left in the channel layer 13.

  As described above, in the thin film transistor 4 according to the fourth embodiment of the present invention, as in the first embodiment, the carrier movement path through which carriers flow between the source electrode 17S and the drain electrode 17D is as shown in FIG. 1A. In addition, there is a first path Ch1 that is dominant when turned off and a second path Ch2 that is dominant when turned on. When off, an off current flows along the first path Ch1, and when on, an on current flows along the second path Ch2.

  Thereby, also in the fourth embodiment, it is possible to suppress the leakage current at the time of OFF while maintaining the TFT drive current at the time of ON, so that a thin film transistor with a good current rising can be realized.

  At this time, in the thin film transistor 4 according to the present embodiment, the channel protective layer 48 is directly formed on the channel layer 13, and therefore, compared to the first embodiment, the buffer layer 44a of the second path Ch2 at the time of OFF. And the ratio of carriers flowing to 44b decreases.

  In addition, since the thin film transistor 4 according to this embodiment includes the channel protective layer 48, the channel layer can be prevented from being etched without strictly controlling the etching rate during etching. it can. Thereby, manufacture management can be performed easily.

  In the present embodiment, a silicon nitride film is used as the channel protective layer 48, but the present invention is not limited to this. In addition, as the channel protective layer 48, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a laminated film with these layers, or the like is used. Alternatively, as the channel protective layer 48, a difficult-to-etch material that is difficult to etch, such as a silicon film to which impurities are added, or an insulating film made of other insulating materials can be used.

  In the present embodiment, as shown in FIG. 8, the channel protective layer 48 is formed in contact with the channel layer 13, but the present invention is not limited to this. For example, the channel protective layer 48 may be formed on the buffer layer without etching the buffer layer film, and the channel protective layer 48 may be configured not to contact the channel layer 13.

  Furthermore, in the present embodiment, hydrogenated amorphous silicon films are used as the buffer layers 44a and 44b, thereby preventing impurities in the channel protective layer 48 from entering the channel portion of the semiconductor layer. . As a result, damage to the channel portion when the channel protective layer 48 itself is formed can be reduced. In addition, the channel protective layer 48 may have any configuration as long as the channel layer 13 can be protected during etching.

  Note that the configuration of the thin film transistor 4 according to this embodiment may be applied not only to the first embodiment but also to the second embodiment or the third embodiment. That is, a channel protective layer can be formed in the thin film transistors 2 and 3 according to the second and third embodiments.

  Next, a method of manufacturing the thin film transistor 4 according to the fourth embodiment of the present invention will be described with reference to FIGS. 5A to 5L with reference to FIGS. The manufacturing method of the thin film transistor 4 according to the fourth embodiment of the present invention is common in many steps to the manufacturing method of the thin film transistor 1 according to the first embodiment of the present invention. Therefore, it demonstrates centering on a different point from the manufacturing method which concerns on 1st Embodiment.

  The difference between the manufacturing method according to the present embodiment and the manufacturing method according to the first embodiment is that in this embodiment, a step of forming the channel protective layer 48 is added.

  The other steps are basically the same as those in the first embodiment, and will be described with reference to the manufacturing method according to the first embodiment and FIGS. 5A to 5L.

  First, the gate electrode 11 is patterned on the substrate 10 by a method similar to the method described in FIGS. 5A to 5D (FIGS. 5A and 5B), and then the gate insulating film 12 is formed so as to cover the gate electrode 11. After that, a channel layer film 13F made of crystalline silicon is formed on the gate insulating film 12 (FIG. 5D).

  Next, in the present embodiment, an insulating film such as a nitride film is formed on the channel layer film 13F, and the insulating film is subjected to photolithography and wet etching to form a channel protective layer 48 having a predetermined shape. Form a pattern.

  Thereafter, a buffer layer film is formed so as to cover the channel layer 13 and the channel protective layer 48 by a method similar to the method described with reference to FIGS. 5E to 5J (FIG. 5E), and then for the first contact layer. Film formation (FIG. 5F), first contact layer film, buffer layer and channel layer island formation (FIG. 5G), second contact layer film formation (FIG. 5H), source / drain metal film formation (FIG. 5G) 5I) and pattern formation of the source and drain electrodes (FIG. 5J) is performed.

  Next, the second contact layer film is removed by etching in the same manner as described with reference to FIG. 5K, and the channel protection layer 48 protects the separated portion between the source electrode 17S and the drain electrode 17D. The buffer layer film, the first contact layer film, and the second contact layer film on the layer 48 are completely removed by etching.

  Thereby, the thin film transistor 4 according to the fourth embodiment of the present invention can be manufactured.

(Fifth embodiment)
Next, a thin film transistor 5 according to a fifth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a cross-sectional view showing a configuration of a thin film transistor according to the fifth embodiment of the present invention. In FIG. 9, the same reference numerals are given to constituent elements made of the same material as the constituent elements shown in FIGS. 1A and 8, and detailed description of the materials, dimensions, and the like is omitted.

  As shown in FIG. 9, the thin film transistor 5 according to the fifth embodiment of the present invention is a top-gate thin film transistor, and includes a substrate 10, a source electrode 17S and a drain electrode, a pair of second contact layers 16a, 16b, a pair of first contact layers 15a and 15b, a pair of buffer layers 44a and 44b, a channel layer 13, a gate insulating film 12, and a gate electrode 11.

  The source electrode 17 </ b> S and the drain electrode 17 </ b> D have a single layer structure or a multilayer structure such as a conductive material and an alloy, respectively, and are formed separately on the substrate 10.

The pair of second contact layers 16a and 16b are amorphous silicon films (n ⁺ Si) containing impurities at a high concentration, and are formed so as to cover the source electrode 17S and the drain electrode 17D. The pair of second contact layers 16 a and 16 b are in contact with the first contact layers 15 a and 15 b and are also in contact with the channel layer 13. The impurity concentration of the pair of second contact layers 16a and 16b is higher by one digit or more than the impurity concentration of the pair of first contact layers 15a and 15b.

The pair of first contact layers 15a and 15b is composed of an amorphous silicon film (n ⁻ Si) having an impurity concentration lower than that of the second contact layers 16a and 16b, and the pair of second contact layers 16a and 16b. Formed on top.

  The pair of buffer layers 44a and 44b are each made of an amorphous semiconductor film such as amorphous silicon, and are formed on the pair of first contact layers 15a and 15b.

  The channel layer 13 is composed of a crystalline silicon film, and is also formed on the substrate 10 so as to cover the pair of buffer layers 44a and 44b.

  The gate insulating film 12 is made of an insulating material such as silicon dioxide, and is formed on the channel layer 13.

  The gate electrode 11 is made of a metal such as molybdenum and is formed on the gate insulating film 12.

  In the present embodiment, a first interface that is an interface between the second contact layer 16a (16b) and the first contact layer 15a (15b), and a first interface that is an interface between the second contact layer 16a (16b) and the channel layer 13 are used. And a fourth interface which is an interface between the second contact layer 16a (16b) and the source electrode 17S or the drain electrode 17D. There is no interface between the second contact layer 16a (16b) and the buffer layer 44a (44b). In the present embodiment, as shown in FIG. 9, the first interface and the fourth interface have a horizontal plane that is substantially horizontal to the main surface of the substrate 10, and the second interface has the substrate 10. There is only a vertical plane that is substantially perpendicular to the main surface.

  As described above, in the thin film transistor 5 according to the fifth embodiment of the present invention, as in the first embodiment, the carrier moving path through which carriers flow between the source electrode 17S and the drain electrode 17D includes the channel layer 13 and the buffer. A first path along which carriers move via the layer 44a (44b), the first contact layer 15a (15b), and the second contact layer 16a (16b), and the channel layer 13 and the second contact layer 16a (16b). Thus, there is a second route along which the carrier moves.

  More specifically, also in the thin film transistor 5 according to the present embodiment, the movement of carriers in the off state is that the first path is dominant and the off current flows along the first path. In the movement, the second path is dominant and the on-current flows along the second path.

  Accordingly, even in the thin film transistor 5 according to the fifth embodiment, the resistance of Ron can be reduced similarly to the thin film transistor 1 according to the first embodiment, so that the TFT drive current at the time of ON can be maintained. On the other hand, a leakage current at the time of off can be suppressed, and a thin film transistor with a good current rise can be realized.

  Furthermore, in the thin film transistor 5 according to this embodiment, the gate insulating film 12 is formed on the channel layer 13, and the channel layer 13 is formed in the last step of the thin film transistor manufacturing process. For this reason, it is possible to prevent the channel layer 13 from being etched in the etching process during the manufacturing process, and to prevent the channel layer 13 from being contaminated with impurities.

  Next, a manufacturing method of the thin film transistor 5 according to the fifth embodiment of the present invention will be described with reference to FIG. In addition, the manufacturing process of each component which concerns on this embodiment can be performed similarly to the manufacturing method of each component which concerns on 1st Embodiment. That is, the manufacturing method according to the present embodiment and the manufacturing method according to the first embodiment are basically the same material components as those in the first embodiment, except that the order of the processes and the mask pattern are different. For the above, the same film forming method and the same etching method as those in the first embodiment can be used.

  First, a source / drain metal film is formed on the substrate 10, and the source electrode 17S and the drain electrode 17D are patterned by photolithography and wet etching.

  Next, the second contact layer film made of amorphous silicon to which phosphorus is added at a high concentration so as to cover the source electrode 17S and the drain electrode 17D, and the amorphous silicon to which phosphorus is added at a low concentration. A first contact layer film and a buffer layer film made of a hydrogenated amorphous silicon film are sequentially formed. Thereafter, these films are simultaneously patterned into a predetermined shape by performing photolithography and etching, and a pair of second contact layers 16a and 16b, a pair of first contact layers 15a and 15b, and a pair of buffer layers 44a and 44b is formed at the same time.

  Next, a channel layer film made of crystalline silicon is formed so as to cover the buffer layers 44a and 44b, and the channel layer 13 is patterned. Thereafter, a gate insulating film made of a silicon oxide film or the like and a gate metal film made of molybdenum or the like are formed on the channel layer 13. Thereafter, the gate insulating film 12 and the gate electrode 11 having a predetermined shape are patterned by performing photolithography and etching.

  Thereby, the thin film transistor 5 according to the fifth embodiment of the present invention can be manufactured.

  In the present embodiment, when the channel layer 13 is formed, the second contact layer 16a (16b), the source electrode 17S, or the drain electrode 17D of high-concentration impurities is already formed below the channel layer 13. It is not preferable to use a high temperature process. Therefore, when forming the channel layer 13 made of a crystalline silicon film, the amorphous silicon film is not annealed and crystallized, but a crystalline silicon film such as microcrystalline silicon is directly formed by a CVD method or the like. The method to do is suitable.

(Sixth embodiment)
Next, thin film transistors 6 and 6A according to other examples of the sixth embodiment and the sixth embodiment of the present invention will be described with reference to FIGS. 10 and 11, respectively. FIG. 10 is a cross-sectional view showing a configuration of a thin film transistor according to the sixth embodiment of the present invention. FIG. 11 is a cross-sectional view showing a configuration of a thin film transistor according to another example of the sixth embodiment of the present invention. 10 and 11, constituent elements made of the same material as the constituent elements shown in FIGS. 1A and 9 are given the same reference numerals, and detailed descriptions of the materials, dimensions, and the like are omitted.

  First, as shown in FIG. 10, a thin film transistor 6 according to a sixth embodiment of the present invention is a top-gate thin film transistor, and includes a substrate 10, a channel layer 13, a buffer layer 14, and a pair of first transistors. Contact layers 15a and 15b, a pair of second contact layers 16a and 16b, a source electrode 17S and a drain electrode 17D, a gate insulating film 12, a gate electrode 11, and an interlayer insulating film 68 are provided.

  The channel layer 13 is composed of a crystalline silicon film and is formed on the substrate 10.

  The buffer layer 14 is made of an amorphous semiconductor film such as amorphous silicon and is formed on the channel layer 13.

The pair of first contact layers 15 a and 15 b are made of an amorphous silicon film (n ⁻ Si) containing impurities at a low concentration, and are formed on the channel layer 13 so as to be separated from each other. The impurity concentration of the pair of first contact layers 15a and 15b is one digit or more lower than the impurity concentration of the pair of second contact layers 16a and 15b.

The pair of second contact layers 16a and 16b are amorphous silicon films (n ⁺ Si) containing impurities at a high concentration. The top surfaces of the first contact layers 15a and 15b, the side surfaces of the channel layer 13, and the buffer layer 14 The side surfaces are formed so as to cover each other. The pair of second contact layers 16 a and 16 b are in contact with the first contact layers 15 a and 15 b and are also in contact with the channel layer 13 and the buffer layer 14.

  The source electrode 17S and the drain electrode 17D have a single layer structure or a multilayer structure such as a conductive material and an alloy, respectively, and are separately formed on the second contact layers 16a and 16b.

  The gate insulating film 12 is made of an insulating material such as silicon dioxide, and is formed in an island shape on the buffer layer 14 between the first contact layer 15a and the first contact layer 15b.

  The gate electrode 11 is made of a metal such as molybdenum and is formed in an island shape on the gate insulating film 12. The gate electrode 11 is patterned at the same time as the gate insulating film 12, and the side surface of the gate insulating film 12 coincides with the gate insulating film 12.

  The interlayer insulating film 68 is formed between the second contact layer 16 a and the second contact layer 16 b so as to cover the island-shaped gate insulating film 12 and the gate electrode 11.

  One of the differences between the thin film transistor 6 according to the present embodiment and the thin film transistor 5 according to the fifth embodiment is that the source electrode 17 </ b> S and the drain electrode 17 </ b> D are not present under the channel layer 13.

  In the present embodiment, the first interface which is the interface between the second contact layer 16a (16b) and the first contact layer 15a (15b) and the interface between the second contact layer 16a (16b) and the channel layer 13 are used. A second interface, a third interface which is an interface between the second contact layer 16a (16b) and the buffer layer 14, and a second interface which is an interface between the second contact layer 16a (16b) and the source electrode 17S or the drain electrode 17D. 4 interfaces. In the present embodiment, as shown in FIG. 10, the first interface has a vertical surface substantially perpendicular to the main surface of the substrate 10 and a horizontal surface substantially horizontal to the main surface of the substrate 10. In the second interface and the third interface, only a vertical plane substantially perpendicular to the main surface of the substrate 10 exists, and in the fourth interface, only a horizontal plane substantially horizontal to the main surface of the substrate 10 exists. Exists.

  As described above, in the thin film transistor 6 according to the sixth embodiment of the present invention, as in the fifth embodiment, the carrier moving path through which carriers flow between the source electrode 17S and the drain electrode 17D includes the channel layer 13 and the buffer. A first path along which carriers move via the layer 14, the first contact layer 15a (15b) and the second contact layer 16a (16b), and a carrier via the channel layer 13 and the second contact layer 16a (16b). There is a second path along which the travels.

  Also in the thin film transistor 6 according to the present embodiment, the carrier movement at the time of OFF is dominated by the first path, and the off current flows along the first path, and the movement of the carrier at the time of ON is the second. The path becomes dominant and the on-current flows along the second path.

  Thereby, even in the thin film transistor 6 according to the sixth embodiment, the resistance of Ron can be reduced similarly to the thin film transistor 6 according to the fifth embodiment, so that the TFT driving current at the time of ON can be maintained. On the other hand, a leakage current at the time of off can be suppressed, and a thin film transistor with a good current rise can be realized.

  In the present embodiment, since the source electrode 17S and the drain electrode 17D do not exist under the channel layer 13, when the channel layer 13 made of crystalline silicon is formed, crystallization is performed by annealing amorphous silicon. Can be used. In this case, it is not necessary to use a refractory metal for the source electrode 17S and the drain electrode 17D in consideration of the heating process for crystallization.

  In addition, according to the structure of the thin film transistor 6 according to this embodiment shown in FIG. 10, the channel layer 13 can be prevented from being etched.

  Next, a thin film transistor 6A according to another example of the sixth embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 11, the thin film transistor 6A according to another example of the sixth embodiment of the present invention is also a top-gate thin film transistor, and the basic configuration is according to the sixth embodiment shown in FIG. The same as the thin film transistor 6. Therefore, in FIG. 11, the same components as those shown in FIG. 10 are denoted by the same reference numerals, and detailed description thereof is omitted.

  A thin film transistor 6A according to another example of the sixth embodiment of the present invention shown in FIG. 11 is different from the thin film transistor 6 according to the sixth embodiment of the present invention shown in FIG. 10 in the configuration of the buffer layer.

  That is, in the thin film transistor 6A according to the present embodiment shown in FIG. 11, the island-like gate insulating film 12 and the buffer layer portion under the gate electrode 11 are completely removed, and the gate insulating film 12 is formed on the channel layer 13. Is formed. That is, only the gate insulating film 12 and the channel layer 13 are formed on the substrate 10 below the gate electrode 11.

  The thin film transistor 6A according to another example of the sixth embodiment of the present invention shown in FIG. 11 configured as described above also has the same effect as the thin film transistor 6 shown in FIG. Furthermore, in this embodiment, since only the gate insulating film 12 and the channel layer 13 are formed under the gate electrode 11, the rise characteristic of the Id-Vg characteristic is improved. That is, the Ron resistance can be further reduced.

  Next, a method for manufacturing the thin film transistor 6 according to the sixth embodiment of the present invention and the thin film transistor 6A according to another example of the sixth embodiment will be described with reference to FIGS. In the present embodiment, the same film forming method and the same etching method as those in the first embodiment can be used for the same material components as those in the first embodiment.

  First, a channel layer film made of a crystalline silicon film is formed on the substrate 10, and then the channel layer 13 is patterned by performing normal photolithography and etching.

  Next, a buffer layer 14 made of a hydrogenated amorphous silicon film is formed so as to cover the channel layer 13, and a first contact layer film containing impurities at a low concentration is formed.

  Thereafter, the first contact layer film is etched by photolithography and etching, thereby patterning the pair of first contact layers 15a and 15b. At this time, the structure shown in FIG. 11 can be obtained by etching and removing the buffer layer in accordance with the separation region (etching removal region) between the first contact layer 15a and the first contact layer 15b.

  Next, the gate insulating film 12 and the gate electrode 11 are simultaneously patterned in an island shape in the separation region of the first contact layers 15a and 15b. Thereafter, an insulating film is formed so as to cover the entire surface, and photolithography and etching are performed, so that interlayer insulation is performed so as to cover part of the gate electrode 11, the gate insulating film 12, and the first contact layers 15a and 15b. The film 68 is patterned.

  Next, a second contact layer film containing a high concentration of impurities and a source / drain metal film are sequentially formed, and photolithography and etching are performed to pattern the source electrode 17S and the drain electrode 17D. Thereafter, the second contact layer film is etched to cover the upper surfaces of the first contact layers 15a and 15b, the side surfaces of the channel layer 13, and the side surfaces of the buffer layers 14 (44a and 44b). Then, the second contact layers 16a and 16b are patterned.

  Thereby, the thin film transistors 6 and 6A according to other examples of the sixth embodiment and the sixth embodiment of the present invention can be manufactured.

  In the thin film transistor 6 according to the sixth embodiment of the present invention shown in FIG. 10, the buffer layer 14 is patterned after the channel layer 13 is patterned. However, the present invention is not limited to this. For example, the channel layer film and the buffer layer film may be continuously formed, and then the channel layer 13 and the buffer layer 14 may be patterned simultaneously.

  Further, the patterning of the first contact layers 15a and 15b is performed after the patterning of the buffer layer 14, but is not limited thereto. For example, after the channel layer film, the buffer layer film, and the first contact layer film are continuously formed, they may be patterned simultaneously, and then the first contact layers 15a and 15b may be patterned. .

  In the thin film transistor 6A according to another example of the sixth embodiment of the present invention shown in FIG. 11, after patterning the channel layer 13, the buffer layers 44a and 44b and the first contact layers 15a and 15b are simultaneously patterned. However, it is not limited to this. For example, after a channel layer film, a buffer layer film, and a first contact layer film are continuously formed, they are simultaneously patterned, and thereafter, the buffer layers 44a and 44b and the first contact layers 15a and 15b Patterning may be performed.

(Seventh embodiment)
Next, a thin film transistor according to a seventh embodiment of the present invention will be described with reference to FIG. FIG. 12 is a cross-sectional view showing a configuration of a thin film transistor according to the seventh embodiment of the present invention.

  The thin film transistor 7 according to the seventh embodiment of the present invention shown in FIG. 12 has the same basic configuration as the thin film transistor according to the first embodiment of the present invention shown in FIG. 1A. Therefore, in FIG. 12, the same components as those shown in FIG. 1A are denoted by the same reference numerals, and the description thereof is omitted.

  The thin film transistor 7 according to the seventh embodiment of the present invention shown in FIG. 12 is different from the thin film transistor 1 according to the first embodiment of the present invention shown in FIG. 1A in the length (Lgm) of the gate electrode. Other configurations are the same as those in the first embodiment.

  As shown in FIG. 12, in the thin film transistor 7 according to the seventh embodiment of the present invention, the length (Lgm) of the gate electrode 71 is the length of the separation portion (Lch) between the source electrode 17S and the drain electrode 17D. ) And shorter than the length (Lsi) of the channel layer 13.

  That is, unlike the thin film transistor 1 according to the first embodiment, the thin film transistor 7 according to the present embodiment has a gate insulating film 12 between the gate electrode 71 and the source electrode 17S (or the drain electrode 17D) in the substrate vertical direction. There is no area that only exists.

  With this configuration, the parasitic capacitance (Cgd or Cgs) between the gate electrode 71 and the source electrode 17S (or the drain electrode 17D) can be reduced. Therefore, by using the thin film transistor 7 according to the present embodiment as a switching transistor of a pixel in the display device, it is possible to prevent a jump voltage from being generated via the parasitic capacitance when the gate electrode 71 is turned from ON to OFF. be able to.

  Furthermore, the thin film transistor 7 according to the present embodiment is compared with the thin film transistor 7 according to the first embodiment in which only the insulating film exists between the gate electrode 11 and the source electrode 17S (or the drain electrode 17D), as in the thin film transistor 1 according to the first embodiment. In addition, since the film thickness between the gate electrode 71 and the source electrode 17S (or the drain electrode 17D) is increased by the channel layer 13 and the buffer layer 14, short-circuit defects are less likely to occur.

  Regarding the carrier movement path, the thin film transistor 7 according to the seventh embodiment of the present invention has the same effect as the thin film transistor 1 according to the first embodiment of the present invention.

  As described above, the configuration of the thin film transistor 7 according to the seventh embodiment of the present invention can be applied not only to the thin film transistor 1 according to the first embodiment but also to thin film transistors according to other embodiments.

(Eighth embodiment)
Next, a thin film transistor 8 according to an eighth embodiment of the present invention will be described with reference to FIG. FIG. 13 is a cross-sectional view showing a configuration of a thin film transistor according to the eighth embodiment of the present invention.

  Note that the thin film transistor 8 according to the eighth embodiment of the present invention shown in FIG. 13 has the same basic configuration as the thin film transistor according to the first embodiment of the present invention shown in FIG. 1A. Therefore, in FIG. 13, the same components as those shown in FIG. 1A are denoted by the same reference numerals, and description thereof is omitted.

  The thin film transistor 8 according to the eighth embodiment of the present invention shown in FIG. 13 is different from the thin film transistor 1 according to the first embodiment of the present invention shown in FIG. 1A in the same manner as in the seventh embodiment. (Lgm). Other configurations are the same as those in the first embodiment.

  As shown in FIG. 13, in the thin film transistor 8 according to the eighth embodiment of the present invention, the length (Lgm) of the gate electrode 81 is shorter than the length (Lsi) of the channel layer 13, and further, the source electrode 17S. Is shorter than the length (Lsi) of the separation portion between the drain electrode 17D and the drain electrode 17D.

  Therefore, in the thin film transistor 8 according to the present embodiment, the gate electrode 81 and the source electrode 17S (or the drain electrode 17D) do not intersect with each other in the vertical direction of the substrate, and the gate electrode 81 and the source electrode 17S (or the drain electrode 17D) are not. There are no overlapping areas.

  Thereby, the short circuit defect between the gate electrode 81 and the source electrode 17S (or the drain electrode 17D) hardly occurs.

  Regarding the carrier movement path, the thin film transistor 8 according to the eighth embodiment of the present invention has the same effect as the thin film transistor 1 according to the first embodiment of the present invention. However, although the thin film transistor 8 according to the present embodiment can reduce the on-current compared to the thin film transistor 1 according to the first embodiment, the off-current can be most suppressed. Therefore, the thin film transistor 8 according to this embodiment is effective as a switching transistor. However, it is preferable to use a crystalline silicon film with high mobility as the channel layer 13.

  As described above, the configuration of the thin film transistor 8 according to the eighth embodiment of the present invention can be applied not only to the thin film transistor 1 according to the first embodiment but also to thin film transistors according to other embodiments.

(Ninth embodiment)
Next, a display device according to a ninth embodiment of the present invention in which the thin film transistor according to the first to eighth embodiments is applied to a display device will be described with reference to FIG. In the present embodiment, an example applied to an organic EL display device will be described. FIG. 14 is a partially cutaway perspective view of an organic EL display device according to a ninth embodiment of the present invention. The thin film transistor according to each embodiment described above can be used as a drive transistor or a switching transistor of an active matrix substrate of an organic EL display device.

  As shown in FIG. 14, the organic EL display device 300 includes an active matrix substrate 310, a plurality of pixels 320 arranged in a matrix on the active matrix substrate 310, and an array on the active matrix substrate 310 connected to the pixels 320. A plurality of pixel circuits 330 arranged in a row, a lower electrode 340 (anode), an organic EL layer 350 and an upper electrode 360 (cathode), which are sequentially stacked on the pixel 320 and the pixel circuit 330, and each pixel circuit 330 and control. A plurality of source lines 370 and gate lines 380 for connecting a circuit (not shown) are provided. The organic EL layer 350 is configured by laminating layers such as an electron transport layer, a light emitting layer, and a hole transport layer.

  Next, the circuit configuration of the pixel 320 in the organic EL display device 300 will be described with reference to FIG. FIG. 15 is a circuit configuration diagram of a pixel using the thin film transistor according to any one of the first to eighth embodiments of the present invention.

  As illustrated in FIG. 15, the pixel 320 controls the organic EL element 321, the drive transistor 322 for controlling the light emission amount of the organic EL element 321, and the driving timing such as on / off of the organic EL element 321. A switching transistor 323 and a capacitor 324 are provided. Note that the thin film transistor according to any of the first to eighth embodiments of the present invention is used as the driving transistor 322 or the switching transistor 323.

  The source electrode 323S of the switching transistor 323 is connected to the source line 370, the gate electrode 323G is connected to the gate line 380, and the drain electrode 323D is connected to the capacitor 324 and the gate electrode 322G of the driving transistor 322.

  Further, the drain electrode 322D of the driving transistor 322 is connected to the power supply line 390, and the source electrode 322S is connected to the anode of the organic EL element 321.

  In this configuration, when a gate signal is input to the gate line 380 and the switching transistor 323 is turned on, the signal voltage supplied through the source line 370 is written to the capacitor 324. Then, the holding voltage written in the capacitor 324 is held throughout one frame period. With this holding voltage, the conductance of the drive transistor 322 changes in an analog manner, and a drive current corresponding to the light emission gradation flows from the anode to the cathode of the organic EL element 321. Thereby, the organic EL element 321 emits light and is displayed as an image.

  Next, the case where the thin film transistor according to the first to eighth embodiments is used as a drive transistor or a switching transistor in a pixel of an organic EL display device will be described in more detail with reference to FIG. FIG. 16 is a cross-sectional view of one pixel of an organic EL display device when the thin film transistor according to the first embodiment of the present invention is used as a drive transistor.

  As shown in FIG. 16, the organic EL display device 400 according to this embodiment includes a first interlayer insulating film 410 on a substrate 10 which is a TFT array substrate on which a driving transistor 1A and a switching transistor (not shown) are formed. A second interlayer insulating film 420, a first contact part 430, a second contact part 440, and a bank 450. Further, as described in FIG. 14, the lower electrode 340, the organic EL layer 350, The upper electrode 360 is provided.

  As shown in FIG. 16, a first interlayer insulating film 410 is formed so as to cover the driving transistor 1A. A source line 370 and a power line 390 are formed on the first interlayer insulating film 410, and the power line 390 and the drain electrode 17 </ b> D of the driving transistor 1 </ b> A pass through the first interlayer insulating film 410. It is electrically connected via. A second interlayer insulating film 420 is formed so as to cover the source line 370 and the power supply line 390.

  On the second interlayer insulating film 420, a bank 450 is formed at a boundary portion between adjacent pixels. Accordingly, a plurality of banks 450 are formed on the substrate 10, and openings are formed by the adjacent banks 450. An organic EL element 321 including a lower electrode 340, an organic EL layer 350, and an upper electrode 360 is formed in the opening of the bank 450.

  The lower electrode 340 is an anode (anode) arranged in pixel units, and is formed on the second interlayer insulating film 420. The lower electrode 340 and the source electrode 17S of the driving transistor 1A are electrically connected via a second contact portion 440 that penetrates the first interlayer insulating film 410 and the second interlayer insulating film 420.

  The organic EL layer (organic light emitting layer) 350 is formed in units of colors (sub pixel columns) or sub pixels, and is composed of a predetermined organic light emitting material as described above.

  The upper electrode 360 is a cathode (cathode) which is disposed above the organic EL layer 350 and is formed so as to straddle a plurality of pixels, and is composed of a transparent electrode such as ITO.

  As described above, the organic EL display device 400 including the thin film transistor according to the first embodiment of the present invention can realize a display device having excellent display performance because the thin film transistor according to the present embodiment has excellent transistor characteristics. it can.

  In the present embodiment, the case where the thin film transistor according to the first embodiment of the present invention is used as a drive transistor has been described. However, the thin film transistor according to another embodiment of the present invention may be used as a drive transistor.

  In this embodiment, the case where the present invention is applied to the drive transistor has been described. However, the present invention may be applied to a switching transistor. In this case, in particular, since the switching transistor needs to charge the capacitor within a limited time, it is necessary to increase the on-current and reduce the off-current in order to keep the Ron resistance low. Therefore, the thin film transistor according to each embodiment of the present invention having a small Ron resistance is particularly useful as a switching transistor.

  As described above, the thin film transistor, the manufacturing method thereof, and the display device according to the present invention have been described based on the embodiments, but the present invention is not limited to these embodiments.

  For example, although an organic EL display device has been described as an embodiment of the display device according to the present invention, the present invention is not limited to this. For example, the thin film transistor according to the first to eighth embodiments of the present invention can be applied to a display device including another display element such as an inorganic EL display element or a liquid crystal display element.

  In addition, the display device including the thin film transistor according to the embodiment of the present invention can be used as a flat panel display, and can be applied to all displays such as a television set 500, a personal computer, and a mobile phone as shown in FIG. can do.

  In addition, in order to reduce the performance variation of individual thin film transistors and ensure the performance and life of the display device, two or more switching transistors may be provided in one pixel of the display device. In this case, the thin film transistors according to the first to third, fifth, seventh, and eighth embodiments of the present invention are not greatly changed in the manufacturing method, and only on the same substrate by changing the mask pattern. Different transistors can be easily formed. Accordingly, an organic EL display device can be obtained with an easy design by combining the thin film transistors according to the embodiments of the present invention or the combination of the thin film transistors according to the present invention and the conventional thin film transistors in one pixel or display device. You can also.

  In addition, the present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention. Moreover, you may combine each component in several embodiment arbitrarily in the range which does not deviate from the meaning of invention.

  The thin film transistor and the display device according to the present invention include, for example, a display device such as a liquid crystal display device or an electroluminescence display device, or a display device such as a television set, a personal computer, or a mobile phone including these display devices. It can be widely used in electrical equipment.

1, 2, 3, 4, 5, 6, 6A, 7, 8, 100, 200 Thin film transistor 1A, 322 Driving transistor 10, 110, 210 Substrate 11, 71, 81, 111, 211 Gate electrode 11M Gate metal film 12, 112, 212 Gate insulating film 13, 23, 213 Channel layer 13F Channel layer film 14, 34, 44a, 44b, 214 Buffer layer 14F Buffer layer film 15a, 15b, 115a, 115b, 215a, 215b First contact layer 15F First contact layer film 16a, 16b, 36a, 36b, 116a, 116b, 216a, 216b Second contact layer 16F Second contact layer film 17S, 117S, 217S Source electrode 17D, 117D, 217D Drain electrode 17M Source drain metal Membrane 18 Passive Application film 38 contact hole 48 channel protective layer 68 interlayer insulating film 113 channel layer 300, 400 organic EL display device 310 active matrix substrate 320 pixel 321 organic EL element 322G gate electrode 322S source electrode 322D drain electrode 323 switching transistor 323G gate electrode 323S source Electrode 323D Drain electrode 324 Capacitor 330 Pixel circuit 340 Lower electrode 350 Organic EL layer 360 Upper electrode 370 Source line 380 Gate line 390 Power supply line 410 Interlayer insulating film 420 Interlayer insulating film 430 Contact portion 440 Contact portion 450 Bank 500 Television set

Claims (21)

A substrate,
A gate electrode and a gate insulating film formed above the substrate;
A channel layer disposed to face the gate electrode through the gate insulating film;
A buffer layer connected to the channel layer;
A first contact layer connected to the buffer layer and doped with a predetermined impurity;
A second contact layer connected to the first contact layer and having a higher impurity concentration than the first contact layer;
A source electrode and a drain electrode connected to the second contact layer,
The carrier movement path between the source electrode and the drain electrode is:
A first path passing through the channel layer, the buffer layer, the first contact layer, and the second contact layer;
And a second path passing through the channel layer and the two contact layers. The thin film transistor according to claim 1, wherein the channel layer is a crystalline silicon film. The thin film transistor according to claim 1, wherein the buffer layer is an amorphous silicon film. In the first path, the carrier is
Move the channel layer, the buffer layer, the first contact layer, and the second contact layer in this order, or vice versa.
In the second path, the carrier is
The thin film transistor according to claim 1, wherein the channel layer and the second contact layer are moved in this order or in the reverse order. The thin film transistor according to claim 1, further comprising a first interface between the first contact layer and the second contact layer. The thin film transistor according to claim 5, wherein the first interface is substantially parallel to a main surface of the substrate. The thin film transistor according to claim 1, further comprising a second interface between the channel layer and the second contact layer. The thin film transistor according to claim 7, wherein the second interface is substantially perpendicular to a main surface of the substrate. The thin film transistor according to claim 7, wherein the second interface is substantially parallel to a main surface of the substrate. The thin film transistor according to claim 5, further comprising a third interface between the buffer layer and the second contact layer. And a contact hole penetrating the buffer layer and the first contact layer,
The thin film transistor according to claim 1, wherein the second contact layer is connected to the channel layer through the contact hole. The thin film transistor according to claim 1, wherein at least the gate electrode, the gate insulating film, the channel layer, and the buffer layer are formed in this order on the substrate. The thin film transistor according to claim 12, further comprising a channel protective layer formed on the channel layer or the buffer layer. In the cut section when the thin film transistor is cut in the direction perpendicular to the substrate,
When the distance between the spaced apart source electrode and the drain electrode is Lch and the length of the gate electrode is Lgm,
The thin film transistor according to claim 12, wherein Lgm> Lch. Furthermore, when the length of the channel layer is Lsi,
The thin film transistor according to claim 14, wherein Lgm <Lsi. The thin film transistor according to claim 14, further comprising a fourth interface between the source electrode or the drain electrode and the second contact layer. In the cut section when the thin film transistor is cut in the direction perpendicular to the substrate,
When the distance between the spaced apart source electrode and the drain electrode is Lch and the length of the gate electrode is Lgm,
The thin film transistor according to claim 12, wherein Lgm <Lch. The thin film transistor according to claim 1, wherein at least the channel layer, the gate insulating film, and the gate electrode are formed in this order on the substrate. The thin film transistor according to claim 18, wherein the buffer layer is formed between the channel layer and the gate insulating film. A substrate, a gate electrode and a gate insulating film formed above the substrate, a channel layer disposed so as to face the gate electrode through the gate insulating film, and a buffer layer connected to the channel layer A first contact layer connected to the buffer layer and doped with a predetermined impurity; a second contact layer connected to the first contact layer and having an impurity concentration higher than that of the first contact layer; A method of manufacturing a thin film transistor comprising a source electrode and a drain electrode connected to two contact layers,
Continuously forming the buffer layer and the first contact layer, and etching the buffer layer and the first contact layer in the same pattern;
Etching the second contact layer, the source electrode and the drain electrode in the same pattern. The thin film transistor according to any one of claims 1 to 19,
A display device connected to the thin film transistor.

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