JP2012018989A - Method of manufacturing semiconductor device - Google Patents

Abstract

A semiconductor device having a buried bit line with reduced variation in height is provided.
A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a bit line and a word line in a semiconductor substrate, wherein the semiconductor substrate is etched to extend in a first direction. Forming a plurality of first semiconductor pillars by forming a groove; forming a diffusion layer on a part of a side surface of the first semiconductor pillar; and the step between adjacent first semiconductor pillars. Forming a bit line connected to the diffusion layer in the first groove; forming a first semiconductor pillar and a first insulating film covering the bit line; and at least a part of the first semiconductor pillar. Forming a second groove extending in a second direction orthogonal to the first direction in the first insulating film so as to be exposed, and forming an epitaxial layer on the exposed first semiconductor pillar. Growing second semiconductor pillar Forming, characterized by having a.
[Selection] Figure 34

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), it is becoming difficult to planarly lay out components, such as gates, sources, and drains, as the density increases. A DRAM (Dynamic Random Access Memory) having a minimum wiring pitch of 90 nm or less requires a three-dimensional layout. Here, the three-dimensional layout is a semiconductor pillar perpendicular to the main surface of the semiconductor substrate (hereinafter referred to as “semiconductor pillar”, but is referred to as “silicon pillar” when the semiconductor is silicon). A source / drain (S / D) is provided at the upper end and lower end of the semiconductor substrate, and a gate insulating film and a gate electrode (word line) are arranged on the surface of the intermediate portion. Are stacked (hereinafter referred to as “vertical transistors”).

JP 2008-140996 A Japanese Patent Application Laid-Open No. 08-250612

FIG. 49 is a sectional view showing an outline of a vertical transistor in a DRAM memory cell.
In a semiconductor substrate 200 made of silicon having a surface 201a, trenches 202a and 202b having a bottom surface 201b are formed. In the region between the trenches, silicon pillars 203a, 203b, and 203c that form the channel of the transistor are formed. A pair of buried gate electrodes 208a and 208b are formed on both side walls of the silicon pillar 203a, and a pair of buried gate electrodes 208c and 208d are formed on both side walls of the adjacent silicon pillar 203b. The gate electrode functions as a word line. Embedded bit lines 205a and 205b are formed at the bottom of the trench via a thermal oxide film 204. In plan view, the extending direction of the bit line is a direction perpendicular to the extending direction of the word line. The buried bit lines 205a and 205b are connected to one of the diffusion layers 206a and 206b formed in the semiconductor substrate 200 and constituting the source or drain (S / D) of the transistor. On the top of each silicon pillar, the other diffusion layer 210 constituting the source or drain (S / D) of the transistor is formed. A capacitor 213 is formed on the diffusion layer 210 via a contact plug 212. The capacitor 213 includes a lower electrode 213a, a capacitive insulating film 213b, and an upper electrode 213c. Each silicon pillar and contact plug are insulated and separated by interlayer insulating films 209 and 211. Focusing on the silicon pillar 203b, one diffusion layer 206b connected to the bit line 205b and constituting the source / drain (S / D), a pair of gate electrodes 208c and 208d formed on both side walls of the pillar, and a capacitor One vertical transistor is constituted by the other diffusion layer 210 constituting the source / drain (S / D).

  By using such a vertical transistor, the occupied area per unit memory cell can be reduced, so that the density of the MOSFET can be increased. In the vertical transistor, since the bit line connected to the drain region has a hierarchical structure in which the bit line is disposed below the gate electrode, the bit line is buried deeper than the gate electrode at the bottom of the groove surrounded by the adjacent semiconductor pillar. There is a need. However, in order to reduce the area occupied by the MOSFET, the opening diameter of the groove to be embedded must be reduced, and as a result, the aspect ratio (depth / opening diameter ratio) of the groove tends to increase.

  As the aspect ratio increases, it becomes difficult to embed the conductive film serving as the bit line, and voids are generated in the trench, making it difficult to embed uniformly. Even if such a conductive film is processed into a bit line, variations in the film thickness (height) cannot be reduced, and the electric resistance of the bit line is not stable, so that the performance of the MOSFET deteriorates. Occurs.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a bit line and a word line in a semiconductor substrate to form a first groove extending in a first direction by etching the semiconductor substrate. Accordingly, a step of forming a plurality of first semiconductor pillars, a step of forming a diffusion layer on a part of a side surface of the first semiconductor pillar, and the first between the adjacent first semiconductor pillars. Forming a bit line connected to the diffusion layer in the trench; forming a first insulating film covering the first semiconductor pillar and the bit line; and at least a part of the first semiconductor pillar. Forming a second groove extending in a second direction orthogonal to the first direction in the first insulating film so as to be exposed, and epitaxially forming on the exposed first semiconductor pillar. Grow the second layer And having the steps of forming a conductive pillar, a.

  According to the method for manufacturing a semiconductor device according to the present invention, since a buried bit line is formed in a shallow trench having a low aspect ratio, a portion that becomes a channel of a vertical transistor is formed by epitaxial growth. It is possible to form a buried bit line with reduced thickness variation.

It is a principal part perspective view which shows the general view of the semiconductor device manufactured with the manufacturing method of the semiconductor device which concerns on this invention. FIG. 2 is a plan view showing a planar layout of the semiconductor device shown in FIG. 1. It is a top view for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing by the AA line in FIG. 3 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is sectional drawing in the same position as FIG. 4 for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is a top view for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is a top view for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. FIG. 40 is a cross-sectional view taken along line AA in FIG. 39 for illustrating a process of the method for manufacturing a semiconductor device to which the present invention is applied. FIG. 40 is a cross-sectional view taken along line B-B in FIG. 39 for illustrating a process of the method for manufacturing a semiconductor device to which the present invention is applied. FIG. 40B is a cross-sectional view at the same position as that in FIG. 40A for describing a process of the semiconductor device manufacturing method to which the present invention is applied. It is sectional drawing in the same position as FIG. 40B for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. FIG. 40B is a cross-sectional view at the same position as that in FIG. 40A for describing a process of the semiconductor device manufacturing method to which the present invention is applied. It is sectional drawing in the same position as FIG. 40B for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. FIG. 40B is a cross-sectional view at the same position as that in FIG. 40A for describing a process of the semiconductor device manufacturing method to which the present invention is applied. It is sectional drawing in the same position as FIG. 40B for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. FIG. 40B is a cross-sectional view at the same position as that in FIG. 40A for describing a process of the semiconductor device manufacturing method to which the present invention is applied. It is sectional drawing in the same position as FIG. 40B for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. FIG. 40B is a cross-sectional view at the same position as that in FIG. 40A for describing a process of the semiconductor device manufacturing method to which the present invention is applied. It is sectional drawing in the same position as FIG. 40B for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. FIG. 40B is a cross-sectional view at the same position as that in FIG. 40A for describing a process of the semiconductor device manufacturing method to which the present invention is applied. It is sectional drawing in the same position as FIG. 40B for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. FIG. 40B is a cross-sectional view at the same position as that in FIG. 40A for describing a process of the semiconductor device manufacturing method to which the present invention is applied. It is sectional drawing in the same position as FIG. 40B for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is a top view for demonstrating the process of the manufacturing method of the semiconductor device to which this invention is applied. It is principal part sectional drawing which shows the general view of the semiconductor device manufactured by the manufacturing method of the conventional semiconductor device.

A semiconductor device manufacturing method according to an embodiment to which the present invention is applied will be described below with reference to the drawings. The same symbols are attached to the same members, and the description is omitted or simplified. Further, the same members will be appropriately omitted. The drawings used in the following description are schematic, and the ratio of length, width, thickness, and the like are different from actual ones.
In the following embodiments, examples will be described together, but the specific conditions such as materials and dimensions are merely examples.

  1 and 2 show an outline of a semiconductor device manufactured by a method of manufacturing a semiconductor device to which the present invention is applied. 3 to 48 are drawings showing steps up to forming a buried word line of a semiconductor device in a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied. 3 to 38 show a method for forming a buried bit line of a semiconductor device, and FIGS. 39 to 48 show a method for forming a buried word line of a semiconductor device.

  1 and 2, a DRAM is described as an example of an outline of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present invention. FIG. 1 is a perspective view of a memory cell portion of a DRAM. FIG. 2 is a plan view showing a planar layout of the semiconductor device shown in FIG.

First, a description will be given with reference to FIG.
The capacitor 113 is formed on the silicon pillars 101a, 101b, 101c, 102a, and 102b formed by digging the semiconductor substrate 100 made of silicon, and the word lines 108a, 108b, 108c, and 108d constituting the gate electrodes of the transistors. The bit lines 105a and 105b are formed at different heights and extending in the vertical direction so as to surround the silicon pillar. That is, each word line extends in the X direction (second direction) at a position higher than the bit line, and each bit line is formed in the deepest part of the trench and is in the Y direction (first direction perpendicular to the X direction). Direction). The transistor constituting the unit cell is composed of one bit line and two word lines. For example, the silicon pillar 101a includes a pair of word lines 108a and 108b connected to the bit line 105a at the end of the cell region. Similarly, the silicon pillar 102a includes a bit line 105a and a pair of word lines 108c and 108d. The same applies to other silicon pillars.

  The word line is a double gate in which two word lines are electrically connected to one pillar, but the bit line is electrically connected to only one silicon pillar. The bit line is not connected by the insulating film (silicon oxide film) formed on the side surface of the silicon pillar from the silicon pillar on the opposite side to be connected, and only the insulating film on the side of the connecting silicon pillar is opened. It is connected to a diffusion layer formed in the silicon pillar. Therefore, the bottom surface of the bit line is insulated from the silicon substrate by the insulating film. The basic configuration is the same as that in FIG.

Next, a description will be given with reference to FIG.
In the memory cell according to the present embodiment, silicon pillars 101a, 101b, 101c, 102a, 102b, 102c, 103a, 103b, and 103c are regularly arranged in a matrix in the X direction and the Y direction perpendicular to the X direction. In FIG. 2, nine silicon pillars are illustrated for convenience of explanation, but the present invention is not limited to this. For example, several thousand to several hundred thousand silicon pillars are arranged. Therefore, in this case, the number of bit lines and word lines is on the order of hundreds to thousands. Bit lines 105a and 105b extending in the Y direction are formed between the silicon pillars arranged in the X direction. Each bit line is shared by a plurality of silicon pillars arranged in the Y direction. For example, the bit line 105a is shared by the silicon pillars 101a, 102a, and 103a.

  Hereinafter, a method of manufacturing the semiconductor device shown in FIGS. 1 and 2, particularly a method of forming a bit line will be described with reference to FIGS. 3 to 38.

As shown in FIGS. 3 and 4, first, a mask film 104 that is a silicon nitride film is formed on a silicon substrate (semiconductor substrate) 100.
In the embodiment, a mask film 104 which is a silicon nitride film having a thickness of about 40 nm is formed by a low pressure CVD (Chemical Vapor Deposition) method. The film formation conditions at this time were dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as source gases, the flow rates were 75 sccm and 750 sccm, the heating temperature was 630 ° C., and the pressure was 300 Pa.

Next, a bit line opening (hole) 105 c extending in the Y direction (first direction) is formed in the mask film 104 by photolithography and dry etching.
Although the end of each bit line opening 105c is formed wide, it is a region where a contact is formed, and does not adversely affect the formation of the bit line. FIG. 4 shows a cross section taken along line AA of FIG. 3, and the same applies to FIG. A silicon substrate (semiconductor substrate) 100 is exposed at the bottom of the opening 105c.
In the example, the width W1 of the opening 105c is 45 nm.

Next, as shown in FIG. 5, the silicon substrate (semiconductor substrate) 100 is anisotropically dry-etched using the mask film 104 as a mask, and a trench (first first) extending in the Y direction (first direction) is formed. Groove) 106 is formed.
In the embodiment, the trench 106 having a depth H1 of 50 nm is formed. In this dry etching, a reactive ion etching (RIE) method using inductively coupled plasma (ICP) was used. Etching conditions are as follows: source power is 1000 W, high frequency power is 50 to 200 W, pressure is 5 to 20 mTorr, stage temperature is 20 to 40 ° C., and sulfur hexafluoride (SF ₆ ) and chlorine (Cl ₂ ) are etched. Gas was used, and the respective flow rates were set to 90 sccm and 100 sccm.
The trench 106 is formed to form a first silicon pillar (first semiconductor pillar) 100b.

Next, as shown in FIG. 6, an insulating film (second insulating film) which is a silicon oxide film so as not to fill the trench 106 and to have a predetermined thickness T1 on the bottom surface of the trench 106. 107 is formed.
In the example, the insulating film 107, which is a silicon oxide film, was formed by radical oxidation at a heating temperature of 800 to 900 ° C. so that the film thickness T1 on the bottom surface of the trench 106 was 10 nm. The thickness of the mask film 104 used as a mask is 40 nm, and the etching depth H1 of the silicon substrate is 50 nm. Since the total depth of the trench formed in the silicon substrate 100 is 90 nm and the width W1 of the opening is 45 nm, the aspect ratio is 2.

Next, as shown in FIG. 7, a buried film 109, which is a silicon film, is formed so as to fill in the trench formed between the adjacent first silicon pillars 100b.
In the embodiment, the buried film 109 which is a silicon film is formed by low pressure CVD using monosilane (SiH ₄ ) as a source gas.

Next, as shown in FIG. 8, anisotropic dry etching is performed under the condition that the buried film 109 that is a silicon film and the insulating film 107 that is a silicon oxide film are etched at a constant speed, and each upper surface has a trench 106. Etch back to the same height from the bottom. As a result, the insulating film 107a covering the bottom and side surfaces of the trench 106 and the trench formed by the insulating film 107a are buried so that the position of each upper surface is the same as the upper surface of the first silicon pillar 100b. The buried film 109a is formed. As a result, a new trench 106a is formed above the upper surfaces of the insulating film 107a and the buried film 109a. At this stage, the buried film 109a does not function as a bit line.
In the embodiment, the anisotropic etching is performed by the reactive ion etching (RIE) method using inductively coupled plasma (ICP), and the upper surface of the buried film 109 and the upper surface of the insulating film 107 are formed. Is etched back from the bottom surface of the trench 106 to a position where the height H2 becomes 50 nm so that the height becomes the same height as the top surface of the first silicon pillar 100b.

Next, as shown in FIG. 9, an insulating film 110 that is a silicon oxide film is formed in the trench 106 a and on the mask film 104.
In the embodiment, the insulating film 110, which is a silicon oxide film having a thickness T3 of 3 nm, is formed in the trench 106a and on the upper surface of the mask film 104 by a thermal oxidation method at a heating temperature of 800 to 900 ° C.

Next, as shown in FIG. 10, after the silicon oxide film formed on the bottom of the trench 106a including the buried film 109a which is a silicon film and the silicon oxide film formed on the upper surface of the mask film 104 are removed. Then, the buried film 109a which is a silicon film is selectively removed.
In the example, first, the silicon oxide film formed on the buried film 109a which is a silicon film and the silicon oxide film formed on the upper surface of the mask film 104 were removed by anisotropic dry etching. As a result, the insulating film 110 remained on the inner wall of the trench 106a, and 39 nm was secured as the opening width W2 of the trench 106a.
Next, the buried film 109a was selectively removed by wet etching with ammonia water (NH ₃ ).
In this wet etching, the silicon oxide film is not etched. Therefore, the insulating film 107a, which is a silicon oxide film, remains while maintaining the bottom film thickness (T1) of 10 nm, and only the buried film 109a, which is a silicon film, is selectively removed. Further, by removing the buried film 109a, a new trench 106b is formed there.

Next, as shown in FIG. 11, a buried film 111 made of a conductive material is formed on the entire surface so as to fill the trenches 106a and 106b.
In the examples, arsenic-doped silicon was used as the conductive material.

  Next, as shown in FIG. 12, the buried film 111 is etched back by anisotropic dry etching to fill the trench 106b. As a result, a new buried film 111a made of the buried film 111 having the upper surface at the same position as the upper surface 107b of the insulating film 107a and the upper surface of the first silicon pillar 100b is formed. At this stage, a new trench 112 is formed above the buried film 111a. The opening width of the trench 112 is 39 nm.

Next, as shown in FIG. 13, a silicon nitride film is formed on the entire surface including the inner surface of the trench 112, and then etched back by anisotropic dry etching to form a sidewall protective film 114 made of a silicon nitride film.
In the embodiment, a silicon nitride film having a thickness of 5 nm is formed on the entire surface including the inner surface of the trench 112 by a CVD method, and then etched back by anisotropic dry etching to form a sidewall protective film 114 made of a silicon nitride film. did. As a result, the silicon nitride film formed on the mask film 104 and the silicon nitride film formed on the buried film 111a are removed. The sidewall protective film 114 has a role of preventing the insulating film 110 from being etched in a later wet etching process. At this stage, the trench 112 becomes a new trench 112a, and its opening width W3 is 29 nm.

Next, as shown in FIG. 14, the buried film 111a whose surface is exposed is etched back and further dug down. The region dug down forms a new trench 112b, and forms a trench 112c together with the trench 112a formed above.
In the embodiment, the buried film 111a whose surface is exposed is etched back and further dug down by 30 nm. As a result, the buried film 111a whose vertical thickness was 40 nm at the stage of formation in FIG. 12 became a buried film 111b with a thickness of 10 nm, and the depth of the trench 112b was 30 nm.

Next, as shown in FIG. 15, sidewalls 115 are formed on the side surfaces of the trench 112c. Thus, the insulating film 107a exposed on the side surface of the trench 112b is also covered with the sidewall 115. In forming the sidewall 115, the titanium nitride film on the upper surface 111c of the buried film 111b is removed (portion indicated by a two-dot chain line black circle in the drawing), and at the same time, the side wall 115 is positioned below the upper surface of the mask mask film 104. Control is performed so that the upper surface of the wall 115 is positioned.
In the embodiment, a titanium nitride film having a thickness of 7 nm serving as an etching sacrificial layer is formed on the entire surface by the CVD method, and then the sidewall 115 is formed at a position 20 nm lower than the upper surface of the mask mask film 104 by anisotropic dry etching. Etchback was performed so that the upper surface was positioned, and a sidewall 115 made of a titanium nitride film was formed on the side surface of the trench 112c.

Next, as shown in FIG. 16, an insulating film 116, which is a silicon oxide film, is formed so as to fill the space remaining in the trench 112c.
For the formation of the insulating film 116, a CVD method, an ALD method (Atomic Layer Deposition), or a spin coating method can be used.

Next, as shown in FIG. 17, the insulating film 116 is etched back to form the insulating film 116a, and at the same time, a trench 117 is formed thereabove. In forming the insulating film 116a, the upper surface of the insulating film 116a is positioned below 15 nm from the upper surface of the mask film 104, and the upper surface of the sidewall 115 made of titanium nitride is controlled not to be exposed.
In the embodiment, the vertical interval between the upper surface of the sidewall 115 made of titanium nitride and the upper surface of the buried insulating film 116a is 5 nm, but may be in the range of 5 to 15 nm. The opening width W4 of the trench 117 is 29 nm as in the stage of FIG.

Next, as shown in FIG. 18, a protective film 118 that is a silicon film is formed on the entire surface including the inner wall of the trench 117 so as not to fill the trench 117. The protective film 118 is preferably an amorphous silicon film that is free from the influence of crystal grains that cause non-uniform etching at the etching stage. The amorphous silicon film can be obtained by setting the film formation temperature to 540 ° C. or lower.
In the example, a silicon film protective film 118 having a thickness of 5 nm was formed by a CVD method.

Next, of the protective film 118, one of the upper surface protective film 118a formed on the mask film 104 and the side wall protective films 118b and 118c formed on the side wall of the trench 117 (the left side wall protection in FIG. 18). Impurities are implanted into the film 118b) and a part of the horizontal protective film 118d formed on the insulating film 116 (the left part in FIG. 18). The introduction of impurities here is performed on the side wall protective film 118b formed on the side wall opposite to the pillar where the bit line contact to be described later is to be formed, of the side wall protective films 118b and 118c. As an impurity added to the protective film 118, boron fluoride (BF ₂ ) or the like can be given.
As a result, the upper surface protective film 118a formed on the mask film 104 and the trench 117 are not implanted into one of the side wall protective films 118b and 118c (the right side wall protective film 118c in FIG. 18). Impurities are implanted into the side wall protective film 118b formed on the side surface as a vertical surface and a part of the horizontal protective film 118d formed on the buried insulating film 116a as a horizontal surface (the left side portion in FIG. 18). Examples of the method for introducing the impurity include an oblique ion implantation method. FIG. 18 shows an example in which impurities are implanted into the protective film 118 using an oblique ion implantation method. Here, since it is necessary to implant ions into both the horizontal plane and the vertical plane, two-stage implantation with different angles can be used so that ion implantation is optimal for each implantation site.
In the examples, conditions of an acceleration energy of 5 keV, an implantation dose of 2E14 cm ⁻² , and an implantation angle of 27 ° to 45 ° were used. Here, the implantation angle means an inclination angle from a perpendicular to the surface of the semiconductor substrate. When performing the above two-stage injection, for example, the injection at an injection angle of 27 ° and the injection at 45 ° are combined. However, the implantation angle can be appropriately changed according to the depth and width of the trench 117, the film thickness of the protective film 118, and the like.

Next, as shown in FIG. 19, the side wall protective film 118c into which impurities are not implanted and a part of the horizontal protective film 118d formed on the right side of the insulating film 116a are removed, and a side made of a silicon nitride film is removed. The wall protective film 114 and a part of the insulating film 116a (the right side portion of the insulating film 116a in FIG. 19) are exposed.
In the examples, the removal was performed by wet etching with aqueous ammonia (NH ₃ ).

  Next, as shown in FIG. 20, with the remaining protective film 118 as a mask, the exposed part of the insulating film 116a (the right part of the insulating film 116a in FIG. 19) is anisotropically dry etched, The upper surface of the right side wall 115 in FIG. 19 is exposed. At this time, the left side wall 115 in FIG. 19 is not exposed because it is covered with the insulating film 116 a and the protective film 118. Conversely, the impurity introduction region for ion implantation into the protective film 118 in FIG. 18 is controlled so that the left side wall 115 is not exposed by this anisotropic dry etching. That is, the implantation angle is determined in consideration of the depth and width of the trench 117 and the thickness of the protective film 118.

Next, as shown in FIG. 21, the right sidewall 115 made of titanium nitride with the upper surface exposed is selectively removed by wet etching. As the etching solution, a mixed solution of ammonia and hydrogen peroxide water or the like can be used. As a result, the sidewall insulating film 114 made of a silicon nitride film, a part of the insulating film 107a formed in the trench 106, and a part of the upper surface of the buried film 111b are exposed.
In the example, the right side wall 115 was selectively removed by wet etching using a mixed solution of ammonia and hydrogen peroxide as an etching solution.

  Next, as shown in FIG. 22, the remaining protective film 118 is removed by isotropic dry etching.

Next, as shown in FIG. 23, the insulating film 107a with a part of the side surface exposed is etched by wet etching to form a side surface opening (opening) 100a that exposes a part of the first silicon pillar 100b. To do. At this time, the oxide film 116a is also removed at the same time. The side opening 100a is formed at a position between the lower surface of the sidewall insulating film 114 and the upper surface of the buried film 111b. On the other hand, since the insulating film 110 is protected by the sidewall insulating film 114 made of a silicon nitride film, it remains without being etched.
In the examples, a hydrofluoric acid (HF) -containing solution was used as the etching solution for the etching.

Next, as shown in FIG. 24, the sidewall 115 made of titanium nitride exposed in the trench is selectively removed. As a result, the inner wall of the trench 112c formed in FIG. 14 is exposed.
In the embodiment, the sidewall 115 was selectively removed using a mixed solution of ammonia and hydrogen peroxide as an etching solution.

Next, as shown in FIG. 25, a buried film 117 made of a conductive material is formed on the entire surface so as to fill the trench 112c. By using the same material as the conductive material of the embedded film 111b as the conductive material of the embedded film 117, the trench 112c can be embedded with the same material.
In the embodiment, the conductive material of the buried film 117 is made of arsenic-doped silicon by the CVD method, and the same material as that of the buried film 111b is used.

  Next, as shown in FIG. 26, the buried film 117 and the buried film 111b are etched back by anisotropic dry etching. As a result, in the side surface opening 100a, a part of the buried film 117 using the sidewall insulating film 114 as a mask remains, while the other buried film 117 in the trench 112a is removed, and the first silicon pillar is removed. A contact (semiconductor film) 117a to 100b is formed.

  Next, as shown in FIG. 27, the sidewall insulating film 114 made of a silicon nitride film is selectively removed to expose the insulating film 110. As a result, the side opening 110a is in a state in which a part of the side wall of the trench 106b formed in FIG. 10 is replaced with the contact 117a from the insulating film 107a. In addition, a new trench 106c serving as a first groove is formed in this step.

Next, as shown in FIG. 28, a barrier film 119 made of a conductive material is formed on the entire surface including the inside of the trench 106c with a thickness that does not fill the trench 106c.
In the example, a barrier film 119 made of titanium nitride having a thickness of 4 nm was formed by a CVD method. The barrier film 119 made of titanium nitride was formed at a temperature of 650 ° C. using titanium tetrachloride and ammonia as source gases. Prior to the formation of the barrier film 119, titanium tetrachloride was plasmatized in the same reaction chamber to form titanium with a thickness of 1 nm on the entire surface of the semiconductor substrate.
Titanium is deposited on the surface of the contact 117a made of an arsenic-doped silicon film, and at the same time, low resistance titanium silicide is formed. Thereby, contact resistance can be reduced. Titanium formed on the insulating film in other parts is nitrided at the time of titanium nitride formation and converted into titanium nitride. In the heat treatment for forming the barrier film 119, arsenic diffuses from the contact 117a made of an arsenic doped silicon film into the silicon substrate 100, and a diffusion layer 150 is formed on one side surface of the first silicon pillar 100b. The diffusion layer 150 may be formed continuously after the buried film 117 shown in FIG.

Next, as illustrated in FIG. 29, a conductive film 120 is formed on the entire surface so as to fill the trench 106 c serving as the first groove through the barrier film 119.
In the example, the conductive film 120 made of tungsten was formed by the CVD method.

Next, as shown in FIG. 30, the conductive film 120 and the barrier film 119 are etched back to the position of the upper surface 107b of the insulating film 107a by anisotropic dry etching. As a result, the bit line 120b formed of the barrier film 119a and the conductive film 120a surrounded by the insulating film 107a is formed in the trench 106c that is the first groove formed between the adjacent first silicon pillars 100b. . The bit line 120b is connected to the diffusion layer 150 via a titanium silicide (not shown) and a contact 117a on the side surface of the first silicon pillar 100b. In addition, a new trench 106d is formed on the bit line 120b by the etch back. By the trench 106d, the surface of the first silicon pillar 100b and the surface of the bit line 120b have the same height and form the same plane.
In the examples, the anisotropic etching was performed by a reactive ion etching (RIE) method using inductively coupled plasma (ICP: Inductively Coupled Plasma). As etching conditions, source power is 1400 W, high-frequency power is 65 W, pressure is 4 mTorr, stage temperature is 40 ° C., sulfur hexafluoride (SF ₆ ), argon (Ar), and chlorine (Cl ₂ ) are used as etching gases. The flow rates were 60 sccm, 40 sccm, and 140 sccm, respectively, and the etching was terminated by setting the time.

Next, as shown in FIG. 31, the insulating film 110 remaining on the sidewall of the trench 106d is removed. Further, the mask film 104 that is a silicon nitride film is removed to expose the silicon substrate 100.
In the example, the insulating film 110 which is a silicon oxide film was removed by wet etching with a hydrofluoric acid-containing solution. The mask film 104, which is a silicon nitride film, was removed by wet etching with phosphoric acid (H ₃ PO ₄ ) heated to 150 ° C.

Next, as shown in FIG. 32, a third insulating film (a part of the first insulating film) 121 and a fourth insulating film (a part of the first insulating film) 122 are sequentially formed on the first silicon. The pillar 100b and the bit line 120b were formed to cover.
In the embodiment, a third insulating film 121 that is a 50 nm thick silicon nitride film is formed so as to cover the entire surface, and then a 200 nm thick silicon oxide film is formed so as to cover the entire surface of the third insulating film 121. A fourth insulating film 122 was formed to cover the first silicon pillar 100b and the bit line 120b.

  Next, as shown in FIG. 33, a third insulating film (a part of the first insulating film) 121 and a fourth insulating film (a part of the first insulating film) 122 are formed by photolithography and dry etching. Then, a trench 123 serving as a second groove extending in the Y direction (first direction) is formed to expose the first silicon pillar 100b.

Next, as shown in FIG. 34, an epitaxial layer 124, which is a single crystal silicon serving as a second silicon pillar (second semiconductor pillar), is grown on the first silicon pillar (first semiconductor pillar) 100b. It was.
In the example, the epitaxial layer 124 having a thickness of 200 nm was grown by the CVD method. The growth conditions at this time were dichlorosilane (SiH ₂ Cl ₂ ) and hydrochloric acid (HCl) as source gases, the flow rates were 70 sccm and 40 sccm, the heating temperature was 780 ° C., and the pressure was 12 Pa.

Next, as shown in FIG. 35, a mask film 125 is formed so as to cover the epitaxial layer 124 to be the second silicon pillar (second semiconductor pillar) and the fourth insulating film 122. Further, a trench 126 is formed in the mask film 125 so that the fourth insulating film 122 is exposed.
In the example, a mask film 125 made of a silicon nitride film having a thickness of 200 nm was formed by CVD, and a trench 126 was formed by photolithography and dry etching.

Next, as shown in FIG. 36, the fourth insulating film 122, which is a silicon oxide film exposed in the trench 126, is removed. At this time, the third insulating film 121, which is a silicon nitride film, the mask film 125, and the epitaxial layer 124, which is a single-crystal silicon serving as a second silicon pillar, are not removed and remain. The side surface portion of the epitaxial layer 124 serving as the second silicon pillar is exposed. By this removal, a new trench 126 a is formed on the third insulating film 121.
In the embodiment, the fourth insulating film 122 which is a silicon oxide film is removed by wet etching using a hydrofluoric acid-containing solution.

Next, as shown in FIG. 37, an insulating film 127 that is a silicon nitride film is formed on the entire surface including the inside of the trench 126a with a thickness that does not bury the trench 126a. Further, the trench 126a is filled with a silicon oxide film on the insulating film 127 and then etched back to form an insulating film 128 that is a silicon oxide film so as to fill a part of the trench 126a. As a result, the shallow trench 126 a remains on the insulating film 128. Thereafter, an insulating film 129, which is a silicon oxide film, is formed so as to fill the shallow trench 126a. At this time, when viewed in plan, it is as shown in FIG. 38, and the trench in which the bit line 120b is embedded extends in the Y direction (first direction) in a parallel state as in FIG. .
In the embodiment, the insulating film 127 which is a silicon nitride film having a thickness of 10 nm is formed by the CVD method. Furthermore, the trench 126a was filled with a silicon oxide film formed by spin coating, and then etched back to form an insulating film 128 that is a 70 nm thick silicon oxide film. Next, an insulating film 129 which is a silicon oxide film is formed by a CVD method so as to fill the shallow trench 126a.

  The bit line is completed through the above steps.

Next, a method for manufacturing the semiconductor device shown in FIGS. 1 and 2, particularly a method for forming a word line, will be described with reference to FIGS.
Hereinafter, FIG. A shows the AA cross section of FIG. 39, and B shows the BB cross section. Here, FIG. A is the same location as the cross-sectional view shown in the bit line formation process, and clarifies the positional relationship between the word line and the bit line, and FIG. B shows the direction perpendicular to the bit line. This shows the positional relationship between adjacent word lines.

  As shown in the plan view of FIG. 39, the insulating films 129 and 127, the mask film 125, and the epitaxial layer 124 serving as the second silicon pillar (second semiconductor pillar) are formed in the Y direction (first direction) by photolithography and dry etching. The word line opening 130a extending in the X direction (second direction) orthogonal to the first direction) is formed.

As shown in FIGS. 40A and 40B, at the bottom of the trench (second groove) 130 having the word line opening 130a, an epitaxial layer 124 serving as a second silicon pillar (second semiconductor pillar) and a third layer are formed. The insulating film 121 is exposed.
In the embodiment, the width W5 of the trench 130 is 63 nm.

Next, as shown in FIGS. 41A and 41B, an insulating film 131 that is a silicon oxide film is formed on the inner wall of the trench 130. Thereby, the side surface portion and the bottom surface portion of the epitaxial layer 124 to be the second silicon pillar (second semiconductor pillar) are covered with the insulating film 131 that also functions as a gate insulating film.
In the embodiment, the insulating film 131 which is a silicon oxide film having a thickness of 10 nm is formed on the inner wall of the trench 130 by a thermal oxidation method at a heating temperature of 800 to 900 ° C.

Next, as shown in FIGS. 42A and 42B, a barrier film 132 is formed on the entire surface including the inside of the trench 130 with a thickness that does not fill the trench 130. This barrier film 132 can be formed at a temperature of 650 ° C. by using, for example, CVD with titanium tetrachloride and ammonia as source gases. Further, a conductive film 133 is formed on the barrier film 132 so as to fill the trench 130. Thereafter, the barrier film 132 and the conductive film 133 remaining on the insulating film 129 are removed. At this time, as shown in FIG. 42B, the epitaxial layer 124 to be the second silicon pillar (second semiconductor pillar) is formed on the insulating film 131 to be the gate insulating film, the barrier film 132, and the conductive film 133. Covered in order.
In the embodiment, a barrier film 132 made of titanium nitride having a thickness of 4 nm is formed on the entire surface including the inside of the trench 130 by a CVD method, and a conductive film 133 made of tungsten is formed by the CVD method so as to fill the trench 130. did. Thereafter, the barrier film 132 and the conductive film 133 which are titanium nitride remaining on the insulating film 129 were removed by CMP.

Next, as shown in FIGS. 43A and 43B, the conductive film 133 is etched back to form a conductive film 133a disposed below the trench 130, and a new trench 134 is formed on the conductive film 133a. To do. Under this etch-back condition, since the barrier film 132 can also be removed at the same speed as the conductive film 133, the barrier film 132 does not remain on the side surfaces of the trench 134 as shown in FIG. 43B. For this reason, the barrier film 132 exists as the barrier film 132 a only on the bottom surface of the trench 134.
In the embodiment, the above-described etch back is performed by a reactive ion etching (RIE) method using inductively coupled plasma (ICP), and the conductive film 133a has a thickness of 50 nm. As etching conditions, the source power is 1400 W, the high frequency power is 65 W, the pressure is 8 mTorr, the stage temperature is 40 ° C., sulfur hexafluoride (SF ₆ ), argon (Ar), and chlorine (Cl ₂ ) are used as etching gases. The flow rates were 60 sccm, 40 sccm, and 120 sccm, respectively, and the etching was terminated by setting the time.

Next, as shown in FIGS. 44A and 44B, an insulating film 135 that is a silicon oxide film is formed so as to cover the trench 134. Since the insulating film 135 is formed with a uniform thickness, a new trench 134a having a width W6 is formed as shown in FIG. 44B. 44A shows a cross section of the insulating film 135 formed on the side surface of the trench 134a, the insulating film 135 covers the top surface of the insulating film 129. FIG.
In the embodiment, the insulating film 135 which is a silicon oxide film having a thickness of 18 nm is formed by the CVD method. In addition, since the insulating film 135 is formed with a uniform thickness, a new trench 134a having an opening width W6 of 27 nm is formed.

Next, as shown in FIGS. 45A and 45B, the insulating film 135 is etched back and divided at the trench 134a. Similarly, the conductive film 133a and the barrier film 132a are also divided to form conductive films 136a to 136d and barrier films 137a to 137d, respectively. Here, the conductive film 136a and the barrier film 137a serve as the word line 138a over the insulating film 131 serving as a gate insulating film. The same applies to the word line 138b, the word line 138c, and the word line 138d.
Here, the word line 138b and the word line 138c are integrated to cover the side surface of the epitaxial layer 124 which becomes the second silicon pillar (second semiconductor pillar), and functions as a double gate. The other word lines 138a and 138d are not shown as paired word lines, but are similarly double gates.
Although a new trench 139 is formed by the etch back, the bottom surface is formed deeper than the barrier film 137 in order to prevent the adjacent word line 138 from being short-circuited.

Next, as shown in FIGS. 46A and 46B, the insulating film 135, which is a silicon oxide film remaining in the trench 139, is removed, and a new trench 140 is formed. At this time, the word line 138 made of tungsten and titanium nitride (in the embodiment), the epitaxial layer 124 made of single crystal silicon that becomes the second silicon pillar (second semiconductor pillar), and the mask film 125 made of silicon nitride film. The insulating film 127 remains without being removed.
In the example, the insulating film 135 was removed by wet etching using a hydrofluoric acid-containing solution.

Next, as shown in FIGS. 47A and 47B, an insulating film 141 that is a silicon nitride film is formed so as to cover the inner wall of the trench 140. Further, an insulating film 142 that is a silicon oxide film is formed so as to fill the trench 140. Thereafter, planarization is performed by removing the insulating film 142 on the surface by CMP. At this time, when viewed in plan, it is as shown in FIG. 48, and as in FIG. 39, the trenches in which the word lines 138 are buried extend in the X direction in parallel with each other. The reason why the right ends of the trenches are not separated is that the two word lines having the double gate structure described above are integrated at the end portions so that electrical control is performed collectively. As shown in FIG. 47A, the bit line 120b is insulated from the word line 138 by the third insulating film 121.
In the embodiment, an insulating film 141 that is a silicon nitride film having a thickness of 8 nm is formed by a CVD method, and an insulating film 142 is formed by a spin coating method.

 Thereafter, the step of removing the mask film 125 and forming the second diffusion layer on the pillar, the step of forming the capacitor contact plug, the step of forming the capacitor, the step of forming the wiring layer, etc. The semiconductor device to be the DRAM shown in FIG. 2 can be completed.

Also in the prior art, although the width W1 in FIG. 4 does not change at 45 nm, the thickness of the mask film 104 is 200 nm and the etching depth H1 is 250 nm, so the total depth is 450 nm and the aspect ratio is It was about 10. For this reason, in the prior art, since the aspect ratio becomes large and it is difficult to embed the bit line, there is a variation in the height (thickness) of the bit line, and the electric resistance is not stable.
On the other hand, according to the semiconductor manufacturing method of the present invention, a bit line is formed in a groove having a low aspect ratio formed between first semiconductor pillars formed by etching a semiconductor substrate, and thereafter A second semiconductor pillar including a portion that becomes a channel of the vertical transistor is formed on the first semiconductor pillar by epitaxial growth. By this method, the aspect ratio of the groove in which the bit line is embedded can be reduced to about 2, so that the bit line height (thickness) does not vary, and a bit line having a stable electric resistance can be obtained.

100 Silicon substrate (semiconductor substrate)
100a Side opening (opening)
100b First silicon pillar (first semiconductor pillar)
104 Mask film (mask)
105c Bit line opening (hole)
106 trench (first groove)
107 Insulating film (second insulating film)
117a Contact (semiconductor film)
121 3rd insulating film (a part of 1st insulating film)
122 4th insulating film (a part of 1st insulating film)
130 trench (second groove)
119a Barrier film (part of bit line)
120a conductive film (part of bit line)
120b bit line
124 Second silicon pillar (second semiconductor pillar, epitaxial layer)
138a, 138b, 138c, 138d Word line 150 Diffusion layer

Claims (9)

In a method for manufacturing a semiconductor device having a bit line and a word line in a semiconductor substrate,
Forming a plurality of first semiconductor pillars by etching a semiconductor substrate to form a first groove extending in a first direction;
Forming a diffusion layer on a part of a side surface of the first semiconductor pillar;
Forming a bit line connected to the diffusion layer in the first groove between the adjacent first semiconductor pillars;
Forming a first insulating film covering the first semiconductor pillar and the bit line;
Forming a second groove extending in a second direction orthogonal to the first direction in the first insulating film so that at least a part of the first semiconductor pillar is exposed;
Growing an epitaxial layer on the exposed first semiconductor pillar to form a second semiconductor pillar;
A method for manufacturing a semiconductor device, comprising: Etching a part of the first insulating film to expose a part of a side surface of the second semiconductor pillar;
Forming a gate insulating film on a part of the side surface of the second semiconductor pillar;
Forming a word line on the gate insulating film;
The method of manufacturing a semiconductor device according to claim 1, wherein: In the step of forming the diffusion layer, a second insulating film is formed so as not to bury the first groove in the first groove, and the first semiconductor is formed on a part of the second insulating film. An opening is formed so as to expose a part of the side surface of the pillar, and an impurity-doped semiconductor film is formed in the opening so as to be in contact with the side surface of the first semiconductor pillar, and the impurity is extracted from the semiconductor film. Forming the diffusion layer by diffusing into the first semiconductor pillar;
In the step of forming the bit line, the side surface of the bit line and the diffusion layer are connected by embedding the first groove through the second insulating film. A method for manufacturing a semiconductor device according to claim 1. In the step of forming the first semiconductor pillar, the etching is performed using a mask having a hole corresponding to the first groove,
In the step of forming the bit line, after the bit line material is embedded in the hole through the second insulating film in the first groove, the bit line material is changed to the first semiconductor pillar. 4. The method of manufacturing a semiconductor device according to claim 1, wherein etching back is performed to the same height as an upper surface of the semiconductor device.   5. The semiconductor device manufacturing method according to claim 1, wherein the bit line is formed by embedding the first groove, and the epitaxial layer is grown in the second groove. 6. Method.   The semiconductor device according to claim 1, wherein the first semiconductor pillar and the second semiconductor pillar are made of silicon, and the epitaxial layer is made of single crystal silicon. Method.   In the step of exposing a part of a side surface of the second semiconductor pillar, the first insulating film is formed by stacking a fourth insulating film on a third insulating film, and at least the above-described etching is performed. The method for manufacturing a semiconductor device according to claim 2, wherein the fourth insulating film is removed.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the third insulating film electrically insulates the bit line and the word line.   The method includes forming a second diffusion layer on the second semiconductor pillar and forming a capacitor connected to the second diffusion layer through a capacitive contact plug. The manufacturing method of the semiconductor device as described in any one of 2 to 8.

Images