JP2012018968A - Semiconductor device manufacturing method - Google Patents

Abstract

When embedding a groove with an insulating film, even if the aspect ratio of the groove is large, the insulating film is filled in the groove without leaving a void inside. This makes it possible to easily manufacture a miniaturized semiconductor device.
An insulating film for a groove is formed in the groove so as to have an overhang shape at the upper end of the groove formed between adjacent convex portions and to have a void above the groove. Impurities are doped into a part of the groove insulating film formed in the groove by ion-implanting the impurity into the groove insulating film from a direction oblique to the height direction of the convex portion. After removing the doped portion of the trench insulating film, the trench insulating film is filled into the trench.
[Selection] Figure 3

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In a semiconductor device, a method of filling an insulating film formed by a CVD method into a groove portion (space portion) in order to bury and planarize a groove portion for element isolation and a space portion between adjacent wirings ( Patent Document 1).

  As the miniaturization progresses, the aspect ratio (aspect ratio) of the groove is increased, and the generation of voids (cavities) when the groove is filled with an insulating film becomes a problem. If voids remain in the insulating film filled in the groove, short circuiting between the conductive layers via the voids is likely to occur in the subsequent process, which causes a reduction in manufacturing yield.

Japanese Patent Laid-Open No. 11-176936

  As a method for preventing voids from remaining in the insulating film filled in the trench, for example, Patent Document 1 proposes a method of performing dry etching while the insulating film is embedded. However, in this method, the amount and range of the insulating film to be removed by dry etching are not sufficiently controlled, and it is difficult to completely fill the step portion with the insulating film without leaving voids.

One embodiment is:
Providing a plurality of convex portions;
The groove portion has an overhang shape in which the groove insulating film protrudes in the width direction of the convex portion at the upper end portion of the groove portion formed between adjacent convex portions, and has a void at the upper portion of the groove portion. Forming a trench insulating film on
Doping impurities into a part of the groove insulating film formed in the groove by ion-implanting the impurity into the groove insulating film from a direction oblique to the height direction of the convex part; and
Selectively removing the impurity-doped portion of the trench insulating film;
Filling the groove insulating film into the groove,
The present invention relates to a method for manufacturing a semiconductor device having

Other embodiments are:
Providing a plurality of convex portions;
An insulating film for a groove is formed in the groove so that the length in the width direction at the top of the void is shorter than the length in the width direction at the bottom of the void at the top of the groove formed between adjacent protrusions. Process,
Doping impurities into a part of the groove insulating film formed in the groove by ion-implanting the impurity into the groove insulating film from a direction oblique to the height direction of the convex part; and
Selectively removing the impurity-doped portion of the trench insulating film;
Filling the groove insulating film into the groove,
The present invention relates to a method for manufacturing a semiconductor device having

  When embedding the groove with an insulating film, the insulating film can be filled in the groove without leaving a void even when the aspect ratio of the groove is large. This makes it possible to easily manufacture a miniaturized semiconductor device.

It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 2nd Example.

  In the method for manufacturing a semiconductor device, a trench insulating film is formed in a trench formed between adjacent convex portions. At this time, the groove insulating film is formed in the groove so as to have an overhang shape in which the groove insulating film protrudes in the width direction of the protrusion at the upper end of the groove and has a void at the upper part of the groove. Due to the overhang shape, the void in the groove portion has a length in the width direction of the void top portion shorter than a length in the width direction of the void bottom portion. Impurities are doped into a part of the groove insulating film formed in the groove by ion-implanting the impurity into the groove insulating film in the groove from a direction oblique to the height direction of the protrusion. Next, after selectively removing the impurity doped portion of the trench insulating film, the trench insulating film is filled into the trench.

  In the method of manufacturing a semiconductor device, it is possible to selectively remove the overhang shape near the opening, which is the cause of void generation, by doping impurities. Even when the aspect ratio of the groove formed between adjacent convex portions is high, the aspect ratio of the groove after selective removal of the overhang shape is low, and insulation is not generated in the groove without causing voids. The membrane can be filled. As a result, even when a trench having a high aspect ratio is embedded with an insulating film, a structure having no voids can be easily formed.

  Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. The following examples are specific examples shown for a deeper understanding of the present invention, and the present invention is not limited to these examples.

(First embodiment)
The present embodiment relates to a method of embedding a groove for forming an element isolation region with an insulating film without voids using STI (Shallow Trench Isolation). Hereinafter, the present embodiment will be described with reference to schematic cross-sectional views of FIGS.

As shown in FIG. 1, after a silicon oxide film (SiO ₂ ) 401 is formed on a semiconductor substrate 400 made of silicon (Si) by thermal oxidation or the like, a mask film is formed using a silicon nitride film (Si ₃ N ₄ ). 402 is formed and patterned.

  Next, dry etching of the semiconductor substrate 400 is performed using the mask film 402 as a mask to form a plurality of convex portions 300 having a height of about 300 nm and a groove portion 403 having a depth of about 300 nm between the adjacent convex portions 300. In this case, the aspect ratio of the height from the groove bottom surface to the upper surface of the mask film 402 with respect to the width of the groove 403 is 3 to 10.

  Next, as shown in FIG. 2, a silicon oxide film 410 having a thickness of about 5 to 8 nm is formed by thermally oxidizing the silicon surface exposed inside the groove 403. Thereafter, a first silicon oxide 404 (corresponding to an insulating film for a trench) containing no impurities is deposited by HDP-CVD (High Density Plasma-Chemical Vapor Deposition) method. At this time, the first silicon oxide 404 covers the inside of the groove 403 and the upper surface of the mask film 402. On the upper portion of the mask film 402, the first silicon oxide 404 is deposited in a tapered shape as shown in FIG. 2 due to the well-known characteristics of the HDP-CVD method.

Here, when the aspect ratio of the groove part 403 is as large as 3 or more, since the blockage starts near the opening of the groove part 403 earlier than the inside of the groove part 403 is completely filled, the vicinity of the opening (the upper end part of the groove part) An overhang shape (a portion 404b surrounded by a dotted line in FIG. 2) in which silicon oxide 404 protrudes in the width direction 302 of the convex portion is obtained. As a result, a void V is formed in the upper part of the groove 403. At this time, the length L ₁ in the width direction 302 of the void top formed in the upper part in the groove is smaller than the length L _{2 in} the width direction 302 of the void bottom. The film thickness of the first silicon oxide 404 is preferably set to such an extent that the upper end portion of the void V is not completely closed by the overhang portion.

  Next, as shown in FIG. 3, an impurity such as phosphorus (P) or boron (B) is introduced into the first silicon oxide 404 on the mask film including the overhang portion to oxidize the impurity. Silicon 404a is formed. Specifically, using an oblique ion implantation method, the implantation angle of the ion implantation to the main surface (height direction of the convex portion) 301 of the semiconductor substrate 400 is set to 3 to 70 °, preferably 5 to 45 °, A portion of the bottom of the groove 403 excluding the silicon oxide 404 is doped with an impurity to form a silicon oxide 404a containing the impurity. The impurity type (conductivity type) may be either N-type or P-type. By using the oblique ion implantation method, it is possible to minimize the introduction of impurities into the upper surface portion S of the first silicon oxide located inside the groove portion 403.

The concentration of the impurity to be doped is set to 1 × 10 ¹⁰ atoms / cm ² or more, and the energy is set to 5 Kev to 100 Kev. The higher the impurity concentration, the wet etching rate described later and the etching rate ratio between the silicon oxide 404a containing the impurity and the silicon oxide 404 containing no impurity (the etching rate of the silicon oxide containing the impurity / containing the impurity). The etching rate of silicon oxide not to be increased) is preferable. The energy is appropriately selected according to the film thickness of the first silicon oxide 404 and the mass number of the impurity element to be introduced, but is preferably set so as to minimize the amount of impurities doped into the mask film 402. . This is because the portion of the mask film 402 doped with impurities undergoes some etching by wet etching, which will be described later, and the shape of the mask film 402 changes.

  As shown in FIG. 4, the silicon oxide 404a containing impurities is selectively removed by wet etching. At this time, wet etching is performed using an etching solution in which an etching rate ratio (etching rate ratio) of silicon oxide 404a containing impurities to silicon oxide 404 containing no impurities is 10 or more. As such an etching solution, isopropyl alcohol (IPA) mixed with hydrofluoric acid (HF) at a ratio of 10% by mass (isopropyl alcohol containing 10% by mass of hydrofluoric acid) can be exemplified. By using such an etchant, the silicon oxide 404a containing impurities can be easily and selectively removed. Further, the silicon oxide 404 containing no impurities has etching resistance to the etching solution, and thus etching does not proceed and remains as it is.

  Next, as shown in FIG. 5, the second silicon oxide film 405 is embedded in the upper portion of the groove portion 403 by using the HDP-CVD method (because it is formed integrally with the first silicon oxide film 404). The boundary line is not shown.) Since the first silicon oxide 404 fills the lower layer portion of the groove portion 403, the groove portion above the first silicon oxide 404 has an aspect ratio of less than 3. Further, since the overhanging portion is removed by the wet etching performed in the process of FIG. 4, the vicinity of the opening of the groove 403 is widely open. Therefore, the second silicon oxide film 405 can easily fill the upper layer portion of the groove 403 without generating voids.

Subsequently, after planarization by the CMP method, the remaining mask film 402 is removed by wet etching using heated phosphoric acid (H ₃ PO ₄ ) as a chemical solution. Subsequently, when wet etching is performed using a chemical solution containing hydrofluoric acid so that the position of the upper surface of the silicon oxide 404 is approximately the same as the surface of the semiconductor substrate 400, as shown in FIG. An element isolation region is completed.

  Alternatively, a liner film using silicon nitride or the like may be sandwiched between the first silicon oxide film 404 and the silicon oxide film 410 for embedding.

  In the present embodiment, when the insulating film is filled in the trench for forming the element isolation region, it is possible to selectively remove the overhang shape in the vicinity of the opening that causes the generation of the void. Further, the aspect ratio of the groove after removing the overhang shape is less than 3. For this reason, even when a groove having an aspect ratio of 3 or more is embedded with an insulating film, a structure having no voids can be easily formed.

(Second embodiment)
The present embodiment relates to a method of forming an interlayer insulating film between wirings without voids. Hereinafter, the present embodiment will be described with reference to FIGS.

  As shown in FIG. 7, an element isolation region 203 is formed on a semiconductor substrate 200 made of P-type silicon using an insulating film such as a silicon oxide film. A region partitioned by the element isolation region 203 becomes an active region 204. The gate electrode 206 of the MOS transistor is formed by a laminated film of a polycrystalline silicon film 206a into which impurities are introduced and a refractory metal film 206b such as tungsten. The lower layer portion of the polycrystalline silicon film is provided so as to fill a recess formed by removing the semiconductor substrate 200 in the active region 204.

  A gate insulating film 202 such as a silicon oxide film is provided at the interface portion between the gate electrode 206 and the semiconductor substrate 200. A cap insulating film 207 for protecting the upper surface of the gate electrode 206 is provided using a silicon nitride film. The cap insulating film 207 is formed by patterning simultaneously with the gate electrode 206. N-type impurity layers 205 are formed on both sides of the gate electrode 206 by ion implantation of N-type impurities such as phosphorus, and function as source / drain electrodes of the MOS transistor 201.

  Next, as shown in FIG. 8, sidewalls 208 are formed with a silicon nitride film so as to cover the side portions of the gate electrode 206 and the cap insulating film 207. Thereafter, a silicon nitride film 220 is formed to a thickness of 3 to 6 nm so as to cover the entire surface of the semiconductor substrate 200. In the present embodiment, the convex portion 300 includes a gate electrode portion protruding upward from the semiconductor substrate 200, a cap insulating film 207, a sidewall 208, and a silicon nitride film 220. The groove portion 240 is a space portion between adjacent groove portions. In this embodiment, the depth of the groove portion 240 (the sum of the height of the gate electrode 206 and the height of the cap insulating film 207) is about 300 nm and the aspect ratio is 3 to 10. Become.

Next, as shown in FIG. 9, the first silicon oxide 230 not containing impurities is deposited to about 200 nm using HDP-CVD. Here, when the aspect ratio of the groove portion 240 is as large as 3 or more, since the blockage starts near the opening of the groove portion 240 earlier than the inside of the groove portion 240 is completely filled, the vicinity of the opening (the upper end portion of the groove portion) An overhang shape (a portion 404b surrounded by a dotted line in FIG. 9) in which silicon oxide 404 protrudes in the width direction 302 of the convex portion is obtained. Thereby, a void V is formed in the upper part of the groove part 240. At this time, the length L ₁ in the width direction 302 of the void top formed in the upper part in the groove is smaller than the length L _{2 in} the width direction 302 of the void bottom. The film thickness of the first silicon oxide 230 is preferably set to such an extent that the upper end portion of the void V is not completely closed by the overhang portion.

  Next, as shown in FIG. 10, an impurity such as phosphorus or boron is introduced by using an oblique ion implantation method to form a silicon oxide 230a containing the impurity. By setting the angle of ion implantation with respect to the main surface (height direction of the convex portion) 301 of the semiconductor substrate 400 in the oblique ion implantation method to 3 to 70 °, preferably 5 to 45 °, The silicon oxide 230 a containing impurities can be formed in a state where doping of impurities is suppressed on the upper surface of the silicon oxide 230.

  Next, as shown in FIG. 11, the silicon oxide 230a containing impurities is selectively removed by wet etching. At this time, wet etching is performed using an etchant in which the etching rate ratio of the silicon oxide 230a containing impurities to the silicon oxide 230 containing no impurities is 10 or more. As such an etching solution, isopropyl alcohol (IPA) mixed with hydrofluoric acid (HF) at a ratio of 10% by mass (isopropyl alcohol containing 10% by mass of hydrofluoric acid) can be exemplified. By using such an etchant, the silicon oxide 230a containing impurities can be easily and selectively removed. In addition, the silicon oxide 230 containing no impurities has etching resistance to the etching solution, and thus etching does not proceed and remains as it is.

  Next, as shown in FIG. 12, the second silicon oxide film 250 is embedded in the upper portion of the groove portion 240 using the HDP-CVD method (because it is formed integrally with the first silicon oxide film 230). (No boundary line is shown).

  Since the first silicon oxide 230 fills the inside of the groove 240, the groove located on the first silicon oxide 230 has an aspect ratio of less than 3. Further, since the overhang-like portion is removed by the wet etching performed in the process of FIG. 11, the vicinity of the opening of the groove 240 is in a widely open state. Therefore, the second silicon oxide film 250 can easily fill the upper layer portion of the groove 240 without generating voids.

  Next, as shown in FIG. 13, if the upper surface is flattened by the CMP method, the filling of the interlayer insulating film using silicon oxide is completed. At this time, there is no problem even if the cap insulating film 207 and part of the upper end of the sidewall 208 are removed by polishing.

  In this embodiment, when the interlayer insulating film is filled in the space portion between the wirings, it is possible to selectively remove the overhang shape in the vicinity of the opening that is the cause of the void generation. Further, the aspect ratio of the groove after removing the overhang shape is less than 3. For this reason, even when a groove having an aspect ratio of 3 or more is embedded with an insulating film, a structure having no voids can be easily formed.

  In this embodiment, even when the wiring interval between the gate electrodes 206 becomes 60 nm or less due to the progress of miniaturization, an insulating film formed by the HDP-CVD method that has been conventionally used as an interlayer insulating film is used. It can be used. As a result, a conventional manufacturing apparatus can be used effectively without using an expensive embedding material formed by a spinner method such as polysilazane, and the semiconductor device can be manufactured at low cost.

  In the present embodiment, the layout of the gate electrode is not particularly limited, but the present invention is applied to the case where the gate electrode (word wiring) is arranged extending in a predetermined direction like a memory cell such as a DRAM element. This is particularly effective.

  In this embodiment, the case where the gate electrode is arranged as the wiring has been described. However, the present invention can also be applied to the case where an interlayer insulating film covering the wiring other than the gate electrode is formed.

200, 400 Semiconductor substrate 201 MOS transistor 202 Gate insulating film 203 Element isolation region 204 Active region 205 N-type impurity layer 206 Gate electrode 206a Polycrystalline silicon film 206b refractory metal film 207 Cap insulating film 208 Side wall 220 Silicon nitride film 230, 404 First silicon oxide 230a, 404a Impurity-containing silicon oxide 240, 403 Groove 250, 405 Second silicon oxide film 300 Convex portion 301 Convex height direction 302 Width direction 401 Silicon oxide film 402 Mask film 404b Over Hang shape 410 Silicon oxide S Upper surface V Void

Claims (14)

Providing a plurality of convex portions;
The groove portion has an overhang shape in which the groove insulating film protrudes in the width direction of the convex portion at the upper end portion of the groove portion formed between adjacent convex portions, and has a void at the upper portion of the groove portion. Forming a trench insulating film on
Doping impurities into a part of the groove insulating film formed in the groove by ion-implanting the impurity into the groove insulating film from a direction oblique to the height direction of the convex part; and
Selectively removing the impurity-doped portion of the trench insulating film;
Filling the groove insulating film into the groove,
A method for manufacturing a semiconductor device comprising: Providing a plurality of convex portions;
An insulating film for a groove is formed in the groove so that the length in the width direction at the top of the void is shorter than the length in the width direction at the bottom of the void at the top of the groove formed between adjacent protrusions. Process,
Doping impurities into a part of the groove insulating film formed in the groove by ion-implanting the impurity into the groove insulating film from a direction oblique to the height direction of the convex part; and
Selectively removing the impurity-doped portion of the trench insulating film;
Filling the groove insulating film into the groove,
A method for manufacturing a semiconductor device comprising: In the step of providing the plurality of convex portions,
The method for manufacturing a semiconductor device according to claim 1, wherein an aspect ratio of a groove formed between adjacent convex portions is 3 or more. In the step of selectively removing the impurity-doped portion of the trench insulating film,
2. The impurity doped portion of the trench insulating film is removed so that the trench has an aspect ratio of less than 3 after removing the impurity doped portion of the trench insulating film. The manufacturing method of the semiconductor device of any one of -3. The step of providing the plurality of convex portions includes:
Etching the semiconductor substrate using a mask pattern to form the semiconductor substrate having a plurality of protrusions;
In the step of filling the groove insulating film in the groove,
The method for manufacturing a semiconductor device according to claim 1, wherein an element isolation region having a groove insulating film filled in the groove is formed. The step of providing the plurality of convex portions includes:
Forming a silicon oxide film on the surface of the semiconductor substrate;
Providing a mask pattern on the silicon oxide film;
By etching the semiconductor substrate and the silicon oxide film using the mask pattern, the portion of the semiconductor substrate protruding in the normal direction of the main surface of the semiconductor substrate, and the silicon oxide film and the mask on the protruding portion of the semiconductor substrate Forming a convex portion composed of a pattern;
Have
In the step of filling the groove insulating film in the groove,
The method for manufacturing a semiconductor device according to claim 1, wherein an element isolation region having a groove insulating film filled in the groove is formed. The step of providing the plurality of convex portions includes:
Forming a plurality of recesses in the semiconductor substrate;
Forming a gate insulating film on the inner wall of each recess;
Forming a gate electrode so as to protrude from the inside of each recess to the semiconductor substrate;
Have
The convex portion is composed of a portion of the gate electrode protruding above the semiconductor substrate,
In the step of filling the groove insulating film in the groove,
The method for manufacturing a semiconductor device according to claim 1, wherein an interlayer insulating film having a groove insulating film filled in the groove is formed. The step of providing the plurality of protrusions further includes the step of forming the gate electrode.
Forming a cap insulating film on each gate electrode;
Forming a sidewall on the side surface of each gate electrode and each cap insulating film;
Have
The method of manufacturing a semiconductor device according to claim 7, wherein the convex portion includes a portion of the gate electrode that protrudes upward from the semiconductor substrate, a cap insulating film, and a sidewall. The method for manufacturing a semiconductor device according to claim 1, wherein the groove insulating film is a silicon oxide film. In the step of forming a trench insulating film in the trench,
10. The method of manufacturing a semiconductor device according to claim 1, wherein the trench insulating film is formed by an HDP-CVD (High Density Plasma-Chemical Vapor Deposition) method. In the step of doping the impurities,
The method of manufacturing a semiconductor device according to claim 1, wherein impurities are ion-implanted at an angle of 3 to 70 ° with respect to a height direction of the convex portion. In the step of doping the impurities,
12. The method of manufacturing a semiconductor device according to claim 1, wherein impurities are ion-implanted under conditions of an impurity concentration of 1 × 10 ¹⁰ atoms / cm ² or more and an energy of 5 Kev to 100 Kev. In the step of selectively removing the impurity-doped portion of the trench insulating film,
The portion of the trench insulating film doped with impurities is removed under the condition that the etching rate ratio of the portion of the trench insulating film doped with the impurity to the portion of the trench insulating film doped with impurities is 10 or more. A manufacturing method of a semiconductor device given in any 1 paragraph of Claims 1-12. In the step of selectively removing the impurity-doped portion of the trench insulating film,
The method for manufacturing a semiconductor device according to claim 13, wherein the impurity-doped portion of the trench insulating film is removed by wet etching using isopropyl alcohol containing 10 mass% hydrofluoric acid.

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