JP2012014802A - Semiconductor storage device - Google Patents

Abstract

A semiconductor memory device capable of preventing erroneous writing of a data signal is provided.
In DL drivers 6 and 7 of this MRAM, after a transistor 20 corresponding to a selected digit line group DLG is turned on, a sub DL driver 21 corresponding to the selected digit line DL is connected in parallel. The four transistors 24.1 to 24.4 are sequentially turned on to pass the magnetizing current IDL. Therefore, the overshoot of the magnetizing current IDL can be small.
[Selection] Figure 7

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a memory cell that magnetically stores a data signal.

  In recent years, MRAM (Magnetic Random Access Memory) has attracted attention as a semiconductor memory device capable of storing nonvolatile data with low power consumption. The MRAM includes a plurality of memory cells MC arranged in a plurality of rows and a plurality of columns, a plurality of digit lines DL provided corresponding to the plurality of rows, and a plurality of bit lines BL provided corresponding to the plurality of columns, respectively. Including. During the write operation, the magnetizing current Im is supplied to the selected digit line DL to activate each memory cell MC corresponding to the digit line, and the selected bit line BL corresponds to the logic of the data signal. A directional write current Iw is supplied to write a data signal to a memory cell MC arranged at the intersection of the selected digit line DL and bit line BL (see, for example, Patent Document 1).

JP 2004-185752 A

  However, in the conventional MRAM, overshoot occurs in each of the magnetizing current Im and the write current Iw during the write operation, and each memory cell MC corresponding to the selected digit line DL and bit line BL is excessively disturbed. There is a problem that the write characteristic margin is lowered and erroneous writing of the data signal occurs.

  Therefore, a main object of the present invention is to provide a semiconductor memory device capable of preventing erroneous writing of data signals.

  The semiconductor memory device according to the present invention is arranged in a plurality of rows and a plurality of columns, each of which stores a plurality of memory cells magnetically, a plurality of digit lines provided corresponding to each of a plurality of rows, and A plurality of bit lines provided corresponding to the plurality of columns, and a decoder that selects any one of the plurality of digit lines and any one of the plurality of bit lines according to an address signal; A digit line driver that activates each memory cell corresponding to the digit line by passing a magnetizing current through the digit line selected by the decoder, and writing in a direction corresponding to the logic of the data signal to the bit line selected by the decoder. And a bit line driver for writing a data signal into an activated memory cell by flowing an inflow current. One ends of the plurality of digit lines are commonly connected to a first node that receives a power supply voltage. A digit line driver is provided corresponding to each digit line, and is selected by a plurality of first transistors connected in parallel between the other end of the corresponding digit line and a second node receiving a reference voltage. And a first control circuit for sequentially conducting a plurality of first transistors corresponding to the digit lines.

  Another semiconductor memory device according to the present invention is arranged in a plurality of rows and a plurality of columns, each of which stores a plurality of memory cells magnetically storing data signals, and a plurality of digits provided corresponding to each of the plurality of rows. Select one of the digit lines and one of the plurality of bit lines according to the address, the plurality of bit lines provided corresponding to the respective columns, and the address signal. A digit line driver that activates each memory cell corresponding to the digit line by passing a magnetizing current through the digit line selected by the decoder, and the bit line selected by the decoder according to the logic of the data signal And a bit line driver for writing a data signal to the activated memory cell by passing a write current in the opposite direction. The bit line driver is provided corresponding to each bit line, and a plurality of first transistors connected in parallel between one end of the corresponding bit line and the first node, and corresponding to each bit line A plurality of second transistors connected in parallel between the other end of the corresponding bit line and the second node, and a first logic data signal when writing a first logic data signal; When supplying a power supply voltage and a reference voltage to each node and writing a data signal of the second logic, a switching circuit for supplying a reference voltage and a power supply voltage to each of the first and second nodes, and a bit selected by the decoder And a control circuit that sequentially turns on the plurality of first transistors corresponding to the lines and turns on the plurality of second transistors corresponding to the bit lines.

  In the semiconductor memory device according to the present invention, the digit line driver is provided corresponding to each digit line, and is connected in parallel between the other end of the corresponding digit line and the second node receiving the reference voltage. The first control circuit includes a first transistor, and sequentially turns on the plurality of first transistors corresponding to the digit line selected by the decoder. Therefore, it is possible to prevent the magnetizing current from overshooting and to prevent the erroneous writing of the data signal.

  In another semiconductor memory device according to the present invention, a bit line driver is provided corresponding to each bit line, and a plurality of bit line drivers connected in parallel between one end of the corresponding bit line and the first node. A control circuit including a first transistor and a plurality of second transistors provided corresponding to each bit line and connected in parallel between the other end of the corresponding bit line and the second node; The plurality of first transistors corresponding to the bit line selected by the decoder are sequentially turned on, and the plurality of second transistors corresponding to the bit line are sequentially turned on. Therefore, it is possible to prevent the write current from overshooting and to prevent erroneous writing of the data signal.

1 is a circuit diagram showing a configuration of an MRAM memory array according to an embodiment of the present invention; FIG. FIG. 2 is a circuit diagram showing a configuration of a memory cell shown in FIG. 1. FIG. 3 is a diagram for explaining a method of writing data in the memory cell shown in FIG. 2. FIG. 5 is another diagram for explaining a data writing method of the memory cell shown in FIG. 2. FIG. 3 is a diagram for explaining a data read method of the memory cell shown in FIG. 2. It is a block diagram which shows the part relevant to the data writing of MRAM shown in FIGS. FIG. 7 is a circuit block diagram illustrating a configuration of the DL driver illustrated in FIG. 6. FIG. 8 is a circuit block diagram illustrating a configuration of a sub DL driver illustrated in FIG. 7. FIG. 9 is a circuit block diagram illustrating a configuration of a signal generation circuit illustrated in FIG. 8. FIG. 10 is a circuit block diagram illustrating a configuration of a delay circuit illustrated in FIG. 9. FIG. 10 is a circuit block diagram showing another configuration of the delay circuit shown in FIG. 9. 12 is a time chart showing an operation of the DL driver shown in FIGS. FIG. 7 is a circuit block diagram illustrating a configuration of the BL driver illustrated in FIG. 6. FIG. 14 is a circuit block diagram illustrating a configuration of a sub-BL driver illustrated in FIG. 13. FIG. 15 is a time chart showing the operation of the BL driver shown in FIGS. 13 and 14. FIG. 16 is a time chart showing a write operation of the MRAM shown in FIGS. It is a circuit block diagram which shows the example of a change of embodiment. It is a circuit diagram which shows the other example of a change of embodiment.

  FIG. 1 is a circuit diagram showing a configuration of an MRAM memory array MA according to an embodiment of the present invention. 1, memory array MA includes a plurality of memory cells MC arranged in a plurality of rows and a plurality of columns (for example, 256 rows and 256 columns), a plurality of word lines WL provided corresponding to the plurality of rows, respectively. A plurality of digit lines DL provided corresponding to the rows and a plurality of bit lines BL provided corresponding to the plurality of columns are included.

  Each memory cell MC includes a tunnel magnetoresistive element TMR and an access transistor (N channel MOS transistor) ATR as shown in FIG. Tunneling magneto-resistance element TMR and access transistor ATR are connected in series between corresponding bit line BL and the ground voltage VSS line, and the gate of access transistor ATR is connected to corresponding word line WL. Tunneling magneto-resistance element TMR is an element whose electric resistance value changes according to the logic of stored data.

  That is, as shown in FIG. 3, tunnel magnetoresistive element TMR includes fixed magnetization film FL, tunnel insulating film TB, and free magnetization film VL stacked between electrode EL and bit line BL. Each of the fixed magnetization film FL and the free magnetization film VL is composed of a ferromagnetic film. The magnetization direction of the fixed magnetization film FL is fixed in one direction. The magnetization direction of free magnetic film VL is written in one of one direction and the other direction. When the magnetization directions of the fixed magnetization film FL and the free magnetization film VL are the same, the resistance value of the tunnel magnetoresistive element TMR becomes a relatively small value, and when the magnetization directions of both are opposite, the tunnel magnetoresistive element TMR The electric resistance value becomes a relatively large value. The two-stage resistance values of tunneling magneto-resistance element TMR are associated with data signals 0 and 1, for example.

  At the time of data writing, as shown in FIG. 3, the word line WL is set to the “L” level of the non-selection level, the access transistor ATR is made non-conductive, the magnetizing current Im flows through the digit line DL, A write current Iw is supplied to the bit line BL. The magnetization direction of free magnetic film VL is determined by the combination of the directions of magnetization current Im and write current Iw.

  FIG. 4 is a diagram showing the relationship between the direction of the magnetization current Im and the write current Iw and the magnetic field direction during data writing. Referring to FIG. 4, a magnetic field Hx indicated by the horizontal axis indicates a magnetic field H (DL) generated by the magnetizing current Im flowing through the digit line DL. On the other hand, the magnetic field Hy indicated on the vertical axis indicates the magnetic field H (BL) generated by the write current Iw flowing through the bit line BL.

  The magnetic field direction stored in the free magnetic film VL is newly written only when the sum of the magnetic fields H (DL) and H (BL) reaches a region outside the asteroid characteristic line shown in the drawing. That is, when a magnetic field corresponding to the area inside the asteroid characteristic line is applied, the magnetic field direction stored in the free magnetic film VL is not updated. Therefore, in order to update the storage data of tunneling magneto-resistance element TMR by the write operation, it is necessary to pass a current through both digit line DL and bit line BL. Here, it is assumed that a magnetizing current Im in one direction flows through the digit line DL, and a writing current Iw flows in the direction according to the logic (0 or 1) of the data signal through the bit line BL. The magnetic field direction once stored in tunneling magneto-resistance element TMR, that is, the stored data is held in a nonvolatile manner until new data writing is executed.

  At the time of data reading, as shown in FIG. 5, word line WL is set to the “H” level of the selection level to make access transistor ATR conductive, and grounded from bit line BL through tunneling magneto-resistance element TMR and access transistor ATR. A current Is flows through the line of the voltage VSS. The value of this current Is changes according to the resistance value of tunneling magneto-resistance element TMR. Therefore, the data stored in tunneling magneto-resistance element TMR can be read by detecting the value of current Is.

  FIG. 6 is a block diagram showing a portion related to data writing of the MRAM. In FIG. 6, in addition to the memory array MA, this MRAM includes an address buffer 1, an IO buffer 2, a write timing controller 3, row decoders 4 and 5, DL drivers 6 and 7, column decoders 8 and 9, a write data controller. 10 and 11 and BL drivers 12 and 13.

  Address buffer 1 takes in external address signals ADD0 to ADD12 in synchronization with the rising edge of clock signal CLK, and generates row address signals RA0 to RA7 and column address signals CA0 to CA3. IO buffer 2 takes in write data signals D0 to D15 in synchronization with the rising edge of clock signal CLK, and generates internal data signals WD0 to WD15.

  In response to the chip enable signal ZCE and the write enable signal ZWE being both set to the activation level “L” at the rising edge of the clock signal CLK, the write timing controller 3 performs the digit line enable signal DLEN and the bit line enable. A signal BLEN is generated.

  Row decoder 4 generates internal address signals SDW0 to SDW3 based on digit line enable signal DLEN and row address signals RA0 and RA1. Row decoder 5 generates internal address signals ZWBS0 to ZWBS15 and MDL0 to MDL63 based on row address signals RA2 to RA7. The 256 digit lines DL of the memory array MA are grouped in groups of 16 in advance.

  The DL driver 6 selects one of the 16 digit line groups according to the internal address signals ZWBS0 to ZWBS15, and ends one end of each of the 16 digit lines DL belonging to the selected digit line group. Is applied with a power supply voltage VDD.

  The DL driver 7 selects one of the 256 digit lines DL according to the internal address signals SDW0 to SDW3 and MDL0 to MDL63, and the line of the ground voltage VSS from the other end of the selected digit line DL. The magnetizing current Im having a value corresponding to the reference voltage VREFDL is caused to flow out. The DL driver 7 prevents the magnetizing current Im from overshooting by increasing the magnetizing current Im in a plurality of stages.

  Each of column decoders 8 and 9 generates bit line selection signals BLS0 to BLS15 based on column address signals CA0 to CA3. Write data controller 10 generates write control signals WDPL0 to WDPL15, WDNL0 to WDNL15 based on internal data signals WD0 to WD15 and bit line enable signal BLEN. Write data controller 11 generates write control signals WDPR0 to WDPR15 and WDNR0 to WDNR15 based on internal data signals WD0 to WD15 and bit line enable signal BLEN. The 256 bit lines BL of the memory array MA are grouped in groups of 16 in advance.

  Each of the BL drivers 12 and 13 selects any one of the 16 bit lines BL in each of the 16 bit line groups according to the bit line selection signals BLS0 to BLS15, for a total of 16 lines. The bit line BL is selected. The BL driver 12 operates according to the write control signals WDPL0 to WDPL15, WDNL0 to WDNL15, and applies the power supply voltage VDD or the ground voltage VSS to one end of each of the selected 16 bit lines BL. The BL driver 13 operates according to the write control signals WDPR0 to WDPR15 and WDNR0 to WDNR15, and applies the ground voltage VSS or the power supply voltage VDD to one end of each of the selected 16 bit lines BL.

  In this way, the BL drivers 12 and 13 pass the write current Iw in the direction (polarity) according to the logic level of the write data signals D0 to D15 to the selected 16 bit lines BL. The value of the write current Iw is set to a value corresponding to the reference voltage VREFBL. The BL drivers 12 and 13 prevent the write current Iw from overshooting by increasing the write current Iw in a plurality of stages.

  FIG. 7 is a circuit diagram showing the configuration of the DL drivers 6 and 7. In FIG. 7, 256 digit lines DL of the memory array MA are divided in advance into 16 digit line groups DLG0 to DLG15. One end of the 16 digit lines DL belonging to each digit line group DLG is commonly connected to the node N20. Each digit line DL has a parasitic resistance.

  DL driver 6 includes 16 P-channel MOS transistors 20 provided corresponding to 16 digit line groups DLG0 to DLG15, respectively. The source of each P-channel MOS transistor 20 receives power supply voltage VDD, and its drain is connected to node N20 of corresponding digit line group DLG. The gates of 16 P channel MOS transistors 20 corresponding to 16 digit line groups DLG0 to DLG15 receive internal address signals ZWBS0 to ZWBS15, respectively.

  The DL driver 7 includes 256 sub DL drivers 21 provided corresponding to 256 digit lines DL and 16 N channels provided corresponding to 16 digit line groups DLG0 to DLG15, respectively. MOS transistor 22 and logic circuit 23 are included.

  The 256 sub DL drivers 21 are controlled by digit line selection signals DLS0 to DLS255, respectively. Each sub-DL driver 21 is connected between the other end of the corresponding digit line DL and the drain (node N21) of the corresponding N-channel MOS transistor 22, and the corresponding digit line selection signal DLS has an activation level “H”. ", The other end of the corresponding digit line DL is connected to the corresponding node N21. In addition, the current driving capability of each sub DL driver 21 is sequentially increased in a plurality of stages.

  N channel MOS transistor 22 is connected between node N21 and a line of ground voltage VSS, and has a gate receiving reference voltage VREFDL. N-channel MOS transistor 22 constitutes a constant current element that causes a current having a value corresponding to reference voltage VREFDL to flow from node N21 to the line of ground voltage VSS.

  Logic circuit 23 selects any one of 256 digit line selection signals DLS0 to DLS255 in accordance with internal address signals SDW0 to SDW3 and MDL0 to MDL63, and selects the selected digit line selection signal DLS at the activation level “H”. To the level.

  FIG. 8 is a circuit block diagram showing a configuration of the sub DL driver 21. In FIG. 8, sub DL driver 21 includes a plurality of (for example, four) N-channel MOS transistors 24.1 to 24.4 and a signal generation circuit 25. A plurality of N channel MOS transistors 24.1 to 24.4 are connected in parallel between the other end of corresponding digit line DL and corresponding node N21. Transistors 24.1 to 24.4 receive output signals φ1 to φ4 of signal generation circuit 25, respectively.

  In response to the corresponding digit line selection signal DLS being raised from the “L” level of the inactivation level to the “H” level of the activation level, the signal generation circuit 25 outputs the control signals φ 1 to φ 4 to a predetermined level. It rises sequentially from “L” level to “H” level at time intervals. When the signals φ1 to φ4 are sequentially raised to “H” level, the transistors 24.1 to 24.4 are sequentially turned on, and the current driving capability of the sub DL driver 21 is sequentially increased in four stages.

  FIG. 9 is a circuit block diagram illustrating the configuration of the signal generation circuit 25. In FIG. 9, the signal generation circuit 25 includes three stages of delay circuits 31 to 33 connected in series and three AND gates 34 to 36. The digit line selection signal DLS becomes the control signal φ1 as it is. The delay circuit 31 delays the control signal φ1 by a predetermined time. The delay circuit 32 further delays the control signal φ1 delayed by the delay circuit 31 by a predetermined time. The delay circuit 33 further delays the control signal φ1 delayed by the delay circuits 31 and 32 by a predetermined time.

  The AND gate 34 outputs a logical product signal of the control signal φ1 and the output signal of the delay circuit 31 as the control signal φ2. The AND gate 35 outputs a logical product signal of the control signal φ1 and the output signal of the delay circuit 32 as the control signal φ3. The AND gate 36 outputs a logical product signal of the control signal φ1 and the output signal of the delay circuit 33 as the control signal φ4.

  When digit line selection signal DLS is at “L” level, control signals φ 1 to φ 4 are both at “L” level. When digit line selection signal DLS rises to “H” level, control signals φ 1 to φ 4 are sequentially raised to “H” level at predetermined time intervals. When digit line selection signal DLS falls to “L” level, control signals φ 1 to φ 4 are all lowered to “L” level.

  FIG. 10 is a circuit diagram illustrating the configuration of the delay circuits 31 to 33. In FIG. 10, each of delay circuits 31-33 includes a resistance element 37 connected between the input node and the output node, and a capacitor 38 connected between the output node and the line of ground voltage VSS. When the input node rises to the “H” level (power supply voltage VDD), a current flows to the capacitor 38 via the resistance element 37, the voltage between the terminals of the capacitor 38 gradually increases, and the output node Become H level. The delay time is determined by the resistance value of the resistance element 37 and the capacitance value of the capacitor 38.

  FIG. 11 is a circuit diagram illustrating another configuration of the delay circuits 31 to 33. In FIG. 11, each of delay circuits 31 to 33 includes an even number (for example, two stages) of inverters 39 connected in series between an input node and an output node. The delay time is determined by the current drive capability of the inverter 39, the number of stages of the inverter 39, and the like.

  In addition, when the digit line selection signal DLS is a clock signal having a fixed period, the signal generation circuit 25 may be configured by a DLL (Deley Locked Loop) circuit. In the DLL circuit, a plurality of clock signals that are out of phase with each other are generated. Therefore, the plurality of clock signals may be used as the control signals φ1 to φ4.

  Further, only the transistors 24.1 to 24.4 may be provided in the sub DL driver 21 and the signal generation circuit 25 may be disposed in the logic circuit 23.

  12A to 12F are time charts showing operations of the DL drivers 6 and 7. Here, it is assumed that second digit line DL from the left in FIG. 7 among 16 digit lines DL belonging to digit line group DLG0 is designated by internal address signals SDW0 to SDW3 and MDL0 to MDL63.

  First, internal address signal ZWBS0 falls to the “L” level of the activation level, and P channel MOS transistor 20 corresponding to digit line group DLG0 becomes conductive. Next, at time t1, when the digit line selection signal DLS1 rises to the “H” level of the activation level, the signal generation circuit 25 of the sub DL driver 21 corresponding to the digit line selection signal DLS1 at a predetermined time interval. Control signals φ1 to φ4 are sequentially raised from “L” level to “H” level (time t1 to t4).

  When the control signals φ1 to φ4 are sequentially raised from the “L” level to the “H” level, the transistors 24.1 to 24.4 of the sub DL driver 21 are sequentially turned on, and the magnetizing current Im is applied to the digit line DL. Flowing. The magnetizing current Im sequentially increases stepwise. At this time, since the current drive capability of the sub DL driver 21 is sequentially increased in a plurality of stages, the overshoot of the magnetizing current Im can be small as shown by the solid line in FIG.

  Conventionally, the sub DL driver 21 is composed of only one large-sized N-channel MOS transistor. Therefore, when the N channel MOS transistor corresponding to the selected digit line DL is turned on, the parasitic capacitance of the node N21, that is, the source capacitance of the 16 N channel MOS transistors and the drain capacitance of the N channel MOS transistor 22 are charged. A large current for transiently flowing flows and a large overshoot of the magnetizing current Im occurs as indicated by the dotted line in FIG.

  When a large overshoot of the magnetizing current Im occurs, each memory cell MC corresponding to the selected digit line DL is excessively disturbed, and the write characteristic margin is reduced. For this reason, there has been a problem that the probability of erroneous writing is high. On the other hand, in the present invention, since the overshoot of the magnetizing current Im is small, the write characteristic margin can be maintained high, and the probability of erroneous writing can be lowered.

  Next, at time t5, when digit line selection signal DLS1 falls to “L” level, which is an inactivation level, both control signals φ1 to φ4 fall to “L” level, and N channel MOS transistor 24.1. ˜24.4 is made non-conductive and the magnetizing current Im is cut off. In addition, internal address signal ZWBS0 is raised to the “H” level of the inactivation level, and P channel MOS transistor 20 corresponding to digit line group DLG0 is rendered non-conductive.

  Note that the sizes of the transistors 24.1 to 24.4 may be the same, but the sizes of the transistors 24.1 to 24.4 may be sequentially reduced. For example, the size of the transistors 24.1 to 24.4 is set to 8: 4: 2: 1. The level of overshoot is the highest when transistor 24.1 is turned on and is the lowest when transistor 24.4 is turned on. Therefore, the peak value of the magnetizing current Im can be suppressed low by turning on the transistor 24.4 having a small size last, as shown by the solid line in FIG.

  FIG. 13 is a circuit diagram showing the configuration of the BL drivers 12 and 13. In FIG. 13, 256 bit lines BL of the memory array MA are divided in advance into 16 bit line groups BLG0 to BLG15. Each bit line BL has a parasitic resistance.

  The BL driver 12 includes a P-channel MOS transistor 40 and N-channel MOS transistors 41 and 42 provided corresponding to each bit line group BLG, and 256 sub-channels provided corresponding to 256 bit lines BL, respectively. And a BL driver 43.

  P channel MOS transistor 40 is connected between a line of power supply voltage VDD and node N40, and has a gate receiving write control signal WDPL0. N channel MOS transistor 41 has its drain connected to node N40 and its gate receiving write control signal WDNL0. N channel MOS transistor 42 is connected between the source of N channel MOS transistor 41 and the line of ground voltage VSS, and the gate thereof receives reference voltage VREFBL. N-channel MOS transistor 42 constitutes a constant current element that causes a current of a value corresponding to reference voltage VREFBL to flow out.

  The 256 sub-BL drivers 43 are controlled by bit line selection signals BLS0 to BLS255, respectively. Each sub-BL driver 43 is connected between one end of the corresponding bit line BL and the corresponding node N40, and in response to the corresponding bit line selection signal BLS being set to the activation level “H” level. , One end of the corresponding bit line BL is connected to the corresponding node N40. In addition, the current driving capability of each sub-BL driver 43 increases sequentially in a plurality of stages. Bit line selection signals BLS0 to BLS255 are generated from column address signals CA0 to CA3.

  The BL driver 13 includes a P-channel MOS transistor 50 and N-channel MOS transistors 51 and 52 provided corresponding to each bit line group BLG, and 256 sub-channels provided corresponding to 256 bit lines BL, respectively. And a BL driver 53.

  P channel MOS transistor 50 is connected between a line of power supply voltage VDD and node N50, and has a gate receiving write control signal WDPR0. N channel MOS transistor 51 has its drain connected to node N50 and its gate receiving write control signal WDNR0. N channel MOS transistor 52 is connected between the source of N channel MOS transistor 51 and the line of ground voltage VSS, and has its gate receiving reference voltage VREFBL. N-channel MOS transistor 52 constitutes a constant current element that causes a current of a value corresponding to reference voltage VREFBL to flow out.

  The 256 sub-BL drivers 53 are controlled by bit line selection signals BLS0 to BLS255, respectively. Each sub-BL driver 53 is connected between the other end of the corresponding bit line BL and the corresponding node N50, and in response to the corresponding bit line selection signal BLS being set to the activation level “H” level. The other end of the corresponding bit line BL is connected to the corresponding node N50. In addition, the current drive capability of each sub-BL driver 53 increases sequentially in a plurality of stages.

  FIG. 14 is a circuit block diagram showing the configuration of the sub-BL drivers 43 and 53. 14, sub-BL driver 43 includes a plurality of (for example, four) N-channel MOS transistors 44.1 to 44.4 and a signal generation circuit 45. A plurality of N channel MOS transistors 44.1 to 44.4 are connected in parallel between one end of corresponding bit line BL and corresponding node N40. The gates of transistors 44.1 to 44.4 receive output signals φ11 to φ14 of signal generation circuit 45.

  In response to the corresponding bit line selection signal BLS being raised from the “L” level of the inactivation level to the “H” level of the activation level, the signal generation circuit 45 outputs the control signals φ11 to φ14 to a predetermined level. It rises sequentially from “L” level to “H” level at time intervals. When the signals φ11 to φ14 are sequentially raised to “H” level, the transistors 44.1 to 44.4 are sequentially turned on, and the current driving capability of the sub-BL driver 43 is sequentially increased in four stages. When the corresponding bit line selection signal BLS is lowered to the “L” level of the inactivation level, both of the control signals φ11 to φ14 are lowered to the “L” level, and the transistors 44.1 to 44.4 are turned off. become. The configuration of the signal generation circuit 45 is the same as that of the signal generation circuit 25 described with reference to FIGS.

  Sub-BL driver 53 includes a plurality of (for example, four) N-channel MOS transistors 54.1 to 54.4 and a signal generation circuit 55. A plurality of N channel MOS transistors 54.1 to 54.4 are connected in parallel between the other end of corresponding bit line BL and corresponding node N50. Transistors 54.1 to 54.4 receive output signals φ21 to φ24 of signal generation circuit 55 at their gates.

  In response to the corresponding bit line selection signal BLS being raised from the “L” level of the inactivation level to the “H” level of the activation level, the signal generation circuit 55 supplies the control signals φ21 to φ24 to a predetermined level. It rises sequentially from “L” level to “H” level at time intervals. When the signals φ21 to φ24 are sequentially raised to “H” level, the transistors 54.1 to 54.4 are sequentially turned on, and the current driving capability of the sub-BL driver 53 is sequentially increased in four stages. When the corresponding bit line selection signal BLS is lowered to the “L” level of the inactivation level, the control signals φ21 to φ24 are all lowered to the “L” level, and the transistors 54.1 to 54.4 are turned off. become. The configuration of the signal generation circuit 55 is the same as that of the signal generation circuit 25 described with reference to FIGS.

  Next, operations of the BL drivers 12 and 13 will be described with reference to FIGS. Here, it is assumed that the second bit line BL from the top in FIG. 13 among the 16 bit lines BL belonging to the bit line group BLG0 is selected. Further, it is assumed that a write current Iw is caused to flow through the bit line BL from the right side to the left side in FIG. 13 by the write control signals WDPL0, WDNL0, WDPR0, and WDNR0. In the initial state, the transistors 40, 41, 50, 51 and the sub-BL drivers 43, 53 are in a non-conductive state.

  First, write control signal WDNL0 is raised to the activation level “H” level, and write control signal WDPR0 is lowered to the activation level “L” level, and transistors 41 and 50 are turned on. Next, the bit line selection signal BLS1 is set to the “H” level of the activation level.

  When the bit line selection signal BLS1 is set to the activation level “H” level, the control signals φ11 to φ14 sequentially rise to the “H” level by the signal generation circuit 45 of the sub-BL driver 43 corresponding to the bit line selection signal BLS1. The transistors 44.1 to 44.4 are sequentially turned on. At the same time, the control signals φ21 to φ24 are sequentially raised to “H” level by the signal generation circuit 55 of the sub-BL driver 53 corresponding to the bit line selection signal BLS1, and the transistors 54.1 to 54.4 are sequentially turned on.

  As a result, the write current Iw flows from the power supply voltage VDD line to the ground voltage VSS line via the transistor 50, sub-BL driver 53, bit line BL, sub-BL driver 43, and transistors 41 and 42. At this time, since the current driving capability of the sub-BL drivers 43 and 53 sequentially increases in a plurality of stages, the overshoot of the write current Iw can be small. After a predetermined time has elapsed, the transistors 50 and 41 and the sub-BL drivers 53 and 43 are turned off, and the write current Iw is cut off.

  When a write current Iw is passed through the bit line BL from the right side to the left side in FIG. 13, for example, data “1” is stored in the memory cell MC at the intersection of the selected bit line BL and the digit line DL. Written. When data “0” is written in the memory cell MC, the transistors 40 and 51 are made conductive instead of the transistors 41 and 50, and the write current Iw is applied to the bit line BL from the left side to the right side in FIG. Just flow away.

  FIGS. 15A to 15F are time charts showing the operations of the BL drivers 12 and 13. Here, the second bit from the top in FIG. 13 among the 16 bit lines BL belonging to the bit line group BLG0. It is assumed that the bit line BL is designated.

  First, write control signal WDNL0 is raised to the activation level “H” level, and write control signal WDPR0 is lowered to the activation level “L” level, and transistors 41 and 50 are turned on. Next, the bit line selection signal BLS1 is set to the “H” level of the activation level.

  When the bit line selection signal BLS1 is set to the activation level “H” level, the control signals φ11, φ21, φ12 and the sub-BL drivers 43, 53 corresponding to the bit line selection signal BLS1 are generated by the signal generation circuits 45, 55. φ22, φ13 and φ23, and φ14 and φ24 are sequentially raised from “L” level to “H” level at predetermined time intervals (time t1 to t4).

  When the control signals φ11 and φ21, φ12 and φ22, φ13 and φ23, φ14 and φ24 are sequentially raised from the “L” level to the “H” level, the transistors 44.1 and 54. 1, 44.2, 54.2, 44.3, 54.3, 44.4, and 54.4 are sequentially conducted, and a write current Iw flows through the bit line. At this time, since the current drive capability of the sub-BL drivers 43 and 53 is sequentially increased in a plurality of stages, the overshoot of the write current Iw can be small.

  Conventionally, each of the sub-BL drivers 43 and 53 is composed of only one large N-channel MOS transistor. Therefore, when the sub-BL drivers 43 and 53 corresponding to the selected bit line BL and the transistors 41 and 50 or the transistors 40 and 51 are brought into conduction, the parasitic capacitance of the node N40 (that is, the drain capacitances of the transistors 40 to 42). , 16 transistors), or a large current for charging a parasitic capacitance of the node N50 (ie, the drain capacities of the transistors 50 to 52 and the 16 transistors). As shown by the dotted line in FIG. 15E, a large overshoot of the write current Iw occurred.

  When a large overshoot of the write current Iw occurs, each memory cell MC corresponding to the selected bit line BL is excessively disturbed, and the write characteristic margin is reduced. For this reason, there has been a problem that the probability of erroneous writing is high. On the other hand, in the present invention, since the overshoot of the write current Iw is small, the write characteristic margin can be maintained high, and the probability of erroneous writing can be lowered.

  Next, at time t5, when bit line select signal BLS1 falls to "L" level, which is an inactive level, control signals φ11 to φ14 and φ21 to φ24 are all lowered to "L" level, and N channel MOS Transistors 44.1 to 44.4, 54.1 to 54.4 are turned off, and write current Iw is cut off. In addition, write control signal WDNL0 is lowered to “L” level, which is an inactivation level, and write control signal WDPR0 is raised to “H” level, which is an inactivation level, so that transistors 41 and 50 are non-conductive. become.

  Note that the sizes of the transistors 44.1 to 44.4 (and 54.1 to 54.4) may be sequentially reduced. For example, the size of the transistors 44.1 to 44.4 (and 54.1 to 54.4) is set to 8: 4: 2: 1. The level of overshoot is greatest when transistor 44.1 (and 54.1) is turned on, and is lowest when transistor 44.4 (and 54.4) is turned on. Therefore, when the small-sized transistor 44.4 (and 54.4) is turned on last, the peak value of the write current Iw can be suppressed low as shown in FIG.

  FIG. 16 is a time chart showing the write operation of this MRAM. In FIG. 13, a period of 1/10 of the clock signal CLK is one unit time. At time t0, when the chip enable signal ZCE and the write enable signal ZWE are set to the “L” level of the activation level at the rising edge of the clock signal CLK, the write command is recognized, the external address signals ADD0 to ADD12 and the write data Signals D0 to D15 are captured. At time t1 after one unit time has elapsed from time t0, the signals ZCE and ZWE are both raised to the “H” level of the inactivation level.

  At time t2 after 2.5 unit time has elapsed from time t0, internal address signals ZWBS and MDL are generated, and the N-channel MOS transistor 20 corresponding to the selected digit line group DLG becomes conductive, so that 16 digit lines DL is charged to the power supply voltage VDD.

  At time t3 after 0.5 unit time has elapsed from time t2, the digit line enable signal DLEN is raised to the “H” level of the activation level, and the internal address signal SDW is generated and applied to the selected digit line DL. The transistors 24.1 to 24.4 of the corresponding sub DL driver 21 are sequentially turned on, and the magnetizing current Im flows through the digit line DL. The overshoot of the magnetizing current Im is small as shown in FIG.

  At time t4 after one unit time has elapsed from time t3, the bit line enable signal BLEN is raised to the “H” level of the activation level, the write control signals WDP and WDN are generated, and the selected bit line BL Transistors 41, 50 or 40, 51 corresponding to are turned on. In addition, a bit line selection signal BLS is generated, and the transistors 44.1 to 44. of the sub BL drivers 43 and 53 corresponding to the selected bit line BL among the 16 bit lines BL belonging to each bit line group BLG. 4 (and 54.1 to 54.4) are sequentially performed, and the write current Iw is supplied to the selected bit line BL. The overshoot of the write current Iw is small as shown in FIG. This state is maintained for 4 unit times from time t4, and data signals D0 to D15 are respectively written in the 16 selected memory cells MC.

  At time t5 after the elapse of 4 unit time from time t4, digit line enable signal DLEN falls to “L” level of the inactivation level, and internal address signal SDW is reset. Thereby, the transistors 24.1 to 24.4 of the sub DL driver 21 are turned off, and the magnetizing current Im is cut off.

  At time t6 after one unit time has elapsed from time t5, the bit line enable signal BLEN falls to the “L” level of the inactivation level, the write control signals WDP and WDN are reset, and the BL drivers 12 and 13 Transistors 40, 41, 50, 51 become non-conductive. At time t6, the bit line selection signal BLS is reset and the transistors 44.1 to 44.4 and 54.1 to 54.4 of the sub-BL drivers 12 and 13 become non-conductive, and the write current Iw is cut off. Is done.

  At time t7 after one unit time has elapsed from time t6, the internal address signals ZWBS and MDL are reset, and the P-channel MOS transistor 20 of the DL driver 6 is turned off. Thereby, the writing operation is completed.

  FIG. 17 is a diagram showing a modified example of this embodiment, and is compared with FIG. In FIG. 17, in this modification, the DL driver 6 is removed, and the power supply voltage VDD is constantly applied to the node N20. In this modified example, the same effect as the embodiment can be obtained, and the layout area can be reduced by the amount corresponding to the DL driver 6.

  FIG. 18 is a diagram showing another modified example of this embodiment, and is a diagram contrasted with FIG. In FIG. 18, in this modification, the N channel MOS transistors 42 and 52 of the BL drivers 12 and 13 are removed, and the sources of the N channel MOS transistors 41 and 51 are directly connected to the line of the ground voltage VSS. The sizes (gate length and gate width) of the N channel MOS transistors 41 and 51 are set in advance so that a predetermined current flows.

  In this modified example, the same effects as in the embodiment can be obtained, and the N-channel MOS transistors 42 and 52, the circuit for generating the reference voltage VREFBL, and the wiring for the reference voltage VREFBL are not required, and the layout area is accordingly increased. Is small.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  MA memory array, MC memory cell, BL bit line, WL word line, DL digit line, TMR tunnel magnetoresistive element, ATR access transistor, VL free magnetic film, TB tunnel insulating film, FL fixed magnetic film, 1 address buffer, 2 IO buffer, 3 write timing controller, 4,5 row decoder, 6,7 DL driver, 8,9 column decoder, 10,11 write data controller, 12,13 BL driver, 20,40,50 P channel MOS transistor , 21 sub DL driver, 22, 24.1 to 24.4, 41, 42, 44.1 to 44.4, 51, 52, 54.1 to 54.4 N-channel MOS transistor, 23 logic circuit, 25, 45, 55 Signal generation circuit.

Claims (10)

A semiconductor memory device,
A plurality of memory cells arranged in a plurality of rows and a plurality of columns, each storing a data signal magnetically;
A plurality of digit lines respectively corresponding to the plurality of rows;
A plurality of bit lines respectively corresponding to the plurality of columns;
A decoder that selects any digit line of the plurality of digit lines and any bit line of the plurality of bit lines according to an address signal;
A digit line driver that applies a magnetizing current to a digit line selected by the decoder and activates each memory cell corresponding to the digit line;
A bit line driver for writing a data signal to an activated memory cell by passing a write current in a direction corresponding to the logic of the data signal to the bit line selected by the decoder;
One end of the plurality of digit lines is commonly connected to a first node that receives a power supply voltage;
The digit line driver is
A plurality of first transistors provided in correspondence with each digit line and connected in parallel between the other end of the corresponding digit line and a second node receiving a reference voltage;
And a first control circuit for sequentially turning on a plurality of first transistors corresponding to the digit line selected by the decoder. The plurality of first transistors have different sizes,
2. The semiconductor memory device according to claim 1, wherein the first control circuit conducts a plurality of first transistors corresponding to digit lines selected by the decoder in descending order of size. The first control circuit is provided corresponding to each digit line, and in response to selection of a corresponding digit line by the decoder, a plurality of first control circuits corresponding to a plurality of corresponding first transistors, respectively. Including a first signal generation circuit that sequentially activates the control signals at predetermined time intervals,
3. The semiconductor memory device according to claim 1, wherein the plurality of first transistors are turned on in response to a plurality of corresponding first control signals being set to an activation level. 4.   4. The digit line driver according to claim 1, further comprising a switching element having one electrode receiving the power supply voltage and the other electrode connected to the first node and conducting during a write operation. 5. A semiconductor memory device according to claim 1.   5. The digit line driver according to claim 1, further comprising: a constant current element having one electrode connected to the second node and the other electrode receiving the reference voltage and flowing a constant current. The semiconductor memory device described in 1. The bit line driver is
A plurality of second transistors provided corresponding to each bit line and connected in parallel between one end of the corresponding bit line and a third node;
A plurality of third transistors provided corresponding to the respective bit lines and connected in parallel between the other end of the corresponding bit line and the fourth node;
When writing a first logic data signal, the power supply voltage and the reference voltage are applied to the third and fourth nodes, respectively, and when writing a second logic data signal, the third logic And a switching circuit that applies the reference voltage and the power supply voltage to the fourth node, respectively.
And a second control circuit for sequentially turning on a plurality of second transistors corresponding to the bit lines selected by the decoder and sequentially turning on a plurality of third transistors corresponding to the bit lines. The semiconductor memory device according to claim 1. A semiconductor memory device,
A plurality of memory cells arranged in a plurality of rows and a plurality of columns, each storing a data signal magnetically;
A plurality of digit lines respectively corresponding to the plurality of rows;
A plurality of bit lines respectively corresponding to the plurality of columns;
A decoder that selects any digit line of the plurality of digit lines and any bit line of the plurality of bit lines according to an address signal;
A digit line driver that applies a magnetizing current to a digit line selected by the decoder and activates each memory cell corresponding to the digit line;
A bit line driver for writing a data signal to an activated memory cell by passing a write current in a direction corresponding to the logic of the data signal to the bit line selected by the decoder;
The bit line driver is
A plurality of first transistors provided corresponding to each bit line and connected in parallel between one end of the corresponding bit line and the first node;
A plurality of second transistors provided corresponding to each bit line and connected in parallel between the other end of the corresponding bit line and the second node;
When the first logic data signal is written, the power supply voltage and the reference voltage are applied to the first and second nodes, respectively, and when the second logic data signal is written, the first logic data signal is written. And a switching circuit for supplying the reference voltage and the power supply voltage to the second node, respectively.
And a control circuit for sequentially turning on the plurality of first transistors corresponding to the bit lines selected by the decoder and sequentially turning on the plurality of second transistors corresponding to the bit lines. The plurality of first transistors have different sizes,
The sizes of the plurality of second transistors are different from each other,
The control circuit conducts a plurality of first transistors corresponding to the bit line selected by the decoder in order from a larger size, and a plurality of second transistors corresponding to the bit line have a larger size. The semiconductor memory device according to claim 7, wherein the semiconductor memory device is electrically connected in order. The control circuit includes:
A plurality of first control signals corresponding to a plurality of corresponding first transistors are provided at a predetermined time interval in response to selection of the corresponding bit line by the decoder. A first signal generation circuit sequentially activated at
A plurality of second control signals corresponding to a plurality of corresponding second transistors are provided for the predetermined time in response to selection of the corresponding bit line by the decoder. A second signal generation circuit that sequentially activates at intervals.
The plurality of first transistors are turned on in response to the activation of the corresponding first control signals,
9. The semiconductor memory device according to claim 7, wherein the plurality of second transistors are turned on in response to the corresponding plurality of second control signals being set to the activation level. 10. The bit line driver is
A first constant current element for passing a constant current;
A second constant current element for flowing the constant current;
The switching circuit is
A first switching element connected between the power supply voltage line and the first node and conducting when writing the data signal of the first logic;
A second switching element connected between the power supply voltage line and the second node and conducting when writing the second logic data signal;
A third switching element connected in series with the first constant current element between the first node and the reference voltage line and conducting when writing a data signal of the second logic;
A fourth switching element connected in series with the first constant current element between the second node and the reference voltage line and conducting when writing the first logic data signal; A semiconductor memory device according to claim 7.

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