JP2012014098A - Thin film transistor array substrate, method for manufacturing the same, and display device - Google Patents

Abstract

A thin film transistor array substrate that can be manufactured by a simple process while preventing defects due to static electricity generated during the manufacturing process and that is suitable for inspection while maintaining thin film transistor characteristics.
A thin film transistor array substrate according to the present invention includes a short ring wiring that is electrically connected to at least one of a gate wiring and a source wiring through a resistor. The resistor 4 is formed of the same layer as the source line 2 and the short ring line 3, and includes a metal film 13 formed integrally with the short ring line 3 and a second semiconductor film 12 formed immediately below the metal film 13. And a stacked body of the first semiconductor films 11 formed immediately below. The shape of the resistor 4 in plan view is such that the width W2 of the second semiconductor film 12 and the metal film 13 is made smaller than the width W1 of the first semiconductor film 11 in at least a part of the region. The resistance value is adjusted according to the shape of the metal film 13.
[Selection] Figure 6

Description

  The present invention relates to a thin film transistor array substrate and a manufacturing method thereof. The present invention also relates to a display device on which the above-described thin film transistor array substrate is mounted.

  A matrix display device usually has a configuration in which an electro-optical element such as liquid crystal or EL (electroluminescence) is sandwiched between two opposing substrates. Display control is performed by selectively applying a voltage or current to the electro-optical element. At least one of the two substrates is an array substrate (hereinafter referred to as a “TFT array substrate”) having a thin film transistor (TFT) functioning as a switching element, and is used for giving a signal to the TFT. Source wiring and gate wiring are arranged in an array.

  Since the TFT array substrate uses an insulating substrate or the like, element destruction may occur due to static electricity generated during the manufacturing process. For example, a dielectric breakdown short circuit may occur due to static electricity generated between the source wiring and the gate wiring.

  In order to overcome this problem, a method of installing a low-resistance short ring wiring around the periphery of the TFT array substrate is known. The short ring wiring and the gate wiring are connected to each other through a low resistance body made of a metal such as chromium or aluminum. The same structure is used for the short ring wiring and the source wiring. Thereby, the source wiring and the gate wiring are set to the same potential through the short ring wiring.

  However, in this method, when performing an operation check after forming a wiring pattern, a switching element, etc. on the TFT array substrate, various inspections including a short-circuit inspection between the source wiring and the gate wiring are accurately performed. There was a problem that it was difficult to do. This is because the source wiring and the gate wiring are short-circuited via the short ring wiring to intentionally have the same potential.

  Therefore, as a technique for solving these problems, a method of connecting at least one of a short ring wiring and a gate wiring, or a short ring wiring and a source wiring through a resistor made of a semiconductor layer is disclosed (Patent Document 1).

JP 2006-163244 A

  As described above, the TFT array substrate is subjected to various inspections after manufacturing. Therefore, it is ideal that the resistance value of the resistor is a value suitable for various inspections. However, in Patent Document 1, it is difficult to adjust the resistance value of the resistor to a desired value while maintaining the TFT characteristics.

  The present invention has been made in view of the above-mentioned background, and the object of the present invention is to be able to be manufactured by a simple process while preventing defects due to static electricity generated during the manufacturing process, and to provide thin film transistor characteristics. A thin film transistor array substrate suitable for inspection after manufacturing while maintaining the above, and a manufacturing method thereof.

  The thin film transistor array substrate according to the present invention includes an insulating substrate, a plurality of gate wirings disposed on the insulating substrate, a first insulating film formed to cover the gate wiring, and the first insulating film. A plurality of source wirings arranged so as to intersect with the gate wiring, thin film transistors formed at intersections of the gate wiring and the source wiring, at least one of the gate wiring and the source wiring, And a short ring wiring that is electrically connected via a resistor provided corresponding to this. The resistor is made of the same layer as the source wiring and the short ring wiring, is formed integrally with the short ring wiring, and is formed immediately below the metal film. A stack of a second semiconductor film that is the same layer as the layer that functions as a film, and a first semiconductor film that is formed immediately below the second semiconductor film and that is the same layer as the active film of the thin film transistor The shape of the resistor in plan view is such that the width W2 of the second semiconductor film and the metal film is smaller than the width W1 of the first semiconductor film in at least a part of the region. Is set to a desired value by adjusting the shape of the metal film.

  A display device according to the present invention is a display device including a thin film transistor array substrate, and the thin film transistor array substrate of the above aspect is used as the thin film transistor array substrate.

  A method of manufacturing a thin film transistor array substrate according to the present invention includes a thin film transistor having a back channel etch structure, at least one of a source wiring and a gate wiring, and a short ring connected via a resistor provided corresponding thereto. A method of manufacturing a thin film transistor array substrate having wiring, wherein the thin film transistor has a gate electrode formed of a first conductive film, and a first semiconductor film and a second semiconductor film formed on the gate electrode via a first insulating film. Are formed in order, and a source electrode and a drain electrode are formed on the semiconductor layer so as to be opposed to at least part of the gate electrode by a second conductive film, and the short ring wiring Is formed of the second conductive film, and the resistor includes the first semiconductor film, the second semiconductor film, and the second conductive film. Each of the thin film transistors is formed in the same process as the thin film transistor so as to have a laminated structure, and the shape of the resistor in plan view is at least partially compared with the width W1 of the first semiconductor film. Thus, the width of the second semiconductor film and the metal film is reduced, and the shape of the metal film is adjusted so that the resistance value of the resistor becomes a desired value.

  According to the present invention, there is provided a thin film transistor array substrate that can be manufactured by a simple process while preventing defects caused by static electricity generated during the manufacturing process, and that is suitable for inspection while maintaining thin film transistor characteristics, and a method for manufacturing the same. It has an excellent effect that it can be provided.

FIG. 3 is a schematic plan view showing a part of the configuration of the TFT array substrate according to the first embodiment. FIG. 3 is a schematic plan view of a main part of a display area of the TFT array substrate according to the first embodiment. FIG. 3 is a schematic plan view of a main part around a gate terminal of the TFT array substrate according to the first embodiment. FIG. 3 is a schematic plan view of a main part around a source terminal of the TFT array substrate according to the first embodiment. FIG. 5 is a cross-sectional view taken along the line VV in FIG. 2. FIG. 6 is a sectional view taken along the line VI-VI in FIG. 3. FIG. 5 is a sectional view taken along the line VII-VII in FIG. 4. VIII-VIII cutting part sectional drawing of FIG. Sectional drawing of a manufacturing process in the position of the VV cutting part sectional view of FIG. Sectional drawing of a manufacturing process in the position of the VV cutting part sectional view of FIG. Sectional drawing of a manufacturing process in the position of the VV cutting part sectional view of FIG. Sectional drawing of a manufacturing process in the position of the VV cutting part sectional view of FIG. Sectional drawing of a manufacturing process in the position of the VV cutting part sectional view of FIG. Sectional drawing of a manufacturing process in the position of the VV cutting part sectional view of FIG. Manufacturing process sectional drawing in the position of VI-VI cutting part sectional drawing of FIG. Manufacturing process sectional drawing in the position of VI-VI cutting part sectional drawing of FIG. Manufacturing process sectional drawing in the position of VI-VI cutting part sectional drawing of FIG. Manufacturing process sectional drawing in the position of VI-VI cutting part sectional drawing of FIG. Manufacturing process sectional drawing in the position of VI-VI cutting part sectional drawing of FIG. Manufacturing process sectional drawing in the position of VI-VI cutting part sectional drawing of FIG. Manufacturing process sectional drawing in the position of the VII-VII cutting part sectional view of FIG. Manufacturing process sectional drawing in the position of the VII-VII cutting part sectional view of FIG. Manufacturing process sectional drawing in the position of the VII-VII cutting part sectional view of FIG. Manufacturing process sectional drawing in the position of the VII-VII cutting part sectional view of FIG. Manufacturing process sectional drawing in the position of the VII-VII cutting part sectional view of FIG. Manufacturing process sectional drawing in the position of the VII-VII cutting part sectional view of FIG. Manufacturing process sectional drawing in the position of the VIII-VIII cutting part sectional view of FIG. Manufacturing process sectional drawing in the position of the VIII-VIII cutting part sectional view of FIG. Manufacturing process sectional drawing in the position of the VIII-VIII cutting part sectional view of FIG. Manufacturing process sectional drawing in the position of the VIII-VIII cutting part sectional view of FIG. Manufacturing process sectional drawing in the position of the VIII-VIII cutting part sectional view of FIG. Manufacturing process sectional drawing in the position of the VIII-VIII cutting part sectional view of FIG. 3 is a schematic plan view showing an example of a resist pattern in the vicinity of a gate terminal according to Embodiment 1. FIG. FIG. 5 is a schematic cross-sectional view corresponding to the position of the VV cut line in FIG. 2 of the TFT array substrate according to the second embodiment. FIG. 4 is a schematic cross-sectional view corresponding to the position of the VI-VI cutting line in FIG. 3 of the TFT array substrate according to Embodiment 2. FIG. 5 is a schematic cross-sectional view corresponding to the position of the VII-VII cutting line in FIG. 4 of the TFT array substrate according to Embodiment 2. FIG. 5 is a schematic cross-sectional view corresponding to the position of the VIII-VIII cutting line in FIG. 3 of the TFT array substrate according to the second embodiment. FIG. 15 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 14. FIG. 15 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 14. FIG. 15 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 14. FIG. 15 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 14. FIG. 15 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 14. FIG. 15 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 14. FIG. 16 is a manufacturing process cross-sectional view at a position of a schematic cross-section in FIG. 15. FIG. 16 is a manufacturing process cross-sectional view at a position of a schematic cross-section in FIG. 15. FIG. 16 is a manufacturing process cross-sectional view at a position of a schematic cross-section in FIG. 15. FIG. 16 is a manufacturing process cross-sectional view at a position of a schematic cross-section in FIG. 15. FIG. 16 is a manufacturing process cross-sectional view at a position of a schematic cross-section in FIG. 15. FIG. 16 is a manufacturing process cross-sectional view at a position of a schematic cross-section in FIG. 15. FIG. 17 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 16. FIG. 17 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 16. FIG. 17 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 16. FIG. 17 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 16. FIG. 17 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 16. FIG. 18 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 17. FIG. 18 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 17. FIG. 18 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 17. FIG. 18 is a manufacturing process cross-sectional view at the position of the schematic cross-sectional view of FIG. 17. 3 is a schematic plan view showing an example of a resist pattern in the vicinity of a gate terminal according to Embodiment 1. FIG.

  Hereinafter, an example of an embodiment to which the present invention is applied will be described. The display device according to the present invention can be applied to display devices such as various flat panel displays such as liquid crystal display devices and organic EL display devices on which a thin film transistor array substrate (hereinafter referred to as “TFT array substrate”) is mounted. is there. In the following embodiments, a transmissive liquid crystal display device will be described as an example. It goes without saying that other embodiments may also belong to the category of the present invention as long as they match the gist of the present invention. Moreover, the size and ratio of each member in the following drawings are for convenience of explanation, and are different from actual ones.

[Embodiment 1]
FIG. 1 is a schematic partial enlarged plan view of the TFT array substrate according to the first embodiment. On a transparent insulating substrate (not shown), a plurality of gate wirings 1 extend in the horizontal direction in FIG. 1 and are arranged in parallel in the vertical direction. On the other hand, the source wiring 2 extends in the vertical direction in FIG. 1 and is arranged in parallel in the horizontal direction so as to intersect with the gate wiring 1 via a first insulating film (not shown). The plurality of gate wirings 1 and the plurality of source wirings 2 form a matrix so as to be substantially orthogonal, and a region surrounded by the adjacent gate wirings 1 and source wirings 2 is a pixel. Accordingly, the pixels are arranged in a matrix. A region where a plurality of pixels are formed is a display region 50. A region partitioned outside the display region 50 is a frame region 51.

  Each gate line 1 extends to the gate terminal 20 provided in the frame region 51. Similarly, each source wiring 2 extends to the source terminal 30 disposed in the frame region 51. The gate terminal 20 and the source terminal 30 are each electrically connected to the short ring wiring 3 through the resistor 4. Each gate line 1 and each source line 2 are electrically separated from each other by being cut along the line AA in FIG. 1 after being assembled as a display panel.

  FIG. 2 shows a partially enlarged plan view of a main part of the display area 50 of the TFT array substrate according to the first embodiment. FIG. 3 is a partial enlarged plan view of the main part around the gate terminal 20 in the frame region 51, and FIG. 4 is a partial enlarged plan view of the main part around the source terminal 30 in the frame region 51. 2 to 4, the insulating substrate, the first insulating film, the second insulating film, the alignment film, and the like are not shown for convenience of explanation.

  Between the adjacent gate lines 1, a storage capacitor line 7 is formed in parallel with the gate line 1 (see FIG. 2). The storage capacitor line 7 is disposed opposite to the pixel electrode 6 formed in the upper layer of the first insulating film (not shown), and forms a storage capacitor with the pixel electrode 6.

  The gate terminal 20 is connected to a wiring board (not shown) such as an IC chip (not shown) or an FPC (Flexible Printed Circuit) via a gate terminal pad 21. Similarly, the source terminal 30 is connected to a wiring board (not shown) via a source terminal pad 31.

  Various signals from the outside are supplied to a gate drive circuit (not shown) and a source drive circuit (not shown) via a wiring board (not shown). The gate driving circuit supplies a video gate signal (scanning signal) to the gate wiring 1 based on a control signal from the outside. The gate lines 1 are sequentially selected by this gate signal. The source drive circuit supplies a display signal (video signal) based on an external control signal and display data to the source wiring 2. As a result, a display voltage corresponding to the display data is supplied to each pixel.

  At least one signal transmission TFT 15 is provided near the intersection of the gate wiring 1 and the source wiring 2 of each pixel. The gate electrode (not shown) is connected to the gate line 1, and the source electrode 9 is connected to the source line 2. When a voltage is applied to the gate electrode, a current flows from the source line 2. Thereby, a display voltage is applied from the source line 2 to the pixel electrode 6 connected to the drain electrode 10.

  5 is a cross-sectional view taken along the line VV in FIG. 2, and FIG. 6 is a cross-sectional view taken along the line VI-VI in FIG. 7 is a cross-sectional view taken along the line VII-VII of FIG. 4, and FIG. 8 is a cross-sectional view taken along the line VIII-VIII of FIG. The VIII-VIII cutting line in FIG. 3 and the VIII-VIII cutting line in FIG. 4 have the same configuration. Therefore, FIG. 8 is also a sectional view taken along the line VIII-VIII in FIG.

  As shown in FIG. 5, the TFT 15 is an inverted stagger type and is manufactured by channel etching. On the insulating substrate 40 in the vicinity of the TFT 15, the pixel electrode 6, the storage capacitor wiring 7, the gate electrode 8, the source electrode 9, the drain electrode 10, the first semiconductor film 11, the second semiconductor film 12, the TFT 15, the first insulating film 41, a second insulating film 42, and the like are formed. The first semiconductor film 11 functions as a semiconductor active film, and the second semiconductor film functions as an ohmic low resistance film.

  In the vicinity of the gate terminal 20, as shown in FIG. 6, a short ring wiring 3, a resistor 4, a short ring connection wiring 5, a gate terminal 20, a gate terminal pad 21, a connection wiring pattern 22, on an insulating substrate 40, A first insulating film 41 and a second insulating film 42 are provided. The resistor 4 is composed of a stacked body of the first semiconductor film 11, the second semiconductor film 12, and the metal film 13. The resistor 4 is formed on the first insulating film 41. Similarly, the short ring wiring 3 and the short ring connection wiring 5 are formed on the first insulating film 41. Further, the metal film 13 of the resistor 4 is made of the second conductive film of the same layer as the short ring wiring 3 and the short ring connection wiring 5, and these are integrally formed. Therefore, the short ring wiring 3 and the short ring connection wiring 5 and the metal film 13 of the resistor 4 have a step structure.

  In the vicinity of the source terminal 30, as shown in FIG. 7, the short ring wiring 3, the resistor 4, the source terminal 30, the source terminal pad 31, the first insulating film 41, and the second insulating film 42 are formed on the insulating substrate 40. It is arranged. The resistor 4 is composed of a stacked body of the first semiconductor film 11, the second semiconductor film 12, and the metal film 13, similarly to the resistor 4 in the vicinity of the gate terminal 20. The resistor 4 is formed on the first insulating film 41. Similarly, the short ring wiring 3 and the source terminal 30 are also formed on the first insulating film 41. The metal film 13 of the resistor 4 is made of the second conductive film in the same layer as the short ring wiring 3 and the source terminal 30, and these are integrally formed. Accordingly, the short ring wiring 3 and the source terminal 30 and the metal film 13 of the resistor 4 have a step structure.

  In the vicinity where the resistor 4 is disposed, a first insulating film 41 and a second insulating film 42 are formed on the insulating substrate 40 in addition to the resistor 4 as shown in FIG. The width W2 of the second semiconductor film 12 and the metal film 13 constituting the resistor 4 in the vicinity of the gate terminal 20 is formed narrower than the width of the short ring wiring 3 and the short ring connection wiring 5 in plan view. (See FIGS. 3 and 8). In other words, the narrow portion connecting the short ring wiring 3 and the short ring connection wiring 5 and connecting them is the metal film 13 of the resistor 4.

  Similarly, the width W2 of the second semiconductor film 12 and the metal film 13 of the resistor 4 near the source terminal 30 is formed narrower than the wiring width of the short ring wiring 3 and the source terminal 30 (FIG. 4, FIG. 4). (See FIG. 8). In other words, the narrow portion connecting the short ring wiring 3 and the source terminal 30 and connecting them is the metal film 13 of the resistor 4.

  As shown in FIG. 8, the resistor 4 has a lateral width of the second semiconductor film 12 and the metal film 13 as compared with a width W1 of the first semiconductor film 11 in the lateral direction (X direction in FIG. 8). W2 is configured to be small.

  In the first embodiment, the width W1 is the same as the width of the short ring wiring 3, the gate terminal 20, and the source terminal 30. As a result, the pattern shape can be prevented from becoming complicated, and the yield can be improved. Note that the value of the width W1 can be arbitrarily set according to the purpose, and may be different from the widths of the short ring wiring 3, the gate terminal 20, and the source terminal 30.

  The resistance value of the resistor 4 is determined by the length L of the resistor 4 and the width W2 of the metal film 13. Therefore, the width W2 and the length L are determined according to the resistance value of the resistor 4 to be set. In other words, the resistance value of the resistor 4 according to the first embodiment can be set to a desired value by adjusting the shape of the metal film 13 (the width W2 and the length L in the first embodiment). . The resistance value of the resistor 4 can be appropriately set according to the purpose and the like. Considering the inspection of the gate wiring 1 and the source wiring 2 and the like, the resistance value of the resistor 4 is preferably about several tens kΩ to several hundred kΩ.

  The length L of the resistor 4, the width W 1 of the first semiconductor film 11, and the width W 2 of the second semiconductor film 12 and the metal film 13 can vary depending on the material used and the purpose. As long as it matches, it is not particularly limited. As a preferred example, for example, Cr is used as the material of the metal film 13, and the length L of the resistor 4 is 10 mm, the width W1 is 10 μm, and the width W2 is 0.5 μm.

  Note that the width W1 of the first semiconductor film 11 of the resistor 4 is set to a common width in the TFT array substrate 100 in the first embodiment, but is different between the gate wiring 1 and the source wiring 2. It may be set. In addition, each of the plurality of gate wirings 1 and / or the plurality of source wirings 2 can be set independently. The same applies to the width W2 of the second semiconductor film 12 and the metal film 13 of the resistor 4. Also, the length L of the resistor 4 is set to a common length in the TFT array substrate 100 in the first embodiment, but a plurality of gate lines 1 and / or a plurality of source lines 2 are used. Each can be set independently.

  In addition, the second semiconductor film 12 and the metal film 13 of the resistor 4 have been described as being narrowly provided at the substantially central portion of the first semiconductor film 11, but the present invention is not limited to the above-described position shape and the gist of the present invention Various modifications are possible without departing from the scope. Further, the example in which the width of the second semiconductor film 12 and the metal film 13 of the resistor 4 is set to W2 over the entire region of the resistor 4 has been described, but the width can be changed as appropriate. For example, the width of the both ends of the resistor 4 may be W1, and the non-end portions may be the width W2. However, in order to prevent the problem that the source wirings and the gate wirings are short-circuited due to the peeling of the metal film, the cutting region of the resistor 4 is preferably narrow. Moreover, although the example in which the second semiconductor film 12 and the metal film 13 of the resistor 4 have a narrow rectangular shape has been described, for example, a curved shape or a structure having a plurality of widths may be used.

  As the insulating substrate 40, a transparent substrate such as a glass substrate, a quartz substrate, or plastic is used. The gate electrode 8 is formed on the insulating substrate 40 and is formed of the same first conductive film as the gate wiring 1, the storage capacitor wiring 7, the gate terminal 20, and the like.

  The first insulating film 41 is formed in an upper layer so as to cover the gate electrode 8 and the like. The first semiconductor film 11 and the second semiconductor film 12 are formed on the first insulating film 41, and are disposed to face at least a part of the gate electrode 8 with the first insulating film 41 interposed therebetween.

  In the second semiconductor film 12, the first semiconductor film 11 is formed in the lower layer, and the source electrode 9 and the drain electrode 10 are formed in the upper layer in the TFT 15 region. The region of the semiconductor layer located below the source electrode 9 is the source region, and the region of the semiconductor layer located below the drain electrode 10 is the drain region. A region of the semiconductor layer in the TFT 15 region where the source electrode 9 and the drain electrode 10 are not formed becomes a channel region. In other words, the channel region is disposed in a region sandwiched between the source region and the drain region. In the channel region, the second semiconductor film 12 is removed by back channel etching.

  The source electrode 9 and the drain electrode 10 are arranged to face at least a part of the gate electrode 12 with the first insulating film 41, the first semiconductor film 11, and the second semiconductor film 12 interposed therebetween. That is, in order to operate as the TFT 15, the thin film transistor region exists on the gate electrode 8 and is easily affected by an electric field when a voltage is applied to the gate electrode 8.

  The second insulating film 42 is formed so as to cover the source electrode 9, the drain electrode 10, the first semiconductor film 11, and the first insulating film 41 (see FIG. 5). On the second insulating film 42, the pixel electrode 6 (see FIG. 5), the gate terminal pad 21, the connection wiring pattern 22 (see FIG. 6), the source terminal pad 31 (see FIG. 7), and the like are formed.

  The first contact hole CH <b> 1 is a through hole formed in the second insulating film 42 so as to connect the drain electrode 10 and the pixel electrode 6. The second contact hole CH2 is a through hole provided in the first insulating film 41 and the second insulating film 42 so as to connect the gate terminal 20 and the gate terminal pad 21. The third contact hole CH3 is a through hole provided in the first insulating film 41 and the second insulating film 42 so as to connect the gate terminal 20 and the connection wiring pattern 22. The fourth contact hole CH4 is a through hole provided in the second insulating film 42 so as to connect the short ring connection wiring 5 and the connection wiring pattern 22, and the fifth contact hole CH5 is the source terminal 30. And a through hole provided in the second insulating film 42 so as to connect the source terminal pad 31 and the source terminal pad 31. An alignment film (not shown) is formed on the inner surface of the TFT array substrate 100.

  The TFT array substrate 100 configured as described above is bonded to a counter substrate (not shown). The counter substrate is, for example, a color filter substrate, and is disposed on the viewing side. On the counter substrate, an insulating substrate, a light shielding film, a color filter for color display, a counter electrode, an alignment film, and the like are formed. The counter electrode may be arranged on the TFT array substrate 100 side.

  The TFT array substrate 100 and the counter substrate are bonded to each other through a certain gap (cell gap), and liquid crystal is sandwiched in this gap. In addition, a polarizing plate, a retardation plate, and the like are provided on the outer main surfaces of the TFT array substrate 100 and the counter substrate. A backlight unit or the like is disposed on the non-viewing side of the liquid crystal display panel. The liquid crystal display device according to the first embodiment has a schematic configuration as described above.

  Next, the operation of the liquid crystal display device according to the first embodiment will be described. The liquid crystal is driven by an electric field between the pixel electrode 6 and a counter electrode (not shown). When the alignment direction of the liquid crystal between the substrates changes, the polarization state of the light passing through the liquid crystal layer changes. The light that has been linearly polarized after passing through the polarizing plate changes its polarization state depending on the liquid crystal layer. And the light quantity which passes the polarizing plate by the side of a counter substrate changes with the polarization states. The alignment direction of the liquid crystal changes depending on the applied display voltage. Therefore, the amount of light passing through the viewing-side polarizing plate can be changed by controlling the display voltage. That is, a desired image can be displayed by changing the display voltage for each pixel.

  Next, an example of a manufacturing method of the TFT array substrate 100 will be described. 9A to 9F are manufacturing process cross-sectional views of FIG. 5, and FIGS. 10A to 10F are manufacturing process cross-sectional views of FIG. 11A to 11F are manufacturing process cross-sectional views of FIG. 7, and FIGS. 12A to 12F are manufacturing process cross-sectional views of FIG. In the first embodiment, an example in which five photolithography processes are performed will be described.

  First, a first conductive film is formed on the insulating substrate 40. Thereafter, a first photolithography process is performed to pattern the first conductive film. Thereby, the storage capacitor line 7 and the gate electrode 8 (see FIG. 9A), the gate terminal 20 (see FIG. 10A), and the gate line 1 (see FIG. 2) are formed.

The material of the first conductive film is not particularly limited, and preferable examples include Al, Mo having a low electrical resistance, or an alloy containing these as a main component. The first conductive film can be formed by a sputtering method or the like. As a preferable specific example, an Al film or the like is formed to a thickness of 200 nm on the insulating substrate 40 by sputtering using a known Ar gas, and then N ₂ gas is added to the known Ar gas. An AlN alloy to which nitrogen (N) atoms are added is formed to a thickness of 50 nm by a reactive sputtering method using a gas. Thereafter, a resist is formed on the first conductive film and patterned by the first photolithography process. Thereafter, an etching process is performed using a known etching solution containing phosphoric acid + nitric acid to remove the resist pattern. Thereby, the storage capacitor line 7, the gate electrode 8, the gate terminal 20, and the like are formed.

  Next, a first insulating film 41 is formed so as to cover the storage capacitor wiring 7, the gate electrode 8, the gate terminal 20, and the like. Further, the first semiconductor film 11 and the second semiconductor film 12 are formed in this order on the first insulating film 41. Thereafter, the first semiconductor film 11 and the second semiconductor film 12 are patterned into a predetermined continuous shape by a second photolithography process (see FIGS. 9B, 10B, 11B, and 12B). The first semiconductor film 11 and the second semiconductor film 12 are formed so as to form a pattern of a predetermined shape at least in a region where the semiconductor layer constituting the TFT 15 and the resistor 4 are formed.

Although the material and the film-forming method of the 1st insulating film 41, the 1st semiconductor film 11, and the 2nd semiconductor film 12 are not specifically limited, The following examples can be given as a suitable example. That is, as the first insulating film 41, a silicon nitride (SiN) film is formed to a thickness of 400 nm by a chemical vapor deposition (CVD) method. Next, an amorphous silicon film having a thickness of 150 nm is formed as the first semiconductor film 11. Further, an n ⁺ amorphous silicon film doped with phosphorus (P) is formed as the second semiconductor film 12 to a thickness of 30 nm. After these are formed, dry etching using a known fluorine-based gas is performed using a resist having a predetermined shape as a mask. A predetermined portion of the first semiconductor film 11 and the second semiconductor film 12 is etched by dry etching. Thereafter, the resist is removed.

  Next, a second conductive film 14 is formed so as to cover the patterned first semiconductor film 11 and second semiconductor film 12. Thereafter, resist patterns 61, 62, 63, and 64 are formed by a third photolithography process (see FIGS. 9C, 10C, 11C, and 12C).

  The resist pattern 61 formed around the TFT 15 is a pattern for forming the source electrode 9, the drain electrode 10, and the source wiring 2 (see FIG. 9C). In the resist pattern 61, an opening OP1 for forming a channel portion that becomes a semiconductor active layer of the TFT 15 is formed (see FIG. 9C). The opening OP1 has a complete extraction pattern.

  The resist pattern 62 formed around the gate terminal 20 is a pattern for forming the short ring wiring 3, the short ring connection wiring 5, and the metal film 13 by the second conductive film 14 (see FIG. 10C). Similarly, the resist pattern 63 formed around the source terminal 30 is a pattern for forming the short ring wiring 3, the metal film 13, and the source terminal 30 (see FIG. 11C).

  FIG. 13 shows a schematic plan view of the resist pattern 62. In FIG. 13, the resist pattern 62 is patterned with a thin center. This narrow pattern is a pattern for forming the second semiconductor film 12 and the metal film 13 of the resistor 4. The pattern of the resistor 4 portion of the resist pattern 63 is the same as that shown in FIG.

  Although the material of the 2nd electrically conductive film 14 is not specifically limited, As a preferable example, the alloy film which has Cr, Mo, or these as a main component is mentioned. By using these materials, the electrical specific resistance value can be lowered. In addition, good electrical contact characteristics with the second semiconductor film 12 are exhibited, and furthermore, good electrical contact characteristics with the pixel electrode 6 can be realized.

As a method for forming the second conductive film 14 and a pattern forming method, for example, a Cr film or the like is formed on the second semiconductor film 12 with a thickness of 300 nm by a known sputtering method using Ar gas. Next, a novolac resin-based positive resist is applied and formed by spin coating so that the film thickness of the maximum portion is about 1.6 μm. Thereafter, exposure is performed to form resist patterns 61 to 64. Thereafter, the second conductive film 14 is etched using a known etchant containing ceric ammonium nitrate + perchloric acid and resist patterns 61 to 64. Further, the second semiconductor film 12 and the upper layer portion of the first semiconductor film 11 are etched by a dry etching method using hydrochloric acid + sulfur hexafluoride (SF ₆ ) gas (see FIGS. 9D, 10D, and 12D). ).

  Thereafter, the resist patterns 61 to 64 are removed (see FIGS. 9E, 10E, 11E, and 12E). Thereby, the source electrode 9 and the drain electrode 10 are formed in the TFT 15 region. In the vicinity of the periphery of the gate terminal 20, a short ring wiring 3, a resistor 4, and a short ring connection wiring 5 are formed. Further, around the source terminal 30, the short ring wiring 3, the resistor 4, and the source terminal 30 are formed. The source wiring 2 and the like are also formed by this process. The short ring wiring 3 and the short ring connection wiring 5 are connected by a resistor 4 as shown in FIG. 10E. Further, as shown in FIG. 11E, the source terminal 30 and the short ring wiring 3 are connected by a resistor 4.

  Next, the second insulating film 42 is formed as a passivation film. Thereafter, the second insulating film 42 is patterned by a fourth photolithography process. In this step, a contact hole CH1 (see FIG. 9F) that penetrates to the drain electrode 10, contact holes CH2 and CH3 (see FIG. 10F) that penetrate to the gate terminal 20, and a contact hole CH4 that penetrates to the short ring connection wiring 5 (see FIG. 10F). 10F) and a contact hole CH5 (see FIG. 11F) penetrating to the source terminal 30 are formed simultaneously.

  Examples of suitable processes for the second insulating film 42 include the following examples. In other words, a silicon nitride film is formed to a thickness of 30 nm using a chemical vapor deposition (CVD) method, and a resist pattern having a predetermined shape is formed on the second insulating film 42. Thereafter, the second insulating film 42 is subjected to a dry etching method using a known fluorine-based gas, and the resist is removed.

  Next, a transparent conductive film is formed. Thereafter, a fifth photolithography process is performed to pattern the transparent conductive film. Thus, the pixel electrode 6 that is electrically connected to the lower drain electrode 10 through the contact hole CH1 is formed (see FIG. 5). Further, a gate terminal pad 21 electrically connected to the lower gate terminal 20 through the contact hole CH2 is formed (see FIG. 6).

  Further, a connection wiring pattern 22 is formed which is electrically connected to the lower gate terminal 20 through the contact hole CH3 and is also electrically connected to the lower short-ring connection wiring 5 through the contact hole CH4. (See FIG. 6). Further, a source terminal pad 31 that is electrically connected to the source terminal 30 in the lower layer through the contact hole CH5 is formed (see FIG. 7).

Although the material and process of a transparent conductive film are not specifically limited, The following examples are mentioned as a suitable example. That is, a suitable material is an ITO film in which indium oxide (In ₂ O ₃ ) and tin oxide (SnO ₂ ) are mixed. The transparent conductive film is formed, for example, by a sputtering method using a known Ar gas to a thickness of 100 nm, a resist having a predetermined pattern is formed on the transparent conductive film, and then a known hydrochloric acid + nitric acid is formed. The transparent conductive film is etched using an etchant containing Thereafter, by removing the resist, the pixel electrode 6, the gate terminal pad 21, and the connection wiring pattern 22 are obtained.

  Through the above steps and the like, the TFT array substrate 100 according to this embodiment is completed. With the above configuration, the gate line 1 and the short ring line 3 are electrically connected via the gate terminal 20, the connection wiring pattern 22, the short ring connection line 5, and the resistor 4. The source wiring 2 and the short ring wiring 3 are electrically connected via the source terminal 30 and the resistor 4.

  According to the TFT array substrate 100 according to the first embodiment, the gate wiring 1 and the short ring wiring 3 are connected via the resistor 4. Similarly, the source wiring 2 and the short ring wiring 3 are connected via a resistor 4. Therefore, it is possible to prevent the TFT array substrate from being defective due to static electricity generated during the manufacturing process.

  In Patent Document 1, since only the semiconductor film is used as the resistor, it is difficult to set the resistance value to a desired value. As a method of adjusting the resistance value, a method of siliciding the surface of the semiconductor film is also conceivable. However, since the silicide layer is also formed in the TFT in the substrate surface, when the semiconductor layer in the channel portion is etched, the silicide layer becomes an etching inhibition layer, which may cause a display defect due to an abnormal transistor characteristic. is there.

  On the other hand, the resistance value of the resistor 4 according to the first embodiment can be appropriately designed to a desired value by adjusting the length L of the resistor and the width W2 of the metal film 13. For this reason, it is possible to easily obtain a desired resistance value without complicating the structure. Since the resistance value necessary for each electrical inspection of the gate wiring 1 and the source wiring 2 can be adjusted to a desired value by adjusting the shape of the metal film, each electrical inspection can be performed with high accuracy.

  Moreover, since the structure of the resistor 4 is simple, it is possible to prevent erroneous determination in each electrical inspection of the TFT array substrate, which is caused by the complexity of the structure. Further, it is possible to secure a resistance value necessary for each electrical inspection related to the gate wiring and the source wiring. Therefore, the electrical inspection can be performed accurately.

  In the first embodiment, when the resistor 4 is cut, the metal film 13 is peeled off together with the lower first semiconductor film 11 and the second semiconductor film 12 so that the peeled metal film contacts the adjacent wiring. Can be prevented. Thereby, the trouble that the peeled metal film short-circuits the gate wirings 1 or the source wirings 2 can be effectively prevented. In addition, since the metal film 13 is narrowed, the exposed surface of the metal film 13 at the cut surface can be reduced. As a result, even if the metal film is peeled off, it is possible to make it difficult to come into contact with the adjacent wiring and to effectively suppress the occurrence of a short circuit by making the amount of the metal peeled small.

  Even if the metal film 13 of the resistor 4 is broken, the first semiconductor film 11 and the second semiconductor film 12 below can prevent element destruction due to static electricity. Furthermore, since the resistor 4 has a step structure, the coverage of the second insulating film 42 can be improved. For this reason, defects such as corrosion of the resistor 4 can be effectively prevented.

  The resistor 4 is composed of the first semiconductor film 11, the second semiconductor film, and the metal film 13, and can be formed in the same process as each film constituting the TFT 15. There is no need to add a new process for. Therefore, it is possible to provide a thin film transistor array substrate that can be manufactured by a simple process while preventing defects due to static electricity generated during the manufacturing process, and that is suitable for inspection while maintaining TFT characteristics.

[Embodiment 2]
Next, an example of a TFT array substrate different from the above embodiment will be described with reference to FIGS. In the following description, the same elements as those in the above embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  The basic structure of the TFT array substrate 100 according to the second embodiment is the same as that of the first embodiment except for the following points. That is, the metal film 13 constituting the resistor 4 according to the first embodiment, the short ring wiring 3 and the short ring connection wiring 5 are integrally formed by a step structure, but the resistance according to the second embodiment. The metal film, the short ring wiring, and the short ring connection wiring constituting the body 4 are different in that they are integrally formed without a step structure.

  In the first embodiment, the lower layer of the short ring wiring 3 and the short ring connection wiring 5 is the first insulating film 41, whereas in the second embodiment, the short ring wiring 3 and the short ring connection wiring. 5 is different in that a second semiconductor film and a first semiconductor film are disposed under the layer 5. In other words, in the second embodiment, the second semiconductor film and the first semiconductor film having the same shape in plan view are stacked below the second conductive film. In the second embodiment, the TFT array substrate is manufactured by four photolithography processes.

  FIG. 14 is a cross-sectional view corresponding to the position of the VV cutting line in FIG. 2 and FIG. 15 is a cross-sectional view corresponding to the position of the VI-VI cutting line in FIG. Show. 16 is a cross-sectional view corresponding to the position of the VII-VII cutting line in FIG. 4, and FIG. 17 is a cross-sectional view corresponding to the position of the VIII-VIII cutting line in FIG.

  The TFT 15a according to the second embodiment and the surrounding structure are of an inverted stagger type as in the first embodiment. Although the basic structure is the same, the second semiconductor film 12a and the first semiconductor film having the same shape in plan view are formed below the second conductive film 14 constituting the source electrode 9 and the drain electrode 10. 11a is provided in this order from the second conductive film 14 side. The channel etch structure is the same as that of the first embodiment.

  In the vicinity of the gate terminal 20, as shown in FIG. 15, the short ring wiring 3a, the resistor 4, the short ring connection wiring 5a, the first semiconductor film 11a, the second semiconductor film 12a, and the gate terminal 20 are formed on the insulating substrate 40. A gate terminal pad 21, a connection wiring pattern 22, a first insulating film 41 and a second insulating film 42 are provided.

  Unlike the first embodiment, the short ring wiring 3a is provided with the second semiconductor film 12a and the first semiconductor film 11a in the lower layer in this order from the short ring wiring 3a side. Similarly, for the short ring connection wiring 5a, the second semiconductor film 12a and the first semiconductor film 11a are disposed in this order from the short ring connection wiring 5a in the lower layer. That is, the metal film 13, the short ring wiring 3a, and the short ring connection wiring 5a of the resistor 4 are integrally formed without providing a step structure, and the first semiconductor layer 11a and the second semiconductor layer 12a are formed under these layers. It is arranged.

  In the vicinity of the source terminal 30, as shown in FIG. 16, the short ring wiring 3a, the resistor 4, the first semiconductor film 11a, the second semiconductor film 12a, the source terminal 30a, the source terminal pad 31, A first insulating film 41 and a second insulating film 42 are provided.

  Unlike the first embodiment, the short ring wiring 3a is provided with the second semiconductor film 12a and the first semiconductor film 11a in the lower layer in this order from the short ring wiring 3a side. Similarly for the source terminal 30a, the second semiconductor film 12a and the first semiconductor film 11a are disposed in this order from the source terminal 30a side in the lower layer. That is, the metal film 13, the short ring wiring 3a, and the source terminal 30a of the resistor 4 are integrally formed without providing a step structure, and the first semiconductor layer 11a and the second semiconductor layer 12a are disposed below these layers. Has been.

  The configuration of the resistor 4 is the same as that of the first embodiment. That is, the width W2 of the second semiconductor film 12a and the metal film 13 constituting the resistor 4 in the vicinity of the gate terminal 20 is formed narrower than the short ring wiring 3a and the short ring connection wiring 5a in plan view. . Similarly, the width W2 of the second semiconductor film 12a and the metal film 13 of the resistor 4 near the source terminal 30a is formed narrower than the wiring width of the short ring wiring 3a and the source terminal 30a. The width W1 of the first semiconductor film 11a of the resistor 4 is the same as that of the short ring wiring 3a, the short ring connection wiring 5a, the short ring wiring 3a, and the source terminal 30a. Note that the width W1 of the first semiconductor film 11a of the resistor 4 does not necessarily coincide with these, and can be set as appropriate.

  Next, an example of a manufacturing method of the TFT array substrate according to the second embodiment will be described. 18A to 18F are manufacturing process cross-sectional views of FIG. 14, and FIGS. 19A to 19F are manufacturing process cross-sectional views of FIG. 20A to 20E are manufacturing process cross-sectional views of FIG. 16, and FIGS. 21A to 21D are manufacturing process cross-sectional views of FIG.

  First, the gate electrode 8, the gate terminal 20, and the like are formed on the transparent insulating substrate 40 by the first photolithography process by the same method as in the first embodiment. Next, a first insulating film 41 is formed so as to cover the gate electrode 8, the storage capacitor line 7, and the gate terminal 20. Further, the first semiconductor film 11a, the second semiconductor film 12a which is an ohmic contact film doped with impurities, and the second conductive film 14 are formed in this order on the first insulating film 41.

  Thereafter, resist patterns 71 to 74 (first pattern) having a predetermined shape are formed on the second conductive film 14 by the second photolithography process (see FIGS. 18A, 19A, 20A, and 21A). . The resist pattern 71 formed around the TFT 15a is a pattern for forming the source electrode 9, the drain electrode 10, the first semiconductor film 11, the second semiconductor film, and the like. The resist pattern 71 has a step structure in order to form a channel portion that becomes a semiconductor active layer of the TFT 15a (see FIG. 18C). The thin film portion 75 of the resist pattern 71 is a region for forming a channel portion.

  The resist pattern 72 formed around the gate terminal 20 is a pattern for forming the short ring wiring 3a, the short ring connection wiring 5a, and the metal film 13 by the second conductive film 14 (see FIG. 19A). A thin film portion 76 for forming the second semiconductor film 12a and the metal film 13 of the resistor 4 is formed. Similarly, the resist pattern 73 formed around the source terminal 30a is a pattern for forming the short ring wiring 3a, the metal film 13, and the source terminal 30a (see FIG. 20C). In the resist pattern 73, a thin film portion 77 for forming the second semiconductor film 12a and the metal film 13 of the resistor 4 is formed.

  FIG. 22 shows a schematic plan view of the resist pattern 72 and the vicinity thereof. In FIG. 22, the resist pattern 72 has a stepped structure pattern in which both ends at the center of the resistor 4 have thin film portions 76. The thin film portion 76 is a region where the second semiconductor film 12a and the metal film 13 of the resistor 4 are removed to expose the first semiconductor film 11a. The pattern of the thin film portion 77 in the resistor 4 of the resist pattern 73 is the same as that in FIG.

Although the material and the film-forming method of the 1st insulating film 41, the 1st semiconductor film 11, and the 2nd semiconductor film 12 are not specifically limited, The following examples can be given as a suitable example. That is, as the first insulating film 41, a silicon nitride (SiN) film is formed to a thickness of 400 nm by a chemical vapor deposition (CVD) method. Next, an amorphous silicon film having a thickness of 150 nm is formed as the first semiconductor film 11. Further, an n ⁺ amorphous silicon film doped with phosphorus (P) is formed as the second semiconductor film 12 to a thickness of 30 nm. Next, a Cr film or the like is formed to a thickness of 300 nm as the second conductive film 42 on the second semiconductor film 12 by a sputtering method using a known Ar gas. Although the material of the 2nd electrically conductive film 14 is not specifically limited, As a preferable example, the material similar to the said Embodiment 1 is mentioned.

  Next, a novolac resin-based positive resist is applied and formed by spin coating so that the film thickness of the maximum portion is about 1.6 μm. Thereafter, in order to form resist patterns 71 to 74, exposure is performed using a gray tone mask. Here, the gray tone mask is a mask in which the transmission amount at the resist position where the thin film portions 75 to 77 are formed is 60%. The gray tone mask can reduce the amount of light transmitted in the wavelength region (usually 350 nm to 450 nm) used for exposure to the predetermined amount by utilizing the light diffraction phenomenon generated from the slit-shaped pattern.

  In the batch exposure using the gray tone mask, the transmission amounts at the mask positions corresponding to the thin film portions 75 to 77 can be arbitrarily set. It should be noted that this transmitted light amount need not be 60% as long as it is less than 100%. In place of the gray tone mask, the resist patterns 71 to 74 may be formed by collective exposure using a half tone mask.

  Next, the second conductive film 14 is etched using a known etchant containing ceric ammonia nitrate + perchloric acid. Further, the second semiconductor film 12a and the upper layer of the first semiconductor film 11a are etched by a dry etching method using hydrochloric acid + sulfur hexafluoride gas. Each etching process uses the resist patterns 71 to 74 as a mask. Each etching process forms a pattern of the first semiconductor film 11a and the second semiconductor film 12a (see FIGS. 18B and 19B).

  Next, the resist patterns 71 to 74 are ashed using oxygen plasma. Thereby, the resist of the thin film portions 75 to 77 is removed. That is, the resist pattern 81 having the opening OP2 (see FIG. 18C) is formed by ashing. Further, a resist pattern 82 having an opening OP3 (see FIG. 19C) in a portion corresponding to the side of the resistor 4, and a resist pattern 83 having an opening OP4 (see FIG. 20B) in a portion corresponding to the resistor 4 again. Form.

  Next, the second conductive film 14 exposed from the openings OP <b> 2 to OP <b> 4 of the resist patterns 81 to 84 (second pattern) is again formed using a known etchant containing ceric ammonia nitrate + perchloric acid. Etch. Subsequently, the second semiconductor film 12a and a part of the first semiconductor film 11a exposed from the openings OP2 to OP4 are etched by a dry etching method using hydrochloric acid + sulfur hexafluoride gas ( FIG. 18D, FIG. 19D, FIG. 20C, and FIG. 21B).

  Thereafter, the resist patterns 81 to 84 are removed (see FIGS. 18E, 19E, 20D, and 21C). Thereby, the source electrode 9 and the drain electrode 10 are formed around the TFT 15a. Also, around the gate terminal 20, a short ring wiring 3a and a short ring connection wiring 5a are formed. Further, the short ring wiring 3 and the source terminal 30 are formed around the source terminal 30.

    Next, the second insulating film 42 is formed as a passivation film. Thereafter, the second insulating film 42 is patterned by a third photolithography process to form contact holes CH1 to CH5 (see FIGS. 18F, 19F, and 20E).

  Next, a transparent conductive film is formed. Thereafter, a fourth photolithography process is performed to pattern the transparent conductive film. Thereby, the pixel electrode 6, the gate terminal pad 21, the source terminal pad 31, and the like are formed. A suitable specific example is the same as that of the first embodiment.

  Through the above process and the like, the thin film transistor substrate according to the second embodiment is completed.

  According to the TFT array substrate according to the second embodiment, since the resistor 4 is provided, the same effect as in the first embodiment can be obtained. Furthermore, a TFT array substrate having the same effect as in the first embodiment can be manufactured by a process in which the number of resist masks is one less than that in the first embodiment. As a result, the manufacturing process can be simplified more effectively. In addition, since the second conductive film 14a is not provided with a step structure, it is possible to effectively suppress the disconnection of the second conductive film 14a itself.

DESCRIPTION OF SYMBOLS 1 Gate wiring 2 Source wiring 3 Short ring wiring 4 Resistor 5 Short ring connection wiring 6 Pixel electrode 7 Retention capacity wiring 8 Gate electrode 9 Source electrode 10 Drain electrode 11 1st semiconductor film 12 2nd semiconductor film 13 Metal film 14 2nd Conductive film 15 TFT (Thin Film Transistor)
20 Gate Terminal 21 Gate Terminal Pad 22 Connection Wiring Pattern 30 Source Terminal 31 Source Terminal Pad 40 Insulating Substrate 41 First Insulating Film 42 Second Insulating Film 50 Display Area 51 Frame Areas 61-64, 61-66, 71-74 81-84 Resist pattern 75-77 Thin film part CH1-CH5 Contact hole OP1-OP4 Opening part 100 TFT array substrate

Claims (8)

An insulating substrate;
A plurality of gate wirings disposed on the insulating substrate;
A first insulating film formed to cover the gate wiring;
A plurality of source lines arranged to intersect the gate lines via the first insulating film;
A thin film transistor formed at an intersection of the gate wiring and the source wiring;
Comprising at least one of the gate wiring and the source wiring, and a short ring wiring electrically connected via a resistor provided corresponding to the gate wiring and the source wiring;
The resistor is made of the same layer as the source wiring and the short ring wiring, is formed integrally with the short ring wiring, and is formed immediately below the metal film. A stack of a second semiconductor film that is the same layer as the layer that functions as a film, and a first semiconductor film that is formed immediately below the second semiconductor film and that is the same layer as the active film of the thin film transistor ,
The shape of the resistor in plan view is such that the width W2 of the second semiconductor film and the metal film is smaller than the width W1 of the first semiconductor film in at least a part of the region,
A thin film transistor array substrate that sets a resistance value of the resistor to a desired value by adjusting a shape of the metal film.   2. The thin film transistor array substrate according to claim 1, wherein each of the gate wiring and the source wiring is connected to the short ring wiring.   3. The thin film transistor according to claim 1, wherein the second semiconductor film and the metal film of the resistor are formed in a central portion of the resistor in the width direction of the first semiconductor film. Array substrate.   The said short ring wiring is formed on the said 1st insulating film, The metal film of the said resistor, and a level | step difference structure are formed, The Claim 1 characterized by the above-mentioned. Thin film transistor array substrate.   The short ring wiring is formed on a stacked body of the first semiconductor film and the second semiconductor film, and is integrally formed at substantially the same height as the metal film of the resistor. The thin film transistor array substrate according to any one of claims 1 to 3. A display device comprising a thin film transistor array substrate,
A display device using the thin film transistor array substrate according to claim 1 as the thin film transistor array substrate. A thin film transistor having a back channel etch structure;
A method of manufacturing a thin film transistor array substrate comprising a short ring wiring connected to at least one of a source wiring and a gate wiring via a resistor provided corresponding thereto,
In the thin film transistor, a gate electrode is formed of a first conductive film, a semiconductor layer in which a first semiconductor film and a second semiconductor film are sequentially formed on the gate electrode with a first insulating film interposed therebetween, and the semiconductor layer A source electrode and a drain electrode are formed of a second conductive film so as to be opposed to at least a part of the gate electrode,
The short ring wiring is formed by the second conductive film,
The resistor is formed in the same process as the thin film transistor so as to have a stacked structure of the first semiconductor film, the second semiconductor film, and the second conductive film, and in plan view of the resistor The width of the second semiconductor film and the metal film is made smaller than the width W1 of the first semiconductor film in at least a partial region, and the resistance value of the resistor is desired. A method of manufacturing a thin film transistor array substrate, wherein the shape of the metal film is adjusted so that the value of The first semiconductor film, the second semiconductor film, and the second conductive film are continuously formed, and a first pattern of a resist film having a step structure is formed thereon,
Forming a pattern of the first semiconductor film, the second semiconductor film, and the second conductive film using the first pattern;
Next, the thin portion of the first pattern is removed to form a second pattern,
8. The method of manufacturing a thin film transistor array substrate according to claim 7, wherein a pattern of the second conductive film and the second semiconductor film is formed using the second pattern.

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