JP2012010246A

JP2012010246A - High frequency switch circuit

Info

Publication number: JP2012010246A
Application number: JP2010146186A
Authority: JP
Inventors: Masami Nagaoka; 正見長岡
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 2010-06-28
Filing date: 2010-06-28
Publication date: 2012-01-12

Abstract

【課題】通過損失が少なく出力特性が良いＳＯＩ基板上の高周波スイッチ回路を提供する。
【解決手段】本発明の実施形態の高周波スイッチ回路は、シリコン基板２０上に形成された酸化膜２１上に、第１の端子１と、入出力端子２と、第１の電極４ｂが前記第１の端子１に電気的に接続され、第２の電極４ｃが前記入出力端子２に接続されたＦＥＴ４とを備える。第１の層間絶縁膜２２が前記ＦＥＴを周囲から離間分離し前記酸化膜２１に達する溝に埋め込まれて配置され、前記酸化膜２１と接続され、前記ＦＥＴ４を周囲から絶縁する。導電体層１０が、前記溝内の前記第１の層間絶縁膜２２上に形成され、接地端子ＧＮＤに接続される。第２の層間絶縁膜２３が、前記導電体層１０上及び前記ＦＥＴ４上に形成される。直流電圧を供給する配線層７が、前記溝内の第１の層間絶縁膜２２上且つ前記導電体層１０上に前記第２の層間絶縁膜２３を介して形成されている。
【選択図】図２A high-frequency switch circuit on an SOI substrate with low passage loss and good output characteristics is provided.
In a high-frequency switch circuit according to an embodiment of the present invention, a first terminal, an input / output terminal, and a first electrode are arranged on an oxide film formed on a silicon substrate. The FET 4 is electrically connected to the first terminal 1 and the second electrode 4 c is connected to the input / output terminal 2. A first interlayer insulating film 22 is disposed so as to be separated from the periphery of the FET and embedded in a groove reaching the oxide film 21, and is connected to the oxide film 21 to insulate the FET 4 from the periphery. A conductor layer 10 is formed on the first interlayer insulating film 22 in the trench and connected to the ground terminal GND. A second interlayer insulating film 23 is formed on the conductor layer 10 and the FET 4. A wiring layer 7 for supplying a DC voltage is formed on the first interlayer insulating film 22 in the trench and on the conductor layer 10 via the second interlayer insulating film 23.
[Selection] Figure 2

Description

本発明の実施形態は、高周波スイッチ回路に関する。 Embodiments described herein relate generally to a high-frequency switch circuit.

携帯電話等の高周波移動体通信機では、アンテナと送信回路及び受信回路などの間で、アンテナから受信回路へ、または送信回路からアンテナへ信号を切り替えるために、高周波スイッチ回路が用いられる。この高周波スイッチ回路には、小型化、高集積化、及び低消費電力化が求められる。近年では、ＳＯＩ（Silicon on Insulator）基板上にシリコンのＭＯＳＦＥＴ（Metal Oxide Field Effect Transistor）を用いて高周波スイッチ回路が形成されている。特に高抵抗シリコン基板を備えたＳＯＩ基板は、ＭＯＳＦＥＴの寄生容量を低減するので、スイッチ回路の、低コスト化、高集積化、高機能化を実現できる。 In a high-frequency mobile communication device such as a cellular phone, a high-frequency switch circuit is used to switch a signal from an antenna to a reception circuit or from a transmission circuit to an antenna between an antenna and a transmission circuit and a reception circuit. This high-frequency switch circuit is required to be small in size, highly integrated, and low in power consumption. In recent years, a high-frequency switch circuit is formed on a SOI (Silicon on Insulator) substrate using a silicon MOSFET (Metal Oxide Field Effect Transistor). In particular, an SOI substrate including a high-resistance silicon substrate reduces the parasitic capacitance of the MOSFET, so that the switch circuit can be reduced in cost, highly integrated, and highly functional.

ＳＯＩ基板のシリコン酸化膜とシリコン基板の界面近傍には、シリコンの未結合手に起因する正の固定電荷が存在する。この固定電荷などに起因して、上記界面近傍のシリコン基板内に自由電子が誘起される。ＳＯＩ基板上に形成されたスイッチ回路の配線に高周波信号が印加されると、この自由電子は高周波信号に対応して複雑な挙動を示す。これが原因で、ＳＯＩ基板上のスイッチ回路の出力特性において、通過損失やクロストークが増大したり、高調波歪みや相互変調歪みなどが発生したりしていた。 In the vicinity of the interface between the silicon oxide film of the SOI substrate and the silicon substrate, positive fixed charges due to silicon dangling bonds exist. Due to this fixed charge and the like, free electrons are induced in the silicon substrate near the interface. When a high frequency signal is applied to the wiring of the switch circuit formed on the SOI substrate, the free electrons exhibit a complicated behavior corresponding to the high frequency signal. Due to this, in the output characteristics of the switch circuit on the SOI substrate, passage loss and crosstalk increase, and harmonic distortion and intermodulation distortion occur.

特開２００８−２２７０８４号公報JP 2008-227084 A

通過損失が少なく出力特性が良好なＳＯＩ基板上の高周波スイッチ回路を提供する。 Provided is a high-frequency switch circuit on an SOI substrate with low output loss and good output characteristics.

本発明の実施形態の高周波スイッチ回路は、シリコン基板上に形成された酸化膜上に、第１の端子と、第１の電極が前記第１の端子に電気的に接続され、前記第１の電極と第２の電極との間を流れる電流を制御するＦＥＴと、前記第２の電極に電気的に接続された入出力端子を備える。第１の層間絶縁膜が前記ＦＥＴを周囲から離間分離し前記酸化膜に達する溝に埋め込まれて配置され、前記酸化膜と接続され、前記ＦＥＴを周囲から絶縁する。導電体層が、前記溝内の前記第１の層間絶縁膜上に形成され、接地端子に接続される。第２の層間絶縁膜が、前記導電体層上及び前記ＦＥＴ上に形成される。直流電圧を供給する配線層が、前記溝内の第１の層間絶縁膜上且つ前記導電体層上に前記第２の層間絶縁膜を介して形成されている。 In the high-frequency switch circuit according to the embodiment of the present invention, a first terminal and a first electrode are electrically connected to the first terminal on an oxide film formed on a silicon substrate, and the first terminal An FET for controlling a current flowing between the electrode and the second electrode, and an input / output terminal electrically connected to the second electrode are provided. A first interlayer insulating film is disposed so as to be separated from the periphery of the FET and embedded in a groove reaching the oxide film, and is connected to the oxide film to insulate the FET from the periphery. A conductor layer is formed on the first interlayer insulating film in the trench and connected to a ground terminal. A second interlayer insulating film is formed on the conductor layer and the FET. A wiring layer for supplying a DC voltage is formed on the first interlayer insulating film in the trench and on the conductor layer via the second interlayer insulating film.

第１の実施形態に係る高周波スイッチ回路の回路図。The circuit diagram of the high frequency switch circuit concerning a 1st embodiment. 第１の実施形態に係る高周波スイッチ回路の要部断面図。FIG. 3 is a cross-sectional view of a main part of the high frequency switch circuit according to the first embodiment. 第１の実施形態に係る変形例の高周波スイッチ回路の要部断面図。The principal part sectional view of the high frequency switch circuit of the modification concerning a 1st embodiment. 比較例の高周波スイッチ回路の回路図。The circuit diagram of the high frequency switch circuit of a comparative example. 比較例の高周波スイッチ回路の要部断面図。Sectional drawing of the principal part of the high frequency switch circuit of a comparative example. 第２の実施形態に係る高周波スイッチ回路の回路図。The circuit diagram of the high frequency switch circuit concerning a 2nd embodiment. 第２の実施形態に係る高周波スイッチ回路の要部断面図。Sectional drawing of the principal part of the high frequency switch circuit which concerns on 2nd Embodiment.

以下、本発明の実施形態について図を参照しながら説明する。実施例中の説明で使用する図は、説明を容易にするための模式的なものであり、図中の各要素の形状、寸法、大小関係などは、実際の実施においては必ずしも図に示されたとおりとは限らず、本発明の効果が得られる範囲内で適宜変更可能である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings used in the description in the embodiments are schematic for ease of description, and the shape, size, magnitude relationship, etc. of each element in the drawings are not necessarily shown in the drawings in actual implementation. The present invention is not limited to the above, and can be appropriately changed within a range in which the effect of the present invention can be obtained.

アンテナと送受信回路の間に設けられる高周波スイッチ回路には、例えば、１つのアンテナ端子と２つの入出力端子からなるＳＰＤＴ（Single Pole Double Throw）、２つのアンテナ端子と２つの入出力端子からなるＤＰＤＴ（Double Pole Double Throw）、１つのアンテナ端子と多数の入出力端子からなるＳＰｎＴ（Single Pole n Throw）、または２つのアンテナ端子と多数の入出力端子からなるＤＰｎＴ（Double Pole n Throw）などがある。以下に説明する発明の各実施の形態では、説明を簡単にするためにＳＰＤＴの高周波スイッチ回路を例に説明するが、他の態様のスイッチ回路においても、入出力端子の数が違うだけなので、同様に本発明を実施することが可能である。また、スイッチ素子がｎチャネルのＭＯＳＦＥＴの場合で説明するが、ｐチャネルのＭＯＳＦＥＴや、ＨＥＭＴなどの他のＦＥＴを用いることも可能である。 The high frequency switch circuit provided between the antenna and the transmission / reception circuit includes, for example, SPDT (Single Pole Double Throw) composed of one antenna terminal and two input / output terminals, and DPDT composed of two antenna terminals and two input / output terminals. (Double Pole Double Throw) There is SPnT (Single Pole n Throw) consisting of one antenna terminal and many input / output terminals, or DPnT (Double Pole n Throw) consisting of two antenna terminals and many input / output terminals. . In the embodiments of the invention described below, the high-frequency switch circuit of SPDT will be described as an example in order to simplify the description. However, since the number of input / output terminals is also different in other types of switch circuits, It is possible to carry out the present invention as well. Although the case where the switching element is an n-channel MOSFET will be described, a p-channel MOSFET or another FET such as a HEMT can also be used.

（第１の実施形態）
図１及び図２を用いて、第１の実施形態に係る高周波スイッチ回路を説明する。図１は、第１の実施形態に係る高周波スイッチ回路の回路図である。
図２は、第１の実施形態に係る高周波スイッチ回路の要部断面図である。図１に示したように、第１の実施形態に係る高周波回路１００は、アンテナと高周波信号の送受信をするためのアンテナ端子１（第１の端子）と、例えば送信回路と接続する第１の入出力端子２と、例えば受信回路と接続する入第２の入出力端子３と、を備える。 (First embodiment)
The high frequency switch circuit according to the first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a circuit diagram of a high-frequency switch circuit according to the first embodiment.
FIG. 2 is a cross-sectional view of a main part of the high-frequency switch circuit according to the first embodiment. As shown in FIG. 1, the high-frequency circuit 100 according to the first embodiment includes a first terminal connected to an antenna terminal 1 (first terminal) for transmitting and receiving a high-frequency signal to and from an antenna, for example, a transmission circuit. An input / output terminal 2 and an input / output second input / output terminal 3 connected to a receiving circuit, for example, are provided.

アンテナ端子１と第１の第１の入出力端子２との間は、以下のように構成される。ｎチャネルの第１のＭＯＳＦＥＴ４は、第１の電極４ｂ、第２の電極４ｃ及びゲート電極４ａを有し、第１の電極４ｂと第２の電極４ｃの間に流れる電流は、ゲート電極４ａで調節される。ｎチャネルの第１のＭＯＳＦＥＴ４の第１の電極４ｂが、第１の高周波線路Ｈ１を介してアンテナ端子１に接続され、第２の電極４ｃが第２の高周波線路Ｈ２を介して第１入出力端子２に接続される。第１のＭＯＳＦＥＴ４は、アンテナ端子１と第１の入出力端子２とのオン／オフを行う第１のスイッチである。第１のゲートバイアス抵抗６の一端が第１のＭＯＳＦＥＴ４のゲート電極４ａに接続され、その他端は第１の制御配線層７の一端に接続されている。第１の制御配線層７の他端は、第１のゲート制御抵抗８を介してゲート制御回路１８へ接続されている。第１のゲートバイアス抵抗６は、第１の高周波線路Ｈ１から第１のＭＯＳＦＥＴ４のゲート電極４ａを介して第１の制御配線層７に漏洩してくる高周波信号を減衰させるためのもので、高周波信号の振幅がゲート制御回路１８へ影響のない大きさとなるように抵抗値が設計される。第１のソース・ドレインバイアス抵抗５が、第１のＭＯＳＦＥＴ４の第１の電極４ｂと第２の電極４ｃの間に並列に接続されている。第１のソース・ドレインバイアス抵抗５は、第１のＭＯＳＦＥＴ４のオン抵抗に対して十分高い値であり、第１のＭＯＳＦＥＴ４がオフの時に、第１の高周波線路Ｈ１から第２の高周波線路Ｈ２への高周波信号を十分に遮断し、且つ第１の電極４ｂと第２の電極４ｃの電位を同電位に保つ。第１の導電体層１０の一端が、第１の抵抗９を介して第１のＭＯＳＦＥＴ４の第２の電極４ｃに接続され、その他端が接地端子ＧＮＤに接続されている。第１の抵抗９は、第２の高周波線路Ｈ２から第１の導電体層１０への高周波信号を遮断するのに十分に抵抗が高く、かつ第１のＭＯＳＦＥＴ４の第２の電極４ｃを接地端子ＧＮＤと同電位にし０Ｖに保つ。接地端子ＧＮＤは、外部から０Ｖの電位を与えられるか、接地されている。 A configuration between the antenna terminal 1 and the first first input / output terminal 2 is as follows. The n-channel first MOSFET 4 includes a first electrode 4b, a second electrode 4c, and a gate electrode 4a. A current flowing between the first electrode 4b and the second electrode 4c is generated at the gate electrode 4a. Adjusted. The first electrode 4b of the n-channel first MOSFET 4 is connected to the antenna terminal 1 via the first high-frequency line H1, and the second electrode 4c is connected to the first input / output via the second high-frequency line H2. Connected to terminal 2. The first MOSFET 4 is a first switch that turns on / off the antenna terminal 1 and the first input / output terminal 2. One end of the first gate bias resistor 6 is connected to the gate electrode 4 a of the first MOSFET 4, and the other end is connected to one end of the first control wiring layer 7. The other end of the first control wiring layer 7 is connected to the gate control circuit 18 via the first gate control resistor 8. The first gate bias resistor 6 is for attenuating a high-frequency signal leaking from the first high-frequency line H1 to the first control wiring layer 7 via the gate electrode 4a of the first MOSFET 4, The resistance value is designed so that the amplitude of the signal does not affect the gate control circuit 18. A first source / drain bias resistor 5 is connected in parallel between the first electrode 4 b and the second electrode 4 c of the first MOSFET 4. The first source / drain bias resistor 5 has a sufficiently high value with respect to the on-resistance of the first MOSFET 4, and when the first MOSFET 4 is off, the first high-frequency line H1 to the second high-frequency line H2. Are sufficiently blocked, and the potentials of the first electrode 4b and the second electrode 4c are kept at the same potential. One end of the first conductor layer 10 is connected to the second electrode 4c of the first MOSFET 4 via the first resistor 9, and the other end is connected to the ground terminal GND. The first resistor 9 is sufficiently high in resistance to cut off a high-frequency signal from the second high-frequency line H2 to the first conductor layer 10, and the second electrode 4c of the first MOSFET 4 is connected to the ground terminal. The same potential as GND is maintained at 0V. The ground terminal GND is given a potential of 0 V from the outside or is grounded.

アンテナ端子１と第２の入出力端子３との間は、上記同様に、以下のように構成される。ｎチャネルの第２のＭＯＳＦＥＴ１１は、第１の電極１１ｂ、第２の電極１１ｃ及びゲート電極１１ａを有し、第１の電極１１ｂと第２の電極１１ｃの間に流れる電流は、ゲート電極１１ａで調節される。ｎチャネルの第２のＭＯＳＦＥＴ１１の第１の電極１１ｂが、第１の高周波線路Ｈ１を介してアンテナ端子１に接続され、第２の電極１１ｃが第３の高周波線路Ｈ３を介して第２入出力端子３に接続される。第２のＭＯＳＦＥＴ１１は、アンテナ端子１と第２の入出力端子３とのオン／オフを行う第２のスイッチである。第２のゲートバイアス抵抗１３の一端が第２のＭＯＳＦＥＴ１１のゲート電極１１ａに接続され、その他端は第２の制御配線層１４の一端に接続されている。第２の制御配線層１４の他端は、第２のゲート制御抵抗１５を介してゲート制御回路１８へ接続されている。第２のゲートバイアス抵抗１３は、高周波線路Ｈ１から第２のＭＯＳＦＥＴ１１のゲート電極１１ａを介して第２の制御配線層１４に漏洩してくる高周波信号を減衰させるためのもので、高周波信号の振幅がゲート制御回路１８へ影響のない大きさとなるように抵抗値が設計される。第２のソース・ドレインバイアス抵抗１２が、第２のＭＯＳＦＥＴ１１の第１の電極１１ｂと第２の電極１１ｃの間に並列に接続されている。第２のソース・ドレインバイアス抵抗１２は、第２のＭＯＳＦＥＴのオン抵抗に対して十分高い値であり、第２のＭＯＳＦＥＴがオフの時に、第１の高周波線路Ｈ１から第３の高周波線路Ｈ３への高周波信号を十分に遮断し、且つ第１の電極１１ｂと第２の電極１１ｃの電位を同電位に保つ。第２の導電体層１７の一端が、第２の抵抗１６を介して第２のＭＯＳＦＥＴ１１の第２の電極１１ｃに接続され、その他端が接地端子ＧＮＤに接続されている。第２の抵抗１６は第１の高周波線路Ｈ１から第２の導電体層１７への高周波信号を遮断するのに十分に抵抗が高く、かつ第２のＭＯＳＦＥＴ１１の第２の電極１１ｃを接地端子ＧＮＤと同電位にし０Ｖに保つ。 Similarly to the above, the antenna terminal 1 and the second input / output terminal 3 are configured as follows. The n-channel second MOSFET 11 includes a first electrode 11b, a second electrode 11c, and a gate electrode 11a, and a current flowing between the first electrode 11b and the second electrode 11c is generated at the gate electrode 11a. Adjusted. The first electrode 11b of the n-channel second MOSFET 11 is connected to the antenna terminal 1 via the first high-frequency line H1, and the second electrode 11c is connected to the second input / output via the third high-frequency line H3. Connected to terminal 3. The second MOSFET 11 is a second switch that turns on / off the antenna terminal 1 and the second input / output terminal 3. One end of the second gate bias resistor 13 is connected to the gate electrode 11 a of the second MOSFET 11, and the other end is connected to one end of the second control wiring layer 14. The other end of the second control wiring layer 14 is connected to the gate control circuit 18 via the second gate control resistor 15. The second gate bias resistor 13 is for attenuating a high-frequency signal leaking from the high-frequency line H1 to the second control wiring layer 14 via the gate electrode 11a of the second MOSFET 11, and the amplitude of the high-frequency signal. The resistance value is designed to have a size that does not affect the gate control circuit 18. A second source / drain bias resistor 12 is connected in parallel between the first electrode 11 b and the second electrode 11 c of the second MOSFET 11. The second source / drain bias resistor 12 has a sufficiently high value with respect to the on-resistance of the second MOSFET, and when the second MOSFET is off, the first high-frequency line H1 to the third high-frequency line H3. Are sufficiently blocked, and the potentials of the first electrode 11b and the second electrode 11c are kept at the same potential. One end of the second conductor layer 17 is connected to the second electrode 11c of the second MOSFET 11 via the second resistor 16, and the other end is connected to the ground terminal GND. The second resistor 16 is sufficiently high in resistance to block a high-frequency signal from the first high-frequency line H1 to the second conductor layer 17, and the second electrode 11c of the second MOSFET 11 is connected to the ground terminal GND. To the same potential as the above.

図１に示した本実施形態に係る高周波スイッチ回路１００をＳＯＩ（Silicon On Insulator）基板上に作成した一例の要部断面を図２に示す。シリコン基板２０と埋込シリコン酸化膜（以後略して埋込酸化膜）２１とシリコン層とからなるＳＯＩ基板のシリコン層中に、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１とが周知の半導体プロセスにより形成されている。第１のＭＯＳＦＥＴ４は、ｎ形シリコン層からなるソース層とドレイン層（以後両者のそれぞれを指すものとして、ソース・ドレイン層２４と略して表記）及びその上にそれぞれオーミック接合された第１の電極４ｂと第２の電極４ｃとを備える。第２のＭＯＳＦＥＴ１１も同様に、ｎ形シリコン層からなるソース層とドレイン層（以後両者のそれぞれを指すものとして、ソース・ドレイン層２５と略して表記）及びその上にそれぞれオーミック接合された第１の電極１１ｂと第２の電極１１ｃとを備える。図２は、ＳＯＩ基板上に形成された第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１が素子分離されている領域の断面を示しており、第１のＭＯＳＦＥＴ４及び第２のＭＯＳＦＥＴ１１の詳細な構造は省略する。ここで、第１の電極及び第２の電極材料としては、導電体であればよいが、一例として、コバルト・シリサイドなどの金属シリサイドを用いることができる。 FIG. 2 shows a cross-sectional view of an essential part of an example in which the high-frequency switch circuit 100 according to the present embodiment shown in FIG. 1 is formed on an SOI (Silicon On Insulator) substrate. A first MOSFET 4 and a second MOSFET 11 are formed by a well-known semiconductor process in a silicon layer of an SOI substrate including a silicon substrate 20, a buried silicon oxide film (hereinafter abbreviated as a buried oxide film) 21, and a silicon layer. Has been. The first MOSFET 4 includes a source layer and a drain layer made of an n-type silicon layer (hereinafter abbreviated as a source / drain layer 24), and a first electrode ohmic-contacted thereon. 4b and a second electrode 4c. Similarly, the second MOSFET 11 includes a source layer and a drain layer (hereinafter, abbreviated as a source / drain layer 25, respectively) made of an n-type silicon layer, and a first ohmic junction formed thereon. Electrode 11b and second electrode 11c. FIG. 2 shows a cross section of a region where the first MOSFET 4 and the second MOSFET 11 formed on the SOI substrate are separated from each other, and detailed structures of the first MOSFET 4 and the second MOSFET 11 are omitted. . Here, the first electrode and the second electrode material may be any conductor, but as an example, metal silicide such as cobalt silicide can be used.

第１のＭＯＳＦＥＴ４のソース・ドレイン層２４が、ＳＯＩ基板の埋込酸化膜２１上に形成されている。第１の電極４ｂと第２の電極４ｃが、ソース層とドレイン層上にそれぞれオーミック接合されて形成されている（ソース層とドレイン層のどちらが第１の電極かは不問）。チャネル層が、ソース層とドレイン層の間に形成され、ゲート電極４ａが、チャネル層上にゲート絶縁膜を介して形成されている。チャネル層を介して第１の電極４ｂと第２の電極４ｃの間を流れる電流をゲート電極４ａが制御する、第１のＭＯＳＦＥＴ４（詳細は図示せず）が埋込酸化膜２１上に形成されている。 The source / drain layer 24 of the first MOSFET 4 is formed on the buried oxide film 21 of the SOI substrate. The first electrode 4b and the second electrode 4c are formed in ohmic contact with the source layer and the drain layer, respectively (whether the source layer or the drain layer is the first electrode). A channel layer is formed between the source layer and the drain layer, and the gate electrode 4a is formed on the channel layer via a gate insulating film. A first MOSFET 4 (not shown in detail) is formed on the buried oxide film 21 and the gate electrode 4a controls the current flowing between the first electrode 4b and the second electrode 4c via the channel layer. ing.

第２のＭＯＳＦＥＴは、第１のＭＯＳＦＥＴと同じ構成である。第２のＭＯＳＦＥＴ１１のソース・ドレイン層２５が、ＳＯＩ基板の埋込酸化膜２１上に形成されている。第１の電極１１ｂと第２の電極１１ｃが、ソース層とドレイン層上にそれぞれオーミック接合されて形成されている（ソース層とドレイン層のどちらが第１の電極かは不問）。チャネル層が、ソース層とドレイン層の間に形成され、ゲート電極１１ａが、チャネル層上にゲート絶縁膜を介して形成されている。チャネル層を介して第１の電極１１ｂと第２の電極１１ｃの間を流れる電流をゲート電極１１ａが制御する、第２のＭＯＳＦＥＴ１１（詳細は図示せず）が埋込酸化膜２１上に形成されている。なお、説明を簡単にするために、図２には、第１のＭＯＳＦＥＴ４及び第２のＭＯＳＦＥＴ１１の一部だけを示し、詳細な構造は省略した。 The second MOSFET has the same configuration as the first MOSFET. The source / drain layer 25 of the second MOSFET 11 is formed on the buried oxide film 21 of the SOI substrate. The first electrode 11b and the second electrode 11c are formed on the source layer and the drain layer by ohmic junction, respectively (whether the source layer or the drain layer is the first electrode). A channel layer is formed between the source layer and the drain layer, and a gate electrode 11a is formed on the channel layer via a gate insulating film. A second MOSFET 11 (not shown in detail) whose gate electrode 11a controls the current flowing between the first electrode 11b and the second electrode 11c through the channel layer is formed on the buried oxide film 21. ing. In order to simplify the description, only a part of the first MOSFET 4 and the second MOSFET 11 is shown in FIG. 2, and the detailed structure is omitted.

第１のＭＯＳＦＥＴ４と第２のＭＳＦＥＴ１１は、第１のＭＯＳＦＥＴ４のソース・ドレイン層２４と第２のＭＯＳＦＥＴ１１のソース・ドレイン層２５の間に設けられた埋込酸化膜まで達する溝により、離間分離されている。また、この溝は、図示しないが、それぞれのＭＯＳＦＥＴを個別に環状に取り囲んで、それぞれのＭＯＳＦＥＴを周囲から離間分離している。この溝の中に第１の層間絶縁膜を埋め込むことで素子分離領域が形成され、この素子分離領域が、第１のＭＯＳＦＥＴと第２のＭＯＳＦＥＴを互いに絶縁分離している。また、それぞれのＭＯＳＦＥＴを周囲から絶縁分離している。図２の断面では、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１との間に両者を分離する溝が１つしか形成されていないが、第１のＭＯＳＦＥＴ４用の溝と第２のＭＯＳＦＥＴ１１用の溝がそれぞれ形成されても良い。すなわち、素子分離領域は、埋込酸化膜２１と接続し、第１のＭＯＳＦＥＴ４を囲む環状の第１の層間絶縁膜と、第２のＭＯＳＦＥＴ１１を囲む環状の第１の層間絶縁膜を含み、この両者の環状の第１の層間絶縁膜が、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１の間に離間配置されていても良い。 The first MOSFET 4 and the second MSFET 11 are separated and separated by a groove reaching a buried oxide film provided between the source / drain layer 24 of the first MOSFET 4 and the source / drain layer 25 of the second MOSFET 11. ing. Although not shown, this groove surrounds each MOSFET individually in a ring shape, and separates and separates each MOSFET from the surroundings. An element isolation region is formed by embedding the first interlayer insulating film in the groove, and the element isolation region insulates and isolates the first MOSFET and the second MOSFET from each other. In addition, each MOSFET is isolated from the surroundings. In the cross section of FIG. 2, only one groove is formed between the first MOSFET 4 and the second MOSFET 11 to separate them, but the groove for the first MOSFET 4 and the groove for the second MOSFET 11 are formed. Each may be formed. That is, the element isolation region includes an annular first interlayer insulating film that is connected to the buried oxide film 21 and surrounds the first MOSFET 4, and an annular first interlayer insulating film that surrounds the second MOSFET 11. Both of the annular first interlayer insulating films may be spaced from each other between the first MOSFET 4 and the second MOSFET 11.

第１の層間絶縁膜は、絶縁体であればよく、例えばシリコン酸化膜、シリコン窒化膜、アルミナ或いはこれらの積層構造などを用いることができる。この第１の層間絶縁膜２２は、この溝を完全に埋め尽くし、第１のＭＯＳＦＥＴ及び第２のＭＯＳＦＥＴ１１の、第１の電極４ｂ、１１ｂ及び第２の電極４ｃ、１１ｃの上面を覆うように形成されている。言い換えれば、第１のＭＯＳＦＥＴ４のソース層またはドレイン層と第２のＭＯＳＦＥＴ１１のソース層またはドレイン層との間に設けられ（以後第１のＭＯＳＦＥＴと第２のＭＯＳＦＥＴとの間に設けられと略記）、埋込酸化膜２１まで達する第１の層間絶縁膜により、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１は互いに絶縁分離されている。 The first interlayer insulating film may be an insulator, and for example, a silicon oxide film, a silicon nitride film, alumina, or a stacked structure thereof can be used. The first interlayer insulating film 22 completely fills the trench and covers the upper surfaces of the first electrodes 4b and 11b and the second electrodes 4c and 11c of the first MOSFET and the second MOSFET 11. Is formed. In other words, it is provided between the source layer or drain layer of the first MOSFET 4 and the source layer or drain layer of the second MOSFET 11 (hereinafter abbreviated as being provided between the first MOSFET and the second MOSFET). The first MOSFET 4 and the second MOSFET 11 are insulated and separated from each other by the first interlayer insulating film reaching the buried oxide film 21.

第１の層間絶縁膜２２は、上記溝の中に埋め込まれて第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１とを絶縁分離できていれば、或いはそれぞれのＭＯＳＦＥＴを個別に周囲から絶縁分離できていれば、その上端が第１のＭＯＳＦＥＴ４及び第２のＭＯＳＦＥＴ１１の、第１の電極４ｂ、１１ｂ及び第２の電極４ｃ、１１ｃの上面より上にくるまで厚く形成される必要はない。その後に形成される層間絶縁膜でこれらを覆えばよい。しかしながら、層間絶縁膜を形成する工程が増えて好ましくないので、本実施形態の説明では、説明を容易にするために、第１の層間絶縁膜２２を上記の構成とした。 If the first interlayer insulating film 22 is buried in the groove and the first MOSFET 4 and the second MOSFET 11 can be insulated and separated, or each MOSFET can be individually insulated from the surroundings. The upper ends of the first MOSFET 4 and the second MOSFET 11 need not be thicker than the upper surfaces of the first electrodes 4b and 11b and the second electrodes 4c and 11c. These may be covered with an interlayer insulating film formed thereafter. However, since the number of steps for forming the interlayer insulating film is not preferable, in the description of the present embodiment, the first interlayer insulating film 22 is configured as described above in order to facilitate the description.

図１に示した前述の第１の導電体層１０が、第１のＭＯＳＦＥＴと第２のＭＯＳＦＥＴの間に設けられた第１の層間絶縁膜の上に形成されている。第１の導電体層１０は、図示しないが、一端でＳＯＩ基板上に形成された第１の抵抗９を介して第１のＭＯＳＦＥＴ４の第２の電極４ｃと接続され、他端で接地端子ＧＮＤと接続されている。図１に示した前述の第２の導電体層１７に対しても同様である。 The above-described first conductor layer 10 shown in FIG. 1 is formed on a first interlayer insulating film provided between the first MOSFET and the second MOSFET. Although not shown, the first conductor layer 10 is connected at one end to the second electrode 4c of the first MOSFET 4 via the first resistor 9 formed on the SOI substrate, and at the other end to the ground terminal GND. Connected with. The same applies to the second conductor layer 17 shown in FIG.

図２の図示しない領域で、第２の導電体層１７が、第１のＭＯＳＦＥＴと第２のＭＯＳＦＥＴの間に設けられた第１の層間絶縁膜の上に形成されている。第２の導電体層１７は、一端でＳＯＩ基板上に形成された第２の抵抗１６を介して第２のＭＯＳＦＥＴ１１の第２の電極１１ｃと接続され、他端で接地端子ＧＮＤと接続されている。 In a region not shown in FIG. 2, the second conductor layer 17 is formed on the first interlayer insulating film provided between the first MOSFET and the second MOSFET. The second conductor layer 17 is connected to the second electrode 11c of the second MOSFET 11 via a second resistor 16 formed on the SOI substrate at one end, and connected to the ground terminal GND at the other end. Yes.

或いは、第１の導電体層１０と第２の導電体層１７は、図２に示したように第１のＭＯＳＦＥＴと第２のＭＯＳＦＥＴの間に設けられた第１の層間絶縁膜の上に両者が一体化されて形成されていてもよい。 Alternatively, the first conductor layer 10 and the second conductor layer 17 are formed on the first interlayer insulating film provided between the first MOSFET and the second MOSFET as shown in FIG. Both may be formed integrally.

或いはまた、図１に示した回路において、第１の導電体層１０と第２の導電体層１７のどちらかを除いて、第１の抵抗９と第２の抵抗１６のどちらかが直接接地端子に接続されてもよい。この場合、第１の導電体層１０と第２の導電体層１７の残された方が、第１のＭＯＳＦＥＴと第２のＭＯＳＦＥＴの間に設けられた第１の層間絶縁膜の上に形成されていればよい。 Alternatively, in the circuit shown in FIG. 1, one of the first resistor 9 and the second resistor 16 is directly grounded, except for either the first conductor layer 10 or the second conductor layer 17. It may be connected to a terminal. In this case, the remaining one of the first conductor layer 10 and the second conductor layer 17 is formed on the first interlayer insulating film provided between the first MOSFET and the second MOSFET. It only has to be done.

さらに、図示しないが、第１の導電体層１０と第２の導電体層１７は、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１との間に設けられた第１の層間絶縁膜上に限られることはなく、それぞれのＭＯＳＦＥＴを囲んでいる溝内に形成された第１の層間絶縁膜上であればどの場所にも形成されてもよい。 Further, although not shown, the first conductor layer 10 and the second conductor layer 17 are limited to the first interlayer insulating film provided between the first MOSFET 4 and the second MOSFET 11. Rather, it may be formed anywhere as long as it is on the first interlayer insulating film formed in the trench surrounding each MOSFET.

以後は、説明を簡単にするために、第１の導電体層１０が、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１の間に設けられた第１の層間絶縁膜２２の上に形成されている場合に対して説明をする。上記第１と第２のＭＯＳＦＥＴをそれぞれ取り囲んで周囲から個別に離間分離し埋込酸化膜２１まで達する溝内に形成された第１の層間絶縁膜上であれば、両者のＭＯＳＦＥＴに挟まれた部分以外の場所に上記第１の導電体層１０が形成された場合でも、同様なので説明は省略する。また、第２の導電体層１７に対して、及び第１の導電体層１０と第２の導電体層１７とを一体化した場合に対しても、第１の導電体層に対する説明と同じなので省略する。 Hereinafter, in order to simplify the description, the first conductor layer 10 is formed on the first interlayer insulating film 22 provided between the first MOSFET 4 and the second MOSFET 11. Will be explained. The first and second MOSFETs are sandwiched between both MOSFETs so long as they are on the first interlayer insulating film formed in the trench that reaches the buried oxide film 21 by being separated and separated from the surroundings individually. Even when the first conductor layer 10 is formed in a place other than the portion, the description is omitted because it is the same. In addition, the description for the first conductor layer is the same for the second conductor layer 17 and for the case where the first conductor layer 10 and the second conductor layer 17 are integrated. So it is omitted.

第１及び第２の導電体層は、ともに導電体であればよいが、一例としては銅やアルミニウムなどの通常の回路配線に用いられる金属材料でよい。また、ポリシリコンなどの半導体材料やそのシリサイドでも可能である。 The first and second conductor layers may both be conductors, but as an example, may be a metal material used for normal circuit wiring such as copper or aluminum. It is also possible to use a semiconductor material such as polysilicon or its silicide.

第１の導電体層１０は、第１のＭＯＳＦＥＴと第２のＭＯＳＦＥＴの間の溝内に設けられた第１の層間絶縁膜に沿って延伸し、水平面内で延伸方向と垂直な方向で、第１の導電体層１０の幅は、上記溝内に設けられた第１の層間絶縁膜の幅より大きく、第１の層間絶縁膜を覆って、その両側で第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１のソース・ドレイン層２４及び２５上に重なっている。第１の導電体層１０を覆って、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１の第１の電極４ｂ、１１ｂ上及び第２の電極４ｃ、１１ｃ上に、第２の層間絶縁膜２３が形成されている。第１のＭＯＳＦＥＴ４及び第２のＭＯＳＦＥＴ１１の第１の電極４ｂ、１１ｂ及び第２の電極４ｃ、１１ｃは、第１の層間絶縁膜２２と第２の層間絶縁膜２３に設けられた開口部より、それぞれ、外部に引き出される。第２の層間絶縁膜は、第１の層間絶縁膜同様に、例えばシリコン酸化膜、シリコン窒化膜、アルミナ或いはこれらの積層構造などを用いることができる。第１の層間絶縁膜と第２の層間絶縁膜は、同じ材料で形成されていても良い。また、説明の便宜上、第１の層間絶縁膜と第２の層間絶縁膜とに分離して説明していたが、両者が一体形成されていてもよい。 The first conductor layer 10 extends along the first interlayer insulating film provided in the groove between the first MOSFET and the second MOSFET, and in a direction perpendicular to the extending direction in the horizontal plane, The width of the first conductor layer 10 is larger than the width of the first interlayer insulating film provided in the trench, covers the first interlayer insulating film, and the first MOSFET 4 and the second MOSFET on both sides thereof. It overlaps with the source / drain layers 24 and 25 of the MOSFET 11. A second interlayer insulating film 23 is formed on the first electrodes 4 b and 11 b and the second electrodes 4 c and 11 c of the first MOSFET 4 and the second MOSFET 11 so as to cover the first conductor layer 10. ing. The first electrodes 4b and 11b and the second electrodes 4c and 11c of the first MOSFET 4 and the second MOSFET 11 are formed through openings provided in the first interlayer insulating film 22 and the second interlayer insulating film 23, respectively. Each is pulled out. As the second interlayer insulating film, for example, a silicon oxide film, a silicon nitride film, alumina, or a stacked structure thereof can be used as in the first interlayer insulating film. The first interlayer insulating film and the second interlayer insulating film may be formed of the same material. For convenience of explanation, the first interlayer insulating film and the second interlayer insulating film have been described separately, but both may be formed integrally.

第１の制御配線層７が、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１の間にあり埋込酸化膜まで達して両者を分離する溝内に設けられた第１の層間絶縁膜２２上、且つ上記第１の導電体層１０上に、第２の層間絶縁膜を介して形成されている。第１の制御配線層７は、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１の間の溝内に設けられた第１の層間絶縁膜２２に沿って第１の導電体層１０とともに同一方向に延伸し、一端は図示しない第１のゲートバイアス抵抗６を介して図示しない第１のＭＯＳＦＥＴ４のゲート電極４ａに接続されている。他の一端は、図示しないゲート制御回路１８に図示しない第１のゲート制御抵抗８を介して接続されている。第１の制御配線層７は、水平面内でその延伸方向と垂直方向では、第１の導電体層１０よりも幅が狭く、上から見たときに第１の導電体層１０の領域内に完全に包含される。更に好ましくは、第１の制御配線層７は、水平面内でその延伸方向と垂直方向では、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１の間の溝内に設けられた第１の層間絶縁膜よりも幅が狭く、上から見たときにその溝内に完全に包含される。前述したように、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１の間以外でも、埋込酸化膜まで達して第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ用ＦＥＴ１１のそれぞれを個別に取り囲んで周囲から両者をそれぞれ分離する溝内に設けられた第１の層間絶縁膜２２上に、第１の導電体層１０が形成されていれば、上記のように、その上に第１の制御配線層を形成してもよい。 The first control wiring layer 7 is located between the first MOSFET 4 and the second MOSFET 11 on the first interlayer insulating film 22 provided in the trench that reaches the buried oxide film and separates them, and the above It is formed on the first conductor layer 10 via a second interlayer insulating film. The first control wiring layer 7 extends in the same direction along with the first conductor layer 10 along the first interlayer insulating film 22 provided in the groove between the first MOSFET 4 and the second MOSFET 11. One end is connected to a gate electrode 4a of a first MOSFET 4 (not shown) via a first gate bias resistor 6 (not shown). The other end is connected to a gate control circuit 18 (not shown) via a first gate control resistor 8 (not shown). The first control wiring layer 7 is narrower in width than the first conductor layer 10 in the direction perpendicular to the extending direction in the horizontal plane, and is within the region of the first conductor layer 10 when viewed from above. Completely included. More preferably, the first control wiring layer 7 is higher than the first interlayer insulating film provided in the groove between the first MOSFET 4 and the second MOSFET 11 in the direction perpendicular to the extending direction in the horizontal plane. It is narrow and completely contained within the groove when viewed from above. As described above, other than between the first MOSFET 4 and the second MOSFET 11, the buried oxide film is reached and each of the first MOSFET 4 and the second MOSFET FET 11 is individually surrounded and separated from the surroundings. If the first conductor layer 10 is formed on the first interlayer insulating film 22 provided in the trench to be formed, the first control wiring layer may be formed thereon as described above. Good.

第２の制御配線層１４に関しても、図示しない領域で第１の制御配線層７と同様に第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１の間にあり埋込酸化膜まで達して両者を分離する溝内に設けられた第１の層間絶縁膜２２上、且つ上記第１の導電体層１０（第１の導電体層１０同様に上記溝内に設けられた第１の層間絶縁膜２２上に形成されていれば、第２の導電体層１７であってもよい）上に、第２の層間絶縁膜２３を介して形成されていてもよい。或いは、図３に示したように、第１の制御配線層７と第２の制御配線層１４とが離間分離して、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１の間の溝内に設けられた第１の層間絶縁膜２２に沿って同一方向に延伸し、それぞれ、上記のように、上記溝内に設けられた第１の層間絶縁膜２２上且つ上記第１の導電体層１０上に、第２の層間絶縁膜２３を介して形成されていてもよい。この場合は、第１の制御配線層７の幅と第２の制御配線層１４の幅との和は、水平面内でその延伸方向と垂直方向では、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１の間の溝内に設けられた第１の層間絶縁膜の幅より狭い。上から見たときに、第１の制御配線層７と第２の制御配線層１４とは、その溝内に完全に包含されて水平方向に配列される。さらに、前述したように、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１の間以外でも、埋込酸化膜まで達して第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ用ＦＥＴ１１のそれぞれを個別に取り囲んで周囲から両者をそれぞれ分離する溝内に設けられた第１の層間絶縁膜２２上に、第１の導電体操１０或いは第２の導電体層１７が形成されていれば、上記の第１の制御配線層７の場合と同じように、その上に第２の制御配線層を形成してもよい。 Similarly to the first control wiring layer 7 in the region not shown, the second control wiring layer 14 is located between the first MOSFET 4 and the second MOSFET 11 and reaches the buried oxide film to separate the two. Formed on the first interlayer insulating film 22 and the first conductor layer 10 (the first interlayer insulating film 22 provided in the groove in the same manner as the first conductor layer 10). If it is, it may be the second conductor layer 17), and may be formed via the second interlayer insulating film 23. Alternatively, as shown in FIG. 3, the first control wiring layer 7 and the second control wiring layer 14 are separated and separated and provided in the groove between the first MOSFET 4 and the second MOSFET 11. Extending in the same direction along the first interlayer insulating film 22, as described above, on the first interlayer insulating film 22 provided in the trench and on the first conductor layer 10, respectively. It may be formed via the second interlayer insulating film 23. In this case, the sum of the width of the first control wiring layer 7 and the width of the second control wiring layer 14 is between the first MOSFET 4 and the second MOSFET 11 in the horizontal direction and in the direction perpendicular to the extending direction. Narrower than the width of the first interlayer insulating film provided in the trench. When viewed from above, the first control wiring layer 7 and the second control wiring layer 14 are completely contained in the groove and arranged in the horizontal direction. In addition, as described above, other than between the first MOSFET 4 and the second MOSFET 11, the buried oxide film is reached and each of the first MOSFET 4 and the second MOSFET FET 11 is individually surrounded to surround both from the surroundings. If the first conductor operation 10 or the second conductor layer 17 is formed on the first interlayer insulating film 22 provided in the trenches to be separated from each other, the first control wiring layer 7 of the first control wiring layer 7 is formed. As in the case, the second control wiring layer may be formed thereon.

以上、図２を用いて本発明の第１の実施の形態のＳＯＩ基板上に形成した高周波スイッチ回路１００の要部断面構造を説明した。次にこの実施形態に係る高周波スイッチ回路１００の動作について説明する。 As described above, the cross-sectional structure of the main part of the high-frequency switch circuit 100 formed on the SOI substrate according to the first embodiment of the present invention has been described with reference to FIG. Next, the operation of the high-frequency switch circuit 100 according to this embodiment will be described.

アンテナ端子１と第１の入出力端子２を接続する場合には、第１のＭＯＳＦＥＴ４のゲート電極４ａに２〜３．５Ｖ程度の電圧（以下ゲートオン電圧と称す）を加えて、第１のＭＯＳＦＥＴ４をオンさせる。両者の端子間を切断する場合は、第１のＭＯＳＦＥＴ４のゲート電極４ａに０Ｖの電圧を加えて第１のＭＯＳＦＥＴ４をオフさせる。アンテナ端子１と第２の入出力端子３との接続／切断においても同様である。第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１をオン状態に維持する間は、ゲート制御回路から直流のゲートオン電圧が、それぞれのゲート電極４ａと１１ａに、それぞれ第１の制御配線層７及び第２の制御配線層１４を介して印加されつづける。通常は、複数の入出力端子がアンテナ端子に同時に接続されることはないので、それぞれの入出力端子とアンテナ端子の間のＭＯＳＦＥＴは、いずれか１つがオン状態を維持している。例えば、アンテナ端子１と第１の入出力端子２とが接続している場合について以後説明する。本実施形態の効果を説明するために、比較例を用いて説明する。 When the antenna terminal 1 and the first input / output terminal 2 are connected, a voltage of about 2 to 3.5 V (hereinafter referred to as a gate-on voltage) is applied to the gate electrode 4a of the first MOSFET 4 so that the first MOSFET 4 Turn on. When cutting between the terminals of both, a voltage of 0 V is applied to the gate electrode 4a of the first MOSFET 4 to turn off the first MOSFET 4. The same applies to the connection / disconnection between the antenna terminal 1 and the second input / output terminal 3. While the first MOSFET 4 and the second MOSFET 11 are maintained in the on state, a direct gate on voltage is applied from the gate control circuit to the gate electrodes 4a and 11a, respectively. It is continuously applied via the wiring layer 14. Usually, since a plurality of input / output terminals are not simultaneously connected to the antenna terminal, any one of the MOSFETs between the input / output terminals and the antenna terminal is kept on. For example, a case where the antenna terminal 1 and the first input / output terminal 2 are connected will be described below. In order to explain the effect of this embodiment, a description will be given using a comparative example.

図４は、本発明の比較例の高周波スイッチ回路２００の回路図であり、図５は、本発明の比較例のＳＯＩ基板上に作成した高周波スイッチ回路２００の要部断面図である。比較例の高周波スイッチ回路２００は、本実施形態の第１の導電体層１０及び第２の導電体層１７を備えていない点で、本実施形態に係る高周波スイッチ回路１００と相異する。それ以外は、全て本実施形態に係る高周波スイッチ回路１００と同じ構成である。ただし、比較例では、説明を簡単にするために、本実施形態の第１の層間絶縁膜２２と第２の層間絶縁膜２３を併せて第１の層間絶縁膜２２と表記した。 FIG. 4 is a circuit diagram of a high-frequency switch circuit 200 of a comparative example of the present invention, and FIG. 5 is a cross-sectional view of a main part of the high-frequency switch circuit 200 created on the SOI substrate of the comparative example of the present invention. The high-frequency switch circuit 200 of the comparative example is different from the high-frequency switch circuit 100 according to the present embodiment in that the first conductive layer 10 and the second conductive layer 17 of the present embodiment are not provided. The rest of the configuration is the same as that of the high-frequency switch circuit 100 according to this embodiment. However, in the comparative example, in order to simplify the description, the first interlayer insulating film 22 and the second interlayer insulating film 23 of the present embodiment are collectively referred to as the first interlayer insulating film 22.

従って、図５に示すように、比較例の高周波スイッチ回路２００では、一端で第１の抵抗９を介して第１のＭＯＳＦＥＴ４の第２の電極４ｃと接続し他端で接地端子ＧＮＤに接続した第１の導電体層１０が、第１のＭＯＳＦＥＴと第２のＭＯＳＦＥＴの間にあり埋込酸化膜まで達して両者を分離する溝内に設けられた第１の層間絶縁膜２２上に形成されていない。このため、第１の制御配線層７は、ＳＯＩ基板のシリコン基板２０と埋込酸化膜２１の界面の直上で、第１の層間絶縁膜２２だけを介して配置されている。 Therefore, as shown in FIG. 5, in the high-frequency switch circuit 200 of the comparative example, one end is connected to the second electrode 4c of the first MOSFET 4 via the first resistor 9, and the other end is connected to the ground terminal GND. A first conductor layer 10 is formed on a first interlayer insulating film 22 provided in a trench which is between the first MOSFET and the second MOSFET and reaches the buried oxide film and separates both. Not. For this reason, the first control wiring layer 7 is disposed just above the interface between the silicon substrate 20 of the SOI substrate and the buried oxide film 21 with only the first interlayer insulating film 22 interposed therebetween.

ＳＯＩ基板では、埋込酸化膜２１とシリコン基板との界面で、埋込酸化膜中には未結合手による固定電荷が存在する。この固定電荷に引き寄せられて、界面のシリコン基板側には自由な電子がキャリア層を形成している。比較例の高周波スイッチ回路２００は、この自由電子のキャリア層の上に、第１の層間絶縁膜２２だけを介して第１の制御配線層７を備える。ここでアンテナ端子１から第１の高周波線路Ｈ１を伝搬した高周波信号は、第１のＭＯＳＦＥＴ４及び第２のＭＯＳＦＥＴ１１のそれぞれのゲート電極４ａ及び１１ａを介して、第１の制御配線層７と第２の制御配線層１４に少量ながら漏洩する。以後第１の制御配線層７を例にこの影響を説明する。第２の制御配線層に関してもこの影響は同様である。 In the SOI substrate, fixed charges due to dangling bonds exist in the buried oxide film at the interface between the buried oxide film 21 and the silicon substrate. Attracted by this fixed charge, free electrons form a carrier layer on the silicon substrate side of the interface. The high-frequency switch circuit 200 of the comparative example includes the first control wiring layer 7 on the free electron carrier layer only through the first interlayer insulating film 22. Here, the high-frequency signal propagated from the antenna terminal 1 through the first high-frequency line H1 passes through the first control wiring layer 7 and the second through the gate electrodes 4a and 11a of the first MOSFET 4 and the second MOSFET 11, respectively. The control wiring layer 14 leaks in a small amount. Hereinafter, this influence will be described by taking the first control wiring layer 7 as an example. This effect is the same for the second control wiring layer.

この第１の制御配線層７に漏洩した高周波信号が、第１の層間絶縁膜２２を通り抜けて、第１の制御配線層７の直下に存在する前述の自由電子からなるチャネル層に振動を発生させる。この振動が、再び第１の制御配線層７や、第１及び第２の高周波線路に漏洩してノイズを発生させる。これが原因で、第１の入出力端子２の出力に、高調波歪みや相互変調歪みが現れ第１の入出力端子２のＳ／Ｎ比を低下させる。第１のＭＯＳＦＥＴ４や第２のＭＯＳＦＥＴ１１の直下でも、前述の界面での自由電子のキャリア層は存在する。しかし、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１が、第１の制御配線層７からの高周波信号の伝搬を遮蔽するので、界面での自由電子の振動がほとんど生じない。このキャリア層での自由電子の振動が顕著に発生するのは、第１の制御配線層７が、埋込酸化膜２１とシリコン基板２０の界面の上に、第１の層間絶縁膜だけを介して配置されている領域である。第１のＭＯＳＦＥＴ４がオン状態である間は、第１の制御配線層７には直流のゲートオン電圧が印可され続ける。ＭＯＳ構造の効果により、この領域では、更に前述の界面での自由電子の密度が増加するので、第１の入出力端子２のＳ／Ｎ比がさらに悪化する。 The high-frequency signal leaked to the first control wiring layer 7 passes through the first interlayer insulating film 22 and generates vibrations in the channel layer made of the above-described free electrons existing immediately below the first control wiring layer 7. Let This vibration leaks again to the first control wiring layer 7 and the first and second high-frequency lines to generate noise. Due to this, harmonic distortion and intermodulation distortion appear at the output of the first input / output terminal 2 and the S / N ratio of the first input / output terminal 2 is lowered. Even immediately below the first MOSFET 4 and the second MOSFET 11, there is a free electron carrier layer at the aforementioned interface. However, since the first MOSFET 4 and the second MOSFET 11 shield the propagation of the high-frequency signal from the first control wiring layer 7, the vibration of free electrons at the interface hardly occurs. The vibration of free electrons in the carrier layer occurs remarkably because the first control wiring layer 7 is located on the interface between the buried oxide film 21 and the silicon substrate 20 only through the first interlayer insulating film. This is the area where While the first MOSFET 4 is in the ON state, a direct current gate-on voltage is continuously applied to the first control wiring layer 7. Due to the effect of the MOS structure, in this region, the density of free electrons at the above-described interface further increases, so that the S / N ratio of the first input / output terminal 2 is further deteriorated.

本実施形態に係る高周波スイッチ回路１００は、埋込酸化膜２１とシリコン基板２０の界面の上に、一端で第１の抵抗９を介して第１のＭＯＳＦＥＴ４の第２の電極４ｃと接続し他端で接地端子ＧＮＤに接続した第１の導電体層１０を、第１のＭＯＳＦＥＴと第２のＭＯＳＦＥＴの間の溝内に設けられた第１の層間絶縁膜の直上に備えている。第１の制御配線層７に漏洩した高周波信号は、第２の層間絶縁膜２３を介して第１の導電体層１０に達すると接地端子ＧＮＤに通り抜けていく。さらに、第１のＭＯＳＦＥＴ４がオン状態の時に第１の制御配線層７に印加されたゲートオン電圧による直流の電界は、接地された第１の導電体層１０により遮蔽されるので、埋込酸化膜２１とシリコン基板２０との界面での自由電子密度の増加が抑制される。これらにより、本実施形態に係る高周波スイッチ回路１００においては、第１の制御配線層７の直下での埋込酸化膜２１とシリコン基板２０との界面の自由電子の振動の発生が抑制されるので、第１の入出力端子２の出力のＳ／Ｎ比が大きく改善され、通過損失が改善される。 The high-frequency switch circuit 100 according to the present embodiment is connected to the second electrode 4c of the first MOSFET 4 through the first resistor 9 at one end on the interface between the buried oxide film 21 and the silicon substrate 20, and the like. A first conductor layer 10 connected at one end to the ground terminal GND is provided immediately above a first interlayer insulating film provided in a groove between the first MOSFET and the second MOSFET. The high-frequency signal leaked to the first control wiring layer 7 passes through the ground terminal GND when it reaches the first conductor layer 10 via the second interlayer insulating film 23. Further, since the DC electric field due to the gate-on voltage applied to the first control wiring layer 7 when the first MOSFET 4 is on is shielded by the grounded first conductor layer 10, the buried oxide film An increase in the free electron density at the interface between 21 and the silicon substrate 20 is suppressed. As a result, in the high-frequency switch circuit 100 according to the present embodiment, generation of free electron vibrations at the interface between the buried oxide film 21 and the silicon substrate 20 immediately below the first control wiring layer 7 is suppressed. The S / N ratio of the output of the first input / output terminal 2 is greatly improved, and the passage loss is improved.

さらに本実施形態に係る高周波スイッチ回路１００では、第１の導電体層１０は、第１のＭＯＳＦＥＴと第２のＭＯＳＦＥＴの間の溝内に設けられた第１の層間絶縁膜に沿って延伸している。水平面内で延伸方向と垂直な方向では、第１の導電体層１０の幅は、上記溝内に設けられた第１の層間絶縁膜の幅より大きく、第１の層間絶縁膜を覆って、その両側で第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１のソース・ドレイン層２４及び２５上に重なっている。このような構造とすることで、さらに第１の制御配線層７からの電界が、埋込酸化膜２１とシリコン基板２０の界面の自由電子まで到達しにくくなっている。 Furthermore, in the high-frequency switch circuit 100 according to the present embodiment, the first conductor layer 10 extends along the first interlayer insulating film provided in the groove between the first MOSFET and the second MOSFET. ing. In the direction perpendicular to the extending direction in the horizontal plane, the width of the first conductor layer 10 is larger than the width of the first interlayer insulating film provided in the groove, covering the first interlayer insulating film, Both sides of the first MOSFET 4 and the second MOSFET 11 overlap the source / drain layers 24 and 25 on both sides. With such a structure, the electric field from the first control wiring layer 7 does not easily reach the free electrons at the interface between the buried oxide film 21 and the silicon substrate 20.

本実施形態に係る高周波スイッチ回路１００と比較例の高周波スイッチ回路２００とで、入出力端子の出力特性を比較した。アンテナ端子１に１９５０ＭＨｚで２０ｄＢｍの信号と１９０ＭＨｚで−１５ｄＢｍの信号を入力し、第１の入出力端子１から出力信号を測定した。二次相互変調歪みが、比較例の高周波スイッチ回路２００では、−１０２ｄＢｍで合ったのに対し、本実施形態に係る高周波スイッチ回路１００では、−１０８ｄＢｍと優れた特性で合った。 The output characteristics of the input / output terminals were compared between the high-frequency switch circuit 100 according to the present embodiment and the high-frequency switch circuit 200 of the comparative example. A signal of 20 dBm at 1950 MHz and a signal of −15 dBm at 190 MHz were input to the antenna terminal 1, and an output signal was measured from the first input / output terminal 1. The second-order intermodulation distortion matched with −102 dBm in the high-frequency switch circuit 200 of the comparative example, whereas it matched with −108 dBm in excellent characteristics in the high-frequency switch circuit 100 according to the present embodiment.

本実施形態に係る高周波スイッチ回路１００は、ＳＯＩ基板の埋込酸化膜２１とシリコン基板２０の界面の上で、第１のＭＯＳＦＥＴと第２のＭＯＳＦＥＴの間にあり埋込酸化膜まで達して両者を分離する溝内に設けられた第１の層間絶縁膜２２上に、一端で第１の抵抗９を介して第１のＭＯＳＦＥＴ４の第２の電極４ｃと接続し、他端で接地端子ＧＮＤに接続した第１の導電体層１０を備えている。第１の制御配線層７が、上記溝内に設けられた第１の層間絶縁膜２２上、且つ上記第１の導電体層１０上に、第２の層間絶縁膜を介して形成されている。このような構造が、第１の制御配線層７に漏洩した高周波信号がＳＯＩ基板の埋込酸化膜２１とシリコン基板２０の界面に存在する自由電子を振動させることを抑制する。この結果、入出力端子の出力に現れる高調波歪みや二次相互変調歪みを低減することができる。高周波スイッチ回路の通過損失が低減できる。 The high-frequency switch circuit 100 according to the present embodiment is located between the first MOSFET and the second MOSFET on the interface between the buried oxide film 21 of the SOI substrate and the silicon substrate 20 and reaches the buried oxide film. Is connected to the second electrode 4c of the first MOSFET 4 via the first resistor 9 at one end and to the ground terminal GND at the other end on the first interlayer insulating film 22 provided in the trench for separating A connected first conductor layer 10 is provided. The first control wiring layer 7 is formed on the first interlayer insulating film 22 provided in the trench and on the first conductor layer 10 via the second interlayer insulating film. . Such a structure suppresses the high-frequency signal leaking to the first control wiring layer 7 from vibrating the free electrons existing at the interface between the buried oxide film 21 and the silicon substrate 20 of the SOI substrate. As a result, harmonic distortion and secondary intermodulation distortion appearing at the output of the input / output terminal can be reduced. The passage loss of the high frequency switch circuit can be reduced.

前述のように、上記効果は、第１の導電体層１０と第１の制御配線層７がそれぞれ、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１との間に設けられた第１の層間絶縁膜上に形成されている場合に限られない。埋込酸化膜まで達し、それぞれのＭＯＳＦＥＴを個別に取り囲み周囲から離間分離する溝内に形成された第１の層間絶縁膜２２上であれば、第１の導電体層１０と第１の制御配線層７が、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１の間以外に形成されてもその効果が得られる。すなわち、本発明の実施形態に係る高周波スイッチ回路は、ＳＯＩ基板の埋込酸化膜とシリコン基板の界面の上で、埋込酸化膜まで達し、それぞれのＭＯＳＦＥＴを個別に環状に取り囲んで周囲から離間分離する溝内に形成された第１の層間絶縁膜上に、接地端子ＧＮＤに電気的に接続した導電体層を備えている。制御配線層が、上記溝内に形成された第１の層間絶縁膜上であり、上記第１の導電体層上に、第２の層間絶縁膜を介して形成されている。このような構造とすることで、高周波スイッチ回路の通過損失を低減できる。 As described above, the above effect is obtained on the first interlayer insulating film in which the first conductor layer 10 and the first control wiring layer 7 are provided between the first MOSFET 4 and the second MOSFET 11, respectively. It is not limited to the case where it is formed. If it is on the first interlayer insulating film 22 formed in the trench that reaches the buried oxide film and surrounds each MOSFET individually and separates from the surroundings, the first conductor layer 10 and the first control wiring Even if the layer 7 is formed other than between the first MOSFET 4 and the second MOSFET 11, the effect can be obtained. That is, the high-frequency switch circuit according to the embodiment of the present invention reaches the buried oxide film on the interface between the buried oxide film of the SOI substrate and the silicon substrate, individually surrounds each MOSFET in a ring shape, and is separated from the surroundings. A conductive layer electrically connected to the ground terminal GND is provided on the first interlayer insulating film formed in the trench to be separated. The control wiring layer is formed on the first interlayer insulating film formed in the trench, and is formed on the first conductor layer via the second interlayer insulating film. With such a structure, the passage loss of the high-frequency switch circuit can be reduced.

（第２の実施の形態）
図６及び図７を用いて、第２の実施の形態に係る高周波スイッチ回路３００を説明する。図６は、第２の実施形態に係る高周波スイッチ回路の回路図である。図７は、第２の実施形態に係る高周波スイッチ回路の要部断面図である。なお、第１の実施の形態と同一又は類似の箇所には同一符号を付して説明し、第１の実施の形態と違う部分のみを説明する。 (Second Embodiment)
A high frequency switch circuit 300 according to the second embodiment will be described with reference to FIGS. 6 and 7. FIG. 6 is a circuit diagram of a high-frequency switch circuit according to the second embodiment. FIG. 7 is a cross-sectional view of a main part of the high-frequency switch circuit according to the second embodiment. In addition, the same code | symbol is attached | subjected and demonstrated to the same or similar location as 1st Embodiment, and only a different part from 1st Embodiment is demonstrated.

本実施の形態に係る高周波スイッチ回路３００は、図６に示したとおり、図４に示した比較例に示した回路図と同様の回路を有する。また、ＳＯＩ基板上に形成した高周波スイッチ回路３００は、図７に示したとおり、その要部断面は第１の実施形態と同様な断面形状を有する。第１の実施の形態に係る高周波スイッチ回路１００は、ＳＯＩ基板の埋込酸化膜２１とシリコン基板２０の界面の上で、第１のＭＯＳＦＥＴと第２のＭＯＳＦＥＴの間にあり埋込酸化膜まで達して両者を分離する溝内に設けられた第１の層間絶縁膜上に、一端で第１の抵抗９を介して第１のＭＯＳＦＥＴ４の第２の電極４ｃと接続し他端で接地端子ＧＮＤに接続した第１の導電体層１０を備えている。しかしながら、本実施形態に係る高周波スイッチ回路３００は、接地端子ＧＮＤに電気的に接続されているが、第１のＭＯＳＦＥＴ４の第２の電極４ｃに電気的に接続されていない導電体層３０を有する点だけが、第１の実施の形態に係る高周波スイッチ回路１００と違う。それ以外は同じ構造である。 The high-frequency switch circuit 300 according to the present embodiment has a circuit similar to the circuit diagram shown in the comparative example shown in FIG. 4 as shown in FIG. The high-frequency switch circuit 300 formed on the SOI substrate has the same cross-sectional shape as that of the first embodiment as shown in FIG. The high-frequency switch circuit 100 according to the first embodiment is located between the first MOSFET and the second MOSFET on the interface between the buried oxide film 21 of the SOI substrate and the silicon substrate 20 up to the buried oxide film. On the first interlayer insulating film provided in the trench that reaches and separates the two, one end is connected to the second electrode 4c of the first MOSFET 4 via the first resistor 9, and the other end is connected to the ground terminal GND. The first conductor layer 10 connected to is provided. However, the high-frequency switch circuit 300 according to this embodiment includes the conductor layer 30 that is electrically connected to the ground terminal GND but is not electrically connected to the second electrode 4c of the first MOSFET 4. Only the point is different from the high-frequency switch circuit 100 according to the first embodiment. The rest is the same structure.

従って、本実施形態に係る高周波スイッチ回路３００においても、第１の実施の形態に係る高周波回路１００と同様に、ＳＯＩ基板の埋込酸化膜２１とシリコン基板２０の界面の上で、第１のＭＯＳＦＥＴと第２のＭＯＳＦＥＴの間にあり埋込酸化膜まで達して両者を分離する溝内に設けられた第１の層間絶縁膜２２上に、接地端子ＧＮＤに接続した第１の導電体層３０を備えている。このような構造とすることで、第１の制御配線層７に漏洩した高周波信号がＳＯＩ基板の埋込酸化膜２１とシリコン基板２０の界面に存在する自由電子を振動させることを抑制する。この結果、入出力端子の出力に現れる高調波歪みや二次相互変調歪みを低減することができる。高周波スイッチ回路の通過損失を低減できる。 Therefore, also in the high-frequency switch circuit 300 according to the present embodiment, the first high-frequency switch circuit 300 on the interface between the buried oxide film 21 of the SOI substrate and the silicon substrate 20 is the same as the high-frequency circuit 100 according to the first embodiment. The first conductor layer 30 connected to the ground terminal GND is formed on the first interlayer insulating film 22 provided in the trench between the MOSFET and the second MOSFET which reaches the buried oxide film and separates them. It has. With such a structure, the high frequency signal leaked to the first control wiring layer 7 is prevented from vibrating free electrons existing at the interface between the buried oxide film 21 of the SOI substrate and the silicon substrate 20. As a result, harmonic distortion and secondary intermodulation distortion appearing at the output of the input / output terminal can be reduced. The passage loss of the high frequency switch circuit can be reduced.

本実施形態に係る高周波スイッチ回路３００は、導電体層３０の一端を第１のＭＯＳＦＥＴ４の第２電極４ｂに電気的に接続する配線を備えないので、ＳＯＩ基板上に回路パターンを形成する際に設計の自由度が増すという利点がある。 Since the high-frequency switch circuit 300 according to the present embodiment does not include a wiring that electrically connects one end of the conductor layer 30 to the second electrode 4b of the first MOSFET 4, the circuit pattern is formed on the SOI substrate. There is an advantage that the degree of freedom of design increases.

さらに、第１の実施形態で説明したとおり、上記効果は、第１の導電体層１０と第１の制御配線層７がそれぞれ、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１との間に設けられた第１の層間絶縁膜上に形成されている場合に限られない。埋込酸化膜まで達し、それぞれのＭＯＳＦＥＴを個別に取り囲み周囲から離間分離する溝内に形成された第１の層間絶縁膜上であれば、第１の導電体層１０と第１の制御配線層７が、第１のＭＯＳＦＥＴ４と第２のＭＯＳＦＥＴ１１の間以外に形成されてもその効果が得られる。すなわち、本発明の実施形態に係る高周波スイッチ回路は、ＳＯＩ基板の埋込酸化膜とシリコン基板の界面の上で、埋込酸化膜まで達し、それぞれのＭＯＳＦＥＴを個別に環状に取り囲んで周囲から離間分離する溝内に形成された第１の層間絶縁膜上に、接地端子ＧＮＤに電気的に接続した導電体層を備えている。制御配線層が、上記溝内に形成された第１の層間絶縁膜上であり、上記第１の導電体層上に、第２の層間絶縁膜を介して形成されている。このような構造とすることで、高周波スイッチ回路の通過損失を低減できる。 Furthermore, as described in the first embodiment, the above effect is that the first conductor layer 10 and the first control wiring layer 7 are provided between the first MOSFET 4 and the second MOSFET 11, respectively. It is not limited to the case where it is formed on the first interlayer insulating film. If it is on the first interlayer insulating film formed in the trench that reaches the buried oxide film and surrounds each MOSFET individually and is separated from the periphery, the first conductor layer 10 and the first control wiring layer Even if 7 is formed other than between the first MOSFET 4 and the second MOSFET 11, the effect can be obtained. That is, the high-frequency switch circuit according to the embodiment of the present invention reaches the buried oxide film on the interface between the buried oxide film of the SOI substrate and the silicon substrate, individually surrounds each MOSFET in a ring shape, and is separated from the surroundings. A conductive layer electrically connected to the ground terminal GND is provided on the first interlayer insulating film formed in the trench to be separated. The control wiring layer is formed on the first interlayer insulating film formed in the trench, and is formed on the first conductor layer via the second interlayer insulating film. With such a structure, the passage loss of the high-frequency switch circuit can be reduced.

以上、上記各実施形態においては、主に第１のＭＯＳＦＥＴ４、第１の導電体層１０、第１の制御配線層７を中心に、各実施形態の特徴と効果を説明してきたが、第２のＭＯＳＦＥＴ１１、第２の導電体層１７、第２の制御配線層１４のそれぞれに対しても同様に説明することができる。 As described above, in each of the above embodiments, the features and effects of each embodiment have been described mainly focusing on the first MOSFET 4, the first conductor layer 10, and the first control wiring layer 7. The same applies to each of the MOSFET 11, the second conductor layer 17, and the second control wiring layer.

上記各実施例では、いずれも一端がＭＯＳＦＥＴのゲート電極４ａ、１１ａに接続され、他端がゲート制御回路１８に接続された制御配線層７の下部での問題点と各実施形態の効果を説明した。制御配線層７にゲート制御回路１８から直流電圧が印加され、これにより、ＭＯＳ構造の作用により制御配線層７下部のシリコン基板２０と埋込酸化膜２１界面の自由電子の密度があがる。この密度の高い自由電子に高周波信号の電界が漏れて加わることで、高周波スイッチ回路の通過損失を悪化させていた。これは、ゲート電極に接続される制御配線層だけに係る問題ではなく、シリコン基板２０と埋込酸化膜２１との界面上に層間絶縁膜だけを介して配置された他の直流電圧が供給される配線層においても共通する問題である。従って、上記各実施形態は、ＭＯＳＦＥＴのゲート電圧に接続される制御配線層だけに限定されることなく、直流電圧を供給する他の配線層に対しても適用することができる。 In each of the above-described embodiments, problems at the bottom of the control wiring layer 7 in which one end is connected to the gate electrodes 4a and 11a of the MOSFET and the other end is connected to the gate control circuit 18 and the effects of the embodiments are described. did. A DC voltage is applied to the control wiring layer 7 from the gate control circuit 18, whereby the density of free electrons at the interface between the silicon substrate 20 and the buried oxide film 21 below the control wiring layer 7 is increased by the action of the MOS structure. The electric field of the high frequency signal leaks and is added to the high density free electrons, thereby deteriorating the passage loss of the high frequency switch circuit. This is not a problem relating only to the control wiring layer connected to the gate electrode, but another DC voltage arranged only on the interface between the silicon substrate 20 and the buried oxide film 21 via the interlayer insulating film is supplied. This is also a problem common to wiring layers. Therefore, each of the above embodiments is not limited to the control wiring layer connected to the gate voltage of the MOSFET, but can be applied to other wiring layers that supply a DC voltage.

従って、本発明の特徴と効果の趣旨を逸脱しない範囲で、以上説明した事項を組み合わせた構造においても、本発明を実施することが可能である。また、ＳＰＤＴ（Single Pole Double Throw）の例で説明したが、アンテナ端子、入出力端子、及びＭＯＳＦＥＴの数を適宜増やすだけで、ｎＰｎＴ（n Pole n Throw）に対応できることは勿論である。 Therefore, the present invention can be implemented even in a structure in which the above-described items are combined without departing from the spirit of the features and effects of the present invention. In addition, although an example of SPDT (Single Pole Double Throw) has been described, it is needless to say that nPnT (n Pole n Throw) can be supported by appropriately increasing the number of antenna terminals, input / output terminals, and MOSFETs.

１アンテナ端子
２、３入出力端子
４、１１ＭＯＳＦＥＴ
５、１２ソース・ドレインバイアス抵抗
６、１３ゲートバイアス抵抗
７、１４制御配線層
８、１５ゲート制御抵抗
９、１６抵抗
１０、１７、３０導電体層
１８ゲート制御回路
２０高抵抗シリコン基板
２１埋込シリコン酸化膜
２２、２３層間絶縁膜
２４、２５ソース・ドレイン領域
１００、１０１、２００、３００高周波スイッチ回路
Ｈ１〜Ｈ３高周波線路
ＧＮＤ接地端子 1 Antenna terminal 2, 3 Input / output terminal 4, 11 MOSFET
5, 12 Source / drain bias resistors 6, 13 Gate bias resistors 7, 14 Control wiring layers 8, 15 Gate control resistors 9, 16 Resistors 10, 17, 30 Conductor layer 18 Gate control circuit 20 High resistance silicon substrate 21 Embedded Silicon oxide films 22, 23 Interlayer insulating films 24, 25 Source / drain regions 100, 101, 200, 300 High frequency switch circuits H1-H3 High frequency line GND Ground terminal

Claims

A first terminal;
A silicon substrate;
An oxide film formed on the silicon substrate;
An FET formed on the oxide film, the first electrode being electrically connected to the first terminal, and controlling a current flowing between the first electrode and the second electrode;
A first interlayer insulating film which is separated from the surroundings and embedded in a groove reaching the oxide film, connected to the oxide film, and insulates the FET from the surroundings;
A conductor layer formed on the first interlayer insulating film in the groove and connected to a ground terminal;
A second interlayer insulating film formed on the conductor layer and the FET;
A wiring layer that is formed on the first interlayer insulating film in the groove and on the conductor layer via the second interlayer insulating film, and supplies a DC voltage;
An input / output terminal electrically connected to the second electrode of the FET;
A high-frequency switch circuit comprising:

The plurality of wiring layers are control wiring layers having one end electrically connected to the gate electrode of the FET and the other end electrically connected to a gate control circuit. High frequency switch circuit.

One end of the conductor layer is connected to the ground terminal,
3. The high-frequency switch circuit according to claim 1, wherein the other end of the conductor layer is electrically connected to the second electrode of the FET via a high-resistance resistor.

4. The apparatus according to claim 1, wherein a plurality of the FETs are provided, and the input / output terminals connected to the second electrode of the FET are provided in correspondence with the number of the FETs. High frequency switch circuit.

The conductor layer has a plurality of layers each made of a conductor,
One end of each of the plurality of layers is connected to the ground terminal,
5. The other end of each of the plurality of layers is electrically connected to the second electrode of each of the plurality of FETs via a high-resistance resistor individually. High frequency switch circuit.

In the part where the wiring layer is formed on the first interlayer insulating film in the groove and on the conductor layer via the second interlayer insulating film, the wiring layer is the same as the conductor layer. The width of the conductor layer in a direction orthogonal to the extension direction in a horizontal plane is larger than the width of the wiring layer in the orthogonal direction. A high-frequency switch circuit according to any one of the above.

The high-frequency switch circuit according to claim 1, wherein the ground terminal is grounded.