[go: up one dir, main page]

JP2012009786A - Memory device - Google Patents

Memory device Download PDF

Info

Publication number
JP2012009786A
JP2012009786A JP2010146804A JP2010146804A JP2012009786A JP 2012009786 A JP2012009786 A JP 2012009786A JP 2010146804 A JP2010146804 A JP 2010146804A JP 2010146804 A JP2010146804 A JP 2010146804A JP 2012009786 A JP2012009786 A JP 2012009786A
Authority
JP
Japan
Prior art keywords
memory element
recording layer
layer
piezoelectric body
recording
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010146804A
Other languages
Japanese (ja)
Inventor
Hiroyuki Omori
広之 大森
Masakatsu Hosomi
政功 細見
Kazuhiro Bessho
和宏 別所
Yutaka Higo
豊 肥後
Ichiyo Yamane
一陽 山根
Hiroyuki Uchida
裕行 内田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2010146804A priority Critical patent/JP2012009786A/en
Publication of JP2012009786A publication Critical patent/JP2012009786A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

【課題】記録を安定に保持できながら少ない電流で記録が可能であり、且つ実用に供し得るスピン注入電流で情報を記録するメモリ素子を提供するものである。
【解決手段】磁化方向が決められた参照層4と、記録情報に依存して磁化方向が変化する記録層5と、参照層4と記録層5との間に設けられた非磁性層6とを有し、スピン注入電流で情報を記録層5に記録するメモリ素子積層体7を有する。さらに、メモリ素子積層体7の側部に設けられた圧電体11と、圧電体11に電界を印加する手段とを備える。
【選択図】図1
The present invention provides a memory element capable of recording information with a spin injection current that can be recorded with a small current while being able to hold the recording stably and can be used practically.
A reference layer with a determined magnetization direction, a recording layer whose magnetization direction changes depending on recording information, a nonmagnetic layer provided between the reference layer and the recording layer, And a memory element stack 7 that records information on the recording layer 5 with a spin injection current. Furthermore, the piezoelectric element 11 provided in the side part of the memory element laminated body 7 and a means for applying an electric field to the piezoelectric element 11 are provided.
[Selection] Figure 1

Description

本発明は、メモリ素子、特に不揮発性メモリに関する。   The present invention relates to a memory element, particularly a nonvolatile memory.

コンピュータなどの情報機器では、ランダム・アクセス・メモリとして、動作が高速で、高密度なDRAMが広く使われている。しかし、DRAMは電源を切ると情報が消えてしまう揮発性メモリであるため、情報が消えない不揮発性メモリが望まれている。   In information devices such as computers, DRAMs with high speed and high density are widely used as random access memories. However, since DRAM is a volatile memory in which information disappears when the power is turned off, a nonvolatile memory in which information does not disappear is desired.

不揮発性メモリの候補としては、磁性体の磁化で情報を記録する磁気ランダム・アクセス・メモリ(MRAM)が注目され、開発が進められている。MRAMの記録を行う方法としては、電流磁場によって磁化を反転させる方法と、スピン分極した電子を直接記録層に注入して磁化反転を起させる方法(特許文献1参照)の2つがある。現在、素子のサイズが小さくなるに従い記録電流を小さくできるスピン注入磁化反転が注目されている。   As a candidate for a nonvolatile memory, a magnetic random access memory (MRAM) that records information by magnetization of a magnetic material has attracted attention and is being developed. There are two methods for recording in the MRAM: a method of reversing magnetization by a current magnetic field, and a method of injecting spin-polarized electrons directly into the recording layer to cause magnetization reversal (see Patent Document 1). Currently, attention is focused on spin-injection magnetization reversal, which can reduce the recording current as the element size decreases.

しかしながら、素子サイズを小さくすると記録の情報が熱ゆらぎによって変化してしまう等、記録の保持能力に問題が生じる。これを避けるためには記録層の磁性層厚を厚くするなどの対策が必要となるが、磁性層の体積を増やすと、スピン注入磁化反転に必要な電流が増加し、消費電力の増加や駆動トランジスタのサイズの増大を招き記録密度の向上が困難になる。   However, when the element size is reduced, there is a problem in the recording holding capability such that the information of recording changes due to thermal fluctuation. To avoid this, it is necessary to take measures such as increasing the magnetic layer thickness of the recording layer. However, increasing the volume of the magnetic layer increases the current required for spin injection magnetization reversal, increasing power consumption and driving. This increases the size of the transistor and makes it difficult to improve the recording density.

特許文献2には、圧電層の伸縮を利用して記録層の面内方向の格子が延びることで熱かく乱耐性を低下させて記録電流の低減を図ったメモリ素子が提案されている。特許文献2では、圧電層、記録層、トンネルバリア層及び参照層を積層した原理的な構成が示されている。   Patent Document 2 proposes a memory element that reduces the recording current by reducing the thermal disturbance resistance by extending the lattice in the in-plane direction of the recording layer by using expansion and contraction of the piezoelectric layer. Japanese Patent Application Laid-Open No. 2004-228561 discloses a basic configuration in which a piezoelectric layer, a recording layer, a tunnel barrier layer, and a reference layer are stacked.

特開2004−193595号公報JP 2004-193595 A 特開2010−80733号公報JP 2010-80733 A

本発明は、上述の点に鑑み、記録を安定に保持できながら少ない電流で記録が可能であり、且つ実用に供し得るメモリ素子を提供するものである。   In view of the above-described points, the present invention provides a memory element that can record with a small current while being able to stably maintain recording and can be practically used.

本発明にかかるメモリ素子は、磁化方向が決められた参照層と、記録情報に依存して磁化方向が変化する記録層と、参照層と記録層との間に設けられた非磁性層とを有し、スピン注入電流で情報を記録層に記録するメモリ素子積層体を備える。さらに、メモリ素子積層体の側部に設けられた圧電体と、圧電体に電界を印加する手段とを備える。   A memory element according to the present invention includes a reference layer having a determined magnetization direction, a recording layer whose magnetization direction changes depending on recording information, and a nonmagnetic layer provided between the reference layer and the recording layer. A memory element stack that records information on the recording layer with a spin injection current. Furthermore, a piezoelectric body provided on a side portion of the memory element stacked body and means for applying an electric field to the piezoelectric body are provided.

本発明のメモリ素子は、参照層、非磁性層及び記録層を有し、スピン注入電流で情報を記録層に記録するメモリ素子積層体の側部に圧電体が設けられるので、記録時、記録層に対して圧電体の変形に基く応力を有効に与えることができる。これによって、記録層の保磁力が低減され、記録電流が低減される。   The memory element of the present invention has a reference layer, a nonmagnetic layer, and a recording layer, and a piezoelectric body is provided on the side of the memory element stack that records information on the recording layer with a spin injection current. The stress based on the deformation of the piezoelectric body can be effectively applied to the layer. Thereby, the coercive force of the recording layer is reduced, and the recording current is reduced.

本発明に係るメモリ素子によれば、記録を安定に保持できながら少ない電流で記録が可能であり、且つ実用に供し得るメモリ素子、すなわち不揮発性メモリを提供することができる。   According to the memory element of the present invention, it is possible to provide a memory element, that is, a non-volatile memory that can be recorded with a small current while being able to stably maintain recording, and can be used practically.

A〜C 本発明に係るメモリ素子の第1実施の形態の概略構成を示す斜視図、断面図及び動作説明図である。1A to 1C are a perspective view, a cross-sectional view, and an operation explanatory view showing a schematic configuration of a first embodiment of a memory element according to the present invention. A、B 本発明に係るメモリ素子の第2実施の形態の概略構成を示す上面図及び断面図である。A and B are a top view and a cross-sectional view showing a schematic configuration of a second embodiment of a memory element according to the present invention. A〜C 第2実施の形態の動作説明に供する電圧印加前の圧電体の状態、電圧印加後の圧電体の状態、及び圧電体の変形に伴う記録層の変形状態を示す説明図である。FIGS. 8A to 8C are explanatory diagrams showing a state of a piezoelectric body before voltage application, a state of a piezoelectric body after voltage application, and a deformation state of a recording layer accompanying deformation of the piezoelectric body, which are used for explaining the operation of the second embodiment. A、B 本発明に係るメモリ素子の第3実施の形態の概略構成を示す上面図及び断面図である。A and B are a top view and a cross-sectional view showing a schematic configuration of a third embodiment of a memory element according to the present invention. 第3実施の形態の動作説明に供する説明図である。It is explanatory drawing with which it uses for operation | movement description of 3rd Embodiment. 本発明に係るメモリ素子の第4実施の形態の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of 4th Embodiment of the memory element which concerns on this invention. A〜D 第4実施の形態に係るメモリ素子の製造方法例を示す製造工程図である。AD is a manufacturing process diagram showing an example of a manufacturing method of the memory element according to the fourth embodiment. 第4実施の形態の動作説明に供する説明図である。It is explanatory drawing with which it uses for operation | movement description of 4th Embodiment. 本発明に係るメモリ素子の第5実施の形態の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of 5th Embodiment of the memory element based on this invention. 本発明に係るメモリ素子の第6実施の形態の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of 6th Embodiment of the memory element based on this invention. 本発明に係るメモリ素子の第7実施の形態の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of 7th Embodiment of the memory element based on this invention. 本発明に係るメモリ素子の第8実施の形態の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of 8th Embodiment of the memory element based on this invention. A、B 本発明に係るメモリ素子の第9実施の形態の概略構成を示す断面図である。A, B It is sectional drawing which shows schematic structure of 9th Embodiment of the memory element based on this invention. A〜D 本発明のメモリ素子の効果の検証のための面内磁化膜を用いたメモリ素子の試料の作製方法を示す作製工程図である。FIGS. 6A to 6D are manufacturing process diagrams illustrating a method for manufacturing a sample of a memory element using an in-plane magnetic film for verifying the effect of the memory element of the present invention. FIGS. 図14のメモリ素子本体の詳細図である。FIG. 15 is a detailed view of the memory element body of FIG. 14. 図14の試料を用いたときの圧電体に印加する電圧(Va)と垂直磁化膜の保磁力の関係を示すグラフである。It is a graph which shows the relationship between the voltage (Va) applied to a piezoelectric material when using the sample of FIG. 14, and the coercive force of a perpendicular magnetization film. 図14の試料を用い、圧電体に印加する電圧を代えたときの書き込み(記録)電圧(Vp)と反転エラーの関係を示すグラフである。15 is a graph showing a relationship between a writing (recording) voltage (Vp) and a reversal error when the sample of FIG. 14 is used and the voltage applied to the piezoelectric body is changed. 本発明の効果の検証に用いた試料であり垂直磁化膜を用いた概略構成図である。It is a sample used for verification of the effect of the present invention and is a schematic configuration diagram using a perpendicular magnetization film. 図18の試料を用いたときの圧電体に印加する電圧(Va)と垂直磁化膜の保磁力の関係を示すグラフである。It is a graph which shows the relationship between the voltage (Va) applied to a piezoelectric material when using the sample of FIG. 18, and the coercive force of a perpendicular magnetization film.

以下、発明を実施するための形態(以下実施の形態とする)について説明する。なお、説明は以下の順序で行う。
1.本発明の実施の形態に係るメモリ素子の概要説明
2.第1実施の形態(メモリ素子の概略構成例)
3.第2実施の形態(メモリ素子の概略構成例)
4.第3実施の形態(メモリ素子の概略構成例)
5.第4実施の形態(メモリ素子の概略構成例とその製造方法例)
6.第5実施の形態(メモリ素子の概略構成例)
7.第6実施の形態(メモリ素子の概略構成例)
8.第7実施の形態(メモリ素子の概略構成例)
9.第8実施の形態(メモリ素子の概略構成例)
10.第9実施の形態(メモリ素子の概略構成例)
11.本発明のメモリ素子の効果の検証
Hereinafter, modes for carrying out the invention (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
1. 1. Outline of memory device according to embodiment of the present invention First Embodiment (Schematic configuration example of memory element)
3. Second Embodiment (Schematic configuration example of memory element)
4). Third Embodiment (Schematic configuration example of memory element)
5. Fourth Embodiment (Schematic configuration example of memory element and manufacturing method thereof)
6). Fifth embodiment (schematic configuration example of memory element)
7). Sixth Embodiment (Schematic configuration example of memory element)
8). Seventh Embodiment (Schematic configuration example of memory element)
9. Eighth Embodiment (Schematic configuration example of a memory element)
10. Ninth Embodiment (Schematic configuration example of memory element)
11. Verification of the effect of the memory device of the present invention

<本発明の実施の形態に係るメモリ素子の概要説明>
本発明の実施の形態に係るメモリ素子は、情報の基準となる参照層(磁性層)と、記録された情報により磁化方向が変化する記録層(磁性層と)との間に非磁性層を挟んだ基本的構成のメモリ素子積層体を有する。メモリ素子積層体の表裏面には対をなす電極が配置される。本メモリ素子は、上記記録層に力学的作用を及ぼす位置に、圧電体を配置し、記録層に情報を記録する際に、圧電体に電界を印加して、記録層の保磁力を低下させるような応力を発生させ、記録に必要なスピン注入電流を低減させる構成とする。あるいは本メモリ素子は、上記圧電体に電界を印加して、高周波の振動によって記録層の磁化の才差運動を補助して、記録に必要なスピン注入電流を低減させる構成とする。
<Overview of Memory Element According to Embodiment of the Present Invention>
The memory element according to the embodiment of the present invention includes a nonmagnetic layer between a reference layer (magnetic layer) serving as a reference for information and a recording layer (magnetic layer) whose magnetization direction changes according to recorded information. It has a memory element stack with a basic structure sandwiched. Paired electrodes are disposed on the front and back surfaces of the memory element stack. In this memory element, a piezoelectric body is disposed at a position that exerts a mechanical action on the recording layer, and when recording information on the recording layer, an electric field is applied to the piezoelectric body to reduce the coercive force of the recording layer. Such a stress is generated to reduce the spin injection current necessary for recording. Alternatively, the memory element is configured to apply an electric field to the piezoelectric body and assist the precession of magnetization of the recording layer by high-frequency vibration to reduce the spin injection current necessary for recording.

圧電体に、例えば電圧をかける等して、電界が印加されると、圧電体がピエゾ効果で変形し、メモリ素子積層体を構成する層への応力が変化する。このとき、記録層へも力が加わるので、記録層が変形し、逆磁歪効果で磁気異方性が変化し、保磁力が変わる。圧電体に電界を印加したときに、記録層の保磁力が低下するように、圧電体の特性、圧電体にかける電圧極性、記録層の磁歪定数などを調整しておく。これにより、圧電体に電界を印加しながら、スピン注入電流を流したとき、記録層の磁化を反転する反転電流、つまりスピン注入電流が低減する。メモリ素子では、圧電体の変形に基く記録層の変形を妨げないような、つまり記録層に応力が発生し易いような対策を施すことが好ましい。   When an electric field is applied to the piezoelectric body, for example, by applying a voltage, the piezoelectric body is deformed by the piezoelectric effect, and the stress on the layers constituting the memory element stack changes. At this time, since a force is also applied to the recording layer, the recording layer is deformed, the magnetic anisotropy is changed by the inverse magnetostrictive effect, and the coercive force is changed. The characteristics of the piezoelectric body, the voltage polarity applied to the piezoelectric body, the magnetostriction constant of the recording layer, and the like are adjusted so that the coercive force of the recording layer decreases when an electric field is applied to the piezoelectric body. Thereby, when a spin injection current is applied while applying an electric field to the piezoelectric body, the reversal current that reverses the magnetization of the recording layer, that is, the spin injection current is reduced. In the memory element, it is preferable to take measures to prevent deformation of the recording layer based on deformation of the piezoelectric body, that is, to easily generate stress in the recording layer.

参照層、記録層は、共に面内磁化膜でも良いし、垂直磁化膜でも良い。面内磁化膜の場合は、圧電体が変形したときに磁化容易方向と磁化困難方向で、伸縮率の変化が大きい方が良い。記録層が面内磁化膜で形成され、記録層の磁歪が正の場合は、磁化困難方向に記録層が引っ張られるか、磁化容易方向に記録層が圧縮されれば、磁気異方性が低下し、保磁力が低下し、記録し易くなる。記録層が面内磁化膜で形成され、記録層の磁歪が負の場合は、磁化容易方向に記録層が引っ張られるか、磁化困難方向に記録層が圧縮されれば、磁気異方性が低下し、保磁力が低下し、記録し易くなる。   Both the reference layer and the recording layer may be in-plane magnetization films or perpendicular magnetization films. In the case of an in-plane magnetized film, it is better that the expansion / contraction rate changes greatly in the easy magnetization direction and the hard magnetization direction when the piezoelectric body is deformed. If the recording layer is formed of an in-plane magnetization film and the magnetostriction of the recording layer is positive, the magnetic anisotropy decreases if the recording layer is pulled in the direction of difficult magnetization or the recording layer is compressed in the direction of easy magnetization However, the coercive force is reduced and recording becomes easy. If the recording layer is formed of an in-plane magnetization film and the magnetostriction of the recording layer is negative, the magnetic anisotropy decreases if the recording layer is pulled in the easy magnetization direction or the recording layer is compressed in the hard magnetization direction. However, the coercive force is reduced and recording becomes easy.

記録層が垂直磁化膜で形成され、記録層の磁歪が正の場合は、膜面均一に引っ張られるか、膜面垂直に圧縮されれば、磁気異方性が低下し、保磁力が低下し、記録し易くなる。記録層が垂直磁化膜で形成され、記録層の磁歪が負の場合は、膜面垂直に引っ張られるか、膜面均一に圧縮されれば、磁気異方性が低下し、保磁力が低下し、記録し易くなる。   When the recording layer is formed of a perpendicularly magnetized film and the magnetostriction of the recording layer is positive, if the film surface is pulled uniformly or compressed perpendicularly to the film surface, the magnetic anisotropy decreases and the coercive force decreases. It becomes easy to record. When the recording layer is formed of a perpendicularly magnetized film and the magnetostriction of the recording layer is negative, if the film layer is pulled perpendicularly or compressed uniformly, the magnetic anisotropy decreases and the coercive force decreases. It becomes easy to record.

また、記録層に加わる力が変動すると記録層の磁化が振動するが、適当な周波数で振動させると、スピン注入トルクによる記録層の磁化の才差運動と同期して磁化の反転電流、つまりスピン注入電流が低減する。メモリ素子積層体に形成する電極、あるいは圧電体に形成する電極は、良導体金属であればよいが、圧電体、磁性層の結晶配向や反応劣化などを考慮して選択するのが好ましい。   When the force applied to the recording layer fluctuates, the magnetization of the recording layer vibrates, but when it vibrates at an appropriate frequency, the magnetization reversal current, that is, the spin is synchronized with the precession of the magnetization of the recording layer due to the spin injection torque. The injection current is reduced. The electrode formed on the memory element laminated body or the electrode formed on the piezoelectric body may be a good conductor metal, but is preferably selected in consideration of the crystal orientation and reaction deterioration of the piezoelectric body and the magnetic layer.

圧電体材料としては、BaTiO、LiNbO、ZnO等の酸化物での良いし、AlN等の窒化物でも良いし、ポリフッ化ビニリデン等の有機物でも良い。圧電体の作製方法は、スパッタ法、化学的気相成長法、ゾルゲル法、塗布法等の方法が可能である。 The piezoelectric material may be an oxide such as BaTiO 3 , LiNbO 3 , or ZnO, a nitride such as AlN, or an organic material such as polyvinylidene fluoride. As a method for manufacturing the piezoelectric body, a sputtering method, a chemical vapor deposition method, a sol-gel method, a coating method, or the like can be used.

圧電体は、メモリ素子積層体の側部に配置することができる。その際、圧電体は、メモリ素子積層体に接触して配置することもでき、あるいはメモリ素子積層体から離れて配置することもできる。圧電体は、非磁性層を残して参照層と記録層の間の側部に配置することもできる。圧電体は、メモリ素子積層体の下に、あるいは上に配置することもできる。圧電体は、非磁性層と参照層との間、あるいは非磁性層と記録層との間に配置することもできる。圧電体は、記録層と離れたところに配置したアーム等の物理的な力の伝達手段を用いて記録層に力を作用させるように構成することもできる。圧電体は、上記の配置を複数組み合わせた配置とすることもできる。   The piezoelectric body can be disposed on the side of the memory element stack. At that time, the piezoelectric body can be disposed in contact with the memory element stack, or can be disposed away from the memory element stack. The piezoelectric body can also be disposed on the side portion between the reference layer and the recording layer, leaving the nonmagnetic layer. The piezoelectric body can be disposed below or on the memory element stack. The piezoelectric body can also be disposed between the nonmagnetic layer and the reference layer, or between the nonmagnetic layer and the recording layer. The piezoelectric body can also be configured to apply a force to the recording layer by using a physical force transmission means such as an arm arranged at a distance from the recording layer. The piezoelectric body may be arranged by combining a plurality of the above arrangements.

圧電体に形成する電極は、圧電体専用に設けてもよい。圧電体を記録層の一部や参照層の一部、あるいは非磁性層の一部に組み込む場合は、メモリ素子の記録の際に流す電流によって発生する電界によりピエゾ効果が発生する。参照層と記録層との間の非磁性層を、圧電体で構成し、圧電体による非磁性層を介したトンネル電流(スピン注入電流)によって、記録層に対してスピン注入磁化反転を起すように構成することもできる。   The electrode formed on the piezoelectric body may be provided exclusively for the piezoelectric body. When the piezoelectric body is incorporated in a part of the recording layer, a part of the reference layer, or a part of the nonmagnetic layer, a piezo effect is generated by an electric field generated by a current flowing during recording of the memory element. The nonmagnetic layer between the reference layer and the recording layer is made of a piezoelectric material, and a spin injection magnetization reversal is caused to the recording layer by a tunnel current (spin injection current) through the nonmagnetic layer by the piezoelectric material. It can also be configured.

上述の本発明に実施の形態に係るメモリ素子によれば、情報の記録時に、スピン注入電流を流すと同時に、圧電体を変形させてその変形に基く力を記録層へ伝搬し記録層の保磁力を低下させることができる。従って、このメモリ素子を用いれば、情報の保持特性に優れながら、少ないスピン注入電流で記録可能な不揮発性メモリを実現することができる。   According to the memory element according to the embodiment of the present invention described above, a spin injection current is passed during recording of information, and at the same time, the piezoelectric body is deformed and a force based on the deformation is propagated to the recording layer to maintain the recording layer. Magnetic force can be reduced. Therefore, if this memory element is used, a nonvolatile memory capable of recording with a small spin injection current while having excellent information retention characteristics can be realized.

<2.第1実施の形態>
[メモリ素子の概略構成例]
図1に、本発明に係るメモリ素子の第1実施の形態の概略構成を示す。第1実施の形態に係るメモリ素子1は、図1A及びBに示すように、メモリ素子本体2と、圧電素子3とを有して構成される。メモリ素子本体2は、磁化方向が決められた参照層(磁性層)4と、記録情報に依存して磁化方向が変化する記録層(磁性層)5と、参照層4と記録層5間に設けられた非磁性層6が積層され、スピン注入電流で情報を記録層5に記録するメモリ素子積層体7を有する。非磁性層6は、いわゆるトンネルバリア膜と呼ばれる。メモリ素子本体2は、さらにメモリ素子積層体7の表裏面に形成した一対の上部電極8及び下部で9を有する。圧電素子3は、圧電体材料からなる圧電体11と、圧電体11の両面に形成された一対の電極12、13とから成る。
<2. First Embodiment>
[Schematic configuration example of memory element]
FIG. 1 shows a schematic configuration of a first embodiment of a memory element according to the present invention. As shown in FIGS. 1A and 1B, the memory element 1 according to the first embodiment includes a memory element body 2 and a piezoelectric element 3. The memory element body 2 includes a reference layer (magnetic layer) 4 in which the magnetization direction is determined, a recording layer (magnetic layer) 5 in which the magnetization direction changes depending on recording information, and between the reference layer 4 and the recording layer 5. The provided nonmagnetic layer 6 is laminated, and has a memory element laminated body 7 that records information in the recording layer 5 with a spin injection current. The nonmagnetic layer 6 is called a so-called tunnel barrier film. The memory element body 2 further includes a pair of upper electrodes 8 formed on the front and back surfaces of the memory element stack 7 and a lower portion 9. The piezoelectric element 3 includes a piezoelectric body 11 made of a piezoelectric material and a pair of electrodes 12 and 13 formed on both surfaces of the piezoelectric body 11.

圧電体11は、メモリ素子積層体7の側部に設けられる。本実施の形態では、基板15上にメモリ素子本体2が配置され、基板15上のメモリ素子本体2の側部から少し離れて圧電素子3が配置される。圧電素子2には、電極12、13に接続して圧電体11に電界を印加する手段(図示せず)が設けられる。   The piezoelectric body 11 is provided on the side portion of the memory element stack 7. In the present embodiment, the memory element body 2 is disposed on the substrate 15, and the piezoelectric element 3 is disposed slightly apart from the side of the memory element body 2 on the substrate 15. The piezoelectric element 2 is provided with means (not shown) for applying an electric field to the piezoelectric body 11 connected to the electrodes 12 and 13.

記録層5及び参照層4は、平面磁化膜で形成されると共に、直交する長軸と短軸を有する形状、本例では楕円形状もしくは楕円形状に近い形状に形成される。記録層5及び参照層4は、本例では磁歪が正の平面磁化膜で形成される。記録層5及び参照層4は、長軸方向が磁化容易方向であり、短軸方向が磁化困難方向となり、長軸方向に磁化される。圧電素子3は、電極12及び13に所要の電圧を与えて圧電体11に電界を印加したときに圧電体11が電極12及び13の対向方向に圧縮変形するように、圧電材料等を選択して構成される。メモリ素子積層体7は、その長軸方向が圧電体11の圧縮方向に平行するように配置される。   The recording layer 5 and the reference layer 4 are formed of a planar magnetization film, and are formed in a shape having a major axis and a minor axis that are orthogonal, in this example, an elliptical shape or a shape close to an elliptical shape. In this example, the recording layer 5 and the reference layer 4 are formed of a plane magnetic film having a positive magnetostriction. The recording layer 5 and the reference layer 4 are magnetized in the major axis direction with the major axis direction being the easy magnetization direction and the minor axis direction being the magnetization difficult direction. The piezoelectric element 3 selects a piezoelectric material or the like so that the piezoelectric body 11 is compressed and deformed in a direction opposite to the electrodes 12 and 13 when a required voltage is applied to the electrodes 12 and 13 and an electric field is applied to the piezoelectric body 11. Configured. The memory element stacked body 7 is arranged so that the major axis direction thereof is parallel to the compression direction of the piezoelectric body 11.

基板15は、圧電素子3の圧電体11の圧縮変形がメモリ素子積層体7の記録層5に伝搬されて記録層5に圧縮応力を与えるための応力伝播部材となるものである。基板15は、圧電体11の変形に基いて変形し易いように、つまり応力が伝わり易いように、硬質部材16の下に軟質部材17を配置した積層基板で形成される。硬質部材としては、例えばSiO、Al、Si等のセラミック材料を用いることができる。軟質部材としては、Au等の金属、あるいは熱硬化レジスト材料などの有機物などを用いることができる。 The substrate 15 serves as a stress propagation member for applying compressive stress to the recording layer 5 by the compressive deformation of the piezoelectric body 11 of the piezoelectric element 3 being propagated to the recording layer 5 of the memory element stack 7. The substrate 15 is formed of a laminated substrate in which a soft member 17 is disposed below the hard member 16 so that the substrate 15 is easily deformed based on the deformation of the piezoelectric body 11, that is, stress is easily transmitted. The rigid member may be for example a SiO 2, Al 2 O 3, Si 3 N 4 ceramic material or the like. As the soft member, a metal such as Au or an organic material such as a thermosetting resist material can be used.

次に、第1実施の形態に係るメモリ素子1の動作を説明する。情報の記録時、メモリ素子本体2の上部電極8及び下部電極9を通じて記録層5にスピン注入電流が流れる。このスピン注入電流の供給と同時に、圧電素子3に所要の電圧が与えられて圧電体11に電界が印加される。図1Cに示すように、この電界によって圧電体11は、電極12及び13の対向方向に力F1を受けて圧縮変形する。この力F1が基板15に伝わり、さらにメモリ素子本体3にも伝わり、メモリ素子積層体の各層に長軸方向の圧縮応力が誘起される。このとき、記録層5にも力F1が伝搬し長軸方向に圧縮変形する。記録層5は、磁歪が正の平面磁化膜で形成されているので、長軸方向に圧縮応力を受けることにより、逆磁歪効果で磁気異方性が弱まり、記録層5の持力が低下する。記録層5の保磁力の低下で、スピン注入電流を低減することができる。   Next, the operation of the memory element 1 according to the first embodiment will be described. When information is recorded, a spin injection current flows through the recording layer 5 through the upper electrode 8 and the lower electrode 9 of the memory element body 2. Simultaneously with the supply of the spin injection current, a required voltage is applied to the piezoelectric element 3 and an electric field is applied to the piezoelectric body 11. As shown in FIG. 1C, this electric field causes the piezoelectric body 11 to compress and deform under the force F1 in the opposing direction of the electrodes 12 and 13. This force F1 is transmitted to the substrate 15 and further to the memory element body 3, and a compressive stress in the major axis direction is induced in each layer of the memory element stack. At this time, the force F1 propagates to the recording layer 5 and is compressed and deformed in the major axis direction. Since the recording layer 5 is formed of a plane magnetic film having a positive magnetostriction, the recording layer 5 receives a compressive stress in the major axis direction, so that the magnetic anisotropy is weakened due to the inverse magnetostriction effect, and the holding power of the recording layer 5 is reduced. . A decrease in coercive force of the recording layer 5 can reduce the spin injection current.

ここで、圧電体11に印加する電圧が高周波電圧のとき、その周波数は1GHz以上で10GHz以下が好ましい。この範囲を外れると、本発明のスピン注入電流を低減させる効果が小さくなり過ぎて好ましくない。上記の周波数範囲は、以下の各実施の形態においても適用できる。   Here, when the voltage applied to the piezoelectric body 11 is a high-frequency voltage, the frequency is preferably 1 GHz or more and 10 GHz or less. Outside this range, the effect of reducing the spin injection current of the present invention becomes too small, which is not preferable. The above frequency range can also be applied to the following embodiments.

第1実施の形態に係るメモリ素子1によれば、メモリ素子本体2の記録層5に力を及ぼすように圧電素子3を配置し、圧電素子3に電圧をかけながら、メモリ素子積層体7にスピン注入電流を流すことにより、スピン注入電流を低減することができる。従って、記録を安定に保持しながら少ないスピン注入電流で記録が可能であり、しかも実用に供し得る不揮発性メモリを提供することができる。   According to the memory element 1 according to the first embodiment, the piezoelectric element 3 is disposed so as to exert a force on the recording layer 5 of the memory element body 2, and the voltage is applied to the piezoelectric element 3 while the memory element stack 7 is applied. By causing the spin injection current to flow, the spin injection current can be reduced. Therefore, it is possible to provide a non-volatile memory that can be recorded with a small spin injection current while maintaining stable recording and that can be used practically.

[変形例]
図1では、記録層5及び参照層4を磁歪が正の平面磁化膜で形成したメモリ素子1に付いて説明した。これに対し、記録層5及び参照層4を磁歪が負の平面磁化膜で形成したメモリ素子にも適用することができる。この場合は、図1の圧電素子2を、圧電体11の変形方向が磁歪が負の平面磁化膜による記録層及び参照層の短軸方向と平行になるように、基板15上に配置して構成される。この構成によれば、記録時に、圧電体11が圧縮変形し、これに伴い基板15を通じてメモリ素子本体2の記録層5が短軸方向に圧縮変形する。記録層5が磁歪が負の平面磁化膜で形成されるので、短軸方向に圧縮応力を受けることにより、逆磁歪効果で磁気異方性が弱まり、記録層5の保磁力が低下する。記録層5の保磁力の低下で、スピン注入電流を低減することができる。従って、記録を安定に保持しながら少ないスピン注入電流で記録が可能であり、しまも実用に供し得る不揮発性メモリを提供することができる。
[Modification]
In FIG. 1, the memory element 1 in which the recording layer 5 and the reference layer 4 are formed of a plane magnetic film having a positive magnetostriction has been described. On the other hand, the present invention can also be applied to a memory element in which the recording layer 5 and the reference layer 4 are formed of a plane magnetic film having a negative magnetostriction. In this case, the piezoelectric element 2 of FIG. 1 is arranged on the substrate 15 so that the deformation direction of the piezoelectric body 11 is parallel to the short axis direction of the recording layer and the reference layer made of the plane magnetization film having a negative magnetostriction. Composed. According to this configuration, the piezoelectric body 11 is compressed and deformed during recording, and accordingly, the recording layer 5 of the memory element body 2 is compressed and deformed in the minor axis direction through the substrate 15. Since the recording layer 5 is formed of a plane magnetization film having a negative magnetostriction, the magnetic anisotropy is weakened by the inverse magnetostriction effect due to the compressive stress in the minor axis direction, and the coercive force of the recording layer 5 is reduced. A decrease in coercive force of the recording layer 5 can reduce the spin injection current. Therefore, it is possible to provide a non-volatile memory which can be recorded with a small spin injection current while maintaining recording stably and which can be used practically.

<3.第2実施の形態>
図2に、本発明に係るメモリ素子の第2実施の形態の概略構成を示す。図2Aはメモリ素子積層体及びその側部に配置された圧電体を含む概略上面図、図2Bはメモリ素子の概略断面図である。第2実施の形態に係るメモリ素子21は、メモリ素子本体2と、圧電体11とを有して構成される。メモリ素子本体2は、前述と同様に、参照層(磁性層)4と、記録層(磁性層)5と、参照層4と記録層5との間に設けた非磁性層6とが積層されたメモリ素子積層体7と、メモリ素子積層体7の表裏面に形成した上部電極8及び下部電極9とから成る。下部電極9は大きめに形成され、この下部電極9上にメモリ素子積層体7及び上部電極8が積層形成される。
<3. Second Embodiment>
FIG. 2 shows a schematic configuration of a second embodiment of the memory element according to the present invention. FIG. 2A is a schematic top view including a memory element stack and a piezoelectric body disposed on the side thereof, and FIG. 2B is a schematic cross-sectional view of the memory element. A memory element 21 according to the second embodiment includes a memory element body 2 and a piezoelectric body 11. As described above, the memory element body 2 includes a reference layer (magnetic layer) 4, a recording layer (magnetic layer) 5, and a nonmagnetic layer 6 provided between the reference layer 4 and the recording layer 5. The memory element stack 7, and the upper electrode 8 and the lower electrode 9 formed on the front and back surfaces of the memory element stack 7. The lower electrode 9 is formed larger, and the memory element stack 7 and the upper electrode 8 are stacked on the lower electrode 9.

記録層5及び参照層4は、平面磁化膜で形成されると共に、直交する長軸と短軸を有する形状、本例では楕円形状もしくは楕円形状に近い形状に形成される。記録層5及び参照層4は、本例では磁歪が正の平面磁化膜で形成される。記録層5及び参照層4は、長軸方向が磁化容易方向であり、短軸方向が磁化困難方向となり、長軸方向に磁化される。   The recording layer 5 and the reference layer 4 are formed of a planar magnetization film, and are formed in a shape having a major axis and a minor axis that are orthogonal, in this example, an elliptical shape or a shape close to an elliptical shape. In this example, the recording layer 5 and the reference layer 4 are formed of a plane magnetic film having a positive magnetostriction. The recording layer 5 and the reference layer 4 are magnetized in the major axis direction with the major axis direction being the easy magnetization direction and the minor axis direction being the magnetization difficult direction.

一方、圧電体11は、下部電極9上に在って、メモリ素子積層体7の短軸方向の両側部に配置される。圧電体11は、メモリ素子積層体7、特に記録層5に力学的に接続される必要がある。後述するように記録層に引っ張り応力を与える場合、圧電体11は、メモリ素子積層体7に対して、接着などにより機械的に接続する必要がある。このため、本例の圧電体11は、下部電極9の表面に接続し、参照層4から記録層5に至るメモリ素子積層体7の側面に接続して、さらに記録層5の表面に一部延長する断面逆L字形状を有して形成される。圧電体11の延長部も記録層5の表面に接続される。圧電体11は、記録時に記録層と参照層間の非磁性層で発生する電界23を受けて伸び変形するように、圧電材料等を選択して構成される。   On the other hand, the piezoelectric body 11 exists on the lower electrode 9 and is disposed on both sides of the memory element stack 7 in the minor axis direction. The piezoelectric body 11 needs to be mechanically connected to the memory element stack 7, particularly the recording layer 5. As will be described later, when a tensile stress is applied to the recording layer, the piezoelectric body 11 needs to be mechanically connected to the memory element stack 7 by adhesion or the like. Therefore, the piezoelectric body 11 of this example is connected to the surface of the lower electrode 9, connected to the side surface of the memory element stacked body 7 from the reference layer 4 to the recording layer 5, and further partially on the surface of the recording layer 5. It is formed having an inverted L-shaped cross section. An extension portion of the piezoelectric body 11 is also connected to the surface of the recording layer 5. The piezoelectric body 11 is configured by selecting a piezoelectric material or the like so as to receive an electric field 23 generated in the nonmagnetic layer between the recording layer and the reference layer during recording and to be deformed by extension.

さらに、上部電極8と下部電極9との間に記録電圧源22が接続される。この記録電圧源22は、メモリ素子積層体7にスピン注入電流を供給するスピン注入電流供給源と、圧電体11に電界を印加する電圧供給源を兼ねている。   Further, a recording voltage source 22 is connected between the upper electrode 8 and the lower electrode 9. The recording voltage source 22 serves both as a spin injection current supply source that supplies a spin injection current to the memory element stack 7 and a voltage supply source that applies an electric field to the piezoelectric body 11.

次に、第2実施の形態に係るメモリ素子21の動作を説明する。先ず、記録前の圧電体11の状態は、図3Aに示すように、電界が印加されていないので、何ら変形していない。情報の記録時、記録電圧源22からメモリ素子本体2の上部電極8及び下部電極9を通じて記録層5にスピン注入電流が流れる。このとき、同時に非磁性層6を挟む参照層4及び記録層5間に電界23が発生し、この電界23が圧電体11に印加される。圧電体11では、電界23を受けた部分が垂直方向に伸びる(矢印b参照)。この伸びに伴って、圧電体11の全体が、図3Bに示すように、矢印a方向に変形する。つまり、圧電体11の内側が伸びて、外側が変化しないので、結果として圧電体11の柱状部が反り、矢印a方向に変形する。メモリ素子積層体7の短軸方向の両側に配置された圧電体11が、メモリ素子積層体7から離れる方向に変形することにより、図3Cに示すように、記録層5が短軸方向に引っ張り変形し、記録層5に短軸方向の引っ張り応力が発生する。記録層5は、磁歪が正の平面磁化膜で形成されているので、短軸方向の引っ張り応力を受けることにより、逆磁歪効果で磁気異方性が弱まり、記録層5の持力が低下する。記録層5の保磁力の低下で、スピン注入電流を低減することができる。   Next, the operation of the memory element 21 according to the second embodiment will be described. First, the state of the piezoelectric body 11 before recording is not deformed at all because no electric field is applied as shown in FIG. 3A. At the time of recording information, a spin injection current flows from the recording voltage source 22 to the recording layer 5 through the upper electrode 8 and the lower electrode 9 of the memory element body 2. At the same time, an electric field 23 is generated between the reference layer 4 and the recording layer 5 sandwiching the nonmagnetic layer 6, and this electric field 23 is applied to the piezoelectric body 11. In the piezoelectric body 11, the portion receiving the electric field 23 extends in the vertical direction (see arrow b). Along with this elongation, the entire piezoelectric body 11 is deformed in the direction of arrow a as shown in FIG. 3B. That is, the inside of the piezoelectric body 11 extends and the outside does not change. As a result, the columnar portion of the piezoelectric body 11 warps and deforms in the direction of arrow a. As shown in FIG. 3C, the piezoelectric elements 11 disposed on both sides of the memory element stack 7 in the short axis direction are deformed in a direction away from the memory element stack 7, so that the recording layer 5 is pulled in the short axis direction. The recording layer 5 is deformed, and a tensile stress in the minor axis direction is generated. Since the recording layer 5 is formed of a plane magnetization film having a positive magnetostriction, when receiving the tensile stress in the minor axis direction, the magnetic anisotropy is weakened by the inverse magnetostriction effect, and the holding power of the recording layer 5 is reduced. . A decrease in coercive force of the recording layer 5 can reduce the spin injection current.

第2実施の形態に係るメモリ素子21によれば、メモリ素子本体2の記録層5に力を及ぼすように圧電体11を配置し、圧電体11に電界を印加しながら、メモリ素子積層体7にスピン注入電流を流すことにより、スピン注入電流を低減することができる。従って、記録を安定に保持しながら少ないスピン注入電流で記録が可能であり、しまも実用に供し得る不揮発性メモリを提供することができる。   According to the memory element 21 according to the second embodiment, the piezoelectric element 11 is arranged so as to exert a force on the recording layer 5 of the memory element body 2, and an electric field is applied to the piezoelectric element 11, while the memory element stack 7. The spin injection current can be reduced by passing the spin injection current through Therefore, it is possible to provide a non-volatile memory which can be recorded with a small spin injection current while maintaining recording stably and which can be used practically.

[変形例]
図2では、記録層5及び参照層4を磁歪が正の平面磁化膜で形成したメモリ素子21に付いて説明した。これに対し、記録層5及び参照層4を磁歪が負の平面磁化膜で形成したメモリ素子にも適用することができる。この場合は、図2の圧電体11を、メモリ素子積層体7の長軸方向の両側に配置して構成される。この構成によれば、記録時に、圧電体11が図3Bに示すように変形することにより、記録層5は長軸方向に引っ張り変形する。記録層5が磁歪が負の平面磁化膜で形成されるので、長軸方向の引っ張り応力を受けることにより、逆磁歪効果で磁気異方性が弱まり、記録層5の保磁力が低下する。記録層5の保磁力の低下で、スピン注入電流を低減することができる。従って、記録を安定に保持しながら少ないスピン注入電流で記録が可能であり、しまも実用に供し得る不揮発性メモリを提供することができる。
[Modification]
In FIG. 2, the memory element 21 in which the recording layer 5 and the reference layer 4 are formed of a plane magnetic film having a positive magnetostriction has been described. On the other hand, the present invention can also be applied to a memory element in which the recording layer 5 and the reference layer 4 are formed of a plane magnetic film having a negative magnetostriction. In this case, the piezoelectric body 11 of FIG. 2 is arranged on both sides in the major axis direction of the memory element stack 7. According to this configuration, during recording, the piezoelectric layer 11 is deformed as shown in FIG. 3B, whereby the recording layer 5 is pulled and deformed in the major axis direction. Since the recording layer 5 is formed of a plane magnetization film having a negative magnetostriction, the magnetic anisotropy is weakened by the inverse magnetostriction effect due to the tensile stress in the major axis direction, and the coercive force of the recording layer 5 is reduced. A decrease in coercive force of the recording layer 5 can reduce the spin injection current. Therefore, it is possible to provide a non-volatile memory which can be recorded with a small spin injection current while maintaining recording stably and which can be used practically.

<4.第3実施の形態>
[メモリ素子の概略構成例]
図4に、本発明に係るメモリ素子の第3実施の形態の概略構成を示す。第3実施の形態に係るメモリ素子25は、図4A及びBに示すように、メモリ素子本体2と圧電体11とを有して構成される。メモリ素子本体2は、前述と同様に、参照層(磁性層)4と、記録層(磁性層)5と、参照層4と記録層5との間に設けた非磁性層6とが積層されたメモリ素子積層体7と、メモリ素子積層体7の表裏面に形成した上部電極8及び下部電極9とから成る。下部電極9は大きめに形成され、この下部電極9上にメモリ素子積層体7及び上部電極8が積層形成される。
<4. Third Embodiment>
[Schematic configuration example of memory element]
FIG. 4 shows a schematic configuration of the third embodiment of the memory element according to the present invention. As shown in FIGS. 4A and 4B, the memory element 25 according to the third embodiment includes a memory element body 2 and a piezoelectric body 11. As described above, the memory element body 2 includes a reference layer (magnetic layer) 4, a recording layer (magnetic layer) 5, and a nonmagnetic layer 6 provided between the reference layer 4 and the recording layer 5. The memory element stack 7, and the upper electrode 8 and the lower electrode 9 formed on the front and back surfaces of the memory element stack 7. The lower electrode 9 is formed larger, and the memory element stack 7 and the upper electrode 8 are stacked on the lower electrode 9.

記録層5及び参照層4は、垂直磁化膜で形成されると共に、所要の厚みを有して円形状に形成される。記録層5及び参照層4は、本例では磁歪が負の垂直磁化膜で形成される。圧電体11は、下部電極9の表面に接してメモリ素子積層体7の外側面に接触するように、あるいは機械的に接続するように円筒形状に形成される。この円筒形状の圧電体11の外周面には、圧電体11と同じ高さで接触しあるいは機械的に接続して、且つ下部電極9と電気的に接続する金属膜26が形成される。圧電体11は、前述したように、メモリ素子積層体7、特に記録層5に力学的に接続される必要がある。後述するように記録層に圧縮応力を与える場合は、圧電体11をメモリ素子積層体7に対して接触するように配置しても良い。または、圧電体11をメモリ素子積層体7に対して機械的に接続することもできる。圧電体11は、円筒形状の厚み方向に電界を受けたときに、厚みが伸びるような変形を起させるように、圧電材料等を選択して構成される。   The recording layer 5 and the reference layer 4 are formed of a perpendicular magnetization film, and are formed in a circular shape having a required thickness. In this example, the recording layer 5 and the reference layer 4 are formed of perpendicular magnetization films having a negative magnetostriction. The piezoelectric body 11 is formed in a cylindrical shape so as to be in contact with the surface of the lower electrode 9 and to be in contact with the outer surface of the memory element stack 7 or mechanically connected thereto. A metal film 26 is formed on the outer peripheral surface of the cylindrical piezoelectric body 11 so as to be in contact with or mechanically connected to the piezoelectric body 11 and to be electrically connected to the lower electrode 9. As described above, the piezoelectric body 11 needs to be mechanically connected to the memory element stack 7, particularly the recording layer 5. As described later, when compressive stress is applied to the recording layer, the piezoelectric body 11 may be disposed so as to be in contact with the memory element stack 7. Alternatively, the piezoelectric body 11 can be mechanically connected to the memory element stack 7. The piezoelectric body 11 is configured by selecting a piezoelectric material or the like so as to cause a deformation that increases the thickness when an electric field is received in the thickness direction of the cylindrical shape.

さらに、上部電極8と下部電極9との間に記録電圧源22が接続される。この記録電圧源22は、メモリ素子積層体7にスピン注入電流を供給するスピン注入電流供給源と、圧電体11に電界を印加する電圧供給源を兼ねている。   Further, a recording voltage source 22 is connected between the upper electrode 8 and the lower electrode 9. The recording voltage source 22 serves both as a spin injection current supply source that supplies a spin injection current to the memory element stack 7 and a voltage supply source that applies an electric field to the piezoelectric body 11.

次に、第3実施の形態に係るメモリ素子25の動作を説明する。情報の記録時、記録電圧源22からメモリ素子本体2の上部電極8及び下部電極9を通じて記録層5にスピン注入電流が流れる。このとき、同時に上部電極8に接続された記録層5と、下部電極9に接続された金属膜26との間に電界27が発生する。つまり、圧電体11の記録層5に対応する内部に電界27が印加されることになる(図4B参照)。圧電体11は、電界27を受けた部分が厚み方向に伸びるように変形する。図5に示すように、圧電体11の上記変形に伴い、記録層5は外周から力が加わり圧縮応力を受ける。円形状の記録層5は、磁歪が負の垂直磁化膜で形成されているので、圧縮応力を受けることにより、逆磁歪効果で磁気異方性が弱まり、記録層5の保磁力が低下する。記録層5の保磁力の低下で、スピン注入電流を低減することができる。   Next, the operation of the memory element 25 according to the third embodiment will be described. At the time of recording information, a spin injection current flows from the recording voltage source 22 to the recording layer 5 through the upper electrode 8 and the lower electrode 9 of the memory element body 2. At this time, an electric field 27 is generated between the recording layer 5 connected to the upper electrode 8 and the metal film 26 connected to the lower electrode 9 at the same time. That is, the electric field 27 is applied to the inside corresponding to the recording layer 5 of the piezoelectric body 11 (see FIG. 4B). The piezoelectric body 11 is deformed so that the portion receiving the electric field 27 extends in the thickness direction. As shown in FIG. 5, along with the deformation of the piezoelectric body 11, the recording layer 5 receives a compressive stress by applying a force from the outer periphery. Since the circular recording layer 5 is formed of a perpendicularly magnetized film having a negative magnetostriction, the magnetic anisotropy is weakened by the inverse magnetostriction effect due to the compressive stress, and the coercive force of the recording layer 5 is reduced. A decrease in coercive force of the recording layer 5 can reduce the spin injection current.

第3実施の形態に係るメモリ素子25によれば、メモリ素子本体2の記録層5に力を及ぼすように圧電体11を配置し、圧電体11に電界を印加しながら、メモリ素子積層体7にスピン注入電流を流すことにより、スピン注入電流を低減することができる。従って、記録を安定に保持しながら少ないスピン注入電流で記録が可能であり、しまも実用に供し得る不揮発性メモリを提供することができる。   According to the memory element 25 according to the third embodiment, the piezoelectric element 11 is arranged so as to exert a force on the recording layer 5 of the memory element body 2, and an electric field is applied to the piezoelectric element 11, while the memory element stack 7. The spin injection current can be reduced by passing the spin injection current through Therefore, it is possible to provide a non-volatile memory which can be recorded with a small spin injection current while maintaining recording stably and which can be used practically.

[変形例]
図4では、記録層5及び参照層4を磁歪が負の垂直磁化膜で形成したメモリ素子25に付いて説明した。これに対し、記録層5及び参照層4を磁歪が正の垂直磁化膜で形成したメモリ素子にも適用することができる。この場合は、図4の圧電体11を、記録層5に対して引っ張り応力を与えるような構成とする。このため、圧電体11は、メモリ素子積層体7に対して機械的に接続するように配置される。このようにすれば、記録時に、圧電体11の変形で記録層5に引っ張り応力を与えることができる。記録層5は磁歪が正の垂直磁化膜で形成されることにより、逆磁歪効果で磁気異方性が弱まり、記録層5の保磁力が低下する。記録層5の保磁力の低下で、スピン注入電流を低減することができる。従って、記録を安定に保持しながら少ないスピン注入電流で記録が可能であり、しまも実用に供し得る不揮発性メモリを提供することができる。
[Modification]
In FIG. 4, the memory element 25 in which the recording layer 5 and the reference layer 4 are formed of a perpendicular magnetization film having a negative magnetostriction has been described. On the other hand, the present invention can also be applied to a memory element in which the recording layer 5 and the reference layer 4 are formed by a perpendicular magnetization film having a positive magnetostriction. In this case, the piezoelectric body 11 of FIG. 4 is configured to give a tensile stress to the recording layer 5. For this reason, the piezoelectric body 11 is disposed so as to be mechanically connected to the memory element stack 7. In this way, a tensile stress can be applied to the recording layer 5 by deformation of the piezoelectric body 11 during recording. Since the recording layer 5 is formed of a perpendicular magnetization film having a positive magnetostriction, the magnetic anisotropy is weakened due to the inverse magnetostriction effect, and the coercive force of the recording layer 5 is reduced. A decrease in coercive force of the recording layer 5 can reduce the spin injection current. Therefore, it is possible to provide a non-volatile memory which can be recorded with a small spin injection current while maintaining recording stably and which can be used practically.

<5.第4実施の形態>
[メモリ素子の概略構成例]
図6に、本発明に係るメモリ素子の第4実施の形態の概略構成を示す。第4実施の形態に係るメモリ素子31は、メモリ素子本体2と、メモリ素子積層体の側部に設けられた圧電体11とを有して構成される。メモリ素子本体2は、前述と同様に、参照層(磁性層)4と、記録層(磁性層)5と、参照層4と記録層5との間に設けた非磁性層6とが積層されたメモリ素子積層体7と、メモリ素子積層体7の表裏面に形成した上部電極8及び下部電極9とから成る。
<5. Fourth Embodiment>
[Schematic configuration example of memory element]
FIG. 6 shows a schematic configuration of the fourth embodiment of the memory element according to the present invention. A memory element 31 according to the fourth embodiment includes a memory element body 2 and a piezoelectric body 11 provided on a side portion of the memory element stack. As described above, the memory element body 2 includes a reference layer (magnetic layer) 4, a recording layer (magnetic layer) 5, and a nonmagnetic layer 6 provided between the reference layer 4 and the recording layer 5. The memory element stack 7, and the upper electrode 8 and the lower electrode 9 formed on the front and back surfaces of the memory element stack 7.

記録層5及び参照層4は、平面磁化膜で形成することもでき、あるいは垂直磁化膜で形成することもできる。つまり、本メモリ素子本体2は、記録層5及び参照層4として、面内磁化膜、垂直磁化膜のいずれにも適応可能である。   The recording layer 5 and the reference layer 4 can be formed of a planar magnetization film or can be formed of a perpendicular magnetization film. That is, the memory element body 2 can be applied to both the in-plane magnetization film and the perpendicular magnetization film as the recording layer 5 and the reference layer 4.

一方、圧電体11は、参照層4と記録層5との間在って中央部でない側部に形成される。つまり、圧電体11は、非磁性層の中央部を残して、参照層4と記録層5との間の端部側に埋め込むように形成される。この圧電体11は、厚み方向に変形する圧電体で形成される。例えば、圧電体11は、厚み方向に伸び変形する圧電体、あるいは厚み方向に圧縮変形する圧電体で形成することができる。   On the other hand, the piezoelectric body 11 is formed between the reference layer 4 and the recording layer 5 on the side portion that is not the central portion. That is, the piezoelectric body 11 is formed so as to be embedded on the end portion side between the reference layer 4 and the recording layer 5, leaving the central portion of the nonmagnetic layer. The piezoelectric body 11 is formed of a piezoelectric body that deforms in the thickness direction. For example, the piezoelectric body 11 can be formed of a piezoelectric body that extends and deforms in the thickness direction, or a piezoelectric body that compressively deforms in the thickness direction.

記録層5は、圧電体11の厚み方向の変形に基いて、上部、下部で圧縮応力、引っ張り応力、あるいはその逆の応力が発生するので上部と下部で磁歪の極性を変えた2層の磁性積層膜で形成することができる。あるいは、記録層5は、上部を非磁性金属膜で形成することもできる。   The recording layer 5 generates compressive stress, tensile stress, or vice versa in the upper and lower portions based on the deformation of the piezoelectric body 11 in the thickness direction. It can be formed of a laminated film. Alternatively, the recording layer 5 can be formed of a nonmagnetic metal film at the top.

さらに、上部電極8と下部電極9との間に記録電圧源22が接続される。この記録電圧源22は、メモリ素子積層体7にスピン注入電流を供給するスピン注入電流供給源と、圧電体11に電界を印加する電圧供給源を兼ねている。   Further, a recording voltage source 22 is connected between the upper electrode 8 and the lower electrode 9. The recording voltage source 22 serves both as a spin injection current supply source that supplies a spin injection current to the memory element stack 7 and a voltage supply source that applies an electric field to the piezoelectric body 11.

[メモリ素子の製造方法例]
図7に第4実施の形態に係るメモリ素子31の製造方法例、特にその圧電体を埋め込んだメモリ素子積層体の製法例を示す。図7は、非磁性層6内に圧電体11を形成する方法の概略図である。先ず、図7Aに示すように、参照層4、非磁性層6及び記録層5を積層したメモリ素子積層体7を形成する。
[Example of memory device manufacturing method]
FIG. 7 shows an example of a method for manufacturing the memory element 31 according to the fourth embodiment, in particular, a method for manufacturing a memory element laminated body in which the piezoelectric body is embedded. FIG. 7 is a schematic view of a method of forming the piezoelectric body 11 in the nonmagnetic layer 6. First, as shown in FIG. 7A, a memory element stack 7 in which a reference layer 4, a nonmagnetic layer 6, and a recording layer 5 are stacked is formed.

次に、図7Bに示すように、化学エッチングなどにより非磁性層の一部を選択的に除去する。すなわち、非磁性層6の中央部を残して、端部側を選択的に除去し、隙間33を形成する。   Next, as shown in FIG. 7B, a part of the nonmagnetic layer is selectively removed by chemical etching or the like. That is, the end portion side is selectively removed leaving the central portion of the nonmagnetic layer 6 to form the gap 33.

次に、図7Cに示すように、例えばゾルゲル法、CVD法などにより、非磁性層6が除去された隙間33内に圧電体材料11Aを充填する。このとき、圧電体材料11Aはメモリ素子積層体7の外周にも被着される。   Next, as shown in FIG. 7C, the piezoelectric material 11A is filled into the gap 33 from which the nonmagnetic layer 6 has been removed by, for example, a sol-gel method or a CVD method. At this time, the piezoelectric material 11 </ b> A is also attached to the outer periphery of the memory element stack 7.

次に、図7Dに示すように、メモリ素子積層体7の外周に被着されている圧電体材料11Aを除去する。これにより、参照層4と記録層5に間に中央の非磁性層6を残して、圧電体11を埋め込んだメモリ素子積層体7が得られる。   Next, as shown in FIG. 7D, the piezoelectric material 11A attached to the outer periphery of the memory element stack 7 is removed. As a result, the memory element stack 7 in which the piezoelectric body 11 is embedded, leaving the central nonmagnetic layer 6 between the reference layer 4 and the recording layer 5 is obtained.

次に、第4実施の形態に係るメモリ素子31の動作を説明する。情報の記録時、記録電圧源22からメモリ素子本体2の上部電極8及び下部電極9を通じて記録層5にスピン注入電流が流れる。このとき、同時に記録層5と参照層4間に挟まれた圧電体11に電界が印加される。この電界で、例えば、図8に示すように、圧電体11が厚み方向に伸びるように変形したときには、記録層5が下に凹状となるように変形されることにより、記録層5の上部は圧縮されて圧縮応力が発生し、下部は引っ張られて引っ張り応力が発生する。   Next, the operation of the memory element 31 according to the fourth embodiment will be described. At the time of recording information, a spin injection current flows from the recording voltage source 22 to the recording layer 5 through the upper electrode 8 and the lower electrode 9 of the memory element body 2. At this time, an electric field is simultaneously applied to the piezoelectric body 11 sandwiched between the recording layer 5 and the reference layer 4. With this electric field, for example, as shown in FIG. 8, when the piezoelectric body 11 is deformed so as to extend in the thickness direction, the recording layer 5 is deformed so as to be concave downward, so that the upper portion of the recording layer 5 is Compressive stress is generated by compression, and the lower portion is pulled to generate tensile stress.

記録層5を面内磁化膜で形成することきは、記録層5の圧縮応力が生じる上部を磁歪が正の面内磁化膜で形成し、引っ張り応力が生じる下部を磁歪が負の面内磁化膜で形成すれば、逆磁歪効果で磁気異方性が弱まり、記録層5の保磁力が低下する。記録層5の保磁力の低下で、スピン注入電流を低減することができる。記録層5を垂直磁化膜で形成することきは、記録層5の圧縮応力が生じる上部を磁歪が負の垂直磁化膜で形成し、引っ張り応力が生じる下部を磁歪が正の垂直磁化膜で形成すれば、逆磁歪効果で磁気異方性が弱まり、記録層5の保磁力が低下する。記録層5の保磁力の低下で、スピン注入電流を低減することができる。   When the recording layer 5 is formed of an in-plane magnetized film, the upper part of the recording layer 5 where the compressive stress is generated is formed of an in-plane magnetized film with a positive magnetostriction, and the lower part where the tensile stress is generated is in-plane magnetization with a negative magnetostriction. If formed of a film, the magnetic anisotropy is weakened by the inverse magnetostrictive effect, and the coercive force of the recording layer 5 is lowered. A decrease in coercive force of the recording layer 5 can reduce the spin injection current. When the recording layer 5 is formed of a perpendicular magnetization film, the upper portion where the compressive stress of the recording layer 5 is formed is formed of a perpendicular magnetization film having a negative magnetostriction, and the lower portion where the tensile stress is generated is formed of a perpendicular magnetization film having a positive magnetostriction. If so, the magnetic anisotropy is weakened by the inverse magnetostriction effect, and the coercive force of the recording layer 5 is lowered. A decrease in coercive force of the recording layer 5 can reduce the spin injection current.

図示しないが、上記電界で圧電体11が逆に厚み方向に縮むように変形したときは、記録層5が上に凸状となるように変形されることにより、記録層5の下部は圧縮されて圧縮応力が発生し、上部は引っ張られて引っ張り応力が発生する。記録層5を面内磁化膜で形成することきは、記録層5の圧縮応力が生じる下部を磁歪が正の面内磁化膜で形成し、引っ張り応力が生じる上部を磁歪が負の面内磁化膜で形成すれば、逆磁歪効果で磁気異方性が弱まり、記録層5の保磁力が低下する。記録層5の保磁力の低下で、スピン注入電流を低減することができる。記録層5を垂直磁化膜で形成することきは、記録層5の圧縮応力が生じる下部を磁歪が負の垂直磁化膜で形成し、引っ張り応力が生じる上部を磁歪が正の垂直磁化膜で形成すれば、逆磁歪効果で磁気異方性が弱まり、記録層5の保磁力が低下する。記録層5の保磁力の低下で、スピン注入電流を低減することができる。   Although not shown, when the piezoelectric body 11 is deformed so as to shrink in the thickness direction by the electric field, the lower portion of the recording layer 5 is compressed by deforming the recording layer 5 to be convex upward. A compressive stress is generated, and the upper part is pulled to generate a tensile stress. When the recording layer 5 is formed of an in-plane magnetization film, the lower portion of the recording layer 5 where the compressive stress is generated is formed of an in-plane magnetization film having a positive magnetostriction, and the upper portion where the tensile stress is generated is in-plane magnetization having a negative magnetostriction. If formed of a film, the magnetic anisotropy is weakened by the inverse magnetostrictive effect, and the coercive force of the recording layer 5 is lowered. A decrease in coercive force of the recording layer 5 can reduce the spin injection current. When the recording layer 5 is formed of a perpendicular magnetization film, the lower portion of the recording layer 5 where the compressive stress is generated is formed of a perpendicular magnetization film having a negative magnetostriction, and the upper portion where the tensile stress is generated is formed of a perpendicular magnetization film having a positive magnetostriction. If so, the magnetic anisotropy is weakened by the inverse magnetostriction effect, and the coercive force of the recording layer 5 is lowered. A decrease in coercive force of the recording layer 5 can reduce the spin injection current.

また、記録層5は、図8において、上部と下部で磁歪の極性を変える構成とせず、上部を非磁性金属層にすれば、上部の影響を無くして、スピン注入電流を低減することができる。   Further, the recording layer 5 is not configured to change the polarity of magnetostriction between the upper part and the lower part in FIG. 8, and if the upper part is made of a nonmagnetic metal layer, the influence of the upper part can be eliminated and the spin injection current can be reduced. .

第4実施の形態に係るメモリ素子31によれば、前述と同様に、圧電体11に電界を印加しながら、メモリ素子積層体7にスピン注入電流を流すことにより、スピン注入電流を低減することができる。従って、記録を安定に保持しながら少ないスピン注入電流で記録が可能であり、しまも実用に供し得る不揮発性メモリを提供することができる。   According to the memory element 31 according to the fourth embodiment, the spin injection current can be reduced by applying the spin injection current to the memory element stack 7 while applying an electric field to the piezoelectric body 11 as described above. Can do. Therefore, it is possible to provide a non-volatile memory which can be recorded with a small spin injection current while maintaining recording stably and which can be used practically.

<6.第5実施の形態>
[メモリ素子の概略構成例]
図9に、本発明に係るメモリ素子の第5実施の形態の概略構成を示す。第5実施の形態に係るメモリ素子35は、基板36上に圧電素子37とメモリ素子本体2とを積層して構成される。メモリ素子本体2は、前述と同様に、参照層(磁性層)4と、記録層(磁性層)5と、参照層4と記録層5との間に設けた非磁性層6とが積層されたメモリ素子積層体7と、メモリ素子積層体7の表裏面に形成した上部電極8及び下部電極9とから成る。圧電素子37は、基板36の表面上に一方の電極38、圧電体11及び他方の電極39を積層して形成される。他方の電極39は、上記メモリ素子本体2の下部電極9と共用している。
<6. Fifth embodiment>
[Schematic configuration example of memory element]
FIG. 9 shows a schematic configuration of the fifth embodiment of the memory element according to the present invention. A memory element 35 according to the fifth embodiment is configured by stacking a piezoelectric element 37 and a memory element body 2 on a substrate 36. As described above, the memory element body 2 includes a reference layer (magnetic layer) 4, a recording layer (magnetic layer) 5, and a nonmagnetic layer 6 provided between the reference layer 4 and the recording layer 5. The memory element stack 7, and the upper electrode 8 and the lower electrode 9 formed on the front and back surfaces of the memory element stack 7. The piezoelectric element 37 is formed by laminating one electrode 38, the piezoelectric body 11 and the other electrode 39 on the surface of the substrate 36. The other electrode 39 is shared with the lower electrode 9 of the memory element body 2.

記録層5及び参照層4は、前述の実施の形態で説明したように、平面磁化膜あるいは主直磁化膜、さらに磁歪の極性を選択して形成される。   As described in the above embodiment, the recording layer 5 and the reference layer 4 are formed by selecting the plane magnetization film or the main direct magnetization film, and the magnetostriction polarity.

圧電素子37の圧電体11は、ピエゾ効果で膜厚が変わるように構成される。メモリ素子本体2の上部電極8は、メモリ素子積層部7が圧電素子の変形に基いて変形し易いように、空隙41を有する凹状に形成される。上部電極8を圧電素子37及びメモリ素子本体2は、例えばシリコン酸化膜などによる絶縁充填材層42により埋め込まれる。   The piezoelectric body 11 of the piezoelectric element 37 is configured such that the film thickness changes due to the piezoelectric effect. The upper electrode 8 of the memory element body 2 is formed in a concave shape having a gap 41 so that the memory element stacking portion 7 is easily deformed based on deformation of the piezoelectric element. The upper electrode 8 is embedded in the piezoelectric element 37 and the memory element body 2 by an insulating filler layer 42 made of, for example, a silicon oxide film.

図示しないが、圧電素子37の一対の電極38及び39(9)間には所要の電圧を印加するための電圧供給源が接続される。また、メモリ素子本体2の上部電極8及び下部電極9間にはスピン注入電流を流すための記録電圧源が接続される。   Although not shown, a voltage supply source for applying a required voltage is connected between the pair of electrodes 38 and 39 (9) of the piezoelectric element 37. Further, a recording voltage source for flowing a spin injection current is connected between the upper electrode 8 and the lower electrode 9 of the memory element body 2.

次に、第5実施の形態に係るメモリ素子35の動作を説明する。情報の記録時、メモリ素子本体2の記録層5にスピン注入電流を流すと同時に、圧電素子37に電圧を印加して圧電体11を厚み方向に変形させる。圧電体11の厚み方向の変形が記録層5に伝搬して、記録層5が変形し、逆磁歪効果で記録層5の磁気異方性が弱まり、保磁力が低下し、スピン注入電流が低減する。   Next, the operation of the memory element 35 according to the fifth embodiment will be described. At the time of recording information, a spin injection current is applied to the recording layer 5 of the memory element body 2 and at the same time, a voltage is applied to the piezoelectric element 37 to deform the piezoelectric body 11 in the thickness direction. The deformation in the thickness direction of the piezoelectric body 11 propagates to the recording layer 5 to deform the recording layer 5. The magnetic anisotropy of the recording layer 5 is weakened by the inverse magnetostrictive effect, the coercive force is lowered, and the spin injection current is reduced. To do.

第5実施の形態に係るメモリ素子35によれば、前述と同様に、圧電素子37に電圧を印加しながら、メモリ素子積層体7にスピン注入電流を流すことにより、スピン注入電流を低減することができる。従って、記録を安定に保持しながら少ないスピン注入電流で記録が可能であり、しかも実用に供し得る不揮発性メモリを提供することができる。
さらに、本実施の形態では、メモリ素子本体2の上部電極8を空隙41を有する凹状に形成されるので、圧電素子37での変形に基く記録層5に対する変形をし易くすることができる。また、圧電素子37の他方の電極39とメモリ素子本体2の下部電極9とを共用しているので、メモリ素子35の全体の構成を簡略化できる。
According to the memory element 35 of the fifth embodiment, the spin injection current can be reduced by causing the spin injection current to flow through the memory element stack 7 while applying a voltage to the piezoelectric element 37 as described above. Can do. Therefore, it is possible to provide a non-volatile memory that can be recorded with a small spin injection current while maintaining stable recording and that can be used practically.
Furthermore, in the present embodiment, since the upper electrode 8 of the memory element body 2 is formed in a concave shape having the gap 41, the recording layer 5 can be easily deformed based on the deformation of the piezoelectric element 37. Further, since the other electrode 39 of the piezoelectric element 37 and the lower electrode 9 of the memory element body 2 are shared, the entire configuration of the memory element 35 can be simplified.

[変形例]
図9に示すメモリ素子35は、圧電素子37をメモリ素子本体2の下部に配置して構成したが、図示しないが、圧電素子37をメモリ素子本体2の上部に配置して構成することもできる。この場合、上部電極9は平面状に形成され、圧電素子37の一方の電極38と共用される。かかる構成のメモリ素子においても、圧電素子37に電圧を印加しながら、メモリ素子積層体7にスピン注入電流を流すことにより、スピン注入電流を低減することができる。従って、記録を安定に保持しながら少ないスピン注入電流で記録が可能であり、しかも実用に供し得る不揮発性メモリを提供することができる。
[Modification]
The memory element 35 shown in FIG. 9 is configured by arranging the piezoelectric element 37 in the lower part of the memory element body 2. However, although not shown, the piezoelectric element 37 may be arranged in the upper part of the memory element body 2. . In this case, the upper electrode 9 is formed in a planar shape and is shared with one electrode 38 of the piezoelectric element 37. Even in the memory element having such a configuration, the spin injection current can be reduced by applying a spin injection current to the memory element stack 7 while applying a voltage to the piezoelectric element 37. Therefore, it is possible to provide a non-volatile memory that can be recorded with a small spin injection current while maintaining stable recording and that can be used practically.

<7.第6実施の形態>
[メモリ素子の概略構成例]
図10に、本発明に係るメモリ素子の第6実施の形態の概略構成を示す。第6実施の形態に係るメモリ素子45は、第5実施の形態と同様に、基板36上に圧電素子37とメモリ素子本体とを積層して構成される。
<7. Sixth Embodiment>
[Schematic configuration example of memory element]
FIG. 10 shows a schematic configuration of the sixth embodiment of the memory element according to the present invention. Similar to the fifth embodiment, the memory element 45 according to the sixth embodiment is configured by stacking a piezoelectric element 37 and a memory element body on a substrate 36.

そして、本実施の形態では、特に、基板36のメモリ素子本体2及び圧電素子37の直下に対応する位置に空隙46が形成される。この空隙46は、圧電素子37の圧電体11の変形に基くメモリ素子積層体7の変形をし易くする。
メモリ素子本体2、圧電素子37などを含むその他の構成は、第5実施の形態で説明したと同様であるので、図10において、図9と対応する部分に同一符号を付して重複説明を省略する。
In the present embodiment, the air gap 46 is formed at a position corresponding to the memory element body 2 and the piezoelectric element 37 of the substrate 36 immediately below. The gap 46 facilitates the deformation of the memory element stacked body 7 based on the deformation of the piezoelectric body 11 of the piezoelectric element 37.
Other configurations including the memory element body 2, the piezoelectric element 37, and the like are the same as those described in the fifth embodiment. Therefore, in FIG. Omitted.

第6実施の形態に係るメモリ素子45によれば、前述と同様に、圧電素子37に電圧を印加しながら、メモリ素子積層体7にスピン注入電流を流すことにより、スピン注入電流を低減することができる。従って、記録を安定に保持しながら少ないスピン注入電流で記録が可能であり、しかも実用に供し得る不揮発性メモリを提供することができる。
さらに、本実施の形態では、基板36のメモリ素子本体2及び圧電素子37の直下の部分に空隙46を有するので、圧電素子37での変形に基く記録層5に対する変形をし易くすることができる。
[変形例]
上述の基板に空洞46を設ける構成は、第1〜第4実施の形態の構成にも適用できる。
According to the memory element 45 according to the sixth embodiment, the spin injection current can be reduced by applying the spin injection current to the memory element stack 7 while applying a voltage to the piezoelectric element 37, as described above. Can do. Therefore, it is possible to provide a non-volatile memory that can be recorded with a small spin injection current while maintaining stable recording and that can be used practically.
Further, in the present embodiment, since the gap 46 is provided in the portion immediately below the memory element body 2 and the piezoelectric element 37 of the substrate 36, the recording layer 5 can be easily deformed based on the deformation of the piezoelectric element 37. .
[Modification]
The above-described configuration in which the cavity 46 is provided in the substrate can also be applied to the configurations of the first to fourth embodiments.

<8.第7実施の形態>
[メモリ素子の概略構成例]
図11に、本発明に係るメモリ素子の第7実施の形態の概略構成を示す。第7実施の形態に係るメモリ素子48は、第5実施の形態と同様に、基板36上に圧電素子37とメモリ素子本体とを積層して構成される。
<8. Seventh Embodiment>
[Schematic configuration example of memory element]
FIG. 11 shows a schematic configuration of the seventh embodiment of the memory element according to the present invention. As in the fifth embodiment, the memory element 48 according to the seventh embodiment is configured by stacking a piezoelectric element 37 and a memory element body on a substrate 36.

そして、本実施の形態では、特に、基板36と圧電素子37との間に基板36より高い弾性を有する高弾性部材49が介挿される。この高弾性部材49は、圧電素子37の圧電体11の変形に基くメモリ素子積層体7の変形をし易くする。高弾性部材49としては、例えばゴム部材などを用いることができる。
メモリ素子本体2、圧電素子37などを含むその他の構成は、第5実施の形態で説明したと同様であるので、図11において、図9と対応する部分に同一符号を付して重複説明を省略する。
In the present embodiment, in particular, a highly elastic member 49 having higher elasticity than the substrate 36 is interposed between the substrate 36 and the piezoelectric element 37. The highly elastic member 49 facilitates the deformation of the memory element stack 7 based on the deformation of the piezoelectric body 11 of the piezoelectric element 37. As the highly elastic member 49, for example, a rubber member or the like can be used.
Other configurations including the memory element body 2 and the piezoelectric element 37 are the same as those described in the fifth embodiment. Therefore, in FIG. 11, portions corresponding to those in FIG. Omitted.

第7実施の形態に係るメモリ素子48によれば、前述と同様に、圧電素子37に電圧を印加しながら、メモリ素子積層体7にスピン注入電流を流すことにより、スピン注入電流を低減することができる。従って、記録を安定に保持しながら少ないスピン注入電流で記録が可能であり、しかも実用に供し得る不揮発性メモリを提供することができる。
さらに、本実施の形態では、基板36と圧電素子37との間に高弾性部材49を有するので、圧電素子37での変形に基く記録層5に対する変形をし易くすることができる。
[変形例]
上述の高弾性部材49を設ける構成は、第1〜第4実施の形態の構成にも適用できる。
According to the memory element 48 according to the seventh embodiment, the spin injection current can be reduced by flowing the spin injection current through the memory element stacked body 7 while applying a voltage to the piezoelectric element 37 as described above. Can do. Therefore, it is possible to provide a non-volatile memory that can be recorded with a small spin injection current while maintaining stable recording and that can be used practically.
Further, in the present embodiment, since the highly elastic member 49 is provided between the substrate 36 and the piezoelectric element 37, the recording layer 5 can be easily deformed based on the deformation of the piezoelectric element 37.
[Modification]
The structure provided with the above-described highly elastic member 49 can also be applied to the structures of the first to fourth embodiments.

<9.第8実施の形態>
[メモリ素子の概略構成例]
図12に、本発明に係るメモリ素子の第8実施の形態の概略構成を示す。第8実施の形態に係るメモリ素子51は、基板52上に、メモリ素子積層体54と、メモリ素子積層体54の表裏面に形成した上部電極8及び下部電極9とからなるメモリ素子本体55を形成して構成される。メモリ素子積層体54は、参照層(磁性層)4と、記録層(磁性層)5と、参照層4と記録層5との間に設けた非磁性層53とが積層して形成される。記録層5及び参照層4は、前述の実施の形態で説明したように、平面磁化膜あるいは主直磁化膜、さらに磁歪の極性を選択して形成される。
<9. Eighth Embodiment>
[Schematic configuration example of memory element]
FIG. 12 shows a schematic configuration of the eighth embodiment of the memory element according to the present invention. A memory element 51 according to the eighth embodiment includes a memory element body 55 including a memory element stacked body 54 and upper and lower electrodes 8 and 9 formed on the front and back surfaces of the memory element stacked body 54 on a substrate 52. Formed and configured. The memory element laminate 54 is formed by laminating a reference layer (magnetic layer) 4, a recording layer (magnetic layer) 5, and a nonmagnetic layer 53 provided between the reference layer 4 and the recording layer 5. . As described in the above embodiment, the recording layer 5 and the reference layer 4 are formed by selecting the plane magnetization film or the main direct magnetization film, and the magnetostriction polarity.

そして、本実施の形態では、特に、非磁性層53を圧電体膜で形成される。この圧電体膜は、ピエゾ効果で膜厚が変わるように構成される。この圧電体膜は、スピン注入電流が流れるトンネルバリア膜として機能するように、膜厚が選定される。メモリ素子本体2の上部電極8及び下部電極9間にはスピン注入電流を流すための記録電圧源56が接続される。   In this embodiment, in particular, the nonmagnetic layer 53 is formed of a piezoelectric film. This piezoelectric film is configured so that the film thickness changes due to the piezoelectric effect. The thickness of the piezoelectric film is selected so as to function as a tunnel barrier film through which a spin injection current flows. A recording voltage source 56 for flowing a spin injection current is connected between the upper electrode 8 and the lower electrode 9 of the memory element body 2.

次に、第8実施の形態に係るメモリ素子51の動作を説明する。情報の記録時、記録電圧源56から上部電極8及び下部電極9を通じて、メモリ素子本体2の記録層5にスピン注入電流が流れて記録が行われる。このとき、非磁性層53を構成する圧電体膜に電界が発生することにより、ピエゾ効果で非磁性層53が膜厚方向に変形する。この非磁性層53の変形が記録層5に伝搬して、記録層5が変形し、逆磁歪効果で記録層5の磁気異方性が弱まり、保磁力が低下し、スピン注入電流が低減する。   Next, the operation of the memory element 51 according to the eighth embodiment will be described. When information is recorded, recording is performed by a spin injection current flowing from the recording voltage source 56 to the recording layer 5 of the memory element body 2 through the upper electrode 8 and the lower electrode 9. At this time, when an electric field is generated in the piezoelectric film constituting the nonmagnetic layer 53, the nonmagnetic layer 53 is deformed in the film thickness direction due to the piezoelectric effect. The deformation of the nonmagnetic layer 53 propagates to the recording layer 5 to deform the recording layer 5. The magnetic anisotropy of the recording layer 5 is weakened by the inverse magnetostriction effect, the coercive force is lowered, and the spin injection current is reduced. .

第8実施の形態に係るメモリ素子51によれば、非磁性層53を圧電体膜で形成することによって、スピン注入電流を低減することができる。従って、記録を安定に保持しながら少ないスピン注入電流で記録が可能であり、しかも実用に供し得る不揮発性メモリを提供することができる。また、非磁性層53を圧電体で形成することにより、メモリ素子全体の構成を簡素化することができる。   According to the memory element 51 according to the eighth embodiment, the spin injection current can be reduced by forming the nonmagnetic layer 53 with a piezoelectric film. Therefore, it is possible to provide a non-volatile memory that can be recorded with a small spin injection current while maintaining stable recording and that can be used practically. Further, by forming the nonmagnetic layer 53 with a piezoelectric body, the configuration of the entire memory element can be simplified.

<10.第9実施の形態>
[メモリ素子の概略構成例]
図13A、Bに、本発明に係るメモリ素子の第9実施の形態の概略構成を示す。図13Aに示す第9実施の形態に係るメモリ素子57は、メモリ素子本体2と、圧電体11とを有して構成される。メモリ素子本体2は、前述と同様に、参照層(磁性層)4と、記録層(磁性層)5と、参照層4と記録層5との間に設けた非磁性層6とが積層されたメモリ素子積層体7と、メモリ素子積層体7の表裏面に形成した上部電極8及び下部電極9とから成る。記録層5及び参照層4は、磁歪が正あるいは負の垂直磁化膜で形成することができる。
<10. Ninth Embodiment>
[Schematic configuration example of memory element]
13A and 13B show a schematic configuration of the ninth embodiment of the memory element according to the present invention. A memory element 57 according to the ninth embodiment illustrated in FIG. 13A includes the memory element body 2 and the piezoelectric body 11. As described above, the memory element body 2 includes a reference layer (magnetic layer) 4, a recording layer (magnetic layer) 5, and a nonmagnetic layer 6 provided between the reference layer 4 and the recording layer 5. The memory element stack 7, and the upper electrode 8 and the lower electrode 9 formed on the front and back surfaces of the memory element stack 7. The recording layer 5 and the reference layer 4 can be formed of a perpendicular magnetization film having a positive or negative magnetostriction.

一方、圧電体11は、参照層4と非磁性層6との間に形成される。この圧電体11は、厚み方向に変形する圧電体で形成される。例えば、圧電体11は、厚み方向に伸び変形する圧電体、あるいは厚み方向に圧縮変形する圧電体で形成することができる。   On the other hand, the piezoelectric body 11 is formed between the reference layer 4 and the nonmagnetic layer 6. The piezoelectric body 11 is formed of a piezoelectric body that deforms in the thickness direction. For example, the piezoelectric body 11 can be formed of a piezoelectric body that extends and deforms in the thickness direction, or a piezoelectric body that compressively deforms in the thickness direction.

さらに、上部電極8と下部電極9との間に記録電圧源22が接続される。この記録電圧源22は、メモリ素子積層体7にスピン注入電流を供給するスピン注入電流供給源と、圧電体11に電界を印加する電圧供給源を兼ねている。   Further, a recording voltage source 22 is connected between the upper electrode 8 and the lower electrode 9. The recording voltage source 22 serves both as a spin injection current supply source that supplies a spin injection current to the memory element stack 7 and a voltage supply source that applies an electric field to the piezoelectric body 11.

図13Bに示す第9実施の形態に係るメモリ素子58は、圧電体11が非磁性層6と記録層5との間に形成される以外は、図13Aと同様に構成される。   The memory element 58 according to the ninth embodiment shown in FIG. 13B is configured in the same manner as in FIG. 13A except that the piezoelectric body 11 is formed between the nonmagnetic layer 6 and the recording layer 5.

次に、第9実施の形態に係るメモリ素子57及び58の動作を説明する。情報の記録時、記録電圧源22からメモリ素子本体2の上部電極8及び下部電極9を通じて記録層5にスピン注入電流が流れる。このとき、同時に参照層4と非磁性層6間の圧電体11(図13A)、あるいは非磁性層6と記録層5間の圧電体11(図13B)に電界が印加される。例えば、記録層5が磁歪が正の垂直磁化膜で形成され、上記の電界で圧電体11が厚み方向に伸びるように変形したときには、記録層5に厚み方向の圧縮応力が発生し、逆磁歪効果で磁気異方性が弱まり、記録層5の保磁力が低下する。   Next, operations of the memory elements 57 and 58 according to the ninth embodiment will be described. At the time of recording information, a spin injection current flows from the recording voltage source 22 to the recording layer 5 through the upper electrode 8 and the lower electrode 9 of the memory element body 2. At this time, an electric field is simultaneously applied to the piezoelectric body 11 (FIG. 13A) between the reference layer 4 and the nonmagnetic layer 6 or the piezoelectric body 11 (FIG. 13B) between the nonmagnetic layer 6 and the recording layer 5. For example, when the recording layer 5 is formed of a perpendicularly magnetized film having a positive magnetostriction and the piezoelectric body 11 is deformed so as to extend in the thickness direction by the above-described electric field, a compressive stress in the thickness direction is generated in the recording layer 5 and the inverse magnetostriction is generated. As a result, the magnetic anisotropy is weakened, and the coercive force of the recording layer 5 is reduced.

逆に、例えば、記録層5が磁歪が負の垂直磁化膜で形成され、上記の電界で圧電体11が厚み方向に縮むように変形したときには、記録層5に厚み方向の引っ張り応力が発生し、逆磁歪効果で磁気異方性が弱まり、記録層5の保磁力が低下する。いずれの場合も、記録層5の保磁力の低下で、スピン注入電流を低減することができる。   On the contrary, for example, when the recording layer 5 is formed of a perpendicular magnetization film having a negative magnetostriction and the piezoelectric body 11 is deformed so as to shrink in the thickness direction by the electric field, a tensile stress in the thickness direction is generated in the recording layer 5. The magnetic anisotropy is weakened by the inverse magnetostriction effect, and the coercive force of the recording layer 5 is lowered. In either case, the spin injection current can be reduced by the reduction of the coercive force of the recording layer 5.

第9実施の形態に係るメモリ素子57及び58によれば、圧電体11に電界を印加しながら、メモリ素子積層体7にスピン注入電流を流すことにより、スピン注入電流を低減することができる。従って、記録を安定に保持しながら少ないスピン注入電流で記録が可能であり、しまも実用に供し得る不揮発性メモリを提供することができる。   According to the memory elements 57 and 58 according to the ninth embodiment, the spin injection current can be reduced by applying the spin injection current to the memory element stack 7 while applying an electric field to the piezoelectric body 11. Therefore, it is possible to provide a non-volatile memory which can be recorded with a small spin injection current while maintaining recording stably and which can be used practically.

<11.本発明のメモリ素子の効果の検証>
初めに、図14に、本発明のメモリ素子の効果を検証のための測定用の試料(メモリ素子)の作製方法について示す。図14Aに示すように、圧電体材料であるBaTiOの単結晶基板61の表面に2本の溝62を形成する。溝62の深さhは、約100nm、溝62と溝62の間の間隔dは100nmである。
<11. Verification of the effect of the memory element of the present invention>
First, FIG. 14 shows a method for manufacturing a measurement sample (memory element) for verifying the effect of the memory element of the present invention. As shown in FIG. 14A, two grooves 62 are formed on the surface of a single crystal substrate 61 of BaTiO 3 that is a piezoelectric material. The depth h of the groove 62 is about 100 nm, and the distance d between the grooves 62 is 100 nm.

次に、図14Bに示すように、2つの溝62内に銅(Cu)を埋めて表面を平坦化し、一対の銅による電極63[63A,63B]を形成する。この一対の電極63A及び63Bと、両電極63A及び63Bで挟まれた圧電体61aとのより圧電素子60が構成される。   Next, as shown in FIG. 14B, copper (Cu) is filled in the two grooves 62 to flatten the surface, and a pair of copper electrodes 63 [63A, 63B] are formed. The pair of electrodes 63A and 63B and the piezoelectric body 61a sandwiched between the electrodes 63A and 63B constitute a piezoelectric element 60.

次に、図14Cに示すように、圧電素子60を含む単結晶基板61の表面上に、絶縁層64、下電極65を成膜し、さらに下電極65上にメモリ素子本体66及び上電極67を成膜する。メモリ素子本体66は、溝62内の両電極63A及び63B間の領域に対応して形成する。絶縁層64は、膜厚20nmのシリコン酸化(SiO)膜で形成される。下電極65は、膜厚10nmのCu膜で形成される。上電極67は、膜厚5nmのTi膜で形成される。 Next, as shown in FIG. 14C, an insulating layer 64 and a lower electrode 65 are formed on the surface of the single crystal substrate 61 including the piezoelectric element 60, and a memory element body 66 and an upper electrode 67 are further formed on the lower electrode 65. Is deposited. The memory element body 66 is formed corresponding to a region between the electrodes 63A and 63B in the groove 62. The insulating layer 64 is formed of a silicon oxide (SiO 2 ) film having a thickness of 20 nm. The lower electrode 65 is formed of a Cu film having a thickness of 10 nm. The upper electrode 67 is formed of a Ti film having a thickness of 5 nm.

メモリ素子本体66は、図15に示すように、各層を積層した、いわゆるトンネル磁気抵抗素子(MTJ素子)として形成される。即ち、下から膜厚5nmのTa膜による下部電極71、膜厚20nmのPtMn膜による反強磁性層72、膜厚2nmのCoFe膜による磁性層73、膜厚0.8nmのRu膜による非磁性層74、膜厚2nmのCoFeB膜による磁性層(参照層)75を成膜する。磁性層73、非磁性層74及び磁性層75の3層により、磁化固定層79が構成される。さらに、膜厚0.8nmのMgO膜による非磁性層(トンネル絶縁層)76、膜厚3nmのCoFeTaB膜による記録層(磁性層)77及び膜厚5nmのTa膜による上部電極78を成膜する。メモリ素子本体66は、長軸が200nm、短軸が80nmの楕円形状に形成される。図14Dの紙面に垂直な方向(紙面の奥行方向)が長軸方向である。上記の各磁性層は面内磁化膜である。   As shown in FIG. 15, the memory element body 66 is formed as a so-called tunnel magnetoresistive element (MTJ element) in which layers are stacked. That is, from the bottom, a lower electrode 71 made of a Ta film having a thickness of 5 nm, an antiferromagnetic layer 72 made of a PtMn film having a thickness of 20 nm, a magnetic layer 73 made of a CoFe film having a thickness of 2 nm, and a nonmagnetic material made of a Ru film having a thickness of 0.8 nm. A magnetic layer (reference layer) 75 made of a layer 74 and a CoFeB film having a thickness of 2 nm is formed. The magnetization fixed layer 79 is constituted by the three layers of the magnetic layer 73, the nonmagnetic layer 74, and the magnetic layer 75. Further, a nonmagnetic layer (tunnel insulating layer) 76 made of a 0.8 nm thick MgO film, a recording layer (magnetic layer) 77 made of a 3 nm thick CoFeTaB film, and an upper electrode 78 made of a 5 nm thick Ta film are formed. . The memory element body 66 is formed in an elliptical shape having a major axis of 200 nm and a minor axis of 80 nm. The direction perpendicular to the paper surface of FIG. 14D (the depth direction of the paper surface) is the major axis direction. Each of the above magnetic layers is an in-plane magnetization film.

次に、図14Dに示すように、メモリ素子本体66及び上電極67の側面及び下電極65の表面を絶縁部材81で被覆し、下電極65の一部に接続する端子82と、上電極67に接続する端子83を形成する。なお、図示しないが、圧電素子60の電極63A、63Bにそれぞれ接続する端子も形成する。このようにして、目的とする圧電素子60及びメモリ素子本体(MTJ素子)66を一体化した、試料となるメモリ素子84を作製する。   Next, as shown in FIG. 14D, the side surfaces of the memory element body 66 and the upper electrode 67 and the surface of the lower electrode 65 are covered with an insulating member 81, and a terminal 82 connected to a part of the lower electrode 65 and the upper electrode 67. A terminal 83 connected to is formed. Although not shown, terminals connected to the electrodes 63A and 63B of the piezoelectric element 60 are also formed. In this manner, the memory element 84 as a sample is manufactured by integrating the target piezoelectric element 60 and the memory element body (MTJ element) 66.

このメモリ素子84を用いて測定を行った。図16に、圧電素子60にかける電圧(Va)とメモリ素子本体(MTJ素子)66の記録層77の保磁力(Hc)との関係を示す。圧電素子60に印加する電圧Vaを絶対値で増やすと、メモリ素子本体(MTJ素子)66の記録層77の保磁力が低下し、圧電素子60(従って圧電体61a)の変化がメモリ素子本体(MTJ素子)66に作用していることが確認できる。   Measurement was performed using the memory element 84. FIG. 16 shows the relationship between the voltage (Va) applied to the piezoelectric element 60 and the coercive force (Hc) of the recording layer 77 of the memory element body (MTJ element) 66. When the voltage Va applied to the piezoelectric element 60 is increased in absolute value, the coercive force of the recording layer 77 of the memory element body (MTJ element) 66 is lowered, and the change of the piezoelectric element 60 (and hence the piezoelectric body 61a) is changed. It can be confirmed that it acts on the MTJ element 66.

図17に、圧電素子60にそれぞれ異なる電圧を印加し、メモリ素子本体(MTJ素子)66に100nsパルス幅のパスル電圧(Vp)を印加してスピン注入磁化反転を行ったときの、反転エラー率と印加パルス電圧(Vp)との関係を示す。本測定では、圧電素子60に夫々電圧を印加しない場合(Va=0V)、10Vの直流電圧(Va=10V)を印加した場合、及び振幅幅3Vで周波数2.5GHzの高周波電圧(Va=rf 3Vpp)を印加した場合である。   FIG. 17 shows a reversal error rate when spin injection magnetization reversal is performed by applying different voltages to the piezoelectric elements 60 and applying a 100 ns pulse width pulse voltage (Vp) to the memory element body (MTJ element) 66. And the applied pulse voltage (Vp). In this measurement, when a voltage is not applied to the piezoelectric element 60 (Va = 0V), a DC voltage of 10V (Va = 10V) is applied, and a high frequency voltage (Va = rf) with an amplitude width of 3V and a frequency of 2.5 GHz. 3Vpp) is applied.

圧電素子60、即ちその圧電体61aに直流あるいは高周波の電圧を印加すると、低いパルス電圧(Vp)で反転エラー率が減少し、本発明のメモリ素子の効果が確認できる。   When a direct current or high frequency voltage is applied to the piezoelectric element 60, that is, the piezoelectric body 61a, the inversion error rate decreases at a low pulse voltage (Vp), and the effect of the memory element of the present invention can be confirmed.

次に、垂直磁化膜に対する本発明のメモリ素子の効果を検証する。図18に、試料を示す。試料86は、下電極8上に垂直磁化膜88と圧電体89の積層体90を複数配列し、各積層体90上にわたって共通の上電極91を形成して構成される。下電極87は、膜厚20nmのAu膜で形成される。上電極91は、透明電極で形成される。垂直磁化膜88は、膜厚0.5nmのCo膜と膜厚0.5nmのNi膜を5周期連続積層した積層膜で形成される。圧電体89は、膜厚10nmのZnO膜で形成される。下電極87と上電極91間の垂直磁化膜88と圧電体89による積層体90が形成されない空間部は例えばシリコン酸化(SiO2)膜などの絶縁膜92が充填される。上記1つの積層体90は、直径100nmのパターンに形成される。   Next, the effect of the memory element of the present invention on the perpendicular magnetization film will be verified. FIG. 18 shows a sample. The sample 86 is configured by arranging a plurality of laminated bodies 90 of perpendicular magnetization films 88 and piezoelectric bodies 89 on the lower electrode 8 and forming a common upper electrode 91 over each laminated body 90. The lower electrode 87 is formed of an Au film having a thickness of 20 nm. The upper electrode 91 is formed of a transparent electrode. The perpendicular magnetization film 88 is formed of a laminated film in which a Co film having a thickness of 0.5 nm and a Ni film having a thickness of 0.5 nm are continuously laminated for five periods. The piezoelectric body 89 is formed of a ZnO film having a thickness of 10 nm. A space where the stacked body 90 of the perpendicular magnetization film 88 and the piezoelectric body 89 between the lower electrode 87 and the upper electrode 91 is not formed is filled with an insulating film 92 such as a silicon oxide (SiO 2) film. The one laminate 90 is formed in a pattern having a diameter of 100 nm.

この積層体90の集合体を光磁気効果で測定した。図19に、圧電体89への印加電圧と、垂直磁化膜88の保磁力の関係を示す。垂直磁化膜88においても、圧電体89に印加する電圧Vaを絶対値で増やすと垂直磁化膜88の保磁力が低下し、本発明の効果が確認できる。   The aggregate of the laminate 90 was measured by the magneto-optical effect. FIG. 19 shows the relationship between the voltage applied to the piezoelectric body 89 and the coercivity of the perpendicular magnetization film 88. Also in the perpendicular magnetization film 88, when the voltage Va applied to the piezoelectric body 89 is increased in absolute value, the coercive force of the perpendicular magnetization film 88 is lowered, and the effect of the present invention can be confirmed.

さらに、より簡単な構成で本発明の効果を検証する。試料は、図示しないが、上面から見て楕円形状のMTJ素子を形成し、このMTJ素子と接する部分に圧電体材料を充填して構成される。試料のMTJ素子は面内磁化膜を用いた。記録時に、試料のMTJ素子のトンネルバリア層(非磁性層)の端部に発生する電界によって圧電体材料が変形し、その変形が記録層に影響を及ぼすことによる反転電流(スピン注入電流)低減効果を測定した。表1に充填する圧電体材料を変えたときの反転電流Jcoの測定結果を示す。表1は、圧電体材料としてAlN膜、BaTiO3膜、LiNbO3膜を用いたMTJ素子を、充填材料として非晶質シリコン酸化(SiO2)を用いたMTJ素子と比較して示す。   Furthermore, the effect of the present invention is verified with a simpler configuration. Although not shown, the sample is configured by forming an elliptical MTJ element as viewed from above and filling a portion in contact with the MTJ element with a piezoelectric material. An in-plane magnetic film was used for the sample MTJ element. During recording, the piezoelectric material is deformed by the electric field generated at the end of the tunnel barrier layer (nonmagnetic layer) of the sample MTJ element, and the reversal current (spin injection current) is reduced by the deformation affecting the recording layer. The effect was measured. Table 1 shows the measurement result of the reversal current Jco when the piezoelectric material to be filled is changed. Table 1 shows an MTJ element using an AlN film, a BaTiO3 film, and a LiNbO3 film as a piezoelectric material in comparison with an MTJ element using amorphous silicon oxide (SiO2) as a filling material.

Figure 2012009786
Figure 2012009786

表1から明らかなように、充填材料にいずれの圧電体材料を用いたMTJ素子では、充填材料に非晶質シリコン酸化膜を用いたMTJ素子と比較して、反転電流Jcoが低減することが確認される。   As can be seen from Table 1, in the MTJ element using any piezoelectric material as the filling material, the reversal current Jco is reduced compared to the MTJ element using an amorphous silicon oxide film as the filling material. It is confirmed.

1・・メモリ素子、2・・メモリ素子本体、3・・圧電素子、4・・参照層、5・・記録層、6・・非磁性層、7・・メモリ素子積層体、8・・上部電極、9・・下部電極、11・・圧電体、12、13・・電極、15・・基板   1. Memory element 2. Memory element body 3. Piezoelectric element 4. Reference layer 5. Recording layer 6. Non-magnetic layer 7. Memory element stack 8, 8. Upper part Electrode, 9 ... Lower electrode, 11 ... Piezoelectric body, 12, 13 ... Electrode, 15 ... Substrate

Claims (11)

磁化方向が決められた参照層と、
記録情報に依存して磁化方向が変化する記録層と、
前記参照層と前記記録層との間に設けられた非磁性層と
を有して、スピン注入電流で情報を前記記録層に記録するメモリ素子積層体と、
前記メモリ素子積層体の側部に設けられた圧電体と、
前記圧電体に電界を印加する手段と
を備えたメモリ素子。
A reference layer with a determined magnetization direction;
A recording layer whose magnetization direction changes depending on the recorded information;
A non-magnetic layer provided between the reference layer and the recording layer, and a memory element stack for recording information on the recording layer with a spin injection current;
A piezoelectric body provided on a side portion of the memory element stack;
A memory element comprising: means for applying an electric field to the piezoelectric body.
前記記録層及び前記参照層が、磁歪が正の平面磁化膜であって、直交する長軸と短軸を有する形状に形成され、
前記圧電体が前記電界によって、前記記録層に対して長軸方向に圧縮応力を与え又は短軸方向に引っ張り応力を与えるように変形する
請求項1記載のメモリ素子。
The recording layer and the reference layer are planar magnetoresistive films having a positive magnetostriction, and are formed in a shape having a major axis and a minor axis orthogonal to each other,
The memory element according to claim 1, wherein the piezoelectric body is deformed so as to apply a compressive stress in a major axis direction or a tensile stress in a minor axis direction with respect to the recording layer by the electric field.
前記記録層及び前記参照層が、磁歪が負の平面磁化膜であって、直交する長軸と短軸を有する形状に形成され、
前記圧電体が前記電界によって、前記記録層に対して長軸方向に引っ張り応力を与え又は短軸方向に圧縮応力を与えるように変形する
請求項1記載のメモリ素子。
The recording layer and the reference layer are planar magnetic films having negative magnetostriction, and are formed in a shape having a major axis and a minor axis orthogonal to each other,
The memory element according to claim 1, wherein the piezoelectric body is deformed by the electric field so as to apply a tensile stress in a major axis direction or a compressive stress in a minor axis direction with respect to the recording layer.
基板上に前記メモリ素子積層体と、一対の電極を有する前記圧電体とが配置される
請求項2又は3記載のメモリ素子。
The memory element according to claim 2, wherein the memory element stack and the piezoelectric body having a pair of electrodes are disposed on a substrate.
一対の前記圧電体が前記メモリ素子積層体を挟んで両側に配置され、
前記圧電体に電界を与える手段と、前記メモリ素子積層体に記録時のスピン注入電流を与える手段とが共用される
請求項2又は3記載のメモリ素子。
A pair of the piezoelectric bodies are disposed on both sides of the memory element stack,
4. The memory element according to claim 2, wherein means for applying an electric field to the piezoelectric body and means for applying a spin injection current during recording to the memory element stack are shared.
前記記録層及び前記参照層が、磁歪が負の垂直磁化膜であって、円形状に形成され、
前記圧電体が前記電界によって、前記記録層に外側から圧縮応力を与えるように変形する
請求項1記載のメモリ素子。
The recording layer and the reference layer are perpendicular magnetization films having negative magnetostriction, and are formed in a circular shape,
The memory element according to claim 1, wherein the piezoelectric body is deformed by the electric field so as to apply a compressive stress to the recording layer from the outside.
前記記録層及び前記参照層が、磁歪が正の垂直磁化膜であって、円形状に形成され、
前記圧電体が前記電界によって、前記記録層に外側に向う引っ張り応力を与えように変形する
請求項1記載のメモリ素子。
The recording layer and the reference layer are perpendicular magnetization films having a positive magnetostriction, and are formed in a circular shape,
The memory element according to claim 1, wherein the piezoelectric body is deformed by the electric field so as to apply an outward tensile stress to the recording layer.
前記圧電体が前記メモリ素子積層体の外側を取り囲む円筒形に形成され、
前記圧電体の外側に前記メモリ素子積層体の下部電極に電気的に接続される導電膜が形成され、
前記圧電体に電界を与える手段と、前記メモリ素子積層体に記録時のスピン注入電流を与える手段とが共用される
請求項6又は7記載のメモリ素子。
The piezoelectric body is formed in a cylindrical shape surrounding the outside of the memory element stack,
A conductive film electrically connected to the lower electrode of the memory element stack is formed outside the piezoelectric body,
The memory element according to claim 6, wherein means for applying an electric field to the piezoelectric body and means for applying a spin injection current during recording to the memory element stack are shared.
前記非磁性層の中央部を残して、前記参照層と前記記録層との間の端部に厚み方向に変形する圧電体が形成される
請求項1記載のメモリ素子。
The memory element according to claim 1, wherein a piezoelectric body that deforms in a thickness direction is formed at an end portion between the reference layer and the recording layer, leaving a central portion of the nonmagnetic layer.
前記記録層が、磁歪の極性が異なる2層の積層磁性膜で形成される
請求項9記載のメモリ素子。
The memory element according to claim 9, wherein the recording layer is formed of two laminated magnetic films having different magnetostrictive polarities.
前記圧電体にかける電圧が高周波電圧であり、
前記高周波電圧の周波数が1GHz以上で10GHz以下である
請求項1記載のメモリ素子。
The voltage applied to the piezoelectric body is a high-frequency voltage,
The memory element according to claim 1, wherein a frequency of the high-frequency voltage is 1 GHz or more and 10 GHz or less.
JP2010146804A 2010-06-28 2010-06-28 Memory device Pending JP2012009786A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010146804A JP2012009786A (en) 2010-06-28 2010-06-28 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010146804A JP2012009786A (en) 2010-06-28 2010-06-28 Memory device

Publications (1)

Publication Number Publication Date
JP2012009786A true JP2012009786A (en) 2012-01-12

Family

ID=45539963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010146804A Pending JP2012009786A (en) 2010-06-28 2010-06-28 Memory device

Country Status (1)

Country Link
JP (1) JP2012009786A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103310847A (en) * 2012-03-13 2013-09-18 株式会社东芝 Shift register memory and driving method thereof
JP2015511072A (en) * 2012-03-22 2015-04-13 マイクロン テクノロジー, インク. Memory cell, semiconductor device structure including such memory cell, system, and method of fabrication
US9196335B2 (en) 2013-03-14 2015-11-24 Kabushiki Kaisha Toshiba Magnetic memory
JP2016164944A (en) * 2015-03-06 2016-09-08 株式会社BlueSpin Magnetic memory, method of writing data to same, and semiconductor device
WO2016194886A1 (en) * 2015-06-03 2016-12-08 国立研究開発法人科学技術振興機構 Magnetoresistive element and storage circuit
US9552860B2 (en) 2015-04-01 2017-01-24 BlueSpin, Inc. Magnetic memory cell structure with spin device elements and method of operating the same
US9768376B2 (en) 2013-07-01 2017-09-19 Micron Technology, Inc. Magnetic memory cells, semiconductor devices, and methods of operation
KR101851549B1 (en) 2014-03-14 2018-04-24 고쿠리츠켄큐카이하츠호진 카가쿠기쥬츠신코키코 Transistor using piezoresistor as channel, and electronic circuit
CN109219849A (en) * 2016-06-28 2019-01-15 英特尔公司 Cross-point magnetic random access memory with piezoelectricity selector
WO2024097451A3 (en) * 2022-08-08 2024-06-06 University Of Washington Tunnel junctions and methods of using the same

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013191692A (en) * 2012-03-13 2013-09-26 Toshiba Corp Shift-register type memory and driving method thereof
US9111855B2 (en) 2012-03-13 2015-08-18 Kabushiki Kaisha Toshiba Shift register memory and driving method thereof
CN103310847A (en) * 2012-03-13 2013-09-18 株式会社东芝 Shift register memory and driving method thereof
JP2015511072A (en) * 2012-03-22 2015-04-13 マイクロン テクノロジー, インク. Memory cell, semiconductor device structure including such memory cell, system, and method of fabrication
US9548444B2 (en) 2012-03-22 2017-01-17 Micron Technology, Inc. Magnetic memory cells and methods of formation
US9196335B2 (en) 2013-03-14 2015-11-24 Kabushiki Kaisha Toshiba Magnetic memory
US9768376B2 (en) 2013-07-01 2017-09-19 Micron Technology, Inc. Magnetic memory cells, semiconductor devices, and methods of operation
US10510947B2 (en) 2013-07-01 2019-12-17 Micron Technology, Inc Semiconductor devices with magnetic regions and stressor structures
US10090457B2 (en) 2013-07-01 2018-10-02 Micron Technology, Inc. Semiconductor devices with magnetic regions and stressor structures, and methods of operation
KR101851549B1 (en) 2014-03-14 2018-04-24 고쿠리츠켄큐카이하츠호진 카가쿠기쥬츠신코키코 Transistor using piezoresistor as channel, and electronic circuit
WO2016143157A1 (en) * 2015-03-06 2016-09-15 株式会社BlueSpin Magnetic memory, method for writing data into magnetic memory, and semiconductor device
CN107210264A (en) * 2015-03-06 2017-09-26 株式会社青纺 Magnetic memory, the method and semiconductor device for writing data into magnetic memory
US9847374B2 (en) 2015-03-06 2017-12-19 BlueSpin, Inc. Magnetic memory with spin device element exhibiting magnetoresistive effect
JP2016164944A (en) * 2015-03-06 2016-09-08 株式会社BlueSpin Magnetic memory, method of writing data to same, and semiconductor device
US10032829B2 (en) 2015-03-06 2018-07-24 BlueSpin, Inc. Magnetic memory with spin device element exhibiting magnetoresistive effect
US9552860B2 (en) 2015-04-01 2017-01-24 BlueSpin, Inc. Magnetic memory cell structure with spin device elements and method of operating the same
US10002655B2 (en) 2015-04-01 2018-06-19 BlueSpin, Inc. Memory cell structure of magnetic memory with spin device elements
EP3306688A4 (en) * 2015-06-03 2018-08-29 Japan Science and Technology Agency Magnetoresistive element and storage circuit
WO2016194886A1 (en) * 2015-06-03 2016-12-08 国立研究開発法人科学技術振興機構 Magnetoresistive element and storage circuit
US10304508B2 (en) 2015-06-03 2019-05-28 Japan Science And Technology Agency Magnetoresistive element and memory circuit including a free layer
JPWO2016194886A1 (en) * 2015-06-03 2018-03-15 国立研究開発法人科学技術振興機構 Magnetoresistive element and memory circuit
CN109219849A (en) * 2016-06-28 2019-01-15 英特尔公司 Cross-point magnetic random access memory with piezoelectricity selector
US11600659B2 (en) 2016-06-28 2023-03-07 Intel Corporaton Cross-point magnetic random access memory with piezoelectric selector
CN109219849B (en) * 2016-06-28 2023-05-30 英特尔公司 Cross-point magnetic random access memory with piezoelectric selector
WO2024097451A3 (en) * 2022-08-08 2024-06-06 University Of Washington Tunnel junctions and methods of using the same

Similar Documents

Publication Publication Date Title
JP2012009786A (en) Memory device
JP5431400B2 (en) Magnetic memory element
Versluijs et al. Magnetoresistance of half-metallic oxide nanocontacts
JP5784114B2 (en) Magnetoelectric memory
JP5727836B2 (en) Magnetic storage element, magnetic storage device, and domain wall motion method
JP5360774B2 (en) Magnetization control method, information storage method, information storage element, and magnetic functional element
TWI621120B (en) Magnetoresistance effect element and magnetic memory
JP4874884B2 (en) Magnetic recording element and magnetic recording apparatus
CN102171766B (en) STT-MRAM cell structure incorporating piezoelectric stress material
JP5121597B2 (en) Magnetoresistive element
EP1318523A1 (en) Method of controlling magnetization easy axis in ferromagnetic films using voltage, ultrahigh-density, low power, nonvolatile magnetic memory using the control method and method of writing information on the magnetic memory
US8976579B2 (en) Magnetic memory element, magnetic memory, and magnetic memory device
JPWO2005069368A1 (en) Current injection domain wall motion element
US20100225312A1 (en) Signal processing device using magnetic film and signal processing method
US20180026177A1 (en) Electromagnetic conversion device and information memory comprising the same
CN112789734B (en) Magnetic element and manufacturing method thereof, magnetic storage, storage tank element, and identifier
JP2012069958A (en) Magnetic recording element
JP2007080952A (en) Multilevel recording spin injection magnetization reversal element and apparatus using the same
Boukari et al. Voltage assisted magnetic switching in Co50Fe50 interdigitated electrodes on piezoelectric substrates
JP5576960B2 (en) Magnetic storage element, magnetic storage device, and magnetic memory
US10998490B2 (en) Magnetic element
US12514126B2 (en) Magnetoelectric device including deformable piezoelectronic and magnetostrictive elements
Wang Characterization and applications of FeGa/PZT multiferroic cantilevers
JP2021180563A (en) Actuators and power utilization devices
JP2018101743A (en) Structure, magnetic device and high frequency device