JP2012009063A5

JP2012009063A5 -

Info

Publication number: JP2012009063A5
Application number: JP2011192704A
Authority: JP
Filing date: 2011-09-05
Publication date: 2012-09-06

Claims

A single logic block that performs priority and control functions for providing interrupt messages to a plurality of processing units and is shared by the plurality of processing units;
A storage area to maintain architectural interrupt state information of the plurality of processing units,
Is connected to the storage area, query in the storage area, to determine the architectural interrupt state information of the plurality of processing units, connected to said logic block, a plurality of processing units for by that process to said logic block An interrupt sequencer block for scheduling interrupt events;
One or more input message queues that receive an input interrupt message and place information from the message in the storage area;
One or more output message queues for sending output interrupt messages;
Having a device.

The apparatus of claim 1, wherein the single logic block has non-redundant circuitry rather than redundant logic for each processing unit.

The apparatus of claim 1, wherein the interrupt sequencer block schedules interrupt events for the plurality of processing units according to a fairness scheme.

4. The apparatus of claim 3, wherein the interrupt sequencer block schedules interrupt events of the plurality of processing units according to a sequential traversal of the storage area.

The apparatus of claim 1, further comprising a scoreboard for maintaining data regarding which of the processing units have pending interrupt events.

The apparatus of claim 1, wherein the storage area further stores microarchitecture state information.

The apparatus of claim 1, wherein the plurality of processors communicate over a local interconnect.

The one or more input message queues include a message queue for receiving an input interrupt message via the local interconnect;
The apparatus of claim 7, wherein the one or more output message queues comprise a message queue for sending output interrupt messages over the local interconnect.

The one or more input message queues include a message queue for receiving an input interrupt message via a system interconnect;
The apparatus of claim 7, wherein the one or more output message queues comprise a message queue for transmitting output interrupt messages over the system interconnect.

The apparatus of claim 1, wherein the one or more output message queues further extract information about the output interrupt message from the storage area.

The apparatus of claim 1, wherein the one or more output message queues further comprise firewall logic for prohibiting one or more transmissions of the output interrupt message.

The apparatus of claim 1, wherein the one or more input message queues further comprise firewall logic for prohibiting one or more transmissions of the input interrupt message to one or more of the processing units.

To determine the architecture interrupt states of the plurality of processing units, comprising the steps of: querying a storage array,
Scheduling interrupt events of the plurality of processing units for processing by non-redundant interrupt providing blocks;
A method comprising:
The non-redundant interrupt providing block performs a priority and control function for providing interrupt messages to a plurality of processing units;
The scheduling is performed according to a fairness scheme that allows each processing unit to have equal access to the interrupt providing block.

The method of claim 13, wherein the interrupt providing block comprises advanced programmable interrupt controller logic.

The method of claim 13, wherein the fairness scheme is a sequential round robin scheme for the processing unit having one or more pending interrupt events.

A plurality of processing units executing one or more threads;
A memory connected to the processing unit;
A shared interrupt controller that provides an interrupt providing service for the plurality of processing units;
A system comprising :
The shared interrupt controller is:
A single logic block that performs priority and control functions for providing interrupt messages to a plurality of processing units and is shared by the plurality of processing units;
A storage area for maintaining architecture interrupt status information of the plurality of processing units;
Connected to the storage area, querying the storage area, determining architecture interrupt status information of the plurality of processing units, connected to the logic block, and interrupt events of the plurality of processing units for processing by the logic block An interrupt sequencer block for scheduling
One or more input message queues that receive an input interrupt message and place information from the message in the storage area;
One or more output message queues for sending output interrupt messages;
Having a system .

The system of claim 16, wherein the shared interrupt controller further provides an APIC interrupt providing service for the plurality of processing units.

The system of claim 16, wherein the processing unit does not have self-contained APIC interrupt providing logic.

The system of claim 16, wherein the shared interrupt controller further comprises firewall logic.

The system of claim 16, further comprising a local interconnect connected to the plurality of processing units.

21. The system of claim 20, wherein the shared interrupt controller further comprises firewall logic that prohibits transmission of one or more interrupt messages over the local interconnect.

The system of claim 16, further comprising a system interconnect connected to the shared interrupt controller.

23. The system of claim 22, wherein the shared interrupt controller further comprises firewall logic that prohibits transmission of one or more interrupt messages over the system interconnect.

The system of claim 16, wherein the shared interrupt controller further schedules an interrupt serial service between the plurality of processing units.