JP2012004506A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device in which rewiring of a multilayer structure is formed at a low cost by a simple method is provided.
A semiconductor substrate having a bump electrode, a first insulating layer formed on the semiconductor substrate and disposed in a lateral direction of the bump electrode, and formed on the first insulating layer. In addition, the first wiring layer 30 provided with the connection hole CH on the bump electrode 18 and the bump electrode 18 and the first wiring layer 30 formed in the connection hole CH are connected and made of a conductive paste or solder. First via conductor 40, second insulating layer 22 formed on first wiring layer 30, via hole VH formed in second insulating layer 22 and reaching first wiring layer 30, and second insulating layer The second wiring layer 32 formed on the via hole VH and extending outward from the outer periphery of the via hole VH is connected to the first wiring layer 30 and the second wiring layer 32 formed in the via hole VH. Or made of solder 2 and a via conductor 40.
[Selection] Figure 14

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device applicable to a semiconductor package in which a rewiring having a multilayer structure is formed on a bump electrode of a semiconductor substrate and a manufacturing method thereof.

  In recent years, with the improvement in performance of multimedia devices and the like, the density of packaging technology that serves as an interface between LSI and electronic devices has been increased.

  As an IC package that meets such requirements, there is a CSP (chip size package) packaged to a size substantially equal to the chip size. Furthermore, a wafer level CSP is known in which film formation or processing related to the CSP structure is performed at the wafer stage, and then dicing is performed to obtain individual CSPs.

  In the wafer level CSP, a rewiring is connected to a connection pad of a silicon wafer on which a transistor or the like is formed, and then a bump electrode is formed on the rewiring.

  Patent Documents 1 and 2 describe forming a wiring pattern connected to a bump electrode after forming an insulating layer on a semiconductor substrate provided with the bump electrode so that the upper portion of the bump electrode is exposed. ing.

  In Patent Document 3, an insulating resin layer and a copper foil are laminated on an inner wiring board, an opening is formed in the copper foil, a non-through hole is formed in the resin insulating layer from the opening of the copper foil by blasting, and then plated. It is described that a conductor circuit pattern is formed in a non-through hole.

Japanese Patent No. 4121542 Japanese Patent No. 4431628 JP 2002-43753 A

  In the conventional wafer level CSP, rewiring formed on a silicon wafer is often formed as a single layer, and no consideration is given to adopting a multilayer wiring structure (for example, Patent Documents 1 and 2). In particular, since semiconductor devices such as ASIC and Logic require a large number of pins, a new method for forming a multi-layer rewiring at low cost is desired.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device in which rewiring of a multilayer structure is formed at a low cost by a simple method and a method for manufacturing the same.

  In order to solve the above problems, the present invention relates to a method for manufacturing a semiconductor device, and a first laminated film in which a first metal layer is laminated on a first insulating layer is formed on a semiconductor wafer provided with bump electrodes. A step of embedding the bump electrode in the first insulating layer and disposing the bump electrode under the first metal layer; and forming an opening in the first metal layer on the bump electrode. Connecting the bump electrode and the first metal layer by the first via conductor by forming a first via conductor made of a conductive paste or solder in the connection hole; A step of forming a first wiring layer by patterning the first metal layer after the step of obtaining the connection hole or after the step of forming the first via conductor; and the first wiring layer On top of the, Forming a second laminated film in which a second metal layer is laminated on the two insulating layers; and providing an opening on the second laminated film at a portion corresponding to the connecting portion of the first wiring layer Forming the resist, etching the second metal layer through the opening of the resist, and forming the opening through the opening of the second metal layer by wet blasting. Etching a layer to form a via hole reaching the first wiring layer; and forming a second via conductor made of a conductive paste or solder in the via hole, thereby forming the second via conductor by the second via conductor. It is performed after the step of connecting one wiring layer and the second metal layer, the step of forming the via hole, or the step of forming the second via conductor, and the second metal layer is patterned. Characterized by a step of forming a second wiring layer is.

  In the method for manufacturing a semiconductor device of the present invention, first, a first stack in which a first metal layer (such as a copper foil) is stacked on a first insulating layer (such as a resin film) on a semiconductor wafer provided with bump electrodes. A film is formed. Thus, the bump electrode is embedded in the first insulating layer, and the bump electrode is disposed under the first metal layer.

  Next, an opening is formed in the first metal layer above the bump electrode to form a connection hole, and the connection portion of the bump electrode is exposed. At this time, the concave electrode may be formed by etching the first insulating layer around the bump electrode at the same time that the bump electrode connecting portion is cleaned by the wet blast method.

  Subsequently, a via conductor made of a conductive paste or solder is formed in the connection hole, thereby electrically connecting the bump electrode and the first metal layer. The first metal layer is patterned at a predetermined stage to become the first wiring layer.

  Next, a second laminated film in which a second metal layer (such as a copper foil) is laminated on a second insulating layer (such as a resin film) is formed on the first wiring layer. Further, a resist having an opening provided in a portion corresponding to the connection portion of the first wiring layer is formed on the first metal layer, and the opening is formed by etching the first metal layer through the opening.

  Next, in this state, a via hole reaching the first wiring layer is formed by etching the second insulating layer from the opening of the second metal layer by wet blasting.

  Thereafter, a via conductor made of a conductive paste or solder is formed in the via hole, thereby electrically connecting the first wiring layer and the second metal layer. The second metal layer is patterned at a predetermined stage to become a second wiring layer.

  By adopting such a manufacturing method, when forming a multilayer wiring (rewiring) connected to the bump electrode of the semiconductor wafer, a metal layer (seed layer, etc.) is formed by sputtering, and a via hole is formed by laser. There is no need to use techniques such as formation, via hole desmear treatment with a permanganate-based strong alkaline solution, and wet plating (electroless Cu plating / electrolytic Cu plating).

  Therefore, since the number of steps involved in manufacturing can be greatly reduced, manufacturing cost can be reduced. Moreover, since a desmear process and a wet plating process become unnecessary, a hazardous waste liquid can be reduced and the environmental load can be reduced.

  In order to solve the above problems, the present invention relates to a semiconductor device, a semiconductor substrate provided with a bump electrode, and a first insulating layer formed on the semiconductor substrate and disposed laterally of the bump electrode. A first wiring layer formed on the first insulating layer and provided with a connection hole on the bump electrode; and formed on the connection hole to connect the bump electrode and the first wiring layer. A first via conductor made of conductive paste or solder, a second insulating layer formed on the first wiring layer, a via hole formed in the second insulating layer and reaching the first wiring layer; A second wiring layer formed on the second insulating layer and extending outward from an outer periphery of the via hole; and formed in the via hole to connect the first wiring layer and the second wiring layer. From conductive paste or solder And having a second via conductor that.

  The semiconductor device of the present invention is manufactured by the above-described manufacturing method, and the bump electrode and the first wiring layer are connected to each other by a via conductor (conductive paste or solder) formed in the connection hole of the first wiring layer. The layer and the second wiring layer are connected by a via conductor (conductive paste or solder) formed in the via hole of the insulating layer.

  The first wiring layer is not disposed on the via conductor connecting the bump electrode and the first wiring layer. Similarly, the second wiring layer is not disposed on the second via connecting the first wiring layer and the second wiring layer.

  In the present invention, it is possible to form a multi-layered rewiring on a semiconductor wafer by a simple method capable of reducing costs. Therefore, it becomes possible to easily cope with the manufacture of a semiconductor device that requires a large number of pins, such as ASIC and Logic.

  As described above, in the semiconductor device of the present invention, the multilayer wiring is formed at a low cost by a simple method.

FIG. 1 is a sectional view (No. 1) showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. 2A and 2B are cross-sectional views (part 2) showing the method for manufacturing the semiconductor device of the embodiment of the present invention. 3A and 3B are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention. 4A and 4B are cross-sectional views (part 4) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention. 5A and 5B are cross-sectional views (part 5) showing the method for manufacturing the semiconductor device of the embodiment of the present invention. 6A and 6B are cross-sectional views (No. 6) showing the method for manufacturing a semiconductor device according to the embodiment of the present invention. 7A and 7B are sectional views (No. 7) showing the method for manufacturing a semiconductor device according to the embodiment of the present invention. 8A and 8B are sectional views (# 8) showing the method for manufacturing a semiconductor device according to the embodiment of the present invention. 9A and 9B are cross-sectional views (No. 9) showing the method for manufacturing a semiconductor device according to the embodiment of the present invention. 10A and 10B are cross-sectional views (No. 10) showing the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 11 is a cross-sectional view (No. 11) showing the method for manufacturing a semiconductor device of the embodiment of the present invention. 12A and 12B are cross-sectional views (No. 12) showing the method for manufacturing a semiconductor device according to the embodiment of the present invention. 13A and 13B are cross-sectional views (No. 13) showing the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 14 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  1 to 13 are sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 14 is a sectional view showing the semiconductor device according to the embodiment.

  In the method of manufacturing a semiconductor device according to the embodiment of the present invention, first, a silicon wafer 10 as shown in FIG. 1 is prepared. In this embodiment, the silicon wafer 10 is illustrated as a semiconductor wafer.

  The silicon wafer 10 includes a connection pad 12 and a passivation layer 14 (protective insulating layer) provided with an opening 14x exposing the connection pad 12 at the top.

  The connection pad 12 is made of aluminum or an aluminum alloy, and the passivation layer 14 is formed by forming a silicon nitride layer 14a and a polyimide resin layer 14b in this order from the bottom. Note that the polyimide resin layer 14b may be omitted, and the passivation layer 14 may be configured from the silicon nitride layer 14a.

  The silicon wafer 10 is provided with a plurality of element formation regions T in which circuit elements such as transistors (semiconductor elements), capacitors, and resistors are formed. On each element formation region T, a multilayer wiring (not shown) for connecting various circuit elements is formed, and the multilayer wiring is connected to the connection pad 12.

  Referring to the plan view of FIG. 1, the silicon wafer 10 is provided with a large number of chip regions A including element forming regions T. The chip area A is defined by being surrounded by dicing lines D arranged in a lattice pattern.

  In the example of the plan view of FIG. 1, the connection pads 12 are arranged in an area array type, and are arranged in a grid pattern in each chip area A. Alternatively, the connection pads 12 may be arranged as a peripheral type and arranged at the peripheral edge of each chip region A. The silicon wafer 10 is later cut by a dicing line D so as to obtain each chip region A to form individual semiconductor chips (semiconductor devices).

  The following process will be described while partially showing one chip region A of the silicon wafer 10 of FIG.

  As shown in FIG. 2A, the silicon wafer 10 described in FIG. 1 is prepared. The thickness of the silicon wafer 10 is about 600 to 800 μm.

  Next, as shown in FIG. 2B, a dry film resist 16 having a thickness of about 50 μm is pasted on the silicon wafer 10, and the dry film resist 16 is patterned by performing exposure and development based on photolithography. To do. Thereby, the dry film resist 16 is left on each chip area A, and the opening 16a of the dry film resist 16 is disposed on the dicing line D.

  Subsequently, as shown in FIG. 3A, etching is performed in the thickness direction from the upper surface of the passivation layer 14 through the opening 16a using the dry film resist 16 as a mask by wet blasting. Thereby, the recessed part C is formed in the dicing line D (FIG. 1) of the silicon wafer 10. The recesses C are formed in a lattice shape so as to surround each chip region A.

  As will be described later, the recess C formed in the silicon wafer 10 functions as an anchor that improves the adhesion of the interlayer insulating layer formed on the silicon wafer 10.

  Thereafter, as shown in FIG. 3B, the dry film resist 16 is removed with a resist stripping solution. A similar mask may be formed using a liquid resist instead of the dry film resist 16.

  Next, as shown in FIG. 4A, the upper surface side of the structure of FIG. 3B is cleaned with oxygen plasma. As a result, the passivation layer 14 is surface-modified (roughened) and the surface of the connection pad 12 is cleaned.

  Subsequently, as shown in FIG. 4B, a gold (Au) wire bump 18 having a sharp tip is formed on the connection pad 12 based on a wire bonding method. Although the gold wire bump 18 is illustrated as a bump electrode, a copper (Cu) wire bump having a similar shape may be formed based on a wire bonding method. Alternatively, gold (Au) bumps or the like may be formed by electrolytic plating, or nickel (Ni) / gold (Au) bumps may be sequentially formed by electroless plating.

  Next, as shown in FIG. 5A, a first copper foil-attached resin film CF1 having a structure in which a copper foil 30a is stuck on a B-stage (semi-cured) resin film 20a is prepared.

  The thickness of the copper foil 30a is 5 to 18 μm, and the thickness of the resin film 20a is about 30 μm. As the resin film 20a, a thermosetting resin such as an epoxy resin or a polyimide resin is used.

  Then, the surface of the resin film 20a of the resin film CF1 with the first copper foil is pressed into the gold wire bump 18 to be pressure bonded. As a result, the gold wire bumps 18 are embedded in the resin film 20a, and the tips of the gold wire bumps 18 are stuck into the copper foil 30a.

  Further, as shown in FIG. 5B, the first copper foil-attached resin film CF1 is flattened by pressing downward with a pressing jig (not shown), and heat-treated at a temperature of about 180 ° C. The first stage insulating layer 20 is obtained by curing the B-stage resin film 20a.

  At this time, the tip of the gold wire bump 18 is crushed by the flattening process to form the connection portion 18a. Moreover, the connection part 18a of the gold wire bump 18 is in a state of being disposed immediately below the copper foil 30a. In this way, the connecting portion 18a of the gold wire bump 18 and the upper surface of the first interlayer insulating layer 20 are planarized so as to form the same surface.

  Further, as described above, since the recess C is formed in the dicing line D (FIG. 1) of the silicon wafer 10, the first interlayer insulating layer 20 is formed on the silicon wafer 10 with good adhesion by the anchor effect.

  In addition, in this embodiment, although resin film CF1 with 1st copper foil is affixed on the silicon wafer 10, the various laminated film by which the metal layer was laminated | stacked on the insulating layer can be used.

  Next, as shown in FIG. 6A, a dry film resist 21 having openings 21a provided on the gold wire bumps 18 is formed on the first copper foil-attached resin film CF1.

  Next, as shown in FIG. 6B, the copper foil 30a is etched through the opening 21a of the dry film resist 21 with a copper etchant such as a cupric chloride aqueous solution to form the opening 30x. The diameter of the opening 30x of the copper foil 30a is set to, for example, 50 to 80 μm.

  At this time, the upper surface of the connection portion 18a of the gold wire bump 18 may be covered with an extremely thin resin film. That is, in the above-described process of pressing and planarizing the first copper foil-attached resin film CF1 on the gold wire bump 18, the resin may wrap around the connection portion 18a of the gold wire bump 18 to form a resin film. For this reason, it is necessary to remove the resin film on the connection part 18a of the gold wire bump 18 to expose the clean connection part 18a.

  Therefore, as shown in FIG. 7 (a), with the dry film resist 21 left (FIG. 6 (b)), the wet wire blast method is performed on the connection portion 18a of the gold wire bump 18 through the opening 30x of the copper foil 30a. The resin film is etched and cleaned.

  The opening 30x of the copper foil 30a is set larger than the area of the connecting portion 18a of the gold wire bump 18. For this reason, the first interlayer insulating layer 20 around the gold wire bump 18 is selectively etched by wet blasting, and a recess 20 x is formed around the gold wire bump 18. At this time, the gold wire bump 18 is hardly etched by wet blasting. The recess 20x provided around the gold wire bump 18 is formed in a U-shape in which the connecting surface between the side surface and the bottom surface is a curved surface.

  In this manner, the opening 30x of the copper foil 30a and the recess 20x provided in the first interlayer insulating layer 20 form a connection hole CH that exposes the connection 18a of the gold wire bump 18.

  Moreover, the dry film resist 21 is set to a film thickness that disappears during etching of the resin, and after the dry film resist 21 disappears, the copper foil 30a functions as a mask. As a result, the surface of the copper foil 30a, which will later become the first wiring layer, is roughened by wet blasting, and anchors are formed simultaneously.

  Further, when the resin film is etched by the wet blast method, there is no possibility of generating a resin smear, and since the connecting portion 18a of the gold wire bump 18 is exposed in a clean state by washing with water, it is not necessary to perform a desmear process. .

  In addition, when a resin film is not formed on the connection part 18a of the gold wire bump 18, the above-described wet blasting process may be omitted. In this case, the anchor is formed by treating and roughening the surface of the copper foil 30a with a formic acid-based chemical. When the wet blasting process is omitted, the opening 30x of the copper foil 30a becomes the connection hole CH.

  At this time, the gold wire bumps 18 and the copper foil 30a serving as the first wiring layer are not electrically connected.

  Therefore, a via conductor is formed in the connection hole CH to electrically connect the gold wire bump 18 and the copper foil 30a. In the present embodiment, as a method for forming the via conductor, a costly technique such as sputtering or electrolysis or electroless plating is not employed.

  That is, as shown in FIG. 7B, after the conductive paste 40 such as silver paste is applied to the connection hole CH from the nozzle 5 of the dispenser device (not shown) by the dispensing method, the conductive paste 40 is heated. To cure. The conductive paste 40 is a paste in which a thermosetting resin is used as a binder and conductive particles such as silver particles are dispersed therein.

  Thereby, as shown in FIG. 8A, the gold wire bump 18 and the copper foil 30 a serving as the first wiring layer are electrically connected by the conductive paste 40. The conductive paste 40 is filled in the connection hole CH and is formed by covering the copper foil 30a in the vicinity of the connection hole CH.

  Since the conductive paste 40 is filled in the recess 20x at the bottom of the connection hole CH, the conductive paste 40 is formed on the gold wire bump 18 with good adhesion by the anchor effect.

  Further, since the upper side surface of the gold wire bump 18 is exposed by forming the recess 20x around the gold wire bump 18, the contact area between the conductive paste 40 and the gold wire bump 18 is increased, and the contact resistance is reduced. is there.

  Note that solder may be filled in the connection holes CH instead of the conductive paste 40. Moreover, it is not always necessary to fill the connection hole CH with the conductive paste 40, and a conformal via formed along the shape of the connection hole CH may be used. Alternatively, a photosensitive conductive paste may be used. For details, refer to a step of forming a via conductor in a via hole described later (FIGS. 11 and 12).

  Next, as shown in FIG. 8B, a resist (not shown) having an opening provided on the copper foil 30a is patterned, and the copper foil 30a is etched through the opening to thereby form the first wiring layer 30. Get.

  In addition, although the process of forming the 1st wiring layer 30 by patterning the copper foil 30a is performed after forming the conductive paste 40 in the connection hole CH, after forming the connection hole CH (FIG. 7A) It may be carried out after the step.

  Next, as shown in FIG. 9A, a second copper foil-attached resin film CF2 having a structure in which a copper foil 32a is adhered onto a B-stage (semi-cured) resin film 22a is prepared. The thickness of the copper foil 32a is 5 to 18 μm, and the thickness of the resin film 22a is about 30 μm. As the resin film 22a, a thermosetting resin such as an epoxy resin or a polyimide resin is used.

  Then, the surface of the resin film 22a of the resin film CF2 with the second copper foil is pressure-bonded onto the first wiring layer 30. Further, by performing a heat treatment at a temperature of about 180 ° C., the B-stage resin film 22 a is cured to obtain the second interlayer insulating layer 22.

  Since the surface of the first wiring layer 30 is roughened, the second interlayer insulating layer 22 is formed on the first wiring layer 30 with good adhesion.

  In this embodiment, the resin film CF2 with the second copper foil is pasted on the first wiring layer 30, but various laminated films in which a metal layer is laminated on the insulating layer can be used.

  Subsequently, as illustrated in FIG. 9B, a dry film resist 23 in which an opening 23 a is provided in a portion corresponding to the connection portion of the first wiring layer 30 is formed. Further, an opening 32x is formed by etching the copper foil 32a through the opening 23a using a dry film resist 23 as a mask with a copper etchant such as a second copper chloride aqueous solution.

  Further, as shown in FIG. 10A, the second interlayer insulating layer 22 exposed in the opening 32x of the copper foil 32a is formed by wet blasting with the dry film resist 23 left (FIG. 9B). By etching, a via hole VH reaching the connection portion of the first wiring layer 30 is formed. The diameter of the via hole VH is set to 50 to 80 μm, for example. At this time, the dry film resist 23 (FIG. 9B) is simultaneously etched and removed by wet blasting.

  In the wet blasting method, a slurry obtained by mixing particles such as alumina abrasive grains and a liquid such as water is jetted at high speed from the jet nozzle using the force of compressed air, and the object is physically treated with the particles in the slurry. It is a processing method which etches automatically.

  In the wet blasting process, the etching rate of the first wiring layer 30 (copper) is considerably low, so that the first wiring layer 30 serves as a stopper when the second interlayer insulating layer 22 is etched. Further, the dry film resist 23 (FIG. 9B) is set to a thickness that completely disappears during the etching of the second interlayer insulating layer 22, and after the dry film resist 23 disappears, the copper foil 32a is used as a mask. Function.

  As a result, the surface of the copper foil 32a, which later becomes the second wiring layer, is roughened by wet blasting, and anchors are formed simultaneously.

  Unlike the present embodiment, when the via hole VH is formed in the second interlayer insulating layer 22 with a laser, a resin smear is generated in the via hole VH. Therefore, the desmear process is performed by a wet process such as a permanganate method. There is a need.

  However, when the wet blast method is used, resin smear hardly occurs, and a clean via hole VH can be easily obtained by forming the via hole VH in the second interlayer insulating layer 22 and then washing with water. Thus, in this embodiment, the desmear process which becomes an environmental load can be abbreviate | omitted.

  Next, as shown in FIG. 10B, the second wiring layer 32 is obtained by patterning an etching resist (not shown) on the copper foil 32a and etching the copper foil 32a using the resist as a mask. .

  At this time, since the via conductor is not formed in the via hole VH, the first wiring layer 30 and the second wiring layer 32 are not electrically connected. Therefore, a via conductor is formed in the via hole VH, and the first wiring layer 30 and the second wiring layer 32 are electrically connected through the via conductor. As a method of forming a via conductor, the cost of sputtering, electrolysis or electroless plating is increased in the same manner as the method of forming a via conductor in the connection hole CH described above (FIGS. 7B and 8A). The method is not adopted.

  That is, as shown in FIG. 11, after applying a conductive paste 40 such as silver paste into the via hole VH from the nozzle 5 of a dispenser device (not shown) by a dispensing method, the conductive paste 40 is heated and cured. Thus, the first wiring layer 30 and the second wiring layer 32 are electrically connected.

  As shown in FIG. 12A, when the conductive paste 40 is formed by the dispensing method, the conductive paste 40 is filled in the via hole VH and covers the second wiring layer 32 in the vicinity of the via hole VH. It is formed.

  Alternatively, the conductive paste 40 may be formed in the via hole VH by an inkjet method instead of the dispensing method. As shown in FIG. 12B, when the ink jet method is used, the conductive paste 40 is not embedded in the via hole VH, and a recess is left in the via hole VH.

  That is, the conductive paste 40 is formed as a so-called conformal via along the bottom and side surfaces of the via hole VH. Even when the inkjet method is used, the conductive paste 40 is formed to cover the second wiring layer 32 in the vicinity of the via hole VH.

  As another method for forming the via conductor, a photosensitive conductive paste containing a photosensitive agent may be used. In this case, a photosensitive conductive paste is applied to the entire upper surface of the silicon wafer 10 with a spin coater or the like, and exposed and developed based on photolithography to selectively form the conductive paste 40 in the via hole VH. The wiring layer 30 and the second wiring layer 32 are electrically connected. Examples of the photosensitive conductive paste include a photosensitive silver paste. When the photosensitive conductive paste is used, it is formed as a conformal via as in the case of forming the conductive paste 40 by the ink jet method.

  Alternatively, other than the conductive paste 40, the via hole VH may be filled with solder, and the first wiring layer 30 and the second wiring layer 32 may be electrically connected with the solder. In this case, a solder ball is mounted on the via hole VH, and reflow heating is performed to fill the via hole VH with solder. Alternatively, a solder paste (cream solder) may be selectively applied to the via hole VH.

  By the above method, via conductors 40 or solder are formed in the via hole VH without using a sputtering method that leads to high costs or a plating method that has a large environmental load and complicated processes. Can be formed.

  In this way, the multi-layered rewiring (first and second wiring layers 30 and 32) is connected to the gold wire bumps 18 provided on the silicon wafer 10. By rewiring (first and second wiring layers 30 and 32), the pitch of the connection pads 12 of the silicon wafer 10 is converted so as to correspond to the pitch of the connection electrodes of the mounting substrate.

  The step of forming the second wiring layer 32 by patterning the copper foil 32a is performed after the via hole VH is formed by the wet blast method, but after the conductive paste 40 is formed in the via hole VH (FIG. 12 ( You may carry out after the process of a) and (b).

  Thereafter, as shown in FIG. 13A, a solder resist 24 having an opening 24 a is formed on the connection portion of the second wiring layer 32. Since the surface of the second wiring layer 32 is roughened, the solder resist 24 is formed on the second wiring layer 32 with good adhesion. Thereafter, the surface of the solder resist 24 is subjected to an ashing treatment with oxygen plasma, thereby modifying the surface to be hydrophilic and improving the wettability.

  Further, as shown in FIG. 13B, external connection terminals 34 connected to the connection portions of the second wiring layer 32 are formed by mounting solder balls in the openings 24a of the solder resist 24 and performing reflow heating. To do. As the solder ball, a resin ball having a solder layer formed on the outer surface may be used.

  Subsequently, as shown in FIG. 13, the thickness of the silicon wafer 10 is reduced to about 50 to 300 μm by grinding the back surface of the silicon wafer 10 with a grinder as necessary. Thereafter, the silicon wafer 10 is cut along the dicing line D (FIG. 1).

  Thereby, as shown in FIG. 14, the silicon wafer 10 is divided into individual silicon substrates 10a (semiconductor substrates), and the semiconductor device 1 having individual CSP structures is obtained.

  In this embodiment, two layers of multilayer wiring (first and second wiring layers 30 and 32) are illustrated, but multilayer wiring having an arbitrary number of layers can be formed by repeating the above-described steps. .

  As described above, in the method of manufacturing a semiconductor device of this embodiment, first, the gold wire bumps 18 are formed on the connection pads 12 of the silicon wafer 10 on which the circuit elements are formed, and the first copper foil-attached resin film CF1 is pressure bonded. Then, after performing the planarization process, the resin film 20a is cured to obtain the first interlayer insulating layer 20. The gold wire bump 18 is embedded in the first interlayer insulating layer 20, and the connecting portion 18a of the gold wire bump 18 is disposed under the copper foil 30a.

  Next, a resist 21 in which an opening 21a is provided on the gold wire bump 18 is formed on the copper foil 30a. Further, an opening 30x is formed in the copper foil 30a through the opening 21a of the resist 21 to form a connection hole CH, and the connection 18a of the gold wire bump 18 is exposed.

  When a resin film is formed on the connection portion 18a of the gold wire bump 18, the resin film is etched by wet blasting to provide a recess 20x, and the opening 30x of the copper foil 30a and the recess 20x below the recess 30x are provided. A connection hole CH is formed.

  Subsequently, the gold wire bump 18 and the copper foil 30a are electrically connected by forming a via conductor made of the conductive paste 40 or solder in the connection hole CH. Then, after forming the connection hole CH or filling the connection hole CH with the conductive paste 40, the copper foil 30 a is patterned to form the first wiring layer 30.

  Next, the resin film CF <b> 2 with the second copper foil is pressure-bonded on the first wiring layer 30 to use the resin film 22 a as the second interlayer insulating layer 22. Further, the dry film resist 23 provided with the opening 23a in the portion corresponding to the connection portion of the first wiring layer 30 is formed on the copper foil 32a, and the copper foil 32a is etched to form the opening 32x.

  Next, in this state, a via hole VH reaching the first wiring layer 30 is formed by etching the second interlayer insulating layer 22 from the opening 32x of the copper foil 32a by wet blasting.

  After that, the first wiring layer 30 and the copper foil 32a are electrically connected by forming a via conductor made of the conductive paste 40 or solder in the via hole VH. Then, after forming the via hole VH or filling the via hole VH with the conductive paste 40, the copper foil 32a is patterned to form the second wiring layer 32.

  By adopting such a method, it is not necessary to use the following technique when forming a multilayer wiring on the silicon wafer 10. 1) Formation of photo vias using photosensitive polyimide, 2) Formation of metal layer (seed layer, etc.) by sputtering, 3) Formation of via holes by laser, 4) Desmear of via holes by permanganic acid strong alkaline solution Treatment, 5) It is not necessary to use a technique related to wiring formation by wet plating (electroless Cu plating / electrolytic Cu plating).

  Therefore, since the number of steps involved in manufacturing can be greatly reduced, manufacturing cost can be reduced. Moreover, since a desmear process and a wet plating process become unnecessary, a hazardous waste liquid can be reduced and the environmental load can be reduced.

  As described above, in this embodiment, it is possible to form the rewiring (first and second wiring layers 30 and 32) having a multilayer structure on the silicon wafer 10 by a simple method capable of reducing the cost. Therefore, it becomes possible to easily cope with the manufacture of a semiconductor device that requires a large number of pins, such as ASIC and Logic.

  As shown in FIG. 14, in the semiconductor device 1 of this embodiment, the silicon substrate 10a (semiconductor substrate) is provided with an element formation region T (FIG. 1) in which circuit elements such as transistors are formed. Connection pads 12 are provided on the silicon substrate 10a, and the connection pads 12 are connected to the element formation region T (FIG. 1) via multilayer wiring (not shown).

  Gold wire bumps 18 (bump electrodes) are formed on the connection pads 12, and a first interlayer insulating layer 20 is formed on the silicon substrate 10 a in the lateral direction of the gold wire bumps 18. On the first interlayer insulating layer 20, a first wiring layer 30 having an opening 30x provided on the gold wire bump 18 is formed. The first wiring layer 30 is formed by patterning the copper foil 30a.

  The opening 30 x of the first wiring layer 30 is set to have a larger area than the connection portion 18 a of the gold wire bump 18. And the 1st interlayer insulation layer 20 between the gold wire bump 18 and the side surface of the opening part 30x of the 1st wiring layer 30 is etched in the thickness direction, and the recessed part 20x is comprised. A connection hole CH is constituted by the opening 30x and the recess 20x of the first wiring layer 30.

  The connection hole CH is filled with a conductive paste 40 (via conductor), and the gold wire bump 18 and the first wiring layer 30 are electrically connected by the conductive paste 40. Solder can be used in place of the conductive paste 40.

  Since the conductive pace 40 is filled in the recess 20x around the gold wire bump 18, the conductive paste 40 is formed on the gold wire bump 18 with good adhesion by the anchor effect of the recess 20x.

  Further, since the upper side surface of the connection portion 18a of the gold wire bump 18 is exposed by the recess 20x around the gold wire bump 18, the contact area between the gold wire bump 18 and the conductive paste 40 can be increased, so that the contact resistance is reduced. There is also a reduction effect.

  The recess 20x is not necessarily provided below the connection hole CH, and the connection hole CH may be configured from the opening 30x of the first wiring layer 30 by omitting the recess 20x.

  A second interlayer insulating layer 22 is formed on the first wiring layer 30, and a via hole VH reaching the connection portion of the first wiring layer 30 is formed in the second interlayer insulating layer 22.

  A second wiring layer 32 extending outward from the outer periphery of the via hole VH is formed on the second interlayer insulating layer 22. The second wiring layer 32 is formed by patterning the copper foil 32a.

  Furthermore, the conductive paste 40 (via conductor) is filled in the via hole VH. The conductive paste 40 is formed from the inside of the via hole VH to the vicinity of the outside thereof and covers the second wiring layer 32 in the vicinity of the via hole VH.

  Thus, the first wiring layer 30 is electrically connected to the second wiring layer 32 via the conductive paste 40 (via conductor). Solder can be used in place of the conductive paste 40.

  As described above, the conductive paste 40 is not necessarily formed by filling the via hole VH, and may be formed as a conformal via along the bottom and side surfaces of the via hole VH.

  Since the semiconductor device 1 of the present embodiment is manufactured by the above-described manufacturing method, the gold wire bump 18 and the first wiring layer 30 are electrically conductive filled in the connection hole CH (the opening 30x of the first wiring layer 30). The first wiring layer 30 is not disposed on the conductive paste 40 (via conductor), which is connected by the paste 40.

  Similarly, the first wiring layer 30 and the second wiring layer 32 are connected by the conductive paste 40 filled in the via hole VH, and the second wiring layer 32 is not disposed on the conductive paste 40 (via conductor). It becomes a structure.

  Further, a solder resist 24 provided with an opening 24 a is formed on the connection portion of the second wiring layer 32. An external connection terminal 34 connected to the second wiring layer 32 is provided in the opening 24 a of the solder resist 24.

  In the semiconductor device 1 of this embodiment, a multilayer wiring structure can be constructed at a low cost by a simple method. Therefore, a semiconductor device having multiple pins such as ASIC and Logic can be easily configured.

  By rewiring (first and second wiring layers 30 and 32), the pitch of the connection pads 12 of the silicon substrate 10a is converted to correspond to the pitch of the connection electrodes of the mounting substrate.

  Although not shown in particular, the external connection terminal 34 of the semiconductor device 1 is mounted by being connected to a connection electrode of a mounting substrate (motherboard or the like), and an underfill resin is filled in the lower gap of the semiconductor device 1.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 5 ... Nozzle, 10 ... Silicon wafer (semiconductor wafer), 10a ... Silicon substrate (semiconductor substrate), 12 ... Connection pad, 14 ... Passivation layer, 14a ... Silicon nitride layer, 14b ... Polyimide resin layer, 14x , 16a, 21a, 23a, 24a, 30x, 32x ... opening, 16, 21, 23 ... dry film resist, 18 ... gold wire bump (bump electrode), 18a ... connection, 20 ... first interlayer insulating layer, 20a, 22a ... resin film, 22 ... second interlayer insulating layer, 20x, C ... recess, 24 ... solder resist, 30 ... first wiring layer, 30a, 32a ... copper foil, 32 ... second wiring layer, 34 ... external connection terminal 40 ... conductive paste (via conductor), A ... chip region, T ... element formation region, CF1 ... resin film with first copper foil, CF2 ... with second copper foil Resin films, D ... Dicing line, CH ... connecting hole, VH ... via hole.

Claims (9)

A semiconductor substrate with bump electrodes;
A first insulating layer formed on the semiconductor substrate and disposed laterally of the bump electrode;
A first wiring layer formed on the first insulating layer and provided with a connection hole on the bump electrode;
A first via conductor formed of a conductive paste or solder, and formed in the connection hole to connect the bump electrode and the first wiring layer;
A second insulating layer formed on the first wiring layer;
A via hole formed in the second insulating layer and reaching the first wiring layer;
A second wiring layer formed on the second insulating layer and extending outward from an outer periphery of the via hole;
A semiconductor device comprising: a second via conductor formed of a conductive paste or solder, and formed in the via hole to connect the first wiring layer and the second wiring layer. The first via conductor fills the connection hole and covers the first wiring layer in the vicinity of the connection hole;
The semiconductor device according to claim 1, wherein the second via conductor fills the via hole and covers the second wiring layer in the vicinity of the via hole. The area of the connection hole of the first wiring layer is set larger than the upper surface of the bump electrode, and the first insulating layer between the bump electrode and the side surface of the connection hole of the first wiring layer is etched. Are provided with recesses,
The semiconductor device according to claim 1, wherein the connection hole includes the recess.   The semiconductor device according to claim 1, wherein the first wiring layer and the second wiring layer are formed of copper foil. By forming a first laminated film in which a first metal layer is laminated on a first insulating layer on a semiconductor wafer provided with a bump electrode, the bump electrode is embedded in the first insulating layer, and Disposing the bump electrode under the first metal layer;
Forming a connection hole by forming an opening in the first metal layer on the bump electrode;
Connecting the bump electrode and the first metal layer by the first via conductor by forming a first via conductor made of conductive paste or solder in the connection hole;
A step of forming a first wiring layer by patterning the first metal layer after the step of obtaining the connection hole or after the step of forming the first via conductor;
Forming a second laminated film in which a second metal layer is laminated on a second insulating layer on the first wiring layer;
Forming a resist having an opening in a portion corresponding to the connection portion of the first wiring layer on the second laminated film;
Etching the second metal layer through the opening of the resist to form the opening;
Forming a via hole reaching the first wiring layer by etching the second insulating layer through the opening of the second metal layer by wet blasting;
Connecting the first wiring layer and the second metal layer by the second via conductor by forming a second via conductor made of conductive paste or solder in the via hole;
And a step of forming a second wiring layer by patterning the second metal layer after the step of forming the via hole or after the step of forming the second via conductor. Device manufacturing method. In the step of obtaining the connection hole,
The area of the opening of the first metal layer is set larger than the upper surface of the bump electrode,
After the opening is formed in the first metal layer through the opening of the resist, the upper surface of the bump electrode is cleaned through the opening by wet blasting, and the first insulating layer around the bump electrode is etched. And forming a recess,
6. The method of manufacturing a semiconductor device according to claim 5, wherein the connection hole is configured by an opening of the first wiring layer and the recess.   The conductive paste is selectively formed in the via hole by a dispensing method or an inkjet method, or the photosensitive conductive paste is selectively formed in the via hole based on photolithography. A method for manufacturing a semiconductor device according to claim 5 or 6. In the step of forming the first via conductor,
The first via conductor is filled in the connection hole and is formed so as to cover the first metal layer in the vicinity of the connection hole,
In the step of forming the second via conductor,
7. The method of manufacturing a semiconductor device according to claim 5, wherein the second via conductor is filled in the via hole and covers the second metal layer in the vicinity of the via hole. In the step of forming the via hole,
7. The resist according to claim 5, wherein the resist disappears during the etching of the second insulating layer by the wet blasting method, and the surface of the second metal layer is roughened by the wet blasting method. The manufacturing method of the semiconductor device of description.

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