JP2012004397A - Method for manufacturing semiconductor device - Google Patents

Abstract

The performance of a semiconductor device is improved.
Channel dope ion implantation is performed by converging an ion beam 22 that has passed through a filter FL having a plurality of regularly arranged fine openings OP by a lens 26 and irradiating a semiconductor wafer 1W. At this time, a voltage having the same polarity as that of the ion beam 22 is applied to the filter FL. The impurity ions incident on the center of the opening OP of the filter FL can go straight through and pass through the opening OP, but are incident on a region other than the center of the opening OP of the filter FL. Impurity ions cannot travel through the opening OP because the traveling direction is bent by the electric field generated by the filter FL. For this reason, the impurity ions implanted into the semiconductor wafer 1W have a regular arrangement, and variations in the threshold voltage of the MISFET can be suppressed.
[Selection] Figure 16

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique effective when applied to the manufacture of a semiconductor device having a MISFET.

  A semiconductor device is manufactured by forming a semiconductor element such as a MISFET on a semiconductor substrate, forming a multilayer wiring structure on the semiconductor substrate, and connecting the semiconductor elements.

  Patent Documents 1 to 4 and Non-Patent Documents 1 and 2 describe techniques relating to variations in threshold voltage of MISFETs.

JP 2009-121401 A JP-A-8-18047 JP 2009-170494 A JP 2003-31682 A

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 24, NO. 5, OCTOBER 1989 2008 Symposium on VLSI Technology Digest of Technical Papers 156

  According to the study of the present inventor, the following has been found.

  A semiconductor device having a MISFET can be manufactured as follows. That is, an element isolation region is formed in a semiconductor substrate, and channel doping ion implantation for adjusting the threshold value of the MISFET is performed in an active region defined by the element isolation region, and then a gate insulating film and a gate electrode are formed. To do. Then, an extension region for LDD and a halo region are formed by ion implantation using the gate electrode as a mask, and then a sidewall insulating film is formed on the sidewall of the gate electrode, and the gate electrode and the sidewall insulating film are used as a mask. By implantation, source / drain regions having a higher impurity concentration than the extension region are formed. Thereafter, a metal silicide layer is formed on the source / drain regions by a salicide process.

  Impurities are introduced into the channel region of the MISFET by performing channel dope ion implantation on the semiconductor substrate. The threshold voltage of the MISFET can be controlled by this channel impurity (impurities introduced into the channel region). A plurality of MISFETs are formed on a semiconductor substrate, but the difference between the impurity distribution and the number of impurities when the channel regions are compared (impurity distribution in the channel region of one MISFET and the impurity distribution in the channel region of another MISFET) If the difference in the number of impurities) is large, the variation in the threshold voltage of the MISFET becomes large. That is, if the channel impurity distribution and the number of impurities differ between MISFETs that should have the same threshold voltage, the threshold voltage also becomes a different value. When the impurity arrangement state and the number of impurities) fluctuate, the threshold voltage fluctuates for each MISFET. In order to improve the performance of the semiconductor device, it is desired to suppress variations in threshold voltage for each MISFET.

  An object of the present invention is to provide a technique capable of improving the performance of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In a method of manufacturing a semiconductor device according to a typical embodiment, a voltage having the same polarity as that of an ion beam is applied to a filter having a plurality of regularly arranged openings, and the ion beam that has passed through the filter is converged. Channel dope ion implantation is performed by irradiating the substrate.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the representative embodiment, the performance of the semiconductor device can be improved.

It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; It is explanatory drawing which shows schematic structure of the ion implantation apparatus used for the channel dope ion implantation in the manufacturing process of the semiconductor device which is one embodiment of this invention. It is explanatory drawing which shows typically a mode that an ion beam passes a filter, is converged with a lens, and is irradiated to a semiconductor wafer. In FIG. 16, it is explanatory drawing which shows typically the state which is not irradiating an ion beam. It is a partial expanded sectional view of a filter. It is explanatory drawing which shows a mode that an ion beam passes the opening part of the filter which applied the voltage. It is explanatory drawing which shows a mode that an ion beam passes the opening part of the filter of the state which has not applied the voltage. It is a partial enlarged plan view of a filter. It is explanatory drawing which shows the arrangement | sequence state of a channel impurity at the time of performing channel dope ion implantation in the state which applied the voltage to the filter. It is explanatory drawing which shows the arrangement | sequence state of a channel impurity at the time of performing channel dope ion implantation without using a filter. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 25 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 24; FIG. 26 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 25; FIG. 27 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 26; FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27; FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28; FIG. 30 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 29; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 32 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 31; FIG. 33 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 32; FIG. 34 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 33; FIG. 35 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 34; FIG. 36 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 35; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 38 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 37; FIG. 39 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 38; FIG. 40 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 39; It is a top view of the semiconductor device which is other embodiments of the present invention. FIG. 42 is an essential part cross sectional view of the semiconductor device of FIG. 41 during a manufacturing step; FIG. 43 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 42; FIG. 44 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 43; FIG. 45 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 44; FIG. 46 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 45; FIG. 47 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 46; FIG. 48 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 47; It is a top view of the semiconductor device which is other embodiments of the present invention.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
A manufacturing process of the semiconductor device of the present embodiment will be described with reference to the drawings. FIG. 1 to FIG. 14 are cross-sectional views of a principal part during a manufacturing process of a semiconductor device according to an embodiment of the present invention, here, a semiconductor device having a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor).

  First, as shown in FIG. 1, a semiconductor substrate (semiconductor wafer) 1 made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is prepared. Then, the element isolation region 2 is formed on the main surface of the semiconductor substrate 1. The element isolation region 2 is made of an insulator such as silicon oxide, and is formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method. For example, the element isolation region 2 can be formed by an insulating film embedded in a groove (element isolation groove) formed in the semiconductor substrate 1. The element isolation region 2 forms an nMIS formation region 1A, which is a region (active region) where an n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) Qn is formed, and a p-channel MISFET Qp. A pMIS formation region 1B which is a region (active region) is defined.

  Next, after forming a thin insulating film (through film) 3 for preventing surface contamination on the surface (main surface) of the semiconductor substrate 1, as shown in FIG. 2, a photoresist covering the pMIS formation region 1B. A film (photoresist pattern) PR1a is formed using a photolithography technique. The nMIS formation region 1A is exposed without being covered with the photoresist film PR1a. The photoresist film PR1a can function as an ion implantation blocking mask for the pMIS formation region 1B.

  Next, in the nMIS formation region 1A, ion implantation for adjusting a threshold value of an n channel MISFET Qn (that is, channel dope ion implantation) IM1a is performed on the upper layer portion of the semiconductor substrate 1 later. In FIG. 2, the channel dope ion implantation IM1a is schematically indicated by an arrow.

  The ion implantation for adjusting the threshold value of the MISFET can also be referred to as channel doping ion implantation. By this channel doping ion implantation (ion implantation for adjusting the threshold value), impurities are introduced (doped) into the channel region of the MISFET. Is done. That is, in channel dope ion implantation, impurities (impurity ions) are introduced (doped) into a region including the channel region of the MISFET. The “channel region of the MISFET” here corresponds to a region that becomes a channel region of the MISFET when the MISFET is formed afterwards even though the MISFET is not formed at the channel doping ion implantation stage. This is common to channel dope ion implantation (threshold adjustment ion implantation) described in the first embodiment and the following second to sixth embodiments.

  In the ion implantation IM1a for adjusting the threshold, that is, the channel dope ion implantation IM1a, impurities (impurity ions) are introduced (ion implantation) into a region including the channel region of the n-channel MISFET Qn to form the channel dope layer 4a. Is done. The channel dope layer 4a includes a region that later becomes a channel region of the n-channel type MISFET Qn. As an impurity introduced into the channel dope layer 4a by the channel dope ion implantation IM1a, for example, a p-type impurity such as boron (B) can be used. In this channel dope ion implantation IM1a, the photoresist film PR1a covering the pMIS formation region 1B functions as an ion implantation blocking mask, so that ions are not implanted into the semiconductor substrate 1 in the pMIS formation region 1B.

  The method of channel dope ion implantation IM1a performed in this embodiment will be described in detail later.

  Next, in the nMIS formation region 1A, a p-type well (p-type semiconductor region) PW is formed from the main surface of the semiconductor substrate 1 to a predetermined depth. The p-type well PW is formed by, for example, ion-implanting a p-type impurity such as boron (B) into the semiconductor substrate 1 in the nMIS formation region 1A using the photoresist film PR1a covering the pMIS formation region 1B as an ion implantation blocking mask. Can be formed. The channel dope layer 4a is formed shallow in the upper layer portion of the semiconductor substrate 1, and the p-type well PW is formed deeper than the channel dope layer 4a in the semiconductor substrate 1. As another form, the p-type well PW may be formed by ion implantation first, and then the channel dope layer 4a may be formed by channel dope ion implantation IM1a. This is also the case with the following second to sixth embodiments. It is the same.

  Next, as shown in FIG. 3, after the photoresist film PR1a is removed by ashing or the like, a photoresist film (photoresist pattern) PR1b covering the nMIS formation region 1A is formed using a photolithography technique. The pMIS formation region 1B is exposed without being covered with the photoresist film PR1b. The photoresist film PR1b can function as an ion implantation blocking mask for the nMIS formation region 1A.

  Next, in the pMIS formation region 1B, ion implantation for adjusting a threshold value of a p-channel type MISFET Qp to be formed later (that is, channel dope ion implantation) IM1b is performed on the upper layer portion of the semiconductor substrate 1. In FIG. 3, the channel dope ion implantation IM1b is schematically indicated by an arrow.

  In the ion implantation IM1b for adjusting the threshold, that is, the channel dope ion implantation IM1b, impurities (impurity ions) are introduced (ion implantation) into a region including the channel region of the p-channel MISFET Qp to form the channel dope layer 4b. Is done. This channel dope layer 4b includes a region that will later become a channel region of the p-channel type MISFET Qp. As an impurity introduced into the channel dope layer 4b by channel dope ion implantation, for example, an n-type impurity such as phosphorus (P) can be used. In this channel dope ion implantation IM1b, the photoresist film PR1b covering the nMIS formation region 1A functions as an ion implantation blocking mask, so that the ion implantation is not performed on the semiconductor substrate 1 in the nMIS formation region 1A.

  Next, in the pMIS formation region 1B, an n-type well (n-type semiconductor region) NW is formed from the main surface of the semiconductor substrate 1 to a predetermined depth. The n-type well NW is formed by, for example, ion-implanting an n-type impurity such as phosphorus (P) into the semiconductor substrate 1 in the pMIS formation region 1B using the photoresist film PR1b covering the nMIS formation region 1A as an ion implantation blocking mask. Can be formed. The channel dope layer 4b is formed shallow in the upper layer portion of the semiconductor substrate 1, and the n-type well NW is formed deeper than the channel dope layer 4b in the semiconductor substrate 1. As another form, the n-type well NW can be formed by ion implantation first, and then the channel dope ion implantation IM1b can be used to form the channel dope layer 4b. This is also the case in the following second to fourth embodiments. It is the same. As yet another form, after the channel dope layer 4b and the n-type well NW are first formed in the pMIS formation region 1B, the channel dope layer 4a and the p-type well PW can be formed in the nMIS formation region 1A. The same applies to the following second to sixth embodiments.

  The method of channel dope ion implantation IM1b performed in this embodiment will be described in more detail later.

  Next, as shown in FIG. 4, after removing the photoresist film PR <b> 1 b by ashing or the like, the insulating film 3 is removed by wet etching or the like using, for example, a hydrofluoric acid (HF) aqueous solution. After the surface is cleaned (washed), the gate insulating film is formed on the surface of the semiconductor substrate 1 (main surface, here, the surface of the p-type well PW and the n-type well NW) in the nMIS formation region 1A and the pMIS formation region 1B. An insulating film 5 is formed. This insulating film 5 will later become a gate insulating film of the n-channel MISFET Qn and the p-channel MISFET Qp. The insulating film 5 is made of, for example, a thin silicon oxide film, and can be formed by, for example, a thermal oxidation method.

  In addition, the channel dope ion implantation IM1a and IM1b, the ion implantation for forming the p-type well PW, and the ion implantation for forming the n-type well NW are performed before the insulating film 5 is formed. It is possible to prevent the insulating film 5 from being damaged by ion implantation.

  Next, on the entire main surface of the semiconductor substrate 1 (that is, on the insulating film 5 in the nMIS formation region 1A and the pMIS formation region 1B), a silicon film such as a polycrystalline silicon film is formed as a conductor film for forming a gate electrode. A film 6 is formed. The nMIS formation region 1A (region to be a gate electrode GE1 described later) in the silicon film 6 is an n-type impurity such as phosphorus (P) or arsenic (As) using a photoresist film (not shown) as a mask. Is ion-implanted to form a low-resistance n-type semiconductor film (doped polysilicon film). Further, the pMIS formation region 1B (region to be a gate electrode GE2 described later) in the silicon film 6 is made of p-type impurities such as boron (B) using another photoresist film (not shown) as a mask. By ion implantation or the like, a low-resistance p-type semiconductor film (doped polysilicon film) is obtained. Further, the silicon film 6 can be changed from an amorphous silicon film at the time of film formation to a polycrystalline silicon film by heat treatment after film formation (after ion implantation).

  Next, as shown in FIG. 5, the silicon film 6 is patterned using a photolithography method and a dry etching method, thereby forming gate electrodes GE1 and GE2.

  The gate electrode GE1 serving as the gate electrode of the n-channel type MISFET Qn is made of polycrystalline silicon (n-type semiconductor film, doped polysilicon film) into which an n-type impurity is introduced, and the p-type well PW (of the nMIS formation region 1A) An insulating film 5 is formed on the upper channel doped layer 4a). The insulating film 5 remaining under the gate electrode GE1 becomes the gate insulating film 5a of the n-channel type MISFET Qn. That is, the gate electrode GE1 is formed on the insulating film 5 (that is, the gate insulating film 5a) in the nMIS formation region 1A. Further, the gate electrode GE2 serving as the gate electrode of the p-channel type MISFET Qp is made of polycrystalline silicon (p-type semiconductor film, doped polysilicon film) into which p-type impurities are introduced, and the n-type well NW in the pMIS formation region 1B. (On the upper channel doped layer 4b) with an insulating film 5 interposed therebetween. The insulating film 5 remaining under the gate electrode GE2 becomes the gate insulating film 5b of the p-channel type MISFET Qp. That is, the gate electrode GE2 is formed on the insulating film 5 (that is, the gate insulating film 5b) in the pMIS formation region 1B.

  Next, as shown in FIG. 6, a photoresist film (photoresist pattern) PR2a covering the pMIS formation region 1B is formed using a photolithography technique. The nMIS formation region 1A is exposed without being covered with the photoresist film PR2a. The photoresist film PR2a can function as a mask for preventing ion implantation into the pMIS formation region 1B. For this reason, in ion implantation IM2a and IM3a described later, the photoresist film PR2a functions as an ion implantation blocking mask, and ions are not implanted into the semiconductor substrate 1 in the pMIS formation region 1B.

Next, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into regions on both sides of the gate electrode GE1 of the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A. A pair of extension regions (first semiconductor region, source / drain extension region, n ⁻ type semiconductor region) EX1 is formed.

The extension region EX1 is an n-type semiconductor region, and has an impurity concentration lower than that of an n ⁺ -type semiconductor region SD1 to be formed later. In FIG. 6, the ion implantation IM2a for forming the extension region EX1 is schematically indicated by an arrow. In this ion implantation IM2a, since the gate electrode GE1 can also function as a mask (ion implantation blocking mask), the extension region EX1 is formed in alignment with the gate electrode GE1 (side wall thereof) and directly below the gate electrode GE1. No impurities are introduced (ion implantation). The depth (junction depth) of the extension region EX1 is shallower than the depth (junction depth) of the n ⁺ type semiconductor region SD1 to be formed later. Further, the ion implantation IM2a for forming the extension region EX1 is preferably not the oblique ion implantation but the ion implantation in a direction perpendicular to the main surface of the semiconductor substrate 1.

  Next, as shown in FIG. 7, ion implantation (halo ion implantation) IM3a of p-type impurities is performed on the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A to perform a halo region (p-type semiconductor region) HA1. Form. In FIG. 7, ion implantation (halo ion implantation) IM3a for forming the halo region HA1 is schematically indicated by an arrow.

  The halo region HA1 has a conductivity type opposite to that of the extension region EX1 and the same conductivity type as that of the p-type well PW, and is a p-type (p-type semiconductor region) here. The halo region HA1 is formed to suppress short channel characteristics (punch through). In the ion implantation IM3a for forming the halo region HA1, the gate electrode GE1 can also function as a mask (ion implantation blocking mask). The halo region HA1 is formed so as to enclose (cover) the extension region EX1, and has an impurity concentration (p-type impurity concentration) higher than that of the p-type well PW. The ion implantation IM3a for forming the halo region HA1 is more preferably an oblique ion implantation (gradient ion implantation), whereby the halo region HA1 is accurately formed so as to wrap (cover) the extension region EX1. Can do. In general ion implantation, impurity ions are accelerated and implanted in a direction perpendicular to the main surface of the semiconductor substrate 1. In oblique ion implantation, a predetermined direction from a direction perpendicular to the main surface of the semiconductor substrate 1 is used. Impurity ions are accelerated and implanted in an inclined direction.

  Next, as shown in FIG. 8, after removing the photoresist film PR2a by ashing or the like, a photoresist film (photoresist pattern) PR2b covering the nMIS formation region 1A is formed by using a photolithography technique. The pMIS formation region 1B is exposed without being covered with the photoresist film PR2b. The photoresist film PR2b can function as an ion implantation blocking mask for the nMIS formation region 1A. For this reason, in ion implantation IM2b and IM3b described later, the photoresist film PR2b functions as an ion implantation blocking mask, and ions are not implanted into the semiconductor substrate 1 in the nMIS formation region 1A.

Next, a p-type impurity such as boron (B) is ion-implanted into regions on both sides of the gate electrode GE2 of the semiconductor substrate 1 (n-type well NW) in the pMIS formation region 1B, thereby (a pair of) extension regions. (First semiconductor region, source / drain extension region, p ⁻ type semiconductor region) EX2 is formed. The extension region EX2 is a p-type semiconductor region, and has an impurity concentration lower than that of the p ⁺ -type semiconductor region SD2 to be formed later. Note that an ion implantation IM2b for forming the extension region EX2 and an ion implantation IM3b for forming a halo region HA2 to be described later are performed as separate ion implantation steps, but in FIG. It is shown schematically.

In the ion implantation IM2b for forming the extension region EX2, since the gate electrode GE2 can also function as a mask (ion implantation blocking mask), the extension region EX2 is formed in alignment with the gate electrode GE2 (side wall thereof). Impurities are not introduced (ion implantation) immediately below the gate electrode GE2. The depth (junction depth) of the extension region EX2 is shallower than the depth (junction depth) of the p ⁺ type semiconductor region SD2 to be formed later. Further, the ion implantation IM2b for forming the extension region EX2 is preferably not ion implantation but oblique implantation in a direction perpendicular to the main surface of the semiconductor substrate 1.

  Next, n-type impurity ion implantation (halo ion implantation) IM3b is performed on the semiconductor substrate 1 (n-type well NW) in the pMIS formation region 1B to form a halo region (n-type semiconductor region) HA2. The halo region HA2 has a conductivity type opposite to that of the extension region EX2 and the same conductivity type as that of the n-type well NW, and here is an n-type (n-type semiconductor region). The halo region HA2 is formed to suppress short channel characteristics (punch through). In the ion implantation IM3b for forming the halo region HA2, the gate electrode GE2 can also function as a mask (ion implantation blocking mask). The halo region HA2 is formed so as to enclose (cover) the extension region EX2, and has an impurity concentration (n-type impurity concentration) higher than that of the n-type well NW. The ion implantation IM3b for forming the halo region HA2 is more preferably an oblique ion implantation (gradient ion implantation), whereby the halo region HA2 is accurately formed so as to wrap (cover) the extension region EX2. Can do.

  As another form, the extension region EX2 and the halo region HA2 may be formed in the pMIS formation region 1B first, and then the extension region EX1 and the halo region HA1 may be formed in the nMIS formation region 1A. The same applies to the second to sixth embodiments.

  The halo regions HA1 and HA2 are preferably formed to suppress short channel characteristics. However, the formation of the halo regions HA1 and HA2 can be omitted if unnecessary, and this is the same in the following second to sixth embodiments. .

  The extension region EX1 and the halo region HA1 do not necessarily have to be formed in this order. However, the ion implantations IM2a and IM3a that form the extension region EX1 and the halo region HA1 are at least after the formation of the gate electrode GE1 and It is necessary to perform this before forming a later-described side wall SW on the side wall of the gate electrode GE1. Similarly, the extension region EX2 and the halo region HA2 do not necessarily have to be formed in this order. However, each ion implantation IM2b and IM3b forming the extension region EX2 and the halo region HA2 is at least after the gate electrode GE2 is formed. In addition, it is necessary to perform this before forming a later-described side wall SW on the side wall of the gate electrode GE2.

  Next, as shown in FIG. 9, after removing the photoresist film PR2b by ashing or the like, as an insulating film (sidewall insulating film) on the side walls of the gate electrodes GE1 and GE2, for example, silicon oxide or silicon nitride or Sidewall spacers or sidewalls (sidewall insulating films, sidewall spacers) SW made of a laminated film of these insulating films are formed. For example, the sidewall SW is formed by depositing a silicon oxide film, a silicon nitride film, or a laminated film thereof on the semiconductor substrate 1 (entire main surface thereof), and depositing the silicon oxide film, the silicon nitride film, or the laminated film thereof by RIE ( Reactive Ion Etching (reactive ion etching) can be formed by anisotropic etching.

  Next, as shown in FIG. 10, a photoresist film (photoresist pattern) PR3a covering the pMIS formation region 1B is formed by using a photolithography technique. The nMIS formation region 1A is exposed without being covered with the photoresist film PR3a. The photoresist film PR3a can function as a mask for preventing ion implantation into the pMIS formation region 1B. For this reason, in the ion implantation IM4a described later, the photoresist film PR3a functions as an ion implantation blocking mask, and ions are not implanted into the semiconductor substrate 1 in the pMIS formation region 1B.

Next, an n-type impurity such as phosphorus (P) or arsenic (As) is ion-implanted into regions on both sides of the gate electrode GE1 and the sidewall SW of the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A. Thereby, (a pair of) n ⁺ type semiconductor regions SD1 (source and drain) are formed. In FIG. 10, ion implantation IM4a for forming the n ⁺ type semiconductor region SD1 is schematically indicated by an arrow. In this ion implantation IM4a, the gate electrode GE1 and the sidewall SW on the side wall thereof can also function as a mask (ion implantation blocking mask), so that the n ⁺ type semiconductor region SD1 is a side on the side wall of the gate electrode GE1. Impurities are not introduced (ion-implanted) immediately below the gate electrode GE1 and the side wall SW. The depth (junction depth) of the n ⁺ -type semiconductor region SD1 is deeper than the depth (junction depth) of the extension region EX1.

The n ⁺ type semiconductor region (second semiconductor region) SD1 and the extension region (first semiconductor region) EX1 have the same conductivity type, but the n ⁺ type semiconductor region SD1 has an impurity concentration (n type) than the extension region EX1. Impurity concentration) is high. Thereby, an n-type semiconductor region (impurity diffusion layer) functioning as a source or drain of the n-channel type MISFET Qn is formed by the n ⁺ -type semiconductor region (impurity diffusion layer) SD1 and the extension region (n ⁻ -type semiconductor region) EX1. Is done. In other words, the extension region EX1 and the n ⁺ type semiconductor region SD1 having a higher impurity concentration function as a semiconductor region for the source or drain of the n-channel type MISFET Qn. Therefore, the source / drain region of the n-channel type MISFET Qn has an LDD (Lightly doped Drain) structure. As described above, the extension region EX1 is formed in a self-aligned manner with respect to the gate electrode GE1, and the n ⁺ type semiconductor region SD1 is in a self-aligned manner with respect to the sidewall SW formed on the sidewall of the gate electrode GE1. Formed.

  Next, as shown in FIG. 11, after removing the photoresist film PR3a by ashing or the like, a photoresist film (photoresist pattern) PR3b that covers the nMIS formation region 1A is formed by using a photolithography technique. The pMIS formation region 1B is exposed without being covered with the photoresist film PR3b. The photoresist film PR3b can function as an ion implantation blocking mask for the nMIS formation region 1A. For this reason, in ion implantation IM4b described later, the photoresist film PR3b functions as an ion implantation blocking mask, and ions are not implanted into the semiconductor substrate 1 in the nMIS formation region 1A.

Next, a p-type impurity such as boron (B) is ion-implanted into regions on both sides of the gate electrode GE2 and the side wall SW of the semiconductor substrate 1 (n-type well NW) in the pMIS formation region 1B. The p ⁺ type semiconductor region SD2 (source, drain) is formed. In FIG. 11, ion implantation IM4b for forming the p ⁺ type semiconductor region SD2 is schematically indicated by an arrow. In this ion implantation IM4b, since the gate electrode GE2 and the sidewall SW on the side wall thereof can also function as a mask (ion implantation blocking mask), the p ⁺ type semiconductor region SD2 is formed on the side on the side wall of the gate electrode GE2. Impurities are not introduced (ion-implanted) immediately below the gate electrode GE2 and the side wall SW. The depth (junction depth) of the p ⁺ type semiconductor region SD2 is deeper than the depth (junction depth) of the extension region EX2.

The p ⁺ type semiconductor region (second semiconductor region) SD2 and the extension region (first semiconductor region) EX2 have the same conductivity type, but the p ⁺ type semiconductor region SD2 has an impurity concentration (p type) higher than that of the extension region EX2. Impurity concentration) is high. Thereby, a p-type semiconductor region (impurity diffusion layer) functioning as a source or drain of the p-channel type MISFET Qp is formed by the p ⁺ -type semiconductor region (impurity diffusion layer) SD2 and the extension region (p ⁻ -type semiconductor region) EX2. Is done. In other words, the extension region EX2 and the p ⁺ type semiconductor region SD2 having a higher impurity concentration function as a semiconductor region for the source or drain of the p channel MISFET Qp. Therefore, the source / drain regions of the p-channel type MISFET Qp have an LDD structure. As described above, the extension region EX2 is formed in a self-aligned manner with respect to the gate electrode GE2, and the p ⁺ type semiconductor region SD2 is in a self-aligned manner with respect to the sidewall SW formed on the sidewall of the gate electrode GE2. Formed.

As another form, after forming the p ⁺ type semiconductor region SD2 in the pMIS formation region 1B first, the n ⁺ type semiconductor region SD1 can be formed in the nMIS formation region 1A. The same applies to Embodiments 2 to 6.

  Next, the photoresist film PR3b is removed by ashing or the like. Then, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed. This annealing process can be performed by, for example, a flash lamp annealing process at about 1050 ° C.

  In this manner, an n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) Qn is formed as a field effect transistor in the nMIS formation region 1A (the p-type well PW). A p-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) Qp is formed as a field effect transistor in the pMIS formation region 1B (n-type well NW thereof). Thereby, the structure of FIG. 12 is obtained. The n-channel type MISFET Qn can be regarded as an n-channel field effect transistor, and the p-channel type MISFET Qp can be regarded as a p-channel field effect transistor.

Next, the surfaces of the gate electrodes GE1, GE2, n ⁺ type semiconductor region SD1 and p ⁺ type semiconductor region SD2 are exposed, and a metal film such as a cobalt (Co) film or nickel (Ni) is deposited and heat-treated. Thus, as shown in FIG. 13, the metal silicide layers 11 are formed on the surfaces of the gate electrodes GE1, GE2, the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2, respectively. As a result, the diffusion resistance, contact resistance, etc. of the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2 can be reduced. Thereafter, the unreacted metal film is removed.

  Next, an insulating film (interlayer insulating film) 12 is formed on the main surface of the semiconductor substrate 1. That is, the insulating film 12 is formed on the semiconductor substrate 1 including the metal silicide layer 11 so as to cover the gate electrodes GE1 and GE2 and the sidewall SW. The insulating film 12 is made of, for example, a single film of a silicon oxide film or a laminated film of a silicon nitride film and a thicker silicon oxide film. Thereafter, the upper surface of the insulating film 12 is planarized by polishing the surface (upper surface) of the insulating film 12 by CMP (Chemical Mechanical Polishing). Even if unevenness is formed on the surface of the insulating film 12 due to the base step, by polishing the surface of the insulating film 12 by the CMP method, an interlayer insulating film having a flattened surface can be obtained. .

Next, using the photoresist pattern (not shown) formed on the insulating film 12 as an etching mask, the insulating film 12 is dry-etched to form contact holes (through holes, holes) 13 in the insulating film 12. To do. At the bottom of the contact hole 13, a part of the main surface of the semiconductor substrate 1, for example, a part of the metal silicide layer 11 on the surface of the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2, and the gate electrodes GE1 and GE2 A part of the metal silicide layer 11 on the surface is exposed.

Next, a conductive plug (connection conductor portion) 14 made of tungsten (W) or the like is formed in the contact hole 13. In order to form the plug 14, for example, a barrier conductor film (for example, a titanium film, a titanium nitride film, or a laminated film thereof) is formed on the insulating film 12 including the inside (on the bottom and side walls) of the contact hole 13 by a plasma CVD method. ). Then, a main conductor film made of a tungsten film or the like is formed by CVD or the like so as to fill the contact hole 13 on the barrier conductor film, and unnecessary main conductor film and barrier conductor film on the insulating film 12 are formed by CMP or etch back. By removing by a method or the like, the plug 14 can be formed. In order to simplify the drawing, the plug 14 is shown by integrating the main conductor film and the barrier conductor film. The plug 14 is in contact with and electrically connected to the metal silicide layer 11 on the surface of the gate electrodes GE1, GE2, n ⁺ type semiconductor region SD1 or p ⁺ type semiconductor region SD2 at the bottom thereof.

  Next, as shown in FIG. 14, an insulating film 15 is formed on the insulating film 12 in which the plugs 14 are embedded. The insulating film 15 can also be formed of a stacked film of a plurality of insulating films.

  Next, the wiring M1 which is the first layer wiring is formed by a single damascene method. Specifically, the wiring M1 can be formed as follows. First, after a wiring groove is formed in a predetermined region of the insulating film 15 by dry etching using a photoresist pattern (not shown) as a mask, a barrier conductor film (on the insulating film 15 including the bottom and side walls of the wiring groove is formed. For example, a titanium nitride film, a tantalum film, a tantalum nitride film, or the like is formed. Subsequently, a copper seed layer is formed on the barrier conductor film by a CVD method or a sputtering method, and a copper plating film is further formed on the seed layer by using an electrolytic plating method. Embed the inside. Then, the main conductor film (copper plating film and seed layer) and the barrier metal film in a region other than the wiring groove are removed by CMP, and the first layer wiring M1 embedded in the wiring groove and using copper as the main conductive material. Form. For simplification of the drawing, the wiring M1 is shown by integrating a barrier conductor film, a seed layer, and a copper plating film.

Wiring M1 is electrically connected to n ⁺ type semiconductor region SD1 and p ⁺ type semiconductor region SD2 for source or drain of n channel type MISFET Qn and p channel type MISFET Qp, gate electrodes GE1, GE2, etc. via plug 14. ing. Thereafter, a second layer wiring is formed by a dual damascene method, but illustration and description thereof are omitted here.

  As described above, the semiconductor device of the present embodiment is manufactured.

  Next, channel dope ion implantation IM1a and IM1b in the present embodiment will be described in more detail.

  In the present embodiment, one of the main features is that when the channel dope ion implantation IM1a and IM1b are performed, the ion implanted impurities are distributed in a regular arrangement in the semiconductor substrate 1. In order to realize this, an ion implantation method as described below is used. Note that, hereinafter, the “ion implantation method according to the first embodiment” refers to the ion implantation method described here (ion implantation method using a filter FL to which a voltage is applied).

  FIG. 15 is an explanatory diagram showing a schematic configuration of an ion implantation apparatus (semiconductor manufacturing apparatus) 21 used for the channel dope ion implantation IM1a and IM1b of the present embodiment.

  As shown in FIG. 15, an ion implantation apparatus 21 includes an ion source (ion source) 23 that generates ions, and an acceleration tube (accelerator) 24 that accelerates ions generated from the ion source 23 to generate an ion beam 22. A mass analyzing magnet 25 capable of bending the traveling direction of the ion beam 22, a lens 26 capable of converging the ion beam 22, and a processing chamber (implantation chamber) 27 for performing ion implantation on the semiconductor wafer 1W. And have. The semiconductor wafer 1W corresponds to the semiconductor substrate 1, and the ion beam 22 converged by the lens 26 is irradiated to the semiconductor wafer 1W disposed in the processing chamber 27 of the end station. The lens 26 is an electromagnetic lens and can focus the ion beam 22 by an electric field. The mass spectrometry magnet 25 also has a function of selecting ions.

  When performing ion implantation using the ion implantation apparatus 21, the semiconductor wafer 1 </ b> W to be subjected to ion implantation processing is disposed in the processing chamber 27. Then, ions generated by the ion source 23 are accelerated by the acceleration tube 24 to generate the ion beam 22, the traveling direction of the ion beam 22 is bent by the mass analysis magnet 25, and the ion beam 22 that has passed through the mass analysis magnet 25. Is converged by the lens 26 and irradiated to the semiconductor wafer 1W in the processing chamber 27. Thereby, impurity ions constituting the ion beam 22 are implanted (introduced) into the semiconductor wafer 1W. The semiconductor wafer 1W for which the predetermined ion implantation processing has been completed is moved (transferred) from the processing chamber 27 to the wafer exchange chamber 28, and the next semiconductor wafer 1W (semiconductor wafer 1W to be subjected to ion implantation processing) enters the processing chamber 27. The semiconductor wafer 1W in the processing chamber 27 is moved (conveyed), and ion implantation processing is performed.

  As shown in FIG. 15, the channel-doped ion implantation IM1a and IM1b of the present embodiment has a filter FL disposed in front of the lens 26, and the ion beam 22 that has passed through the filter FL is converged by the lens 26 to be a semiconductor. Irradiating the wafer 1W is one of the main features. Therefore, the ion implantation apparatus 21 further includes a filter FL arranged in front of the lens 26 (between the mass analysis magnet 25 and the lens 26 in the case of FIG. 15).

  FIG. 16 is an explanatory diagram schematically showing a state in which the ion beam 22 passes through the filter FL, is converged by the lens 26, and is irradiated onto the semiconductor wafer 1W. FIG. 17 is an explanatory diagram schematically showing a state where the ion beam 22 is not irradiated in FIG. Accordingly, a view in which the illustration of the ion beam 22 is omitted from FIG. 16 corresponds to FIG. FIG. 18 is a partially enlarged sectional view (main part sectional view) of the filter FL, showing a section parallel to the thickness direction of the filter FL.

  As shown in FIGS. 16 and 17, the filter FL is disposed in front of the lens 26 and at a position where the ion beam 22 passes. The filter FL is made of a conductor and is preferably made of a metal material. For example, the filter FL can be formed of tungsten (W), tantalum (Ta), platinum (Pt), or the like.

  Also, as shown in FIGS. 16 to 18, the filter FL has a plurality of openings (holes, through holes) OP arranged regularly. The size and shape of each opening OP are the same between the openings OP. The planar shape of the opening OP is preferably a square, but more preferably a square. In the filter FL, the plurality of openings OP are regularly arranged, but are preferably arranged in a lattice (array) form. Therefore, the filter FL is preferably a grid filter in which square openings OP are arranged in a grid pattern.

The dimension (side length) W ₁ of the opening OP can be set to, for example, about 5 to 20 μm, and the interval W ₂ between the adjacent openings OP is set to, for example, about 5 to 20 μm. The thickness W _{3 of the} filter FL can be set to about 10 to 50 μm, for example, but these dimensions (W ₁ , W ₂ , W ₃ ) can be changed as necessary. (W ₁ , W ₂ , W ₃ are shown in FIG. 18).

  The filter FL has a flat outer shape and has two main surfaces (a front surface and a back surface) that are parallel to each other and located on opposite sides, but the main surface on the side on which the ion beam 22 is incident is the surface of the filter 22. The front surface is called the front surface, and the opposite main surface is called the back surface of the filter FL. The opening OP is a through-hole penetrating the filter FL and reaches from the front surface to the back surface of the filter FL, and the side wall (inner wall) of the opening OP is perpendicular to the front surface and the back surface of the filter FL. The filter FL is arranged so that the ion beam 22 is incident perpendicular to the surface of the filter FL. Here, the ion beam 22 before reaching the filter FL is referred to as an ion beam 22a, the ion beam 22 that has passed through the opening OP of the filter FL is referred to as an ion beam 22b, and the lens after passing through the opening OP of the filter FL. The ion beam 22 converged at 26 and incident on the semiconductor wafer 1W is referred to as an ion beam 22c. The semiconductor wafer 1W is irradiated with this ion beam 22c.

  When performing channel dope ion implantation IM1a and IM1b of the present embodiment, a voltage is applied to the filter FL, and the ion beam 22 (that is, the ion beam 22b) that has passed through the opening OP of the filter FL to which the voltage is applied. ) Is converged by the lens 26, and the converged ion beam 22 (that is, the ion beam 22c) is irradiated onto the semiconductor wafer 1W.

  The polarity of the voltage applied to the filter FL is the same as the polarity of the impurity ions to be ion-implanted (that is, the polarity of the ion beam 22). Specifically, when the impurity ions constituting the ion beam 22 (22a) (the impurity ions are implanted into the semiconductor wafer 1W) are positive ions, a positive voltage is applied to the filter FL, while the ions When the impurity ions constituting the beam 22 (22a) (the impurity ions are implanted into the semiconductor wafer 1W) are negative ions, a negative voltage is applied to the filter FL. That is, when the ion beam 22 (22a) is a positive ion beam, a positive voltage is applied to the filter FL, and when the ion beam 22 (22a) is a negative ion beam, a negative voltage is applied to the filter FL. Although the voltage applied to the filter FL depends on the acceleration energy of the ion beam 22 and the size of the opening OP of the filter FL, for example, a positive or negative continuous voltage having an absolute value of about 0 to 100 V, or a pulsed voltage. It can be.

  FIG. 19 is an explanatory diagram showing a state in which the ion beam 22 passes through the opening OP of the filter FL to which a voltage (voltage having the same polarity as the ion beam 22) is applied, and a cross section corresponding to FIG. 18 is shown. . FIG. 20 is an explanatory diagram showing a state in which the ion beam 22 passes through the opening OP of the filter FL in a state where no voltage is applied to the filter FL and no voltage is applied, unlike the present embodiment. In FIG. 19 and FIG. 20, the locus of each impurity ion constituting the ion beam 22 is schematically shown by an arrow.

  When performing channel dope ion implantation IM1a and IM1b, the ion beam 22a tends to enter perpendicularly to the surface of the filter FL. At this time, out of the impurity ions constituting the ion beam 22a, the impurity ions that have traveled toward the non-opening portion of the filter FL (portion made of a metal material constituting the filter FL) apply a voltage to the filter FL. Regardless of whether it is open or not, as shown in FIG. 19 and FIG. 20, it is not possible to pass through the opening OP by being shielded by the non-opening portion.

  In contrast to the present embodiment, when no voltage is applied to the filter FL, as shown in FIG. 20, the impurity ions constituting the ion beam 22a are directed toward the opening OP of the filter FL. Since the impurity ions that have traveled in this way have no shielding, all can pass through the opening OP. For this reason, when no voltage is applied to the filter FL, an amount of impurity ions corresponding to the plane area of the opening OP passes through the entire opening OP in each opening OP.

  On the other hand, in the present embodiment, among the impurity ions constituting the ion beam 22a, the impurity ions that have progressed toward the center (center) of the opening OP of the filter FL (denoted by reference numeral 22d in FIG. 19). As shown in FIG. 19, the impurity ions shown in FIG. 19 can pass (pass through) the center (center) of the opening OP. This is because even when a voltage (voltage having the same polarity as the ion beam 22) is applied to the filter FL, the center (center) of the opening OP is in a state where the electric field is just balanced (balanced). The impurity ions 22d incident toward the center (center) of the portion OP are not bent by the electric field (electric field) generated by the filter FL, but go straight and pass (pass through) the center (center) of the opening OP. Because it can.

  However, in the present embodiment, among the impurity ions constituting the ion beam 22a, the impurity ions that have progressed toward a position shifted from the center (center) of the opening OP of the filter FL (impurity ions 22d in FIG. 19). Impurity ions indicated by arrows other than (corresponding to this) cannot pass (pass through) the opening OP as shown in FIG. This is because a voltage (voltage having the same polarity as that of the ion beam 22) is applied to the filter FL, so that impurity ions incident toward a position shifted from the center (center) of the opening OP are an electric field generated by the filter FL. This is because the traveling direction is bent by the (electric field) and cannot pass (pass through) the opening OP linearly.

  FIG. 21 is a partially enlarged plan view (main part plan view) of the filter FL. FIG. 21 is a plan view, but the filter FL is hatched for easy understanding. FIG. 21 shows one opening OP, but in the actual filter FL, a large number of openings OP are arranged in a lattice pattern.

  Unlike the present embodiment, when no voltage is applied to the filter FL, as described with reference to FIG. 20, the impurity ions constituting the ion beam 22a are formed in the opening shown in FIG. Go straight through the OP (pass through). On the other hand, in the present embodiment, since a voltage is applied to the filter FL, impurity ions (impurity ions in FIG. 19) incident toward the center (center) CT of the opening OP shown in FIG. 22d) can pass straight through the opening OP as it is, but the impurity ions incident toward the region other than the central portion CT are bent in the traveling direction by the electric field (electric field) by the filter FL ( Scattered) and cannot pass through the opening OP. That is, in the present embodiment, out of the impurity ions constituting the ion beam 22a, the impurity ions incident on the center (central portion CT) of the opening OP pass through the opening OP and the semiconductor wafer 1W (semiconductor substrate 1). The impurity ions injected into the peripheral portion of the opening OP (regions other than the central portion CT) are scattered by the electric field generated by the filter FL and are not injected into the semiconductor wafer 1W (semiconductor substrate 1).

That is, when no voltage is applied to the filter FL, the entire opening OP functions as an opening through which impurity ions (ion beams) pass, but by applying a voltage to the filter FL as in the present embodiment, Only the central portion CT of the opening OP functions as an effective opening that allows the impurity ions to pass therethrough, and even in the opening OP, the region (peripheral region) other than the central portion CT does not pass (blocks) the impurity ions. ) It can function as an effective mask area. In FIG. 21, a line indicating the center portion CT is a virtual line indicating a region through which impurity ions can pass, and an object is not particularly present. By applying a voltage to the filter FL in this way, the size of the effective opening (the central portion CT through which impurity ions can pass) of the filter FL can be made sufficiently smaller than the size W ₁ of the opening OP. In other words, it can be a minute dimension exceeding the processing limit of miniaturization of the opening OP. The dimensions of the effective aperture (impurity ions that can pass through the central portion CT) of the filter FL is adjusting the voltage applied to the filter FL in accordance with the size W ₁ of the energy (accelerating energy) and the opening of the ion beam 22 By doing so, it can be controlled.

  In the present embodiment, impurity ions 22d that have passed through the central portion CT of each opening OP of the filter FL constitute an ion beam 22b. For this reason, the ion beam 22b has a considerably lower density of impurity ions than the ion beam 22a. The impurity ions 22d that have passed through the central portion CT of each opening OP of the filter FL have an arrangement reflecting the arrangement of the opening OP in the filter FL. However, the opening OP is regularly arranged in the filter FL. Since they are arranged, the impurity ions 22d that have passed through the central portion CT of each opening OP of the filter FL have a regular arrangement reflecting the arrangement of the openings OP in the filter FL. For this reason, the ion beam 22b is configured by the regularly arranged impurity ions 22d that have passed through the filter FL. The ion beam 22b is converged by the lens 26, and the focused ion beam 22c is irradiated onto the semiconductor wafer 1W, whereby impurity ions are implanted into the semiconductor wafer 1W (ie, the semiconductor substrate 1). Since the impurity ions 22d that have passed through the central portion CT of each opening OP of the filter FL have a regular arrangement, the impurity ions implanted into the semiconductor wafer 1W (that is, the semiconductor substrate 1) are also regularly arranged. It will have.

  FIG. 22 is an explanatory view (perspective view) showing an arrangement state of channel impurities 30 when channel dope ion implantation (IM1a, IM1b) is performed with a voltage (voltage having the same polarity as the ion beam 22) applied to the filter FL. Figure). Here, the channel impurity 30 corresponds to the impurity introduced into the channel region by channel dope ion implantation (IM1a, IM1b). FIG. 23 is an explanatory view (perspective view) showing an arrangement state of channel impurities 30 when channel dope ion implantation is performed without using the filter FL, unlike the present embodiment. 22 and 23, the gate insulating films 5a and 5b, the gate electrodes GE1 and GE2, and the sidewall SW are lifted up (moved) in order to make it easy to see the arrangement state of the channel impurities 30 in the channel region. It is shown.

  In the ion beam 22, impurity ions are not perfectly regularly arranged. Therefore, unlike this embodiment, when channel dope ion implantation is performed without using the filter FL, the channel impurities 30 are not regularly arranged as shown in FIG.

  On the other hand, in this embodiment, channel dope ion implantation (IM1a, IM1b) is performed in a state where a voltage (voltage having the same polarity as the ion beam 22) is applied to the filter FL. As described above, the semiconductor wafer 1W (semiconductor substrate 1) is irradiated with the ion beam 22b composed of the impurity ions 22d passing through only the central portion CT of each opening OP of the filter FL by the lens 26. Since the openings OP are regularly arranged in the filter FL, the impurity ions implanted into the semiconductor wafer 1W (that is, the semiconductor substrate 1) also have a regular arrangement. For this reason, as shown in FIG. 22, the channel impurities 30 can be regularly arranged. That is, even if the impurity ions are not regularly arranged in the ion beam 22a before entering the filter FL, the impurity ions are regularly arranged in the ion beam 22c irradiated to the semiconductor wafer 1W (semiconductor substrate 1). Therefore, as shown in FIG. 22, it is possible to realize a state in which the channel impurities 30 are regularly arranged in the channel region.

In FIG. 22, the arrangement interval of channel impurities 30 (the interval between channel impurities 30 adjacent in the plane direction) W ₄ is the arrangement pitch P ₁ of the openings OP in the filter FL (the arrangement pitch P ₁ is shown in FIG. 18 above). And P ₁ = W ₁ + W ₂ ) and the convergence rate by the lens 26 can be controlled. For example, the area of the ion beam 22c irradiated to the semiconductor wafer 1W (the area when the ion beam 22c reaches the surface of the semiconductor wafer 1W) is 1 / n of the area of the ion beam 22b before being converged by the lens 26. ^{When the} ion beam 22 b is converged by the lens 26 so as to be doubled, the arrangement interval W ₄ of the channel impurities 30 is approximately W ₄ = P ₁ / n. That is, in the filter FL, the channel impurities 30 are regularly arranged at an arrangement interval W ₄ (= P ₁ / n), reflecting that the openings OP are regularly arranged at the arrangement pitch P _1. It will be in the state. Here, n is referred to as a convergence rate by the lens 26.

Channel doping ion implantation IM1a of this embodiment, the IM1b, although depending on the arrangement pitch P ₁ of opening OP, as compared with the ion implantation without using a filter FL, it is necessary to increase the convergence rate n by the lens 26 . And minimize the array pitch P ₁ of opening OP, and more significantly the convergence rate n by the lens 26, it is possible to reduce the arrangement interval W ₄ of the channel impurity 30. By this channel impurity 30, the threshold voltage of the MISFET can be controlled.

Although depending on the processing limit of the filter FL, it is more preferable that the dimension W ₁ of the opening OP and the arrangement pitch P ₁ be as small as possible because the convergence rate n of the lens 26 does not need to be increased. For this reason, it is more preferable that the dimension W ₁ of the opening OP and the arrangement pitch P ₁ are minute dimensions close to the processing limit of the filter FL. From this viewpoint, it is preferable that the dimension W ₁ of the opening OP is 20 μm or less, and the arrangement pitch P ₁ is 20 μm or less.

  Further, unlike the present embodiment, when no voltage is applied to the filter FL, as shown in FIG. 20, each opening OP entirely passes impurity ions, so that the opening is opened. When the semiconductor wafer 1W is irradiated with the ion beam that has passed through the portion OP, a region in which impurities are introduced at a high concentration is formed like a patch pattern. For this reason, when no voltage is applied to the filter FL, a regular arrangement state of the channel impurities 30 cannot be obtained.

  In order to obtain a regular arrangement state of the channel impurities 30, a large number of fine openings OP are provided in the filter FL in a regular arrangement, and a voltage (voltage having the same polarity as the ion beam 22) is applied to the filter FL. It is important to. As a result, only the central portion CT of the fine opening OP can pass the impurity ions, so that the ion beam 22b that has passed through the opening OP is converged by the lens 26 and irradiated onto the semiconductor wafer 1W. In the semiconductor wafer 1W (semiconductor substrate 1), the impurity ions do not exist in a plane and are scattered and distributed regularly over the entire region irradiated with the ion beam 22c. For this reason, in the semiconductor wafer 1W (semiconductor substrate 1), a region into which impurities are introduced at a high concentration is not formed like a spotted pattern.

  In channel-doped ion implantation IM1a and IM1b, the irradiation position of the ion beam 22 is not scanned while continuously irradiating the semiconductor wafer 1W with the ion beam 22, but the main surface of the semiconductor wafer 1W is formed into a plurality of shot regions. It is preferable to irradiate the ion beam 22c for each shot region (with the irradiation region fixed). This makes it easy to obtain a regular arrangement state of the channel impurities 30. In FIG. 16, the main surface of the semiconductor wafer 1W is divided by dotted imaginary lines, and each divided area corresponds to this shot area. The area of each shot region is the same as the area of the ion beam 22c irradiated onto the semiconductor wafer 1W (the area when the ion beam 22c reaches the surface of the semiconductor wafer 1W). Then, by irradiating a certain shot region of the semiconductor wafer 1W with the ion beam 22c, ion implantation into the shot region is performed, and then the irradiation of the ion beam 22 is temporarily stopped, and then the ion beam 22c is applied to the next shot region. , The ion implantation into the shot region is performed, and the ion implantation for the entire semiconductor wafer 1W (all shot regions) is completed by repeating this. The movement from the shot area to the next shot area includes a case where the lens 26 is provided with a function of scanning the ion beam 22 to move the irradiation position of the ion beam 22c while fixing the semiconductor wafer 1W, and the semiconductor wafer 1W. In the case of moving the semiconductor wafer 1W while fixing the irradiation position of the ion beam 22c by using the XY stage that can move the semiconductor wafer 1W in the XY direction, and the combination of both There can be. The dose amount of impurity ions implanted into the semiconductor wafer 1W (semiconductor substrate 1) in each shot region can be controlled by the irradiation time of the ion beam 22 irradiated to the same shot region. Further, in each shot region, the ion beam 22 can be generated in a pulse shape and irradiated with the ion beam 22c. In this case, the dose of impurity ions implanted into the semiconductor wafer 1W (semiconductor substrate 1) in each shot region. The amount can also be controlled by the number of pulses of the ion beam 22 applied to the same shot region.

  Further, with respect to one semiconductor chip, the ion implantation method (that is, voltage application) of the first embodiment as described above is applied only to a part of the region (memory region MRY in the case of the fifth and sixth embodiments described later). In the case of applying the ion implantation using the filter FL), the ion beam 22c is irradiated only to the target region in each chip region (region from which one semiconductor chip is obtained) in the semiconductor wafer 1W. That's fine. In this case, in each chip region of the semiconductor wafer 1W, channel doping ion implantation using the ion implantation method of the first embodiment as described above is performed only in a region where it is desired to particularly suppress the fluctuation of the threshold voltage of the MISFET. In other regions, channel doping ion implantation can be performed by general ion implantation without using the filter FL. As a result, in a region where it is particularly desired to suppress the threshold voltage fluctuation of the MISFET, the threshold voltage fluctuation can be accurately suppressed or prevented, and an increase in the manufacturing time of the semiconductor device can be suppressed.

  In the present embodiment, channel doping ion implantation IM1a and IM1b is performed by the ion implantation method of the first embodiment (that is, ion implantation using the filter FL to which a voltage is applied) as described above, whereby a channel is formed in the channel region. The impurities 30 can be regularly arranged. The reason why the channel impurities 30 are regularly arranged is as follows.

  Impurities are introduced into the channel region of the MISFET by performing channel dope ion implantation on the semiconductor substrate. The threshold voltage of the MISFET can be controlled by this channel impurity (impurities introduced into the channel region). A plurality of MISFETs are formed on a semiconductor substrate, but the difference between the impurity distribution and the number of impurities when the channel regions are compared (impurity distribution in the channel region of one MISFET and the impurity distribution in the channel region of another MISFET) If the difference in the number of impurities) is large, the variation in the threshold voltage of the MISFET becomes large. That is, if the channel impurity distribution and the number of impurities differ between MISFETs that should have the same threshold voltage, the threshold voltage also becomes a different value. If the impurity arrangement state and the number of impurities) fluctuate, the threshold voltage fluctuates for each MISFET. In order to improve the performance of the semiconductor device, it is desired to suppress the variation (fluctuation) of the threshold voltage for each MISFET. For this purpose, the distribution of channel impurities between MISFETs that should have the same threshold voltage. Are desired to be the same.

  Therefore, in this embodiment, channel doping ion implantation IM1a and IM1b is performed in the channel region by the ion implantation method of the first embodiment (that is, ion implantation using the filter FL to which a voltage is applied) as described above. The channel impurities 30 can be regularly arranged. Thereby, since it is possible to suppress or prevent the channel region state (arrangement of impurities in the channel region and the number of impurities) from changing for each MISFET, it is possible to suppress or prevent the threshold voltage from changing for each MISFET. be able to. That is, by regularly arranging channel impurities, it is possible to suppress or prevent the channel impurity distribution and the number of impurities from being different between MISFETs that should have the same threshold voltage. The voltage can be controlled to a desired value without variation. Therefore, the performance of the semiconductor device can be improved.

In this embodiment, channel doping ion implantation IM1a and IM1b is performed by the ion implantation method of the first embodiment as described above (that is, ion implantation method using a filter FL to which a voltage is applied). For ion implantation other than implantation, the ion implantation method of the first embodiment (that is, ion implantation using the filter FL to which a voltage is applied) as described above is not applied, and ion implantation is performed without using the filter FL. For example, each ion implantation for forming the p-type well PW and the n-type well NW, each ion implantation IM2a, IM2b for forming the extension regions EX1, EX2, and each ion implantation for forming the halo regions HA1, HA2 Each of the ion implantations IM4a and IM4b for forming the IM3a, IM3b, the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2 performs ion implantation without using the filter FL. This is for the following reason.

  In the ion implantation method of the first embodiment as described above (ion implantation using a filter FL to which a voltage is applied), most of the impurity ions constituting the ion beam 22a are filtered by the filter FL to which a voltage is applied. It will be shielded. Then, only the impurity ions 22d incident on the central portion CT of the opening OP (incident from the direction perpendicular to the surface of the filter FL) (a part of the impurity ions as viewed from the entire ion beam 22a) are included in the filter FL. The ion beam 22b is linearly passed through the opening OP. Therefore, in the ion implantation method of the first embodiment as described above (ion implantation using the filter FL to which a voltage is applied), the impurity ions introduced into the semiconductor substrate 1 can be regularly arranged. It is disadvantageous to increase the dose. If the dose amount is increased, the time required for the ion implantation process becomes longer, and the throughput of the semiconductor device decreases.

  However, the channel doping ion implantation (IM1a, IM1b) applies the ion implantation method of the first embodiment as described above (ion implantation using the filter FL to which a voltage is applied). Since channel dope ion implantation has a smaller impurity dose than other ion implantation processes, it is disadvantageous to use the ion implantation method of the first embodiment as described above (the time required for the ion implantation process). It is possible to suppress a reduction in throughput of the semiconductor device. Moreover, the arrangement state of channel impurities introduced into the channel region by channel doping ion implantation greatly affects the variation (fluctuation) of the threshold voltage of the MISFET. Therefore, since the channel impurities can be regularly arranged by applying the ion implantation method of the first embodiment as described above to the channel dope ion implantation (IM1a, IM1b), the threshold voltage of the MISFET It is possible to obtain a remarkable effect that the variation (variation) of can be suppressed.

  On the other hand, ion implantation processes other than channel dope ion implantation have a larger impurity dose than channel dope ion implantation. Here, in ion implantation processes other than channel dope ion implantation, each ion implantation process for forming a well region (p-type well PW, n-type well NW) and extension regions (EX1, EX2) are formed. There are each ion implantation step, each ion implantation step for forming the halo regions (HA1, HA2), and each ion implantation step for forming the source / drain regions (SD1, SD2). In the ion implantation process other than the channel dope ion implantation, the ion implantation method of the first embodiment (that is, the ion implantation using the filter FL to which a voltage is applied) as described above is not applied, and the ion is used without using the filter FL. By performing the implantation, the time required for the ion implantation step can be reduced even when the dose is large, and the throughput of the semiconductor device can be improved. In addition, the alignment state of the impurities introduced in the ion implantation process other than the channel doping ion implantation is more varied in the threshold voltage of the MISFET than the alignment state of the channel impurities introduced into the channel region by the channel doping ion implantation (see FIG. Fluctuation) is small. For this reason, even if the regularity of the arrangement of the introduced impurity ions is disturbed without applying the ion implantation method of the first embodiment as described above to the ion implantation process other than the channel dope ion implantation, the MISFET is not affected. Almost no influence on variation (variation) in threshold voltage.

  Therefore, channel doping ion implantation (IM1a, IM1b) is performed by the ion implantation method of the first embodiment as described above, and the ion implantation process other than the channel doping ion implantation is performed by the ion implantation method of the first embodiment as described above. By applying ion implantation without using the filter FL, it is possible to suppress variations in the threshold voltage of the MISFET, reduce the manufacturing time of the semiconductor device, and improve the throughput of the semiconductor device Can do.

  The filter FL used in the present embodiment is essentially different from the aperture for shaping the ion beam. The filter FL is provided with a large number (at least 10,000 or more) of fine opening portions (20 μm or less) arranged regularly (preferably in a lattice shape). In addition, by applying a voltage (voltage having the same polarity as the ion beam) to the filter FL at the time of ion implantation, impurity ions incident on the central portion CT of the opening OP (a part of the impurity ions as viewed from the entire ion beam). Only passes through the opening OP of the filter FL linearly and becomes an ion beam (22b) for semiconductor wafer irradiation. Impurity ions (most impurity ions as viewed from the whole ion beam) incident on a region other than the central portion CT of the opening OP (including the periphery of the opening OP) are shielded or scattered by the filter FL, and the opening OP Therefore, the ion beam 22b cannot be obtained. Thus, the filter FL is used based on a technical idea that is completely different from the aperture for shaping the ion beam.

(Embodiment 2)
A manufacturing process of the semiconductor device according to the second embodiment will be described with reference to the drawings. 24 to 30 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment.

First, after obtaining the structure shown in FIG. 1 in the same manner as in the first embodiment, in this embodiment, the first element ion implantation IM5 is performed on the semiconductor substrate 1 as shown in FIG. Thus, a semiconductor layer (semiconductor region, diffusion preventing region) 17 into which the first element is introduced is formed. In FIG. 24, the ion implantation IM5 is schematically indicated by an arrow. The semiconductor layer 17 is formed on the upper layer portion of the semiconductor substrate 1 over a predetermined depth from the surface of the semiconductor substrate 1. The first element implanted into the semiconductor substrate 1 by the ion implantation IM5 for forming the semiconductor layer 17 is made of one or more of carbon (C), nitrogen (N), and fluorine (F). Therefore, the semiconductor layer 17 is a semiconductor region into which one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced. When the semiconductor substrate 1 is single crystal silicon, the semiconductor layer 17 Is composed of single crystal silicon (Si) into which one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced (doped). The concentration of the first element in the semiconductor layer 17 can be, for example, about 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ . The semiconductor layer 17 is formed with such a thickness that channel doped layers 4 a and 4 b to be formed later can be included in the semiconductor layer 17. Of the semiconductor layers 17 formed on the semiconductor substrate 1, the semiconductor layer 17 formed in the nMIS formation region 1A is referred to as a semiconductor layer (semiconductor region, diffusion prevention region) 17a, and the semiconductor formed in the pMIS formation region 1B. The layer 17 is referred to as a semiconductor layer (semiconductor region, diffusion preventing region) 17b.

  Note that the ion implantation method of the first embodiment (that is, ion implantation using the filter FL to which a voltage is applied) as described above is not applied to the ion implantation IM5, and the ion implantation IM5 is performed without using the filter FL. Do.

  As another form, the semiconductor layer 17 into which one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced can be epitaxially grown on the semiconductor substrate 1. Compared to the case where the semiconductor layer 17 is formed by ion implantation, when the semiconductor layer 17 is formed by epitaxial growth, the thickness of the semiconductor layer 17 is likely to be increased. Therefore, the thickness of the semiconductor layer 17 is formed later. The thickness may be such that the p-type well PW and the n-type well NW can be included in the semiconductor layer 17. When the semiconductor layer 17 is formed by either ion implantation or epitaxial growth, the thickness of the semiconductor layer 17 is set such that the channel doped layers 4a and 4b to be formed later can be included in the semiconductor layer 17. The

  A semiconductor substrate having a semiconductor layer 17 (17a, 17b) on which one or more of carbon (C), nitrogen (N), or fluorine (F) (ie, the first element) has been introduced by the above steps. 1 will be prepared.

  Next, as shown in FIG. 25, the same photoresist film PR1a as in the first embodiment (a photoresist film PR1a covering the pMIS formation region 1B and exposing the nMIS formation region 1A) is formed. Then, in the nMIS formation region 1A, channel doping ion implantation (ion implantation for adjusting the threshold value of the n channel MISFET Qn to be formed later) IM1a similar to the channel doping ion implantation IM1a of the first embodiment is performed. Then, a channel dope layer 4 a is formed in the upper layer portion of the semiconductor substrate 1. Then, a p-type well PW is formed in the semiconductor substrate 1 by ion implantation in the nMIS formation region 1A.

  In the present embodiment, the channel dope layer 4a formed on the semiconductor substrate 1 is formed so as to be included in the semiconductor layer 17 (specifically, the semiconductor layer 17a). That is, the semiconductor layer 17 is formed by the ion implantation IM5 so that the channel dope layer 4a is included in the semiconductor layer 17.

  Next, as shown in FIG. 26, after removing the photoresist film PR1a, the same photoresist film PR1b as that in the first embodiment (the photoresist covering the nMIS formation region 1A and exposing the pMIS formation region 1B). A film PR1b) is formed. Then, in the pMIS formation region 1B, channel doping ion implantation (ion implantation for adjusting the threshold value of the p channel MISFET Qp to be formed later) IM1b similar to the channel doping ion implantation IM1b of the first embodiment is performed. The channel dope layer 4b is formed in the upper layer portion of the semiconductor substrate 1. Then, an n-type well NW is formed in the semiconductor substrate 1 by ion implantation in the pMIS formation region 1B.

  In the present embodiment, channel dope layers 4 a and 4 b formed on semiconductor substrate 1 are formed so as to be included in semiconductor layer 17. That is, the channel dope layer 4a is formed so as to be included in the semiconductor layer 17a, and the channel dope layer 4b is included in the semiconductor layer 17b. That is, the semiconductor layer 17 (semiconductor layers 17a and 17b) is formed by the ion implantation IM5 so that the channel dope layers 4a and 4b are included in the semiconductor layer 17 (semiconductor layers 17a and 17b).

  In the first embodiment, channel dope ion implantation IM1a and IM1b are performed on the semiconductor substrate 1 to form the channel dope layers 4a and 4b. On the other hand, in this embodiment, channel dope ion implantation IM1a and IM1b are performed in the semiconductor layer 17 of the semiconductor substrate 1 to form channel dope layers 4a and 4b. The configurations of the channel dope ion implantation IM1a and IM1b and the channel dope layers 4a and 4b are the same as those in the first embodiment. Therefore, also in the present embodiment, the channel dope ion implantation IM1a and IM1b are performed by the ion implantation method of the first embodiment as described above (that is, ion implantation using the filter FL to which a voltage is applied).

  Further, in the present embodiment, as shown in FIG. 24, ion implantation IM5 is performed on the entire main surface of the semiconductor substrate 1 including the nMIS formation region 1A and the pMIS formation region 1B, and the semiconductor layer 17 is bundled. It was formed. That is, the semiconductor layer 17a in the nMIS formation region 1A and the semiconductor layer 17b in the pMIS formation region 1B are formed by the same ion implantation IM5. As another form, the semiconductor layer 17a in the nMIS formation region 1A and the semiconductor layer 17b in the pMIS formation region 1B can be formed by separate ion implantation. In this case, the first film is formed with the photoresist film PR1a formed. The semiconductor layer 17a in the nMIS formation region 1A is formed by performing ion implantation of one element, and the semiconductor layer 17b in the pMIS formation region 1B is formed by performing ion implantation of the first element in a state where the photoresist film PR1b is formed. That's fine. In this case, it is preferable to form the semiconductor layer 17a before forming the channel dope layer 4a and to form the semiconductor layer 17b before forming the channel dope layer 4b.

  The subsequent steps are the same as those in the first embodiment.

  That is, as shown in FIG. 27, after removing the photoresist film PR1b and then removing the insulating film 3 to clean the surface of the semiconductor substrate 1, the semiconductors in the nMIS formation region 1A and the pMIS formation region 1B are removed. An insulating film 5 for a gate insulating film is formed on the surface of the substrate 1 (surfaces of the p-type well PW and the n-type well NW), and gate electrodes GE1 and GE2 are formed on the insulating film 5. Then, as shown in FIG. 28, the extension region EX1 and the halo region HA1 are formed in the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A, and the semiconductor substrate 1 (n-type in the pMIS formation region 1B). An extension region EX2 and a halo region HA2 are formed in the well NW). The formation method and configuration of the insulating film 5, the gate electrodes GE1 and GE2, the extension regions EX1 and EX2, and the halo regions HA1 and HA2 in the present embodiment are the same as those in the first embodiment.

Next, as shown in FIG. 29, sidewalls (sidewall insulating films) SW are formed on the sidewalls of the gate electrodes GE1 and GE2, and then n is formed on the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A. ^{A +} type semiconductor region SD1 is formed, and a p ⁺ type semiconductor region SD2 is formed in the semiconductor substrate 1 (n type well NW) in the pMIS formation region 1B. The formation method and configuration of the sidewall SW, the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2 in the present embodiment are the same as those in the first embodiment.

  Next, similarly to the first embodiment, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed.

Thereafter, as shown in FIG. 30, similarly to the first embodiment, the metal silicide layers 11 are respectively formed on the surfaces of the gate electrodes GE1, GE2, the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2, An insulating film 12 is formed on the main surface of the semiconductor substrate 1 so as to cover the gate electrodes GE1 and GE2 and the sidewall SW, a contact hole 13 is formed in the insulating film 12, and a plug 14 is formed in the contact hole 13. Then, as in the first embodiment, the insulating film 15 is formed on the insulating film 12 in which the plugs 14 are embedded, and the wiring M1 is formed on the insulating film 15 by the damascene method.

  In the present embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

  Also in this embodiment, the channel dope ion implantation (IM1a, IM1b) is performed by the ion implantation method of the first embodiment (that is, ion implantation using the filter FL to which a voltage is applied) as described above. The impurity ions implanted into the region are regularly arranged immediately after the implantation. However, if channel impurities are diffused (moved) in various subsequent heating steps, the regularity of the channel impurity arrangement state may be lower than that immediately after implantation. For this reason, the threshold of the MISFET can be obtained by devising such a way that the regular arrangement state of the channel impurities implanted into the semiconductor substrate 1 by the channel dope ion implantation (IM1a, IM1b) can be maintained until the stage after the manufacture of the semiconductor device. The variation (fluctuation) of the value voltage can be further prevented, and thereby the performance of the semiconductor device can be further improved.

Further, when ion implantation is performed on the semiconductor substrate 1, point defects are also generated in the region of the semiconductor substrate 1 doped with impurity ions, but the point defects are easily diffused. For this reason, the point defects generated by the respective ion implantations when forming the extension regions EX1, EX2, the halo regions HA1, HA2, the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2 are caused by various subsequent heating processes. Thus, there is a possibility of diffusing up to the channel region of MISFET (region immediately below gate electrodes GE1 and GE2). In particular, since the extension regions EX1 and EX2 and the halo regions HA1 and HA2 are close to the channel region (the region immediately below the gate electrodes GE1 and GE2), they are generated in the extension regions EX1 and EX2 and the halo regions HA1 and HA2 by ion implantation. Point defects are likely to diffuse into the channel region. When point defects diffuse into the channel region, the density of point defects in the channel region increases. However, the larger the density of point defects, the easier the impurities introduced into the channel region by channel doping ion implantation move (diffuse). This is because when there are many point defects, impurities easily move (diffuse) through the point defects.

Therefore, in order to maintain the regular arrangement state of the channel impurities implanted by the channel dope ion implantation IM1a and IM1b until the stage after the manufacture of the semiconductor device, the extension regions EX1 and EX2, the halo regions HA1 and HA2, n ⁺ It is effective to prevent the point defects generated by the respective ion implantations that form the type semiconductor region SD1 and the p ⁺ type semiconductor region SD2 from diffusing into the channel region, and to suppress the density of point defects in the channel region. It is.

  According to the study of the present inventor, a region in which at least one of carbon (C), nitrogen (N), and fluorine (F) is introduced into a substrate region (semiconductor substrate 1) made of single crystal silicon (this embodiment) The semiconductor layers 17a and 17b of this form and the diffusion prevention regions 18a and 18b of the third embodiment to be described later) have a function of preventing the point defects from being diffused (moved) and preventing the point defects from being diffused (moved). I found out that

  Therefore, in this embodiment, a semiconductor substrate 1 having a semiconductor layer 17 (17a, 17b) into which one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced is prepared. In the semiconductor layer 17, channel doped layers 4a and 4b of an n channel MISFET Qn and a p channel MISFET Qp are formed. That is, in the present embodiment, the channel dope layer 4a of the n-channel type MISFET Qn is formed in the semiconductor layer 17a into which one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced, The channel dope layer 4b of the p-channel type MISFET Qp is formed on the semiconductor layer 17b into which one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced.

For this reason, in this embodiment, point defects are diffused (moved) over the entire semiconductor layers 17a and 17b into which at least one of carbon (C), nitrogen (N), and fluorine (F) is introduced. Hard to do. Therefore, the point defects generated by the respective ion implantations when forming the extension regions EX1, EX2, the halo regions HA1, HA2, the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2 are the n channel type MISFET Qn and the p channel. Diffusion to the channel region of the type MISFET Qp (region immediately below the gate electrodes GE1 and GE2) can be prevented, and the density of point defects in the channel region can be suppressed. As a result, it is possible to suppress or prevent the impurities introduced into the channel region by channel doping ion implantation (IM1a, IM1b) from being rearranged (diffused) during the subsequent heating step. A regular arrangement of channel impurities can be maintained. Therefore, variations in threshold voltage for each MISFET can be more accurately suppressed, and the performance of the semiconductor device can be further improved.

  In addition, one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced into the semiconductor layer 17, but carbon (C), nitrogen (N), and fluorine (F) Of these, carbon (C) is most effective in preventing the diffusion of point defects. For this reason, it is more preferable that at least carbon (C) is introduced into the semiconductor layer 17 among carbon (C), nitrogen (N), or fluorine (F).

In the present embodiment, the channel dope layer 4a is formed in the semiconductor layer 17a, and the channel dope layer 4b is formed in the semiconductor layer 17b. As another form, the thickness of the semiconductor layers 17a and 17b can be increased to form the extension region EX1, the halo region HA1, and the n ⁺ -type semiconductor region SD1 in the semiconductor layer 17a. Also, the extension region EX2, the halo The region HA2 and the p ⁺ type semiconductor region SD2 can also be formed in the semiconductor layer 17b.

(Embodiment 3)
A manufacturing process of the semiconductor device according to the third embodiment will be described with reference to the drawings. 31 to 36 are fragmentary cross-sectional views of the semiconductor device of the present embodiment during the manufacturing process.

  First, after obtaining the structure shown in FIG. 5 in the same manner as in the first embodiment, as shown in FIG. 31, the photoresist film PR2a (covering the pMIS formation region 1B and covering the nMIS as in the first embodiment) is obtained. A photoresist film PR2a) exposing the formation region 1A is formed. Then, in this embodiment, the first element ion implantation IM6a is performed on the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A to form the diffusion prevention region 18a. In FIG. 31, the ion implantation IM6a for forming the diffusion prevention region 18a is schematically indicated by an arrow. During this ion implantation IM6a, the gate electrode GE1 can also function as a mask (ion implantation blocking mask). The diffusion prevention region 18a is a region (semiconductor region) into which the first element is introduced (doped). The first element implanted into the semiconductor substrate 1 by the ion implantation IM6a for forming the diffusion prevention region 18a is made of one or more of carbon (C), nitrogen (N), and fluorine (F).

  The ion implantation IM6a for forming the diffusion prevention region 18a and the ion implantation IM6b to be described later for forming the diffusion prevention region 18b to be described later are applied to the ion implantation method (that is, the voltage of the first embodiment described above). The ion implantation IM6a and IM6b are performed without using the filter FL.

  Next, as shown in FIG. 32, the extension region EX1 is formed by ion implantation IM2a in the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A, and the halo region HA1 is formed by ion implantation IM3a. .

  The method of forming the extension region EX1 and the halo region HA1 (ion implantation IM2a, IM3a) is the same as that in the first embodiment. However, in this embodiment, the extension region EX1 and the halo region HA1 are formed in the diffusion prevention region 18a. Formed. That is, the extension region EX1 and the halo region HA1 are formed in the region into which the first element has been introduced (doped) by the ion implantation IM6a (here, the diffusion prevention region 18a). Since the relationship between the extension region EX1 and the halo region HA1 has been described in the first embodiment, the repeated description thereof is omitted here.

The diffusion prevention region 18a prevents point defects generated by each ion implantation when forming the extension region EX1, the halo region HA1, and the n ⁺ type semiconductor region SD1 from diffusing into the channel region of the n-channel type MISFET Qn. It has a function. Therefore, at least a part of the diffusion prevention region 18a needs to be located between the extension region EX1, the halo region HA1, the n ⁺ type semiconductor region SD1, and the channel region of the n channel MISFET Qn. Accordingly, it is preferable that the diffusion prevention region 18a wraps (covers) the halo region HA1 when the diffusion prevention region 18a, the extension region EX1 and the halo region HA1 are formed.

  For this reason, in the ion implantation IM6a for forming the diffusion prevention region 18a, it is preferable to ion-implant the first element to a position deeper than the halo region HA1. The ion implantation IM6a for forming the diffusion preventing region 18a is preferably oblique ion implantation (tilted ion implantation). Thereby, the diffusion prevention region 18a can be accurately positioned between the halo region HA1 and the channel region of the n-channel type MISFET Qn.

  It is further preferable that the inclination angle of the ion implantation IM6a for forming the diffusion prevention region 18a is larger than the inclination angle of the ion implantation IM3a for forming the halo region HA1. As a result, the diffusion prevention region 18a can be positioned more accurately between the halo region HA1 and the channel region of the n-channel type MISFET Qn. Here, the tilt angle of ion implantation corresponds to the tilt angle from the direction perpendicular to the main surface of the semiconductor substrate 1 in the ion implantation direction, and when impurity ions are implanted in the direction perpendicular to the main surface of the semiconductor substrate 1. The tilt angle is 0 °.

  Next, as shown in FIG. 33, after removing the photoresist film PR2a by ashing or the like, the photoresist film PR2b (covering the nMIS formation region 1A and exposing the pMIS formation region 1B) as in the first embodiment is exposed. A photoresist film PR2b) is formed. Then, in the present embodiment, the diffusion prevention region 18b is formed by performing ion implantation IM6b of the first element into the semiconductor substrate 1 (n-type well NW) in the pMIS formation region 1B. In FIG. 33, the ion implantation IM6a for forming the diffusion prevention region 18b is schematically indicated by an arrow. In this ion implantation IM6b, the gate electrode GE2 can also function as a mask (ion implantation blocking mask). The diffusion prevention region 18b is a region (semiconductor region) into which the first element is introduced (doped). The first element implanted into the semiconductor substrate 1 by the ion implantation IM6b for forming the diffusion prevention region 18b is made of one or more of carbon (C), nitrogen (N), and fluorine (F).

  Next, as shown in FIG. 34, the extension region EX2 is formed by ion implantation IM2b in the semiconductor substrate 1 (n-type well NW) in the pMIS formation region 1B, and the halo region HA2 is formed by ion implantation IM3b. .

  The method of forming the extension region EX2 and the halo region HA2 (ion implantation IM2b, IM3b) is the same as that in the first embodiment. However, in this embodiment, the extension region EX2 and the halo region HA2 are formed in the diffusion prevention region 18b. Formed. That is, the extension region EX2 and the halo region HA2 are formed in the region into which the first element is introduced (doped) by the ion implantation IM6b (here, the diffusion prevention region 18b). Since the relationship between the extension region EX2 and the halo region HA2 has been described in the first embodiment, repeated description thereof is omitted here.

The diffusion prevention region 18b prevents the point defects generated by the respective ion implantations when forming the extension region EX2, the halo region HA2, and the p ⁺ type semiconductor region SD2 from diffusing into the channel region of the p channel MISFET Qp. It has a function. Therefore, at least a part of the diffusion prevention region 18b needs to be located between the extension region EX2, the halo region HA2, the p ⁺ type semiconductor region SD2, and the channel region of the p channel MISFET Qp. Accordingly, it is preferable that the diffusion prevention region 18b wraps (covers) the halo region HA2 when the diffusion prevention region 18b, the extension region EX2 and the halo region HA2 are formed.

  For this reason, in the ion implantation IM6b for forming the diffusion prevention region 18b, it is preferable to ion-implant the first element to a position deeper than the halo region HA2. The ion implantation IM6b for forming the diffusion preventing region 18b is preferably oblique ion implantation (tilted ion implantation). As a result, the diffusion prevention region 18b can be accurately positioned between the halo region HA2 and the channel region of the p-channel type MISFET Qp.

  It is further preferable that the inclination angle of the ion implantation IM6b for forming the diffusion prevention region 18b is larger than the inclination angle of the ion implantation IM3b for forming the halo region HA2. As a result, the diffusion prevention region 18b can be positioned more accurately between the halo region HA2 and the channel region of the p-channel type MISFET Qp. Here, the tilt angle of ion implantation corresponds to the tilt angle from the direction perpendicular to the main surface of the semiconductor substrate 1 in the ion implantation direction, and when impurity ions are implanted in the direction perpendicular to the main surface of the semiconductor substrate 1. The tilt angle is 0 °.

  In the ion implantation IM6a, IM2a, IM3a (FIGS. 31 and 32), the photoresist film PR2a functions as an ion implantation blocking mask, and ions are not implanted into the semiconductor substrate 1 in the pMIS formation region 1B. Further, in ion implantation IM6b, IM2b, IM3b (FIGS. 33 and 34), the photoresist film PR2b functions as an ion implantation blocking mask, and ions are not implanted into the semiconductor substrate 1 in the nMIS formation region 1A.

  The diffusion prevention region 18a, the extension region EX1, and the halo region HA1 do not necessarily have to be formed in this order. However, the ion implantations IM6a, IM2a, and IM3a that form the diffusion prevention region 18a, the extension region EX1, and the halo region HA1. It is necessary to perform at least after forming the gate electrode GE1 and before forming the sidewall SW on the sidewall of the gate electrode GE1. Similarly, the diffusion prevention region 18b, the extension region EX2 and the halo region HA2 do not necessarily have to be formed in this order, but the respective ion implantations IM6b, IM2b, which form the diffusion prevention region 18b, the extension region EX2 and the halo region HA2 IM3b needs to be performed at least after forming the gate electrode GE2 and before forming the sidewall SW on the sidewall of the gate electrode GE2.

  The subsequent steps are the same as those in the first embodiment.

That is, as shown in FIG. 35, after removing the photoresist film PR2b, sidewalls (sidewall insulating films) SW are formed on the sidewalls of the gate electrodes GE1 and GE2. Then, an n ⁺ type semiconductor region SD1 is formed in the semiconductor substrate 1 (p type well PW) in the nMIS formation region 1A, and a p ⁺ type semiconductor region SD2 is formed in the semiconductor substrate 1 (n type well NW) in the pMIS formation region 1B. Form. The formation method and configuration of the sidewall SW, the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2 in the present embodiment are the same as those in the first embodiment.

  Next, similarly to the first embodiment, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed.

Thereafter, as shown in FIG. 36, similarly to the first embodiment, the metal silicide layers 11 are formed on the surfaces of the gate electrodes GE1, GE2, the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2, respectively. An insulating film 12 is formed on the main surface of the semiconductor substrate 1 so as to cover the gate electrodes GE1 and GE2 and the sidewall SW, a contact hole 13 is formed in the insulating film 12, and a plug 14 is formed in the contact hole 13. Then, as in the first embodiment, the insulating film 15 is formed on the insulating film 12 in which the plugs 14 are embedded, and the wiring M1 is formed on the insulating film 15 by the damascene method.

  In the present embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

  As described above, a region in which at least one of carbon (C), nitrogen (N), and fluorine (F) is introduced into a substrate region (semiconductor substrate 1) made of single crystal silicon (diffusion in this embodiment) The prevention regions 18a and 18b) have a function of preventing point defects from diffusing (moving) and preventing point defects from diffusing (moving).

  Therefore, in the present embodiment, as described above, one or more of carbon (C), nitrogen (N), and fluorine (F) is applied to the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A ( That is, the first element) is ion-implanted to form the diffusion prevention region 18a, and carbon (C), nitrogen (N), or fluorine (F) is added to the semiconductor substrate 1 (n-type well NW) in the pMIS formation region 1B. One or more of these (first element) are ion-implanted to form the diffusion prevention region 18b.

The diffusion prevention region 18a, which is a region into which one or more of carbon (C), nitrogen (N), or fluorine (F) is introduced, forms the extension region EX1, the halo region HA1, and the n ⁺ type semiconductor region SD1. It has a function of preventing the point defects generated by the respective ion implantations from being diffused to the channel region of the n-channel type MISFET Qn (the region immediately below the gate electrode GE1). Further, the diffusion prevention region 18b, which is a region into which one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced, includes the extension region EX2, the halo region HA2, and the p ⁺ type semiconductor region SD2. Has a function of preventing the point defects generated by the respective ion implantations during the formation of the diffusion into the channel region of the p-channel type MISFET Qp (region immediately below the gate electrode GE2).

In order for the diffusion prevention region 18a to have the above-described function, at least a part of the diffusion prevention region 18a includes the extension region EX1, the halo region HA1, the n ⁺ type semiconductor region SD1, and the channel region (gate electrode) of the n channel type MISFET Qn. It is necessary to be located between the region immediately below GE1). Of the extension region EX1, the halo region HA1, and the n ⁺ type semiconductor region SD1, the halo region HA1 is closest to the channel region of the n-channel type MISFET Qn. Therefore, when the halo region HA1 is formed, at least a part of the diffusion prevention region 18a. May be positioned between the halo region HA1 and the channel region of the n-channel type MISFET Qn. In order to do this, it is preferable to form the diffusion prevention region 18a so as to wrap (cover) the halo region HA1. When the formation of the halo region HA1 is omitted, since the extension region EX1 is close to the channel region, at least a part of the diffusion prevention region 18a may be located between the extension region EX1 and the channel region of the n-channel type MISFET Qn. In order to do this, it is preferable to form the diffusion preventing region 18a so as to wrap (cover) the extension region EX1.

  When at least a part of the diffusion prevention region 18a is located between the halo region HA and the channel region of the n-channel type MISFET Qn, the extension region EX1 and the channel region of the n-channel type MISFET Qn are necessarily formed. At least a part of the diffusion preventing region 18a is located between them. Therefore, regardless of whether or not the halo region HA1 is formed, the halo region HA1 is formed by positioning at least a part of the diffusion prevention region 18a between the extension region EX1 and the channel region of the n-channel type MISFET Qn. In this case, at least a part of the diffusion prevention region 18a may be positioned between the halo region HA1 and the channel region of the n-channel type MISFET Qn.

In order for the diffusion prevention region 18b to have the above-described function, at least a part of the diffusion prevention region 18b includes the extension region EX2, the halo region HA2, the p ⁺ type semiconductor region SD2, and the channel region of the p channel type MISFET Qp ( It is necessary to be located between the region immediately below the gate electrode GE2. Of the extension region EX2, the halo region HA2, and the p ⁺ type semiconductor region SD2, the halo region HA2 is closest to the channel region of the p-channel type MISFET Qp. Therefore, when the halo region HA2 is formed, at least a part of the diffusion prevention region 18b. However, it suffices to be positioned between the halo region HA2 and the channel region of the p-channel type MISFET Qp. In order to do this, it is preferable to form the diffusion prevention region 18b so as to wrap (cover) the halo region HA2. When the formation of the halo region HA2 is omitted, since the extension region EX2 is close to the channel region, at least a part of the diffusion prevention region 18b may be located between the extension region EX2 and the channel region of the p-channel type MISFET Qp. In order to do this, it is preferable to form the diffusion prevention region 18b so as to wrap (cover) the extension region EX2.

  When at least a part of the diffusion prevention region 18b is located between the halo region HA2 and the channel region of the p-channel type MISFET Qp, the extension region EX2 and the channel region of the p-channel type MISFET Qp are necessarily formed. At least a part of the diffusion preventing region 18b is located between them. Therefore, regardless of whether or not the halo region HA2 is formed, when the halo region HA2 is formed by positioning at least a part of the diffusion prevention region 18b between the extension region EX2 and the channel region of the p-channel type MISFET Qp. In other words, at least a part of the diffusion prevention region 18b may be positioned between the halo region HA2 and the channel region of the p-channel type MISFET Qp.

In the present embodiment, since the diffusion prevention regions 18a and 18b are formed, each ion when forming the extension regions EX1 and EX2, the halo regions HA1 and HA2, the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2 is used. Point defects generated by implantation can be prevented from diffusing into the channel regions of the n-channel MISFET Qn and the p-channel MISFET Qp, and the density of point defects in the channel region can be suppressed. As a result, it is possible to suppress or prevent the impurities introduced into the channel region by channel doping ion implantation (IM1a, IM1b) from being rearranged (diffused) during the subsequent heating step. A regular arrangement of channel impurities can be maintained. Therefore, variations in threshold voltage for each MISFET can be more accurately suppressed, and the performance of the semiconductor device can be further improved.

  In addition, one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced into the diffusion prevention regions 18a and 18b, but carbon (C), nitrogen (N), and fluorine ( Among F), carbon (C) is most effective for preventing the diffusion of point defects. For this reason, it is more preferable that at least carbon (C) of carbon (C), nitrogen (N), or fluorine (F) is introduced into the diffusion prevention regions 18a and 18b. Thereby, the above-mentioned effect by providing the diffusion prevention regions 18a and 18b can be obtained more accurately.

  In the present embodiment, diffusion prevention regions 18a and 18b are formed by ion implantation of one or more of carbon (C), nitrogen (N), and fluorine (F) only in necessary regions in a semiconductor substrate. can do. For this reason, carbon (C), nitrogen (N) or fluorine (F) can be prevented from being introduced into unnecessary areas, and carbon (C), nitrogen (N) or fluorine (F) is introduced into unnecessary areas. The negative effect by being done can be eliminated.

  In addition, the variation in threshold voltage for each MISFET due to the rearrangement (diffusion) of impurities introduced by channel doping ion implantation is larger in the n-channel MISFET than in the p-channel MISFET. In general, n-channel MISFETs are implanted with p-type impurities by channel dope ion implantation, and p-channel MISFETs are implanted with n-type impurities by channel dope ion implantation. This is because a p-type impurity such as boron (B) is more easily thermally diffused than an n-type impurity. For this reason, the present embodiment (forming those corresponding to the diffusion prevention regions 18a and 18b) is not only a semiconductor device having a CMISFET but also a semiconductor device having only one of a p-channel MISFET and an n-channel MISFET. However, if applied to a semiconductor device having at least an n-channel MISFET, the effect is great.

(Embodiment 4)
A manufacturing process of the semiconductor device according to the fourth embodiment will be described with reference to the drawings. 37 to 40 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment. The present embodiment corresponds to a combination of the second embodiment and the third embodiment.

  First, the structure shown in FIG. 27 is obtained in the same manner as in the second embodiment. Accordingly, also in the present embodiment, as in the second embodiment, the semiconductor layer 17a, the channel doped layer 4a, and the p-type well PW are formed on the semiconductor substrate 1 in the nMIS formation region 1A, and the semiconductor in the pMIS formation region 1B. A semiconductor layer 17b, a channel dope layer 4b, and an n-type well NW are formed on the substrate 1.

  Then, as shown in FIG. 37, after forming the same photoresist film PR2a (the photoresist film PR2a covering the pMIS formation region 1B and exposing the nMIS formation region 1A) as in the third embodiment, Similar to the third embodiment, the diffusion prevention region 18a, the extension region EX1, and the halo region HA1 are formed. The ion implantation IM6a for forming the diffusion prevention region 18a, the ion implantation IM2a for forming the extension region EX1, and the ion implantation IM3a for forming the halo region HA1 are performed as separate ion implantation steps. However, in FIG. 37, they are collectively shown by arrows. In addition, since the relationship between the diffusion prevention region 18a, the extension region EX1, and the halo region HA1 has been described in the third embodiment, the repeated description thereof is omitted here.

  Next, as shown in FIG. 38, after removing the photoresist film PR2a, the same photoresist film PR2b as in the third embodiment (a photoresist that covers the nMIS formation region 1A and exposes the pMIS formation region 1B). After the formation of the film PR2b), the diffusion prevention region 18b, the extension region EX2, and the halo region HA2 are formed in the same manner as in the third embodiment. The ion implantation IM6b for forming the diffusion prevention region 18b, the ion implantation IM2b for forming the extension region EX2, and the ion implantation IM3b for forming the halo region HA2 are performed as separate ion implantation steps. However, in FIG. 38, they are collectively shown by arrows. In addition, since the relationship between the diffusion prevention region 18b, the extension region EX2, and the halo region HA2 has been described in the third embodiment, repeated description thereof is omitted here.

  The subsequent steps are the same as those in the first to third embodiments.

That is, as shown in FIG. 39, after removing the photoresist film PR2b, sidewalls (sidewall insulating films) SW are formed on the sidewalls of the gate electrodes GE1 and GE2. Then, an n ⁺ type semiconductor region SD1 is formed in the semiconductor substrate 1 (p type well PW) in the nMIS formation region 1A, and a p ⁺ type semiconductor region SD2 is formed in the semiconductor substrate 1 (n type well NW) in the pMIS formation region 1B. Form. The formation method and configuration of the sidewall SW, the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2 in the present embodiment are the same as those in the first embodiment.

  Next, similarly to the first embodiment, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed.

Thereafter, as shown in FIG. 40, similarly to the first embodiment, the metal silicide layers 11 are formed on the surfaces of the gate electrodes GE1, GE2, the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2, respectively. An insulating film 12 is formed on the main surface of the semiconductor substrate 1 so as to cover the gate electrodes GE1 and GE2 and the sidewall SW, a contact hole 13 is formed in the insulating film 12, and a plug 14 is formed in the contact hole 13. Then, as in the first embodiment, the insulating film 15 is formed on the insulating film 12 in which the plugs 14 are embedded, and the wiring M1 is formed on the insulating film 15 by the damascene method.

In the present embodiment, by forming the semiconductor layers 17a and 17b and the diffusion prevention regions 18a and 18b, the extension regions EX1 and EX2, the halo regions HA1 and HA2, the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2 are formed. The effect of preventing point defects generated by each ion implantation at the time of formation from diffusing into the channel regions of the n-channel type MISFET Qn and the p-channel type MISFET Qp can be enhanced as compared with the second and third embodiments. . Thereby, the density of point defects in the channel region can be further suppressed than in the second and third embodiments. For this reason, the impurities introduced into the channel region by channel doping ion implantation (IM1a, IM1b) can be more accurately suppressed or prevented from being rearranged (diffused) during the subsequent heating step. A regular arrangement of channel impurities immediately after implantation can be maintained more accurately. Therefore, the effect of suppressing variation in threshold voltage of the MISFET can be further enhanced, and the performance of the semiconductor device can be improved more accurately.

(Embodiment 5)
FIG. 41 is a plan view showing an example of the semiconductor device (semiconductor chip) CP1 manufactured by the manufacturing steps of the first to fourth embodiments.

  A semiconductor device (semiconductor chip) CP1 of the present embodiment shown in FIG. 41 has a memory area (memory circuit area, memory cell array area, SRAM area) MRY in which a memory cell array such as SRAM (Static Random Access Memory) is formed. And a peripheral circuit region PCR in which circuits (peripheral circuits) other than the memory are formed. The peripheral circuit region PCR includes, for example, an analog circuit region in which an analog circuit is formed, a CPU region in which a control circuit (logic circuit) is formed, and the like. The memory region MRY and the peripheral circuit region PCR or between the peripheral circuit regions PCR are electrically connected as necessary via the internal wiring layer of the semiconductor device CP1. In addition, a plurality of pad electrodes PD are formed along the four sides of the main surface of the semiconductor device CP1 at the periphery of the main surface (front surface) of the semiconductor device CP1. Each pad electrode PD is electrically connected to the memory region MRY, the peripheral circuit region PCR, etc. via the internal wiring layer of the semiconductor device CP1.

  In the present embodiment, the manufacturing technique of the first to fourth embodiments can be applied in manufacturing the semiconductor device CP1, but all regions (the memory region MRY and all the peripheral circuit regions PCR) in the semiconductor device CP1 are applicable. This is applied to the memory area MRY, but not to the peripheral circuit area PCR. That is, in manufacturing the semiconductor device CP1, in the memory region MRY, the ion implantation method of the first embodiment (that is, ion implantation using the filter FL to which a voltage is applied) as described above is used for channel dope ion implantation. In the peripheral circuit region PCR, general channel dope ion implantation without using the filter FL is performed without using the ion implantation method of the first embodiment as described above for channel dope ion implantation. FIG. 41 is a plan view, but for the sake of easy understanding, channel-doped ions are obtained by the ion implantation method of the first embodiment (that is, ion implantation using the filter FL to which a voltage is applied) as described above. The region to be implanted is shown with hatching.

  A manufacturing process of the semiconductor device CP1 will be specifically described below with reference to FIGS. 42 to 48 are main-portion cross-sectional views during the manufacturing process of the semiconductor device CP1 of the present embodiment.

  In the present embodiment, as in the first embodiment, first, a semiconductor substrate (semiconductor wafer) 1 is prepared. FIG. 42 shows a part of the memory region MRY and a part of the peripheral circuit region PCR in the semiconductor substrate 1.

  Of the memory region MRY, FIG. 42 shows a memory nMIS formation region 1C, which is a region where an n-channel MISFET constituting the memory (memory cell) is formed, and a p-channel MISFET constituting the memory (memory cell). A memory pMIS formation region 1D, which is a region to be formed, is shown.

  In the peripheral circuit region PCR, MISFETs having different breakdown voltages are formed. Therefore, in FIG. 42, a low breakdown voltage nMIS formation region 1L, which is a region where a low breakdown voltage n-channel MISFET is formed in the peripheral circuit region PCR, and a high breakdown voltage n-channel MISFET are formed in the peripheral circuit region PCR. A high breakdown voltage nMIS formation region 1H, which is a region to be connected, is shown.

  Then, the element isolation region 2 is formed on the main surface of the semiconductor substrate 1.

  Next, after the insulating film 3 similar to that of the first embodiment is formed on the surface of the semiconductor substrate 1, as shown in FIG. 43, the p-type well PW1 is formed in the memory nMIS formation region 1C, and the memory pMIS formation region. An n-type well NW1 is formed in 1D, a p-type well PW2 is formed in the low breakdown voltage nMIS formation region 1L, and a p-type well PW3 is formed in the high breakdown voltage nMIS formation region 1H. The p-type wells PW1, PW2, PW3 and the n-type well NW1 can be formed by ion implantation using a photoresist film (not shown) as an ion implantation blocking mask, respectively. If the ion implantation for forming the p-type well PW1, the ion implantation for forming the p-type well PW2, and the ion implantation for forming the p-type well PW3 are performed in the same ion implantation step, the number of steps can be reduced. However, it may be performed as a different ion implantation step.

  Next, channel dope ion implantation (ion for adjusting the threshold voltage of the MISFET formed therein) is performed in each of the memory nMIS formation region 1C, the memory pMIS formation region 1D, the low breakdown voltage nMIS formation region 1L, and the high breakdown voltage nMIS formation region 1H. Injection) IM1c, IM1d, IM1e, IM1f are performed. In FIG. 43, channel dope ion implantation IM1c, IM1d, IM1e, IM1f is schematically shown by arrows.

  The channel dope ion implantation IM1c forms a channel dope layer 4c in the upper layer portion of the semiconductor substrate 1 (p-type well PW1) in the memory nMIS formation region 1C. Further, the channel dope ion implantation IM1d forms the channel dope layer 4d in the upper layer portion of the semiconductor substrate 1 (n-type well NW1) in the memory pMIS formation region 1D. Further, the channel dope ion implantation IM1e forms the channel dope layer 4e in the upper layer portion of the semiconductor substrate 1 (p-type well PW2) in the low breakdown voltage nMIS formation region 1L. Further, the channel dope ion implantation IM1f forms the channel dope layer 4f in the upper layer portion of the semiconductor substrate 1 (p-type well PW3) in the high breakdown voltage nMIS formation region 1H. The channel dope layers 4c, 4d, 4e, and 4f are regions serving as channel regions of the MISFETs formed in the memory nMIS formation region 1C, the memory pMIS formation region 1D, the low breakdown voltage nMIS formation region 1L, and the high breakdown voltage nMIS formation region 1H. Contains.

  In the present embodiment, the channel doping ion implantation IM1c into the memory nMIS formation region 1C is similar to the channel doping ion implantation IM1a performed in the nMIS formation region 1A in the first embodiment (that is, a voltage is applied). Ion implantation is performed by ion implantation using a filter FL. The channel dope ion implantation IM1d into the memory pMIS formation region 1D is performed using the same technique as the channel dope ion implantation IM1b performed on the pMIS formation region 1B in the first embodiment (that is, using the filter FL to which a voltage is applied). Ion implantation). On the other hand, the channel dope ion implantation IM1e to the low breakdown voltage nMIS formation region 1L and the channel dope ion implantation IM1f to the high breakdown voltage nMIS formation region 1H are the same as those used in the channel dope ion implantation IM1a and IM1b of the first embodiment. The first ion implantation method (that is, ion implantation using the filter FL to which a voltage is applied) is not applied, and a general ion implantation method (that is, ion implantation that does not use the filter FL) is used.

  Note that when performing channel doped ion implantation IM1c into the memory nMIS formation region 1C, a photoresist film (not shown) covering the memory pMIS formation region 1D, the low breakdown voltage nMIS formation region 1L, and the high breakdown voltage nMIS formation region 1H is used. What is necessary is just to use as an ion implantation prevention mask. Further, when performing channel dope ion implantation IM1d into the memory pMIS formation region 1D, a photoresist film (not shown) covering the memory nMIS formation region 1C, the low breakdown voltage nMIS formation region 1L, and the high breakdown voltage nMIS formation region 1H is used. What is necessary is just to use as an ion implantation prevention mask. Further, when performing channel dope ion implantation IM1e to the low breakdown voltage nMIS formation region 1L, a photoresist film (not shown) covering the memory nMIS formation region 1C, the memory pMIS formation region 1D, and the high breakdown voltage nMIS formation region 1H is used. What is necessary is just to use as an ion implantation prevention mask. Further, when performing channel dope ion implantation IM1f into the high breakdown voltage nMIS formation region 1H, a photoresist film (not shown) covering the memory nMIS formation region 1C, the memory pMIS formation region 1D, and the low breakdown voltage nMIS formation region 1L is used. What is necessary is just to use as an ion implantation prevention mask.

  Further, when the doping amount (dose amount) of the channel dope ion implantation IM1e in the low breakdown voltage nMIS formation region 1L and the doping amount (dose amount) of the channel dope ion implantation IM1f in the high breakdown voltage nMIS formation region 1H may be the same, the low breakdown voltage The channel dope ion implantation IM1e in the nMIS formation region 1L and the channel dope ion implantation IM1f in the high breakdown voltage nMIS formation region 1H can be performed in the same ion implantation step.

  Next, after the insulating film 3 is removed and the surface of the semiconductor substrate 1 is cleaned, a memory gate is formed on the semiconductor substrate 1 in the memory nMIS formation region 1C and the memory pMIS formation region 1D as shown in FIG. The insulating film 5c is formed by applying a low breakdown voltage gate insulating film 5d on the semiconductor substrate 1 in the low breakdown voltage nMIS formation region 1L, and forming a high breakdown voltage gate insulating film 5e on the semiconductor substrate 1 in the high breakdown voltage nMIS formation region 1H. Form. The high breakdown voltage gate insulating film 5e is thicker and has a higher breakdown voltage than the memory gate insulating film 5c and the low breakdown voltage gate insulating film 5d.

  The gate insulating films 5c, 5d, and 5e having different thicknesses can be formed as follows, for example.

  That is, after an insulating film for the gate insulating film 5e is formed on the entire main surface of the semiconductor substrate 1 by thermal oxidation, CVD, or the like, the memory nMIS formation region 1C, the memory pMIS formation region 1D, and the low breakdown voltage nMIS formation region 1L are etched. Then, this insulating film is removed, and this insulating film is left in the high breakdown voltage nMIS formation region 1H. Then, a silicon oxide film is formed on the main surface of the semiconductor substrate by thermal oxidation. Thereby, gate insulating films 5c and 5d made of a thin silicon oxide film (thermal oxide film) are formed on the semiconductor substrate 1 in the memory nMIS formation region 1C, the memory pMIS formation region 1D, and the low breakdown voltage nMIS formation region 1L. In the high breakdown voltage nMIS formation region 1H, the thickness of the insulating film for the gate insulating film 5e is increased, resulting in a thick gate insulating film 5e. When it is necessary to make the gate insulating film 5c thinner than the gate insulating film 5d, the silicon oxide film on the surface of the semiconductor substrate 1 in the memory nMIS formation region 1C and the memory pMIS formation region 1D is removed by etching, and then heat is applied again. A silicon oxide film may be formed on the main surface of the semiconductor substrate by oxidation.

  Since the high breakdown voltage gate insulating film 5e is thicker than the memory gate insulating film 5c and the low breakdown voltage gate insulating film 5d, the breakdown voltage of the MISFET formed in the high breakdown voltage nMIS formation region 1H is the memory nMIS formation region. 1C, higher than the breakdown voltage of the MISFET formed in the memory pMIS formation region 1D and the low breakdown voltage nMIS formation region 1L.

  Next, a silicon film such as a polycrystalline silicon film is formed over the entire main surface of the semiconductor substrate 1 as a conductive film for forming a gate electrode, and this silicon film is formed using a photolithography method and a dry etching method. By patterning, gate electrodes GE3, GE4, GE5 and GE6 are formed as shown in FIG. The gate electrodes GE3, GE4, GE5, and GE6 are formed of a patterned silicon film. In FIG. 45 and FIGS. 46 to 48 to be described later, the channel dope layers 4c, 4d, 4e, and 4f are omitted for easy understanding of the drawings.

  The gate electrode GE3 is formed on the p-type well PW1 via the gate insulating film 5c in the memory nMIS formation region 1C. The gate electrode GE4 is formed on the n-type well NW1 via the gate insulating film 5c in the memory pMIS formation region 1D. The gate electrode GE5 is formed on the p-type well PW2 via the gate insulating film 5d in the low breakdown voltage nMIS formation region 1L. The gate electrode GE6 is formed on the p-type well PW3 via the gate insulating film 5e in the high breakdown voltage nMIS formation region 1H.

  Next, as shown in FIG. 46, as in the first embodiment, the extensions are formed by ion implantation into the semiconductor substrate 1 (p-type wells PW1, PW2) in the memory nMIS formation region 1C and the low breakdown voltage nMIS formation region 1L. Region EX1 and halo region HA1 are formed. Similarly to the first embodiment, the extension region EX2 and the halo region HA2 are formed in the semiconductor substrate 1 (n-type well NW1) in the memory pMIS formation region 1D by ion implantation. In order to simplify the drawing, the halo regions HA1 and HA2 are not shown in FIG.

  In the present embodiment, the memory nMIS formation region 1C and the low breakdown voltage nMIS formation region 1L except that the gate electrode GE1 becomes the gate electrodes GE3 and GE5 and the p-type well PW becomes the p-type wells PW1 and PW2. The formation method and configuration of the extension region EX1 and the halo region HA1 in FIG. 3 are the same as those in the first embodiment, and thus description thereof is omitted here. In the present embodiment, the extension region EX2 and the halo region HA2 in the memory pMIS formation region 1D except that the gate electrode GE2 becomes the gate electrode GE4 and the n-type well NW becomes the n-type well NW1. Since the formation method and configuration are the same as those in the first embodiment, description thereof is omitted here.

  When the extension region EX1 and the halo region HA1 are formed in the memory nMIS formation region 1C and the low breakdown voltage nMIS formation region 1L, a photoresist film (not shown) covering the memory pMIS formation region 1D and the high breakdown voltage nMIS formation region 1H. ) May be used as an ion implantation blocking mask. When the extension region EX2 and the halo region HA2 are formed in the memory pMIS formation region 1D, a photoresist film (not shown) covering the memory nMIS formation region 1C, the low breakdown voltage nMIS formation region 1L, and the high breakdown voltage nMIS formation region 1H. ) May be used as an ion implantation blocking mask.

  In addition, in the high breakdown voltage nMIS formation region 1H, a MISFET having a higher breakdown voltage than the MISFETs in the memory nMIS formation region 1C, the memory pMIS formation region 1D, and the low breakdown voltage nMIS formation region 1L is formed. An extension region and a halo region are not formed in the MISFET, but an extension region and a halo region can be formed if necessary.

  Next, as shown in FIG. 47, sidewalls (sidewall insulating films) SW are formed on the sidewalls of the gate electrodes GE3, GE4, GE5, and GE6 as in the first embodiment.

Next, n is implanted into the semiconductor substrate 1 (p-type wells PW1, PW2, PW3) in the memory nMIS formation region 1C, the low breakdown voltage nMIS formation region 1L, and the high breakdown voltage nMIS formation region 1H by ion implantation as in the first embodiment. ^{A +} type semiconductor region SD1 (source, drain) is formed. Further, a p ⁺ type semiconductor region SD2 (source, drain) is formed in the semiconductor substrate 1 (n type well NW1) in the memory pMIS formation region 1D by ion implantation in the same manner as in the first embodiment. The formation method and configuration of the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2 in the present embodiment are the same as those in the first embodiment.

When the n ⁺ type semiconductor region SD1 is formed in the memory nMIS formation region 1C, the low breakdown voltage nMIS formation region 1L, and the high breakdown voltage nMIS formation region 1H, a photoresist film (not shown) that covers the memory pMIS formation region 1D May be used as an ion implantation blocking mask. Further, when forming the p ⁺ type semiconductor region SD2 in the memory pMIS formation region 1D, a photoresist film (not shown) covering the memory nMIS formation region 1C, the low breakdown voltage nMIS formation region 1L, and the high breakdown voltage nMIS formation region 1H. May be used as an ion implantation blocking mask.

  Next, similarly to the first embodiment, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed.

Subsequent steps are substantially the same as those in the first embodiment. That is, as shown in FIG. 48, similarly to the first embodiment, the metal silicide layers 11 are formed on the surfaces of the gate electrodes GE3 to GE6, the n ⁺ type semiconductor region SD1 and the p ⁺ type semiconductor region SD2, An insulating film 12 is formed on the main surface of the semiconductor substrate 1 so as to cover the gate electrodes GE3 to GE6 and the sidewall SW, a contact hole 13 is formed in the insulating film 12, and a plug 14 is formed in the contact hole 13. Then, as in the first embodiment, the insulating film 15 is formed on the insulating film 12 in which the plugs 14 are embedded, and the wiring M1 is formed on the insulating film 15 by the damascene method.

  Further, the second, third, and fourth embodiments can be applied to this embodiment. When the second and fourth embodiments are applied to the present embodiment, the semiconductor layer 17 (17a, 17b) is formed in the memory region MRY (the memory nMIS formation region 1C and the memory pMIS formation region 1D). The semiconductor layer 17 (17a, 17b) is not formed in the peripheral circuit region PCR (the low breakdown voltage nMIS formation region 1L and the high breakdown voltage nMIS formation region 1H). When the third and fourth embodiments are applied to the present embodiment, the diffusion prevention regions 18a and 18b are formed in the memory region MRY (the memory nMIS formation region 1C and the memory pMIS formation region 1D). The diffusion prevention regions 18a and 18b are not formed in the peripheral circuit region PCR (the low breakdown voltage nMIS formation region 1L and the high breakdown voltage nMIS formation region 1H).

  Carbon (C), nitrogen (N), and fluorine (F) are not introduced compared to a substrate region into which one or more of carbon (C), nitrogen (N), or fluorine (F) are ion-implanted. The substrate region can increase the activation rate of n-type impurities (for example, phosphorus) or p-type impurities (for example, boron). Therefore, in the present embodiment, when the second, third, and fourth embodiments are applied to the present embodiment, in the peripheral circuit region PCR, the semiconductor layers 17a and 17b and the diffusion prevention regions 18a and 18b. By not forming, the activation rate of n-type impurities (for example, phosphorus) or p-type impurities (for example, boron) introduced into the peripheral circuit region PCR can be increased, and the resistance component of the MISFET can be easily lowered. Thereby, in the memory region MRY, variation in threshold voltage for each MISFET can be suppressed, and in the peripheral circuit region PCR, the activation rate of the ion-implanted impurity can be increased.

  In this embodiment, a technique similar to that of the channel dope ion implantation IM1a and IM1b of the first embodiment (that is, ion implantation using the filter FL to which a voltage is applied) is used for channel dope ion implantation for the MISFET in the memory region MRY. On the other hand, it is not applied to channel dope ion implantation for the MISFET in the peripheral circuit region PCR. Thereby, the following effects can be obtained.

  In the memory region MRY, if the threshold voltage fluctuates for each MISFET, an accurate operation of the memory cannot be performed. Therefore, it is desirable to suppress the fluctuation of the threshold voltage as much as possible. Further, MISFETs constituting memory cells (particularly MISFETs constituting SRAMs) are miniaturized as compared to MISFETs constituting circuits other than the memory. When the state of the channel region (impurity arrangement state or number of impurities in the channel region) varies for each MISFET, the threshold voltage varies more as the MISFET (MISFET with a smaller gate area) is miniaturized. For this reason, in the MISFET in the memory region MRY, the threshold voltage fluctuates easily due to the impurity arrangement state and the number of impurities in the channel region, compared to the MISFET in the peripheral circuit region PCR.

  On the other hand, in this embodiment, the channel doping ion implantation for the MISFET in the memory region MRY uses the same technique as the channel doping ion implantation IM1a and IM1b in the first embodiment (that is, uses a filter FL to which a voltage is applied). Applied ion implantation). As a result, in the channel region of the MISFET in the memory region MRY, the impurities (channel impurities) are regularly arranged, so that variation (variation) in the threshold voltage of the MISFET in the memory region MRY can be prevented. Since the variation (variation) in the threshold voltage of the MISFET in the memory region MRY can be prevented, the reliability and performance of the memory formed in the memory region MRY can be improved and the memory region MRY is formed in the memory region MRY. The margin of writing and reading of the memory cell becomes better than the design standard, and the occurrence rate of product defects can be greatly reduced.

  In addition to the SRAM, other types of memory cell arrays such as a flash memory can be formed in the memory area MRY. However, in the case of SRAM, the element is particularly miniaturized and the allowable amount of variation in threshold voltage is small, so that the effect is particularly great when the memory formed in the memory region MRY is SRAM.

  As described above, the MISFET in the memory region MRY is an element in which threshold voltage variation (variation) is likely to occur due to variations in the impurity arrangement state and the number of impurities in the channel region. It is an element that is desired to suppress fluctuations in as much as possible. On the other hand, as compared with the memory region MRY, the peripheral circuit region PCR can tolerate fluctuations (variations) in the threshold voltage of the MISFET. In addition, since the MISFET in the memory region MRY is smaller than the MISFET in the peripheral circuit region PCR, the peripheral circuit region PCR has a channel region state (impurities in the channel region) compared to the memory region MRY. Variation of the threshold voltage due to variations in the arrangement state and the number of impurities).

  For this reason, in the present embodiment, the channel implantation ion implantation for the MISFET in the peripheral circuit region PCR uses the ion implantation method of the first embodiment (that is, ion implantation using the filter FL to which a voltage is applied) as described above. A general channel dope ion implantation is performed without applying the filter FL. As described above, the ion implantation method of the first embodiment (that is, ion implantation using the filter FL to which a voltage is applied) requires a longer time for the ion implantation process than general ion implantation that does not use the filter FL. Become. In this embodiment, the channel implantation ion implantation for the MISFET in the peripheral circuit region PCR does not apply the ion implantation method of the first embodiment as described above (that is, ion implantation using the filter FL to which a voltage is applied). Thus, the manufacturing time of the semiconductor device can be shortened and the throughput can be improved. Further, in the peripheral circuit region PCR, a regular arrangement of channel impurities as in the memory region MRY cannot be obtained, but in the peripheral circuit region PCR, the threshold voltage of the MISFET varies more than in the memory region MRY. Since it is difficult or the fluctuation of the threshold voltage can be allowed, it is possible to suppress or prevent the performance of the peripheral circuit region PCR from deteriorating.

  Therefore, in the present embodiment, the performance of the semiconductor device CP1 having the memory region MRY and the peripheral circuit region PCR can be improved, and the manufacturing time of the semiconductor device can be shortened. For this reason, the throughput can be improved and the manufacturing cost of the semiconductor device can be reduced.

(Embodiment 6)
FIG. 49 is a plan view showing an example of a semiconductor device (semiconductor chip) CP2 manufactured by the manufacturing process of the first to fourth embodiments.

  A semiconductor device (semiconductor chip) CP2 of the present embodiment shown in FIG. 49 includes a memory region MRY in which a memory cell array such as SRAM is formed, and a peripheral circuit region PCR in which circuits (peripheral circuits) other than the memory are formed. have. The semiconductor device (semiconductor chip) CP2 is mainly formed with a memory region MRY. The semiconductor device CP2 is a so-called memory chip, and the analog circuit region and CPU region are the same as the semiconductor device CP1 of the fifth embodiment. I don't have it. The memory region MRY and the peripheral circuit region PCR are electrically connected as necessary via an internal wiring layer of the semiconductor device CP2. A plurality of pad electrodes PD are formed along the two sides of the main surface of the semiconductor device CP2 in the peripheral portion of the main surface (front surface) of the semiconductor device CP2. Each pad electrode PD is electrically connected to the memory region MRY, the peripheral circuit region PCR, etc. via the internal wiring layer of the semiconductor device CP2.

  As in the fifth embodiment, in the present embodiment, the manufacturing technique of the first to fourth embodiments can be applied in manufacturing the semiconductor device CP2, but all regions (memory) in the semiconductor device CP2 can be applied. This is not applied to all of the region MRY and the peripheral circuit region PCR), but applied to the memory region MRY, but not to the peripheral circuit region PCR. That is, in manufacturing the semiconductor device CP2, in the memory region MRY, the ion implantation method of the first embodiment (that is, ion implantation using the filter FL to which a voltage is applied) as described above is used for channel dope ion implantation. On the other hand, in the peripheral circuit region PCR, the channel implantation ion implantation does not use the ion implantation method of the first embodiment (that is, ion implantation using the filter FL to which a voltage is applied) as described above, and does not use the filter FL. Channel doping ion implantation is performed. FIG. 49 is a plan view, but for the sake of easy understanding, channel-doped ions are obtained by the ion implantation method of the first embodiment (that is, ion implantation using a filter FL to which a voltage is applied) as described above. The region to be implanted is shown with hatching.

  Since the manufacturing process of the semiconductor device CP2 is substantially the same as the process described with reference to FIGS. 42 to 48 in the fifth embodiment, the repetitive description thereof is omitted here.

  Also in the present embodiment, similar to the fifth embodiment, a technique similar to that of the channel dope ion implantation IM1a and IM1b of the first embodiment (that is, ion implantation using the filter FL to which a voltage is applied) is used for the memory. By applying to the channel dope ion implantation for the MISFET in the region MRY, while not applying to the channel dope ion implantation for the MISFET in the peripheral circuit region PCR, the same effect as in the fifth embodiment can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1A nMIS formation area 1B pMIS formation area 1C Memory nMIS formation area 1D Memory pMIS formation area 1H High breakdown voltage nMIS formation area 1L Low breakdown voltage nMIS formation area 1W Semiconductor wafer 2 Element isolation area 3 Insulating films 4a, 4b, 4c, 4d , 4e, 4f Channel doped layer 5 Insulating films 5a, 5b, 5c, 5d, 5e Gate insulating film 6 Silicon film 11 Metal silicide layer 12 Insulating film 13 Contact hole 14 Plug 15 Insulating films 17, 17a, 17b Semiconductor layers 18a, 18b Diffusion prevention region 21 Ion implanter 22, 22a, 22b, 22c Ion beam 22d Impurity ion 23 Ion source 24 Accelerating tube 25 Mass analysis magnet 26 Lens 27 Processing chamber 28 Wafer exchange chamber 29 Stage 30 Channel impurities CP1, CP2 Semiconductor device C Central portion EX1, EX2 Extension region FL filter GE1, GE2, GE3, GE4, GE5, GE6 Gate electrodes HA1, HA2 Halo regions IM1a, IM1b, IM1c, IM1d, IM1e, IM1f Channel dope ion implantation (ion for threshold adjustment) Injection)
IM2a, IM2b, IM3a, IM3b, IM4a, IM4b, IM5, IM6a, IM6b Ion implantation M1 wiring MRY memory area NW, NW1 n-type well OP opening P ₁ arrangement pitch PCR peripheral circuit area PD pad electrodes PR1a, PR1b, PR2a, PR2b, PR3a, PR3b Photoresist pattern PW, PW1, PW2, PW3 p-type well Qn n-channel type MISFET
Qp p-channel MISFET
SD1 n ⁺ type semiconductor region SD2 p ⁺ type semiconductor region SW Side wall W ₁ dimension W ₂ interval W ₃ thickness W ₄ array interval

Claims (12)

A method of manufacturing a semiconductor device having a MISFET,
(A) a step of preparing a semiconductor substrate;
(B) performing ion implantation for adjusting the threshold value of the MISFET into the semiconductor substrate;
(C) a step of forming an insulating film for the gate insulating film of the MISFET on the main surface of the semiconductor substrate after the step (b);
(D) after the step (c), forming a gate electrode of the MISFET on the insulating film;
Have
In the step (b),
The ion implantation is performed by converging an ion beam that has passed through a filter having a plurality of regularly arranged openings and irradiating the semiconductor substrate,
A method of manufacturing a semiconductor device, wherein a voltage having the same polarity as impurity ions implanted into the semiconductor substrate by the ion implantation is applied to the filter. In the manufacturing method of the semiconductor device according to claim 1,
In the step (b), an impurity is introduced into the channel region of the MISFET. The method of manufacturing a semiconductor device according to claim 2.
The method of manufacturing a semiconductor device, wherein the filter is made of a conductive material. In the manufacturing method of the semiconductor device according to claim 3,
In the step (b),
Among the impurity ions constituting the ion beam, impurity ions incident on the center of the opening are injected into the semiconductor substrate through the opening,
Impurity ions incident on the periphery of the opening are not implanted into the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 4,
In the filter, the plurality of openings are arranged in a lattice pattern. In the manufacturing method of the semiconductor device according to claim 5,
After the step (d),
(E) performing ion implantation on the semiconductor substrate using the gate electrode as a mask to form a first semiconductor region of a first conductivity type in the semiconductor substrate;
(F) after the step (e), forming a sidewall insulating film on the sidewall of the gate electrode;
(G) After the step (f), ion implantation is performed on the semiconductor substrate using the gate electrode and the sidewall insulating film as a mask, and the first conductivity type having a higher impurity concentration than the first semiconductor region is formed in the semiconductor substrate. Forming a second semiconductor region of
Further comprising
The method for manufacturing a semiconductor device, wherein the first and second semiconductor regions function as a semiconductor region for a source or a drain of the MISFET. The method of manufacturing a semiconductor device according to claim 6.
In the step (e) and the step (g), the filter is not used at the time of ion implantation. The method of manufacturing a semiconductor device according to claim 7.
In the step (a), the semiconductor substrate having an upper semiconductor layer into which one or more of carbon, nitrogen, and fluorine are introduced is prepared.
In the step (b), an ion implantation for adjusting a threshold value of the MISFET is performed on the semiconductor layer. The method of manufacturing a semiconductor device according to claim 7.
After the step (d) and before the step (f),
(E1) performing ion implantation of a first element on the semiconductor substrate;
Further comprising
The first element ion-implanted in the step (e1) is composed of one or more of carbon, nitrogen, and fluorine,
At least a part of the region into which the first element is introduced in the step (e1) is located between the channel region of the MISFET and the first semiconductor region. In the manufacturing method of the semiconductor device according to claim 9,
In the step (e1),
A method of manufacturing a semiconductor device, wherein the first element is introduced into the semiconductor substrate by oblique ion implantation. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having a memory region in which a memory is formed and a peripheral circuit region in which a circuit other than the memory is formed,
When performing the step (b) in the memory region, the ion beam that has passed through the filter to which the voltage has been applied is converged and irradiated onto the semiconductor substrate, thereby performing the ion implantation in the step (b). ,
When performing the step (b) in the peripheral circuit region, the semiconductor device manufacturing method is characterized in that the ion implantation of the step (b) is performed without using the filter. A method of manufacturing a semiconductor device having a MISFET,
By applying a voltage having the same polarity as the ion beam to a filter having a plurality of openings regularly arranged, and converging the ion beam that has passed through the filter to which the voltage has been applied to irradiate the semiconductor substrate, A step of channel-doped ion implantation,
A method for manufacturing a semiconductor device, comprising:

Images