JP2012000813A - Image forming apparatus and program - Google Patents

Abstract

An image forming apparatus and a program capable of reducing the influence of noise mixed in a pixel data transfer clock signal.
An image forming apparatus according to an embodiment of the present invention operates with a memory input shift clock generated by an engine control unit and outputs a signal having the same data string as image data from a controller control unit. A receiving circuit 110 including a D-type flip-flop circuit 113 is provided. For this reason, since it is not necessary to use the pixel data clock signal transmitted via the communication line 90, it is possible to suppress the occurrence of communication failure due to noise mixed in the pixel data clock signal.
[Selection] Figure 8

Description

  The present invention relates to an image forming apparatus and a program.

  Conventionally, when image data is transmitted from the first control unit to the second control unit via the communication line inside the image forming apparatus, it is easier to determine the effective area of the image data included in the image data. There is known an image forming apparatus that can be performed in a short time (for example, Patent Document 1).

  However, in the image forming apparatus disclosed in Patent Document 1, since the pixel data transfer clock signal is transmitted together with the image data from the first control unit to the second control unit, noise is mixed in the pixel data transfer clock signal. However, there is a problem that it is difficult to receive image data with high accuracy.

  Accordingly, an object of the present invention is to obtain an image forming apparatus and a program capable of reducing the influence of noise mixed in a pixel data transfer clock signal.

  The present invention provides a first control unit that outputs image data and an image data effective region signal indicating an effective region of the image data, a second control unit that outputs a memory input shift clock, and the first control Receiving the image data and the image data valid area signal from the communication unit via a communication line, and indicating that the image data valid area signal is a valid area, A first circuit that outputs the image data, and the image data valid area signal from the first control unit via a communication line and the memory input shift clock from the second control unit, and the image A second circuit for outputting a second signal of the same data string as the memory input shift clock in a state in which the data valid area signal indicates that it is a valid area; And the first signal as a D input signal. When the second signal changes from a low level to a high level, the D signal is sent to the second control unit. And a D-type flip-flop circuit that outputs data of an input signal.

  According to the present invention, since it is not necessary to transmit the pixel data transfer clock signal from the first control unit to the second control unit, it is possible to avoid an influence caused by noise mixed in the pixel data transfer clock signal. can do.

FIG. 1 is a schematic diagram showing the overall configuration of an image forming apparatus according to an embodiment of the present invention. FIG. 2 is a plan view showing a schematic configuration inside the exposure unit of the image forming apparatus according to the embodiment of the present invention. FIG. 3 is a side view of a polygon motor and a polygon mirror included in the exposure device according to the embodiment of the present invention. FIG. 4 is a plan view showing a schematic configuration of the operation display unit of the image forming apparatus according to the embodiment of the present invention. FIG. 5 is a block diagram showing a schematic configuration of a control unit of the image forming apparatus according to the embodiment of the present invention. FIG. 6 is a block diagram showing a circuit configuration for processing image data by the controller control unit of the image forming apparatus according to the embodiment of the present invention. FIG. 7 is an explanatory diagram illustrating data output from the circuit of FIG. FIG. 8 is a diagram showing a schematic configuration of a receiving circuit included in the image forming apparatus according to the embodiment of the present invention. FIG. 9 is a diagram illustrating a timing chart of signals of respective units of the image forming apparatus according to the embodiment of the present invention.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, the image forming apparatus 1 according to the present embodiment includes an electrophotographic process unit for each color of black (Bk), magenta (M), cyan (C), and yellow (Y) along a transfer belt 10. All-in-one cartridges (hereinafter simply referred to as cartridges) 11Bk, 11M, 11C, and 11Y are arranged as a so-called tandem type image forming apparatus.

  The endless transfer belt 10 rotates counterclockwise in FIG. A plurality of cartridges 11 </ b> Bk, 11 </ b> M, 11 </ b> C, and 11 </ b> Y are arranged in order from the upstream side in the rotation direction of the transfer belt 10 so as to face the outer peripheral surface of the transfer belt 10. The cartridge 11Bk forms a black image, the cartridge 11M forms a magenta image, the cartridge 11C forms a cyan image, and the cartridge 11Y forms a yellow image. The plurality of cartridges 11Bk, 11M, 11C, and 11Y have the same internal configuration although the colors of the toner images to be formed are different. Therefore, in the following description, the cartridge 11Bk will be mainly described with respect to the portions common to the plurality of cartridges 11Bk, 11M, 11C, and 11Y, the common portions are given common reference numerals, and the other cartridges 11M, 11C, and 11Y are described. Detailed explanation is omitted.

  The transfer belt 10 is wound around a secondary transfer driving roller 20 as a main driving roller that is rotationally driven and a transfer belt tension roller 21 as a driven roller. The secondary transfer drive roller 20 is rotationally driven by a drive motor (not shown). The drive motor, the secondary transfer drive roller 20, and the transfer belt tension roller 21 correspond to a rotary mechanism (moving mechanism) that rotates the transfer belt 10. In the present embodiment, the toner mark sensor 22 and the transfer belt cleaner 23 are provided to face the outer peripheral surface of the transfer belt 10.

  The cartridge 11Bk includes a paddle 12Bk, a photoconductor 16Bk, a charger 17Bk, an exposure device 19, a developing device 14Bk, a supply roller 13Bk, a developing blade 15Bk, a cleaner blade 18Bk, and the like. The paddle 12Bk stirs the toner. The charger 17Bk is disposed around the photoreceptor 16Bk. The supply roller 13Bk supplies toner to the developing device 14Bk. The exposure unit 19 also includes black laser light LBk, magenta laser light LM, cyan laser light LC, and yellow laser light that are exposure light corresponding to the image colors formed by the cartridges 11Bk, 11M, 11C, and 11Y. Irradiate LY.

  At the time of image formation, the outer peripheral surface of the photoreceptor 16Bk is uniformly charged by the charger 17Bk in the dark, and then exposed by the laser beam LBk corresponding to the black image from the exposure unit 19. Thereby, an electrostatic latent image is formed on the outer peripheral surface of the photoconductor 16Bk. The developing device 14Bk visualizes the electrostatic latent image with black toner. As a result, a black toner image is formed on the photoreceptor 16Bk. The toner image is transferred onto the transfer belt 10 by the action of the primary transfer roller 24Bk at a position (primary transfer position) where the photoreceptor 16Bk and the transfer belt 10 are in contact with each other. In this way, a black toner image is formed on the transfer belt 10.

  After the toner image transfer is completed, the photoreceptor 16Bk waits for the next image formation after unnecessary toner remaining on the outer peripheral surface is wiped off by the cleaner blade 18Bk. The waste toner is sent to the waste toner box 27. The waste toner in the waste toner box 27 is replaced with a new waste toner box 27 when the waste toner full detection sensor 28 detects fullness.

  The portion of the transfer belt 10 to which the black toner image is transferred by the cartridge 11Bk moves to a position corresponding to the next cartridge 11M as the transfer belt 10 rotates. The magenta toner image is superimposed and transferred onto the black toner image by the same process. Further, the portion of the transfer belt 10 to which the black and magenta toner images are superimposed and transferred sequentially moves to a position corresponding to the cartridges 11C and 11Y. Then, cyan and magenta toner images are superimposed and transferred to the portion. In this way, a full-color superimposed image is formed on the transfer belt 10. The portion of the transfer belt 10 where the full-color superimposed image is formed moves to a position corresponding to the secondary transfer roller 32.

  When only black is printed, the primary transfer roller 24M, the primary transfer roller 24C, and the primary transfer roller 24Y of the other colors are spaced apart from the photoconductor 16M, the photoconductor 16C, and the photoconductor 16Y, respectively. The image forming process described above is performed only for black.

  Regarding the conveyance of the paper 26, the paper 26 positioned on the top of the papers 26 stored in the paper feed tray 25 is sent out by rotating the paper feed roller 29 counterclockwise. Then, by detecting the paper 26 by the sensor 30 and controlling the timing to stop the rotation of the paper feed roller 29, the paper 26 can be put on standby at a position corresponding to the registration roller 31. Next, at the timing when the position of the toner image and the paper 26 overlaps on the secondary transfer roller 32, the driving of the paper feed roller 29 and the registration roller 31 is started, and the paper 26 is sent out. The rotation of the paper feed roller 29 and the registration roller 31 is stopped based on the non-detection of the paper 26 by the sensor 30.

  The toner image on the transfer belt 10 is transferred to the paper 26 sent out by the registration roller 31 by the secondary transfer roller 32, and the toner image is fixed to the paper 26 by heat and pressure by the fixing device 33. Then, the paper 26 is discharged outside the image forming apparatus 1 by a paper discharge roller 35 that is driven to rotate.

  When duplex printing is performed, immediately after the trailing edge of the paper 26 passes through the paper discharge sensor 34, the paper discharge roller 35 is stopped and rotated counterclockwise. As a result, the paper 26 is conveyed to the double-sided conveyance path provided on the further right side in FIG. The sheet 26 conveyed to the duplex conveyance path is conveyed again to the registration roller 31 via the duplex roller 36.

  In the secondary transfer roller 32, the toner image is transferred to the surface of the paper 26 opposite to the surface on which the toner image has already been transferred, and the toner image is fixed by the fixing device 33 with heat and pressure. Then, the paper 26 is discharged to the outside of the image forming apparatus 1 by a paper discharge roller 35 that is driven to rotate clockwise. Note that the timing of passing through the double-sided roller 36 is detected by a double-sided sensor 37.

  In addition, a control unit 38 is constructed inside the casing by electronic components (not shown) such as elements mounted on the substrate. The control unit 38 executes image data processing of the image forming apparatus 1, engine control, control of the operation display unit 39 on which an operator performs various input operations, and the like.

  2 is a plan view showing a schematic configuration inside the exposure unit 19, and FIG. 3 is a side view of a polygon motor and a polygon mirror included in the exposure unit 19. As shown in FIG.

  The exposure unit 19 is a unit for writing image information on the photosensitive member in the form of a set of light spots by raster scanning of laser light. The exposure device 19 has a laser light source such as a semiconductor laser light source.

  As shown in FIG. 2, the polygon mirror 54 has a regular polygonal shape (regular hexagonal shape in the present embodiment) in a plan view, and has an upper side surface 54a and a lower side surface 54b as shown in FIG. It has a two-stage configuration. The polygon mirror 54 is controlled by a polygon motor 65 so as to rotate at a constant rotational speed in a constant rotational direction. The rotation speed is determined by the rotation speed of the photosensitive member, the writing speed, the number of surfaces of the polygon mirror 54, and the like.

  The laser beams LBk and LY from the black light source unit 50 and the yellow light source unit 52 enter the lower side surface 54b of the polygon mirror 54, are deflected by the rotation of the polygon mirror 54, pass through the fθ lenses 55 and 56, It is folded by one mirror 58, 60 and exposed to the photoreceptors 16Bk, 16Y (FIG. 1). The laser beams LM and LC from the magenta light source unit 51 and the cyan light source unit 53 enter the upper side surface 54a of the polygon mirror 54, are deflected by the rotation of the polygon mirror 54, and pass through the fθ lenses 55 and 56. The second mirrors 57 and 59 are folded back and exposed to the photoconductors 16M and 16C (FIG. 1). Referring to FIG. 2, it can be understood that the laser beams LBk, LM, LC, and LY are scanned on the photoreceptors 16Bk, 16M, 16C, and 16Y as the polygon mirror 54 rotates. In the present embodiment, the main scanning direction SD of the laser beams LBk and LM and the main scanning direction SD of the laser beams LY and LC are opposite to each other.

  A first cylinder mirror 61 and a first synchronization sensor 63 are arranged corresponding to the end portions of the black and magenta laser beams LBk and LM in the main scanning direction, and the main laser beams LY and LC of yellow and cyan are arranged. A second cylinder mirror 62 and a second synchronization sensor 64 are arranged corresponding to the end portion in the scanning direction. Laser light reflected by the first and second cylinder mirrors 61 and 62 through the fθ lenses 55 and 56 respectively enters the first and second synchronization sensors 63 and 64. That is, the first and second synchronization sensors 63 and 64 function as synchronization sensors.

  The control unit 38 performs lighting control of the light source units 50 and 51 using at least one of the detection signals of the laser beams LBk and LM incident on the first synchronization sensor 63. Further, the control unit 38 performs lighting control of the light source units 52 and 53 using at least one of the detection signals of the laser beams LY and LC incident on the second synchronization sensor 64. That is, the control unit 38 uses the start-side synchronization detection signal generated based on the detection results of the first and second synchronization sensors 63 and 64, and the number of rotations of the polygon mirror 54 and one line formed on each photoconductor. Synchronize. Then, this operation is sequentially repeated, so that the image formed line by line becomes one image as a whole and is formed on each photoconductor.

  As shown in FIG. 4, the operation display unit 39 includes an operation input key 67 for receiving various operation information by the user, a liquid crystal display screen 68 for displaying various work screens and information for the user, An LED 69 is provided for notifying the user of various modes, device states, and warnings. The operation display unit 39 is controlled by the controller control unit 70 (FIG. 5) of the control unit 38.

  As shown in FIG. 5, the control unit 38, for example, image data of each color of black, magenta, cyan, and yellow of document data input from an external personal computer (or image data input from a scanner). Is transmitted from the controller control unit 70 to the engine control unit 80 via the communication line 90.

  The control unit 38 includes a controller control unit 70 as a first control unit, and an engine control unit 80 as a second control unit for outputting image data to the LD corresponding to each color.

  A controller control unit 70 that executes image data processing and other input / output control includes a CPU (Central Processing Unit) 71, a RAM (Random Access Memory) 72, a ROM (Read Only Memory) 73, an image data input interface (I). / F) 74, an input / output interface 75, a bus 76, and the like. The CPU 71 performs various control processes when transmitting each image data to the engine control unit 80. The RAM 72 is a memory for temporarily storing each image data and various information to be controlled. The ROM 73 stores a program indicating a procedure for performing various control processes. The image data input interface 74 performs processing for inputting image data from the outside. The input / output interface 75 exchanges various signals including image data. The bus 76 exchanges data between the respective units in the controller control unit 70.

  The engine control unit 80 includes a CPU 81, a RAM 82, a ROM 83, an input / output interface 84, a bus 85, and the like. The CPU 81 performs various control processes when receiving and printing each image data from the controller control unit 70. The RAM 82 is a memory that temporarily stores a work area for performing various control processes and each image data. The ROM 83 stores a program indicating a procedure for the CPU 81 to perform various control processes. The input / output interface 84 exchanges various signals including image data with the controller control unit 70. The bus 85 exchanges data between each unit in the engine control unit 80.

  In the image forming apparatus 1, the controller control unit 70 and the engine control unit 80 are connected via a communication line 90, and various types of data including image data are exchanged via the communication line 90. . Signals transmitted from the controller control unit 70 to the engine control unit 80 include an image data effective area signal, a vertical image effective area signal for each color, and image data for each color. On the other hand, signals transmitted from the engine control unit 80 to the controller control unit 70 include a reference horizontal direction synchronization signal, image data vertical direction image effective area signal of each color, and the like. The reference horizontal direction synchronization signal serves as a reference for transmission / reception timing of all other signals.

  The circuit shown in FIG. 6 is configured as hardware, for example, at the subsequent stage of the controller control unit 70. Note that the same function as the circuit shown in FIG. 6 can be realized by software. As shown in FIG. 6, the image data input from the image data input interface 74 to the controller control unit 70 is color-matched by the color matching conversion circuit 100 and then input to the γ conversion circuit 101. The γ conversion circuit 101 converts the image data into image data that matches the input / output characteristics of the image forming apparatus 1 and inputs the image data to the data depth switching mechanism unit 102.

  In the data depth switching mechanism unit 102, the parallel image data is converted to a predetermined quantization level (three types in the present embodiment) by the first switch (SW). Specifically, the γ conversion circuit 101 outputs 8-bit data (see FIG. 7A), the 4-bit conversion circuit 103 outputs 4-bit data (see FIG. 7B), The binarization circuit 104 converts the input 8-bit multi-value data into binary data according to a preset threshold value and outputs it as 1-bit data (see FIG. 7C). In addition, the dither circuit 105 outputs 1-bit data (see FIG. 7C) for creating an area gradation. That is, the difference between the data output from the binarization circuit 104 and the data output from the dither circuit 105 is the presence or absence of area gradation processing. Then, one of the four data types is selected by the first switch and the second switch (SW), and data 0 to data 7 is output. The switching of the first switch and the second switch (SW) is controlled by the controller control unit 70 so as to correspond to the format of data that is input to the preset circuit and sent to the engine control unit 80.

  The CPU 81 of the engine control unit 80 controls the oscillation of the semiconductor lasers of the light source units 50 to 53 of the exposure unit 19 and controls the polygon motor 65 based on the signals detected by the first and second synchronization sensors 63 and 64. I do. The CPU 81 of the engine control unit 80 performs drive control of the photoreceptors 16Bk, 16M, 16C, and 16Y, voltage control of the chargers 17Bk, 17M, 17C, and 17Y, and the cleaner blades 18Bk, 18M, 18C, and 18Y. The CPU 81 of the engine control unit 80 performs voltage control of the developing devices 14Bk, 14M, 14C, and 14Y, the supply rollers 13Bk, 13M, 13C, and 13Y, the developing blades 15Bk, 15M, 15C, and 15Y. The CPU 81 of the engine control unit 80 performs voltage control of the primary transfer rollers 24Bk, 24M, 24C, and 24Y at a position (primary transfer position) where the photoconductors 16Bk, 16M, 16C, and 16Y are in contact with the transfer belt 10. . Further, the CPU 81 of the engine control unit 80 conveys the transfer belt 10 on which the full-color superimposed image is formed to the position of the secondary transfer roller 32, and outputs the toner image to the paper 26 at the timing when the position of the toner image and the paper 26 overlap. Current control and voltage control on the secondary transfer roller 32 for transferring are performed. Further, the engine control unit 80 controls a paper feeding operation by the registration roller 31 by controlling a motor, a clutch, a solenoid (all not shown) and the like.

  The input / output interface 84 is provided with a receiving circuit 110 shown in FIG. The receiving circuit 110 is provided for each color and each bit of input data (maximum 8 bits as shown in FIG. 7 in this embodiment). Therefore, in this embodiment, 4 × 8 = 32 reception circuits 110 are provided as an example. The receiving circuit 110 is configured as hardware as an example, and includes first and second OR gate circuits 111 and 112 and a D-type flip-flop circuit 113. Note that the same function as that of the reception circuit 110 can be realized by software.

  The reception circuit 110 includes a first OR gate circuit 111 as a first circuit, a second OR gate circuit 112 as a second circuit, and a D-type flip-flop circuit 113. The first signal as the output of the first OR gate circuit 111 and the second signal as the second OR gate circuit are input to the D-type flip-flop circuit 113.

  The first OR gate circuit 111 calculates the logical sum of the image data input from the controller control unit 70 and the image data valid area signal. That is, the first OR gate circuit 111 outputs a high level (H) signal as the first signal when at least one of the image data and the image data effective area signal is at a high level (H). When both are at the low level (L), a low level (L) signal is output as the first signal. In this embodiment, the low level (L) of the image data valid area signal is the valid area (asserted). Therefore, when the image data effective area signal is an effective area, the first signal as the output of the first OR gate circuit 111 is the same data string as the image data as shown as FF-D input in FIG. Similar to the change of the signal, that is, the high level (H) and low level (L) of the image data, the level changes and the frequency (cycle) becomes the same signal. However, the first signal is slightly delayed with respect to the image data. On the other hand, when the image data valid area signal is an invalid area (negate), that is, at a high level (H), the first signal as the output of the first OR gate circuit 111 is at a high level (H). It becomes a constant signal.

  On the other hand, the second OR gate circuit 112 calculates the logical sum of the image data valid area signal and the memory input shift clock generated in the engine control unit 80. That is, the second OR gate circuit 112 outputs a high level (H) signal as the second signal when at least one of the image data effective area signal and the memory input shift clock is at the high level (H). When both are at the low level (L), a low level (L) signal is output as the second signal. As described above, in this embodiment, the low level (L) of the image data effective area signal is the effective area (asserted). Therefore, when the image data valid area signal is the valid area, the second signal as the output of the second OR gate circuit 112 is the same data as the memory input shift clock as shown as FF-CLK input in FIG. Similar to the change in the signal of the column, that is, the high level (H) and low level (L) of the memory input shift clock, the signal changes in level and has the same frequency (period). However, the second signal is slightly delayed with respect to the memory input shift clock. On the other hand, when the image data valid area signal is an invalid area (negate), that is, at a high level (H), the second signal as the output of the second OR gate circuit 112 is at a high level (H). It becomes a constant signal.

  As described above, when the image data valid area signal is in the valid area (low level, L), the first signal of the same data string as the image data is input to the D input terminal of the D flip-flop circuit 113. When the image data valid area signal is in the invalid area (high level, H), a constant signal is input at the high level (H). Here, in the D-type flip-flop circuit 113, the signal input to the CLK input terminal (clock input signal, in this embodiment, as an example, the second signal, the FF-CLK input in FIG. 9) is low level (L ) To the high level (H), the data inputted and held from the D input terminal (in this embodiment, as an example, the first signal, that is, the data of the FF-D input in FIG. 9) The output is maintained until the signal input to the CLK input terminal changes from the low level (L) to the high level (H) next time. Therefore, in this embodiment, as shown in FIG. 9, when the image data valid area signal is the valid area (low level, L), Q output of the same data string as the image data is obtained, and this Q output is The image data is input to the CPU 81 of the engine control unit 80. That is, in the present embodiment, a signal having the same waveform (profile) as the image data is taken into the engine control unit 80 in accordance with the memory input shift clock generated by the engine control unit 80. Therefore, according to the present embodiment, the same signal as the level change (profile) of the input signal of the image data is obtained without sending the pixel data clock signal from the controller control unit 70 to the engine control unit 80. On the other hand, when the signal input to the CLK input terminal (clock input signal, in this embodiment, as an example, the second signal, the FF-CLK input in FIG. 9) is constant, the output of the D-type flip-flop circuit 113 The signal becomes a constant signal at a high level (H), for example. Note that the frequency of the memory input shift clock is set to at least twice the frequency of the image data, and preferably set to an integer multiple (however, twice or more).

  The receiving circuit 110 can also be configured by a program that operates the engine control unit 80. In this case, in the image forming apparatus, when the user turns on the power, the OS (operating system) is read into the RAM 82 from the ROM 83 or the hard disk (not shown), and the OS is activated by the CPU 81. The activated OS reads an application program from the ROM 83, a hard disk (not shown) or the like into the RAM 82 in response to a user operation, and starts up, reads or saves information. In addition, the application program is not limited to one that runs on a predetermined OS, but may be one that causes the OS to execute a part of various processes described later, or constitutes a predetermined application program or OS. It may be included as part of a group of program files.

  The application program installed on the hard disk or the like is recorded on a storage medium such as a CD-ROM (not shown), and the application program recorded on the storage medium is installed on the hard disk or the like. That is, a portable storage medium such as a CD-ROM can be a storage medium for storing an application program. Furthermore, the application program may be imported from the outside via, for example, a communication interface (not shown) with the outside and installed on a hard disk or the like.

  The CPU 81 can function as the receiving circuit 110 shown in FIG. 8 by executing an application program held in the RAM 82. In this case, the program includes modules that cause the CPU 81 to operate as the first OR gate circuit 111, the second OR gate 112, and the D-type flip-flop circuit 113.

  As described above, the image forming apparatus 1 according to the present embodiment operates with the memory input shift clock generated by the engine control unit 80 and outputs a signal having the same data string as the image data from the controller control unit 70. A receiving circuit 110 including a D-type flip-flop circuit 113 is provided. For this reason, since it is not necessary to use the pixel data clock signal transmitted via the communication line 90 as in the above-described prior art, it is possible to suppress the occurrence of communication failure due to noise mixed in the pixel data clock signal. be able to. In addition, the receiving circuit 110 can obtain a filtering effect and the like. Furthermore, since the signal of the same data string as the image data is output only when the image data valid area signal is the valid area, it is possible to prevent erroneous data input to the engine control unit 80 when the image data is the invalid area. can do.

  In the present embodiment, the second OR gate circuit 112 is provided before the clock input signal of the receiving circuit 110 is input. Therefore, the timing for capturing the image data can be delayed by the time required to pass through the second OR gate circuit 112. As a result, the second OR gate circuit 112 sends the image data to the engine control unit 80. The timing for capturing can be adjusted more easily.

  In this embodiment, the period of the image data and the memory input shift clock as the clock input signal for each period in which the image data effective area signal becomes the effective area (asserted) (that is, in the vertical image effective area unit). The period can be changed. By doing so, it is possible to increase the processing amount of the image data per unit time according to the situation and to improve the image processing efficiency. The cycle can be set by operating the operation display unit 39 or the like. In this case, data indicating the set cycle is transmitted from the controller control unit 70 to the engine control unit 80 via the communication line 90 at an appropriate timing, and stored in a storage unit such as the RAM 82.

  Further, the period of the image data and the period of the clock input signal can be variably set by the operation of the controller control unit 70, for example. That is, the CPU 71 of the controller control unit 70 receives data input by the operation of the operation display unit 39 by the user, determines (variably sets) the cycle of image data corresponding to the data, and uses the cycle (frequency). Image data in which values (levels) are arranged is generated. In this case, the CPU 71 preferably stores the determined cycle (or frequency) of the image data in a nonvolatile memory (NV-RAM, hard disk, etc.). Further, the CPU 71 transmits data indicating the cycle of the clock input signal to the engine control unit 80 via the input / output interface 75, the communication line 90, the input / output interface 84, and the like. The engine control unit 80 determines the shift clock cycle based on the received data, and generates a clock input signal at the cycle. That is, in the present embodiment, the CPU 71 corresponds to a cycle setting control unit (frequency setting control unit).

  The operations of the controller control unit 70 and the engine control unit 80 can be obtained by a program that causes the CPU 71 and the CPU 81 to operate. In this case, the program for the CPU 71 includes a module for operating the CPU 71 as at least a cycle setting control unit.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments, and various modifications can be made. For example, the signal waveform (high level, low level, assert, negate setting) is not limited to the above embodiment. In addition, another gate circuit can be provided as the gate circuit. In addition, the configuration of the receiving circuit can be changed as appropriate.

1 Image forming apparatus 70 Controller control unit (an example of a first control unit)
71 CPU (an example of a cycle setting control unit)
80 engine control unit (an example of a second control unit)
90 communication line 111 first OR gate circuit (example of first circuit)
112 Second OR gate circuit (an example of a second circuit)
113 D-type flip-flop circuit

JP 2009-172999 A

Claims (4)

A first control unit for outputting image data and an image data effective area signal indicating an effective area of the image data;
A second control unit for outputting a memory input shift clock;
Same as the image data in a state where the image data and the image data valid area signal are received from the first control unit via a communication line and the image data valid area signal indicates the valid area. A first circuit for outputting a first signal of the data string;
Receiving the image data valid area signal from the first control unit via a communication line and receiving the memory input shift clock from the second control unit, and confirming that the image data valid area signal is a valid area. A second circuit for outputting a second signal of the same data string as the memory input shift clock in the state shown in FIG.
When the second signal is received as a clock input signal and the first signal is received as a D input signal, and the second signal changes from a low level to a high level, the second signal is directed to the second control unit. A D-type flip-flop circuit for outputting the data of the D input signal;
An image forming apparatus comprising: The low level of the image data effective area signal indicates the effective area,
The first circuit is a first OR gate circuit that performs a logical sum of the image data and the image data effective area signal,
The image forming apparatus according to claim 1, wherein the second circuit is a second OR gate circuit that performs a logical sum of the memory input shift clock and the image data effective area signal.   The image forming apparatus according to claim 1, further comprising a cycle setting control unit configured to variably set the cycle of the image data and the cycle of the memory input shift clock. On the computer,
Outputting image data and an image data effective area signal indicating an effective area of the image data from the first control unit;
Outputting a memory input shift clock from the second control unit;
Same as the image data in a state where the image data and the image data valid area signal are received from the first control unit via the communication line and the image data valid area signal indicates the valid area. Outputting a first signal of the data sequence;
The image data effective area signal is received from the first control unit via the communication line and the memory input shift clock is received from the second control unit, and the image data effective area signal is an effective area. Outputting a second signal of the same data string as the memory input shift clock in a state shown in FIG.
When the first signal and the second signal are received and the second signal changes from a low level to a high level, the data of the first signal is output to the second control unit Step to do,
A program that executes

Images