JP2012094929A - Semiconductor memory and method of manufacturing thereof - Google Patents

Abstract

A semiconductor memory structure is simplified and a manufacturing process is simplified.
A semiconductor memory having a semiconductor substrate and first and second source regions 104 and 109 formed in the semiconductor substrate and extending in first and second directions orthogonal to each other. Each of the first and second source regions is a diffusion region and is electrically connected at an intersecting portion. In addition, the semiconductor memory includes a bit line 108 extending in the same direction as the second source region 109 and a source line formed on the second source region 109, and the source line and the second source region 109. And the contact between the bit line 108 and the drain region formed in the semiconductor substrate are arranged in a straight line.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor memory, and more particularly to a technique that enables a simplified structure of a nonvolatile semiconductor memory device and a simplified manufacturing process.

  A flash memory, which is one of semiconductor memories, is a kind of electrically rewritable ROM, and is a nonvolatile semiconductor memory device that is widely used in mobile phones, digital still cameras, communication network devices, and the like. Flash memory is roughly classified into NOR type and NAND type. Among these, NOR type flash memory is generally capable of random access and has a higher reading speed than NAND type flash memory. In order to further improve the characteristics, various proposals have been made regarding the wiring structure arranged in the memory cell array (see, for example, Patent Document 1).

  FIG. 1 is a schematic diagram for explaining a configuration example of a conventional NOR flash memory. FIG. 1 (a) is a top view of a part of the flash memory, and FIG. 1 (b) is FIG. FIG. 1C is a cross-sectional view taken along the line AA ′, and FIG. 1C is a view for explaining the state of the gate line near the source contact.

  Referring to FIG. 1B, a plurality of diffusion regions (active regions) 18 extending in the vertical direction (Y direction) are formed on the main surface of the silicon semiconductor substrate 10. 1A and 1C schematically show the diffusion region 18. These diffusion regions 18 are spaced apart in the lateral direction (X direction). In each diffusion region 18, the drain region 11 is periodically formed. The portion indicated by reference numeral 18 also indicates a bit line formed of a wiring layer obtained by patterning a metal such as aluminum. The bit line 18 is electrically connected to the drain region 11 via the drain contact 15.

  A plurality of word lines (gate lines) 17 extending in the horizontal direction (X direction) are formed on the semiconductor substrate 10. The word line 17 includes a gate electrode 13. Under the gate electrode 13, a floating gate 20 formed on a tunnel oxide film formed on the semiconductor substrate 10 and an insulating film ONO (oxide-nitride-oxide) 21 formed thereon are formed. ing. The gate electrode 13 is formed on the insulating film ONO21.

  Between the word lines 17 adjacent in the vertical direction, a source region 14 extending in the horizontal direction is formed. The source region 14 is formed of a diffusion region 12 formed on the surface of the semiconductor substrate 10 as shown in FIG. Since the source region 12 is set to a reference potential Vss (for example, ground), it is also referred to as a Vss line. A source line 19 extending in the vertical direction of the semiconductor substrate 10 is formed for each of a plurality of (for example, 8 or 16) bit lines 18. The source line 19 is a wiring layer obtained by patterning a metal such as aluminum. The source line 19 is electrically connected to the source region 14 via the source contact 16.

JP 2002-1000068 A

  However, the NOR type flash memory having the conventional structure as shown in FIG. 1 has the following problems.

  First, in order to secure a sufficient space necessary for providing the source contact 16, it is necessary to form the gate line 17 in the vicinity of the source contact 16 by bending it.

  Second, in order to secure a space for forming the source contact 16, the geometrical arrangement of the drain contact 15 and the source contact 16 when viewed from the top view (FIG. 1A) is different. When the cycle in the Y direction of these contacts 15 and 16 is L, the source contact 16 and the drain contact 15 are shifted by a half cycle (L / 2).

  Third, as shown in FIG. 1C, the distance C between the wiring layers 18 that connect the drain contacts 15, the wiring layer 19 that connects the source contacts 16, and the wiring layer 18 that connects the drain contacts 15. When the distance D is compared with the distance D, it is necessary to satisfy C <D, and a relatively large dead space is formed in the vicinity of the source contact 16.

Fourth, the diameter d ₁ of the source contact 16 and the diameter d ₂ of the drain contact 15 ′ adjacent thereto and d ₃ of the other drain contacts 15 are different (d ₁ > d ₃ > d ₂ ), and The shape can also be different. For this reason, it is necessary to acquire OPC (Optimum Write Power Control) data for each of these contacts.

  The present invention has been made in view of such a problem, and an object thereof is to realize simplification of the structure of a semiconductor memory and simplification of a manufacturing process.

  The present invention is a semiconductor memory having a semiconductor substrate and first and second source regions formed in the semiconductor substrate and extending in first and second directions orthogonal to each other. Since the source region extending in the vertical and horizontal directions on the surface portion of the semiconductor substrate is formed, a degree of freedom is formed in forming the source contact, and the structure of the semiconductor memory and the manufacturing process can be simplified.

  In the semiconductor memory, preferably, the first and second source regions are diffusion regions, and are electrically connected at intersecting portions. Preferably, the first and second source regions each have a linear region. The semiconductor memory includes a drain region formed in the semiconductor substrate, a bit line extending in the same direction as the second source region, and a source line formed on the second source region. Preferably, the contact between the source line and the second source region and the contact between the bit line and the drain region formed in the semiconductor substrate are arranged in a straight line. Further, it is preferable that the bit lines are disposed on both sides of the second source region. The distance between the source line and the bit line adjacent to the source line is preferably smaller than the distance between adjacent bit lines. The semiconductor memory preferably has a linear word line extending in the same direction as the first source region, and the first source region is disposed between adjacent word lines. The word line may include a gate electrode formed on the semiconductor substrate. The first and second source regions are diffusion regions formed in separate diffusion processes. Further, the semiconductor memory is, for example, a NOR type flash memory having a floating gate.

  The present invention also includes forming a first source region extending in a first direction in a semiconductor substrate, and a second source region extending in a second direction orthogonal to the first direction. Forming a semiconductor memory. This manufacturing method preferably includes a step of forming a floating gate and a gate electrode after forming the second source region.

  In the present invention, since the source line is formed by two diffusion regions extending in the vertical and horizontal directions (X direction and Y direction when the substrate surface is an XY plane), the curved portion of the gate line (word line) Thus, there is provided a technique capable of simplifying the structure of the semiconductor memory device and simplifying the manufacturing process.

It is the schematic for demonstrating the structure of the conventional NOR type flash memory, (a) is a top view of the partial area | region of this flash memory, (b) is sectional drawing which follows the AA 'line in (a). (C) is a diagram for explaining the state of the gate line in the vicinity of the source contact. BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic for demonstrating the structure of the NOR type flash memory of this invention, (a) is a top view of a partial area | region of this flash memory, (b) is a cross section in alignment with the BB 'line in (a). FIGS. 4A and 4C are diagrams for explaining the state of the gate line in the vicinity of the source contact. FIG. 5 is a diagram for explaining a manufacturing process of a flash memory according to the present invention, and shows each process from STI (Shallow Trench Isolation) formation to vertical source line and floating gate formation. It is a figure for demonstrating the manufacturing process of the flash memory of this invention, and shows each process from gate formation to horizontal source line formation. It is a figure for demonstrating the manufacturing process of the flash memory of this invention, and shows each process from contact formation to wiring layer formation. 3 is a flowchart for explaining a manufacturing process of the flash memory according to the present invention.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  In the present invention, the second source line (wiring layer) having the above-described conventional configuration is formed in the diffusion region. That is, in the semiconductor memory of the present invention, two diffusion regions extending in the horizontal direction and the vertical direction are provided, and the gate line (word line) can be formed without being bent.

  FIG. 2 is a diagram for explaining a configuration example of a semiconductor memory device according to the present invention. Here, it is assumed that the semiconductor memory device is a NOR flash memory. 2A is a top view of a part of the flash memory, FIG. 2B is a cross-sectional view taken along the line BB ′ in FIG. 2A, and FIG. 2C is the vicinity of the source contact. It is a figure for demonstrating the mode of this gate line. The cross-sectional view taken along the line AA ′ shown in FIG. 1B is the same in this embodiment.

  Referring to FIG. 2B, a diffusion region (active region) 102 extending in the vertical direction (Y direction) is formed on the main surface of the silicon semiconductor substrate 100. The diffusion region 102 is a source region (second source region) and constitutes a source line 109. The source line 109 replaces 19 formed by the metal wiring layer described above. The source line 109 is provided for each of a plurality of (for example, 8 or 16) bit lines 108. The source line 109 intersects the source line 104 formed by a diffusion region (first source region) extending in the X direction. That is, the diffusion region 102 of the source line 109 and the diffusion region of the lateral source line 104 (corresponding to the diffusion region 12 of FIG. 1B) intersect. In the intersecting diffusion region portions, the source lines 109 and 106 are electrically connected to have the same potential. The source line 109 is electrically connected to a wiring layer formed of a metal such as aluminum, which will be described later, via the source contact 106.

  The bit line 108 is a wiring layer formed of a metal such as aluminum. A diffusion region is formed on the surface of the semiconductor substrate 100 located below the bit line 108. In this diffusion region, drain regions 11 are periodically formed. The bit line 108 is electrically connected to the drain region via the drain contact 105.

  A plurality of word lines (gate lines) 107 extending in the horizontal direction (X direction) are formed on the semiconductor substrate 100. The word line 107 includes a gate electrode 103. Under the gate electrode 103, a floating gate 120 formed on a tunnel oxide film on the semiconductor substrate 100 and an insulating film ONO 121 formed thereon are formed. The gate electrode 103 is formed on the insulating film ONO121.

  In the flash memory having such a configuration, two vertical and horizontal source lines 104 and 109 formed as diffusion regions in the crystal of the semiconductor substrate 100 without using a wiring layer provided on the main surface of the semiconductor substrate 100. Is formed. This eliminates the need to provide the source contact 106 on the source line 104 in the X direction, can secure a space for forming the source contact 106 without bending the gate line (word line) 107, and reduce the area of the memory cell. Is possible.

  Further, since it is not necessary to provide the source contacts 106 on the source line 104 in the X direction, the same arrangement can be achieved without shifting the arrangement period of the drain contacts 105 and the source contacts 106. That is, it is possible to make the arrangement interval of the source contacts 106 in the Y direction equal to the arrangement interval of the drain contacts 105 in the Y direction, and arrange the source contacts 106 on a straight line connecting a plurality of the drain contacts 105 in the X direction. It becomes. Furthermore, the diameter of the source contact 106, the diameter of the drain contact 105 ′ to be provided adjacent thereto, and the diameters (and their shapes) of the other drain contacts 105 can be designed to be equal.

  Further, as shown in FIG. 2C, the interval B between the source line 109 for connecting the source contact 106 and the bit line (wiring layer) 108 adjacent thereto is set as the bit line 108 for connecting the drain contact 105. It is possible to lay out so as to be equal to or less than the mutual interval A. Further, since the s-curved portion of the gate line 107 is eliminated, it is easy to align the mask when forming the source line by ion implantation.

  As described above, the structure of the semiconductor memory device of the present invention in which the source line is formed by two vertical and horizontal diffusion regions is greatly simplified, and the manufacturing process thereof is also simplified. An example of the method for manufacturing the semiconductor memory of Example 1 will be described in detail in Example 2.

  3 to 6 are diagrams for explaining the manufacturing process of the flash memory in this embodiment. FIG. 3 shows from STI (Shallow Trench Isolation) formation to vertical source line 109 and floating gate formation, and FIG. FIG. 5 shows each process from the formation of the source line 104 in the lateral direction to the formation of the lateral source line, and FIG. 5 is a flowchart of these processes.

  3 to 5, the left diagram is a schematic top view, the upper right diagram is a schematic sectional view taken along the line EE ′ in the left diagram, and the lower right diagram is a line FF ′ in the left diagram. FIG. 4B is a schematic cross-sectional view taken along the line GG ′.

  First, referring to FIG. 3A, one main surface of the silicon semiconductor substrate 100 is provided with STI in which the surface of the silicon semiconductor substrate 100 is etched and filled with an insulator 110. Is exposed in a striped manner extending in the vertical direction of the left figure. Such STI formation is performed by a known photolithography technique, etching technique, and gap fill technique (step S101). The STI is provided because the STI element isolation is effective for reducing the size of the memory cell.

  Of the surface of the semiconductor substrate 100 exposed in the form of stripes, the region denoted by reference numeral 100a corresponds to a region that later becomes the source line 109 in the vertical direction (Y direction) (in the left figure), The region indicated by reference numeral 100b later corresponds to the formation region of the bit line 108 in the vertical direction (in the left figure).

  Subsequent to the formation of the STI 110, the region other than the region indicated by 100a on the surface of the semiconductor substrate 100 is covered with a photoresist 111, and ion implantation is performed at a desired implantation depth and dose from the mask opening of the photoresist 111. As a result, a source line 109 (diffusion layer 102) extending in the Y direction is formed as shown in FIG. 3B (step S102).

  After the ion implantation is completed, the photoresist 111 is removed, and a layer 112 to be the floating gate 120 is formed on the tunnel oxide film using a known photolithography technique, a film forming technique, and an etching technique (FIG. 3C). Step S103).

  Next, after a layer for forming the word line 107 is formed on the entire surface of the wafer, predetermined patterning is performed by a known photolithography technique and etching technique, and a gate line (word line) 107 extending in the X direction is formed. Form.

  As a result, a gate portion having a structure formed by the straight gate line 107 having no curved portion is obtained (step S104). At the time of the above etching, the layers 112 other than those located under the gate line 107 are removed, and the above-described floating gate 120 is formed (FIG. 4A).

  Subsequently, the region illustrated in the left diagram of FIG. 4B is covered with a photoresist 113 to form a mask, and ion implantation is performed from the opening of the mask at a predetermined inclination angle, implantation depth, and dose. Thus, the source line 104 in the X direction is formed (step S105). In this step, a region where the source line 109 in the Y direction intersects with the source line 104 in the X direction is electrically connected (FIG. 4B).

  Further, after the interlayer insulating film 114 is formed on the entire surface of the wafer, a contact hole is provided at a predetermined position by a known photolithography technique and etching technique. Then, a metal is buried in the contact hole to form the drain contact 105 and the source contact 106 (FIG. 5A, step S106). Finally, a metal wiring 115 for connecting these contacts to each other is formed (FIG. 5B, step S107). A metal wiring 115 formed on the source line 109 in the Y direction is connected to the source line 109 via the source contact 106. Further, the metal wiring 115 serving as a bit line is connected to the drain region via the drain contact 105.

  As described above, in manufacturing the semiconductor memory device of the present invention, first, before forming the gate line 107, a portion other than the diffusion region where the source contact 106 is formed is covered with a photoresist, and ion implantation is performed in the Y direction. A source line 109 is formed in the semiconductor substrate 100. Then, a source line 104 extending in the X direction after forming the gate line 107 is formed in the semiconductor substrate 100 and connected to the Y direction source line 109. In this manner, the source contact 106 can be formed without bending the gate line 107, and the source contact 106 having the same arrangement as the drain contact 105 can be obtained.

  As described above, according to the present invention, it is possible to provide a technique capable of simplifying the structure of the semiconductor memory device and simplifying the manufacturing process, and various disadvantages of the conventional semiconductor memory device. Is resolved.

  Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

Claims (12)

  A semiconductor memory having a semiconductor substrate and first and second source regions formed in the semiconductor substrate and extending in first and second directions orthogonal to each other.   2. The semiconductor memory according to claim 1, wherein each of the first and second source regions is a diffusion region and is electrically connected at an intersecting portion.   The semiconductor memory according to claim 1, wherein each of the first and second source regions has a linear region.   The semiconductor memory has a drain region formed in the semiconductor substrate, a bit line extending in the same direction as the second source region, and a source line formed on the second source region. The contact between the source line and the second source region and the contact between the bit line and the drain region formed in the semiconductor substrate are arranged in a straight line. A semiconductor memory according to claim 1.   The semiconductor memory according to claim 4, wherein the bit line is arranged on both sides of the second source region.   6. The semiconductor memory according to claim 4, wherein a distance between the source line and the bit line adjacent to the source line is smaller than a distance between adjacent bit lines.   7. The semiconductor memory according to claim 1, wherein the semiconductor memory has a linear word line extending in the same direction as the first source region, and the first source region is arranged between adjacent word lines. A semiconductor memory according to claim 1.   The semiconductor memory according to claim 7, wherein the word line includes a gate electrode formed on the semiconductor substrate.   9. The semiconductor memory according to claim 1, wherein each of the first and second source regions is a diffusion region formed in a separate diffusion process. 10.   The semiconductor memory according to claim 1, wherein the semiconductor memory is a NOR type flash memory having a floating gate. Forming a first source region extending in a first direction in a semiconductor substrate;
Forming a second source region extending in a second direction orthogonal to the first direction.   12. The method of manufacturing a semiconductor memory according to claim 11, wherein the manufacturing method includes a step of forming a floating gate and a gate electrode after forming the second source region.