JP2012089579A - Manufacturing method of semiconductor device - Google Patents

Abstract

A method of manufacturing a CoC type semiconductor device capable of suppressing breakage of a connection portion between semiconductor chips and occurrence of cracks in a semiconductor chip is provided.
A method for manufacturing a semiconductor device includes: a first semiconductor chip 10a having a bump electrode 12 provided on a first surface 91; and a second semiconductor chip 10b having a bump electrode 12 provided on both sides. The step of preparing, laminating the second semiconductor chip on the first surface 91 of the first semiconductor chip, and electrically connecting the bump electrode of the first semiconductor chip and the bump electrode of the second semiconductor chip The first semiconductor chip and the second semiconductor in a state where at least the outer periphery of the second surface 92 of the first semiconductor chip is in close contact with the mounting surface 93. There are a step of filling the gap between the chip and the sealing resin 14 and a step of connecting and fixing the second semiconductor chip of the chip stack and the wiring board after the step of filling the sealing resin.
[Selection] Figure 3

Description

  The present invention relates to a method for manufacturing a semiconductor device including a chip stack in which a plurality of semiconductor chips are stacked.

  2. Description of the Related Art In recent years, CoC (Chip on Chip) type semiconductor devices including a chip stack composed of a plurality of stacked semiconductor chips have been studied along with downsizing and higher functionality of electronic devices.

  As a method of manufacturing a CoC type semiconductor device, a plurality of semiconductor chips are sequentially connected and fixed on a wiring substrate or a support substrate, and a gap between each semiconductor chip is filled with an underfill material, and then a plurality of underfill materials are included. A method of sealing with a resin so as to cover the entire semiconductor chip is known. A method of manufacturing such a CoC type semiconductor device is described in Patent Document 1.

JP 2007-36184 A

  The semiconductor device manufacturing method described above includes a step of sequentially fixing a plurality of semiconductor chips on a wiring board. In this process, there is a difference in thermal expansion coefficient and rigidity between the wiring board or the supporting board and the semiconductor chip, or variation in the heat distribution of the entire semiconductor device. There is a risk that the connecting portions may be broken or a crack may occur in the semiconductor chip.

  In one embodiment of the present invention, a method of manufacturing a semiconductor device includes preparing a first semiconductor chip having a bump electrode on a first surface and a second semiconductor chip having a bump electrode on both surfaces. And stacking the second semiconductor chip on the first surface of the first semiconductor chip, and electrically connecting the bump electrode of the first semiconductor chip and the bump electrode of the second semiconductor chip. The first semiconductor chip and the second semiconductor chip are formed in a state in which at least the outer circumference of the second surface opposite to the first surface of the first semiconductor chip is in close contact with the mounting surface. A step of filling the gap between the semiconductor chip and the sealing resin, and a step of connecting and fixing the second semiconductor chip of the chip stack and the wiring board after the step of filling the sealing resin. .

  In the method of manufacturing a semiconductor device as described above, after a chip stacked body in which a sealing resin is formed between semiconductor chips is manufactured, the chip stacked body is fixed to a wiring board. Therefore, even if there is a difference in thermal expansion coefficient and rigidity between the semiconductor chip and the wiring board, or variation in the thermal distribution of the entire semiconductor device, the thermal stress applied to the connection parts between the semiconductor chips and the semiconductor chip is reduced. it can. Thereby, it is possible to suppress the breakage of the connection part between the semiconductor chips and the occurrence of cracks in the semiconductor chip. Further, in the above manufacturing method, at least the outer periphery of the second surface of the first semiconductor chip is in close contact with the mounting surface in the step of filling the sealing resin. Therefore, there is an advantage that the sealing resin does not flow between the first semiconductor chip and the mounting surface, and the risk that the chip stack is lifted by the flow of the sealing resin is suppressed.

It is sectional drawing which shows an example of the semiconductor device of 1st Embodiment. It is a figure which shows an example of the assembly procedure of the chip laminated body shown in FIG. It is a figure which shows an example of the assembly procedure of the chip laminated body shown in FIG. FIG. 3 is a diagram illustrating an example of an assembly procedure of the semiconductor device illustrated in FIG. 1. It is a figure which shows an example of the assembly procedure of the semiconductor device of a comparative example. FIG. 3 is a diagram illustrating an example of an assembly procedure of the semiconductor device illustrated in FIG. 1. It is sectional drawing which shows an example of the semiconductor device of 2nd Embodiment. FIG. 8 is a diagram illustrating an example of an assembly procedure of the semiconductor device illustrated in FIG. 7. FIG. 8 is a diagram illustrating an example of an assembly procedure of the semiconductor device illustrated in FIG. 7. It is sectional drawing which shows an example of the semiconductor device of 3rd Embodiment.

  The present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view showing an example of the semiconductor device of the first embodiment. The semiconductor device 1 according to the first embodiment includes a chip stacked body 11 including a plurality of semiconductor chips 10a and 10b stacked on each other. The chip stack 11 is connected and fixed to the wiring board 20.

  A plurality of bump electrodes 12 are formed on one surface (first surface) 91 of the first semiconductor chip 10 a located farthest from the wiring substrate 20 in the chip stack 11. Bump electrodes are not formed on the other surface (second surface) 92 of the first semiconductor chip 10a, and the second surface 92 is a flat surface.

  Bump electrodes 12 are formed on both surfaces of the second semiconductor chip 10b other than the first semiconductor chip 10a. The bump electrode 12 on one side and the bump electrode 12 on the other side are connected by a through wiring 13. The semiconductor chips 10 a and 10 b are connected to each other through the bump electrode 12.

  The chip stacked body 11 only needs to have one first semiconductor chip 10a and at least one second semiconductor chip 10b. In the example shown in FIG. 1, there is one first semiconductor chip 10a and five second semiconductor chips 10b.

  The semiconductor chips 10a and 10b may have various circuits. As an example, the second semiconductor chip 10b connected and fixed to the wiring board 20 can be an interface chip, and the other second semiconductor chip 10b can be a chip on which a memory circuit is formed. The first semiconductor chip 10a may be, for example, a chip on which a memory circuit is formed, or a support chip on which no circuit is formed.

  A sealing resin (first sealing resin) 14 is provided in the gap between the semiconductor chips 10a and 10b. The sealing resin 14 preferably has a substantially trapezoidal cross-sectional shape and covers the periphery of the chip stack 11. The sealing resin 14 is formed using, for example, an underfill material.

  As the wiring board 20, for example, a glass epoxy board having predetermined wirings formed on both sides is used. This wiring is covered with an insulating film such as a solder resist film except for the connection pad 21 and the land 23.

  On one surface of the wiring substrate 20, a plurality of connection pads 21 for connecting to the chip stack 11 are formed. A plurality of lands 23 for connecting metal balls 22 as external terminals are formed on the other surface of the wiring board 20. These connection pads 21 are connected to predetermined lands 23 by wiring. The lands 23 are arranged at a predetermined interval, for example, in a lattice shape.

  Wire bumps 15 made of, for example, Au or Cu are formed on the connection pads of the wiring board 20. The wire bump 15 is connected to the bump electrode 12 of the second semiconductor device 10b. In addition, the chip stack 11 and the wiring board 20 are preferably bonded and fixed by an adhesive member 24 such as NCP (Non Conductive Paste). Bonding parts such as the wire bumps 15 and the connection pads 21 are protected by the adhesive member 24.

  The chip stack 11 on the wiring substrate 20 is sealed with a sealing resin (second sealing resin) 25. Metal balls 22 serving as external terminals of the semiconductor device 1 are connected to a plurality of lands 23 provided on the surface of the wiring board 20 on the side opposite to the surface on which the chip stack 11 is mounted.

  Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described. When manufacturing the semiconductor device 1 of the first embodiment, first, the first semiconductor chip 10a and the second semiconductor chip 10b are prepared. The semiconductor chips 10a and 10b have a configuration in which a predetermined circuit such as a memory circuit is formed on one surface of a plate-like substrate made of, for example, a substantially square Si.

  Bump electrodes 12 are provided on one surface 91 of the first semiconductor chip 10a. The other surface 92 of the first semiconductor chip is flat. Bump electrodes 12 are provided on both surfaces of the second semiconductor chip 10b.

  Next, the first semiconductor chip 10a is placed on the suction stage 100 (see FIG. 2A). At this time, the second surface 92 of the first semiconductor chip 10a is directed toward the suction stage. The first semiconductor chip 10a is preferably vacuum-sucked by a vacuum device (not shown) through a suction hole 102 provided in the suction stage 100. Accordingly, the first semiconductor chip 10a is stably held on the suction stage 100.

  The second semiconductor chip 10b is mounted on the first semiconductor chip 10a held on the suction stage 100 (see FIG. 2B). At this time, the bump electrode 12 of the first semiconductor chip 10a and the bump electrode 12 of the second semiconductor chip 10b are joined. Thereby, the first semiconductor chip 10a and the second semiconductor chip 10 are connected and fixed.

  The third-stage semiconductor chip 10b is connected and fixed on the second-stage semiconductor chip 10b, and the fourth-stage semiconductor chip 10b is connected and fixed on the third-stage semiconductor chip 10b. In this way, the chip stacked body 11 having an arbitrary number of semiconductor chips 10a and 10b is configured (see FIG. 2C). In the example illustrated in FIG. 2, the chip stacked body 11 includes one first semiconductor chip 10 a and five second semiconductor chips 10 b.

For joining the bump electrodes 12, for example, a thermocompression bonding method can be used. As a specific example, for example, a thermocompression bonding method in which a predetermined load is applied by pressing the semiconductor chips 10a and 10b with the bonding tool 110 set to a high temperature (for example, about 300 ° C.) may be used. For joining the semiconductor chips 10a and 10b, not only a thermocompression bonding method but also an ultrasonic pressure bonding method in which ultrasonic waves are applied while applying ultrasonic waves, or an ultrasonic thermocompression bonding method in which both thermocompression bonding and ultrasonic pressure bonding are used are used. May be.

The order of stacking the semiconductor chips 10a and 10b is not limited to the example shown in FIG. First, the second semiconductor chip 10b may be placed on the suction stage 100. In this case, the first semiconductor device 10a is finally stacked such that the second surface 92 faces upward. That is, the chip stacked body 11 is configured such that the second surface 92 of the first semiconductor chip 10a is directed outward.

  Next, in a state where the second surface 92 of the first semiconductor chip 10a is in close contact with the flat surface (mounting surface) 93, the sealing resin 14 is placed in the gap between the adjacent semiconductor chips 10a and 10b. Fill. Here, as shown in FIG. 3A, the chip stack 11 is placed so that the second surface 92 of the first semiconductor chip 10a is in close contact with the coating sheet 121 attached to the stage 120 without a gap. Place on stage 120. In this case, the surface of the coating sheet 121 is a flat surface 93.

  The coating sheet 121 is preferably an adhesive sheet from which the chip stack 11 can be peeled off. Note that the coating sheet 121 does not need to be applied directly on the stage 120, and may be anywhere on a flat surface. For example, the coating sheet may be attached to a predetermined jig or the like placed on the stage 120.

  Next, as illustrated in FIG. 3B, the underfill material 131 is supplied from the vicinity of the end of the chip stack 11 by the dispenser 130. The supplied underfill material 131 enters the gap between the semiconductor chips 10 by capillary action while forming a fillet around the chip stack. Thereby, the gap between the semiconductor chips 10 is filled with the underfill material 131.

  The chip stack 11 supplied with the underfill material 131 is cured (heat treated) at a predetermined temperature, for example, about 150 ° C. while being placed on the coating sheet 121, so that the underfill material 131 is heated. Cured. As a result, as shown in FIG. 3C, a sealing resin 14 made of an underfill material 131 that covers the periphery of the chip stack 11 and fills the gaps between the semiconductor chips 10 is formed.

  In the manufacturing method of the present embodiment, since the second surface 92 of the first semiconductor chip 10a of the chip stack 11 is in close contact with the flat surface 93, the underfill material 121 is in contact with the semiconductor chip 10a and the flat surface 93. It does not flow in between. Accordingly, the outer precision of the sealing resin 14 is improved without the chip stack 11 being lifted during this process.

  In the present embodiment, the second surface 92 of the first semiconductor chip 10a and the placement surface 93 on which the semiconductor chip 10a is placed are flat, but these surfaces 92 and 93 are not necessarily flat. Absent. When the underfill material 131 is supplied, it is sufficient that at least the outer periphery of the second surface 92 of the first semiconductor chip 10 a is in close contact with the mounting surface 93. Also in this case, the underfill material 131 does not flow between the first semiconductor chip 10a and the mounting surface 93, and the risk that the chip stack 11 is lifted by the flow of the underfill material 131 is suppressed.

  After the thermosetting of the sealing resin 14, the chip laminated body 11 including the sealing resin 14 is picked up from the coating sheet 121 and stored in the storage jig 140 as necessary (see FIG. 3D).

  The coating sheet 121 is preferably a material having poor wettability with respect to the sealing resin (underfill material) 14, such as a fluorine-based sheet or a sheet coated with a silicone-based adhesive.

  When the coating sheet 121 is made of a material having poor wettability with respect to the underfill material 131, the advantage that the spread of the liquid underfill material 131 is suppressed and the fillet width is suppressed, or to the coating sheet 121 during thermosetting. There is an advantage that adhesion of the underfill material 131 is prevented, and an advantage that the chip stack 11 can be easily picked up from the coating sheet 121.

  Next, a procedure for assembling the semiconductor device according to the first embodiment will be described. FIG. 4 shows an example of an assembly procedure for collectively forming a plurality of semiconductor devices 1.

  First, a wiring board 20 having a plurality of product forming portions 26 arranged in a matrix is prepared. The product forming unit 26 is a part that becomes the wiring substrate 20 of each semiconductor device 1. Each product forming section 26 is formed with a predetermined pattern of wiring. Each wiring is covered with an insulating film such as a solder resist film except for the connection pad 21 and the land 23. A dicing line is formed between the product forming portions 26 of the wiring board 20 when the semiconductor devices 1 are individually separated.

  A plurality of connection pads 21 for connecting to the chip stack 11 are formed on one surface of the wiring board 20, and a plurality of lands 23 for connecting metal balls 22 serving as external terminals are formed on the other surface. Is formed. These connection pads 21 are connected to predetermined lands 23 by wiring.

  Next, the second semiconductor chip 10a located at the end of the chip stack 11 and the wiring board 20 are connected and fixed. Specifically, first, the wire bumps 15 are formed on the connection pads 21 of the wiring board 20. The wire bump 15 is bonded to the connection pad 21 by using, for example, an ultrasonic thermocompression bonding method using a wire bonding apparatus (not shown), and a wire such as Au or Cu that has been melted into a ball shape. What is necessary is just to form by drawing a wire.

  As shown in FIG. 4A, an insulating adhesive member 24, for example, NCP (Non Conductive Paste) is applied onto each product forming portion 26 of the wiring board 20 by a dispenser 150.

  Next, the second surface 92 of the first semiconductor chip 10 of the chip stack 11 is sucked and held by the bonding tool 160 or the like and mounted on the product forming portion 26 of the wiring board 20 (see FIG. 4B). . Then, the wire bumps 15 of the wiring board 20 and the bump electrodes 12 of the chip stack 11 are bonded using, for example, a thermocompression bonding method. At this time, the adhesive member 24 on the wiring board 20 is filled between the chip stack 11 and the wiring board 20, and the wiring board 20 and the chip stack 11 are bonded and fixed (see FIG. 4C). Here, since the sealing resin 14 is formed in a taper shape around the chip laminated body 11, creeping of the adhesive member 24 is suppressed. As a result, damage to the chip stack 11 and poor bonding due to the adhesive member 24 adhering to the bonding tool 160 are reduced.

  In the present embodiment, an example in which the wire bumps 15 are formed on the connection pads 21 of the wiring board 20 is shown, but the connection pads 21 of the wiring board 20 may be directly connected to the bump electrodes 12 of the chip stack 11.

  Here, as a comparative example, a method of manufacturing a semiconductor device using the chip stacked body 11 in which the second surface 92 of the first semiconductor chip 10a is not flat will be described with reference to FIG. In FIG. 5, bump electrodes 12 are formed on both surfaces of the first semiconductor chip 10a, and the second surface of the first semiconductor chip 10a is not flat.

  When the chip stack 11 of the comparative example is placed on the coating sheet 121, a gap is formed between the first semiconductor chip 10 a and the coating sheet 121 for the bump electrode 12. When sealing resin (underfill material) is supplied in this state, the underfill material flows into the gap between the first semiconductor chip 10a and the coating sheet 121. Since the chip laminated body 11 is placed on or adhered to the coating sheet 121 via the bump electrode 12, the chip laminated body 11 is lifted from the coating sheet 121 due to the influence of the flow of the underfill material. (See FIG. 5 (a)). As a result, the outer shape of the sealing resin 14 may vary, and subsequent processes may not be performed accurately or the yield may be reduced. In particular, as shown in FIG. 5B, when one surface of the chip stack 11 is sucked and held by the bonding tool 160, the chip stack 11 may be inclined with respect to the bonding tool 160. As shown in FIG. 5C, when the connection is fixed to the wiring board 20 in this state, the connection strength is lowered or a connection failure occurs. In FIG. 5C, a connection failure occurs at a location indicated by a dotted area A.

  On the other hand, according to the manufacturing method of the present embodiment, as described above, the external accuracy of the sealing resin 14 is improved, so that poor connection between the chip stack 11 and the wiring board 20 is suppressed.

  After the process described with reference to FIG. 4, the wiring substrate 20 on which the chip stack 11 is mounted is set in a molding die including an upper mold and a lower mold (not shown), and the process proceeds to the molding process.

  A cavity (not shown) that collectively covers the plurality of chip stacks 11 is formed in the upper mold of the molding die, and the chip stacks 11 mounted on the wiring board 20 are accommodated in the cavities. Next, the sealing resin heated and melted is injected into the cavity provided in the upper mold of the molding die, and the cavity is filled with the sealing resin 25 so as to cover the entire chip stack 11. For the sealing resin 25, for example, a thermosetting resin such as an epoxy resin is used.

  Subsequently, in a state where the cavity is filled with the sealing resin 25, the sealing resin 25 is thermally cured by curing at a predetermined temperature, for example, about 180 ° C., and as shown in FIG. A sealing resin 25 that covers the stacked body 11 is formed. Furthermore, the sealing resin (second sealing resin) 25 is completely cured by baking at a predetermined temperature.

  In the present embodiment, the gap between the semiconductor chips 10 of the chip stack 11 is sealed with the first sealing resin layer (underfill material) 14 and then the second sealing resin 25 covering the entire chip stack 11 is formed. Therefore, the generation of voids in the gap between the semiconductor chips 10 can be suppressed.

  When the second sealing resin 25 is formed, the process proceeds to a ball mounting process, and the lands 23 formed on the other surface of the wiring substrate 20 as shown in FIG. Metal balls 22 such as solder balls are connected.

  In the ball mounting process, the plurality of metal balls 22 are sucked and held using a mounting tool 170 having a plurality of suction holes whose positions coincide with the lands 23 of the wiring board 20, and the flux is transferred to each metal ball 22. The held metal balls 22 are collectively mounted on the lands 23 of the wiring board 20.

  After the mounting of the metal balls 22 on all the product forming portions 26 is completed, the metal balls 22 and the lands 23 are connected by reflowing the wiring board 20.

  When the connection of the metal balls 22 is completed, the process proceeds to a substrate dicing process, and the individual product forming portions 26 are cut and separated by a predetermined dicing line to form the semiconductor device 1.

  In the substrate dicing process, the product forming portion 26 is supported by sticking the dicing tape 180 to the second sealing resin 25. Then, as shown in FIG. 6C, the product forming unit 26 is separated by cutting along a predetermined dicing line with a dicing blade 181 provided in a dicing device (not shown). After cutting and separating, the dicing tape 180 is picked up from the product forming section 26, whereby the CoC type semiconductor device 1 shown in FIG. 1 is obtained.

  As described above, according to the manufacturing method of the present embodiment, after the chip stack 11 having the sealing resin 14 formed thereon, the chip stack 11 is fixed to the wiring board 20. Therefore, even if there is a difference in thermal expansion coefficient and rigidity between the semiconductor chip 10a and the wiring substrate 20 or a variation in the heat distribution of the entire semiconductor device, the connection part between the semiconductor chips 10a and 10b, the semiconductor chip 10a, The thermal stress applied to 10b can be reduced. Thereby, it is possible to suppress the breakage of the connection portion between the semiconductor chips 10a and 10b and the occurrence of cracks in the semiconductor chips 10a and 10b.

  FIG. 7 is a cross-sectional view showing an example of the semiconductor device of the second embodiment. As shown in FIG. 7, the semiconductor device 2 of the second embodiment includes a metal substrate (support) that supports the chip stack 11 in addition to the chip stack 11 and the wiring substrate 20 shown in the first embodiment. Substrate) 30. The chip stack 11 is bonded and fixed on the metal substrate 30 by an adhesive member 31, for example, DAF (Die Attached Film). For the metal substrate 30, for example, an iron / nickel alloy (42 alloy or the like) is used.

  The configuration of the chip stack 11 is substantially the same as that of the first embodiment, and is different from that of the first embodiment in that it includes four semiconductor chips 10a and 10b.

  The flat surface 92 of the first semiconductor chip 10 is connected to the metal substrate 30 via the adhesive member 31. The wiring substrate 20 is connected and fixed to the surface of the chip stack 11 facing away from the metal substrate 30 via the wire bumps 15.

  In the semiconductor device 2 of the second embodiment, the warp of the semiconductor device 2 can be reduced by fixing the chip stack 11 on the metal substrate 30. Further, since the chip stack 11 is supported by the metal substrate 30, it is possible to use the wiring substrate 20 having a size smaller than that of the metal substrate 30, and the size of the wiring substrate 20 is optimal according to the number of external terminals. Can be designed.

  Next, the assembly procedure of the semiconductor device according to the second embodiment will be described with reference to the drawings. 8 and 9 are diagrams showing an example of an assembly procedure of the semiconductor device shown in FIG. 8 and 9 show an example of an assembly procedure for forming a plurality of semiconductor devices 2 at once.

  Also in the second embodiment, the chip stack 11 is formed in the same procedure as in the first embodiment. Therefore, as described above, there is an advantage that the external accuracy of the sealing resin 14 around the chip stack 11 is improved. Thereby, the connection failure of the chip laminated body 11 and the wiring board 20, and the connection failure of the chip laminated body 11 and the metal substrate 30 are suppressed. In addition, a metal substrate 30 including a plurality of product forming portions 32 arranged in a matrix is prepared as a support substrate that supports the chip stack 11.

  When the preparation of the metal substrate 30 is completed, an insulating adhesive member 31, for example, DAF, is mounted on each product forming portion 32 of the metal substrate 30 as shown in FIG. Next, as shown in FIG. 8B, the chip stacked body 11 is bonded and fixed on each product forming portion 32 of the metal substrate 30 by an insulating adhesive member 31. At this time, the second surface (flat surface) 92 of the first semiconductor chip 10 a of the chip stack 11 is made to face the metal substrate 30.

  The metal substrate 30 on which the chip stack 11 is mounted is set in a molding die composed of an upper mold and a lower mold (not shown), and proceeds to a molding process.

  A cavity (not shown) that collectively covers the plurality of chip stacks 11 is formed in the upper mold of the molding die, and the chip stacks 11 mounted on the metal substrate 30 are accommodated in the cavities. At this time, a sheet having elasticity is arranged in the cavity, and the upper die and the lower die are closed to cover the surface of the semiconductor chip 10 at the top of the chip stack 11 with the sheet. By doing in this way, the sealing resin mentioned later is prevented from wrapping around the surface of the semiconductor chip 10 at the top of the chip stack 11.

  Next, the sealing resin heated and melted is injected into the cavity provided in the upper mold of the molding die, and the cavity is filled with the sealing resin so as to cover the entire chip stack 11. As the sealing resin, for example, a thermosetting resin such as an epoxy resin is used.

  Subsequently, in a state where the cavity is filled with the sealing resin, the sealing resin is thermally cured by curing at a predetermined temperature, for example, about 180 ° C., and as shown in FIG. A second sealing resin 25 is formed to collectively cover the chip stack 11 mounted on each of the layers 32. Further, the second sealing resin 25 is completely cured by baking at a predetermined temperature. At this time, since the surface of the semiconductor chip 10 at the top of the chip stacked body 11 was covered with the sheet, the bump electrode 12 is exposed without the second sealing resin layer 25 being formed.

  In the present embodiment, the gap between the semiconductor chips 10 of the chip stack 11 is sealed with the first sealing resin (underfill material) 14, and then the second sealing resin 25 covering the entire chip stack 11 is formed. Therefore, generation of voids in the gap between the semiconductor chips 10 can be suppressed.

  Next, wire bumps 15 are formed on the bump electrodes 12 at the top of the chip stack 11. The wire bump 15 is formed by using, for example, an ultrasonic thermocompression bonding method, such as an ultrasonic thermocompression bonding method, on a bump electrode 12 of the semiconductor chip 10 by using a wire bonding apparatus (not shown) to melt and form a wire such as Au or Cu. What is necessary is just to form by joining and pulling a wire after that.

  In the present embodiment, solder bumps may be formed on the bump electrodes 12 of the semiconductor chip 10 instead of the wire bumps 15. Further, in the present embodiment, an example in which the wire bumps 15 are formed on the bump electrodes 12 in order to facilitate the connection between the chip stack 11 and the wiring board 20 is shown. The connection pads 21 of the substrate 20 may be directly connected.

  Next, as shown in FIG. 8D, the adhesive member 24, for example, NCP is selectively applied to the exposed surface of the semiconductor chip 10b at the top of the chip stacked body 11, and the wiring board 20 is mounted thereon (see FIG. 8D). FIG. 9A).

  For the wiring substrate 20, a polyimide substrate having a smaller area than the product forming portion 32 of the metal substrate 30, for example, a substantially rectangular wiring, or a flexible substrate having a wiring is used.

  Next, the wiring board 20 is sucked and held by the bonding tool 190 or the like and mounted on the chip stack 11, and the connection pads 21 of the wiring board 20 and the wire bumps 15 of the chip stack 11 are bonded using, for example, a thermocompression bonding method. Join. At this time, the adhesive member 24 (NCP material) applied on the chip stack 11 is filled between the chip stack 11 and the wiring board 20, and the wiring board 20 is bonded and fixed on the chip stack 11.

  In the present embodiment, as described above, since the wiring board 20 having a smaller area than the product forming part 32 of the metal substrate 30 can be mounted, the wiring on the chip stacked body 11 arranged adjacently when the wiring board 20 is mounted. It is possible to reduce the problem that the substrates 20 are in contact with each other and the problem that the adhesive members 24 (NCP materials) on the adjacent chip stacks 11 are in contact with each other. For this reason, the wiring board 20 is satisfactorily mounted on each chip stack 11.

  Finally, as shown in FIG. 9B, the metal balls 22 are mounted on the lands 23 on the other surface of the wiring board 20 using the mounting tool 170 as in the first embodiment. As shown in FIG. 7C, the semiconductor device 2 shown in FIG. 7 is formed by cutting and separating each product forming portion 32 of the metal substrate 30 by a dicing blade 181 provided in a dicing device (not shown).

  Since the semiconductor device 2 of the second embodiment includes the metal substrate 30, the warp of the semiconductor device 2 can be reduced. Further, by providing the metal substrate 30, the mechanical strength of the semiconductor device 2 is improved and the heat dissipation characteristics of the semiconductor device 2 are also improved.

  Furthermore, since the chip stack 11 is supported by the metal substrate 30 in the semiconductor device 2 according to the second embodiment, it is possible to use the wiring substrate 20 having a size smaller than that of the metal substrate 30. The size of the wiring board 20 can be optimally designed according to the number of arrangements.

  FIG. 10 is a cross-sectional view showing an example of the semiconductor device of the third embodiment. As shown in FIG. 10, the semiconductor device 3 of the third embodiment has functions different from those of the chip stack 11 shown in the first embodiment and the semiconductor chip 10 of the chip stack 11 on the wiring substrate 20. Another semiconductor chip (function expansion chip) 200 provided is provided.

  The chip stack 11 shown in FIG. 10 is created in the same procedure as in the first embodiment. Therefore, as described above, there is an advantage that the external accuracy of the sealing resin 14 around the chip stack 11 is improved. Thereby, the connection failure of the chip laminated body 11 and the wiring board 20, and the connection failure of the chip laminated body 11 and the metal substrate 30 are suppressed.

  In the function expansion chip 200, a circuit (for example, a logic circuit) having a function different from that of the semiconductor chips 10a and 10b is formed on one surface of a substantially rectangular Si substrate, and a plurality of electrode pads are formed in the vicinity of the periphery and in the vicinity of the center. It is a configuration.

  The function expansion chip 10 </ b> A is bonded and fixed to the wiring board 20 on the surface on which no circuit is formed using an insulating adhesive member 41, for example, DAF. The electrode pads arranged in the vicinity of the periphery of the function expansion chip 10A are connected to the connection pads of the wiring board 20 through the conductive wires. The pads arranged near the center of the wiring board are connected to the chip stack 11 by a flip chip connection method. The function expansion chip 200, the chip stack 11, and the conductive wire 42 on the wiring substrate 20 are sealed with the second sealing resin 25.

  FIG. 10 shows an example of the semiconductor device 3 in which the function expansion chip 10A and the chip stack 11 are mounted on the wiring board 20. Instead of this, the semiconductor device may have a configuration in which the chip stacked body 11 and the function expansion chip 10A are mounted on the metal substrate 30 and the wiring substrate 20 is mounted thereon as in the second embodiment.

  According to the third embodiment, in addition to the effects as in the first embodiment, by providing the function expansion chip 200, a semiconductor device having a larger memory capacity or more functions can be obtained. .

  As mentioned above, although the invention made | formed by this inventor was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to the said embodiment, A various change is possible in the range which does not deviate from the summary. Yes.

  For example, in the first to third embodiments, the chip stack 11 on which the semiconductor chips 10a and 10b on which the memory circuits are formed is described as an example. However, the semiconductor chips 10a and 10b are formed with logic circuits. A chip having any function such as a chip may be used.

  In the first to third embodiments, the BGA type semiconductor device using the metal balls 22 as the external terminals has been described as an example. However, the present invention is not limited to other package type semiconductors such as LGA (Land Grid Array). It can also be applied to devices.

1, 2, 3 Semiconductor device 10a First semiconductor chip 10b Second semiconductor chip 11 Chip stack 12 Bump electrode 13 Through electrode 14 Sealing resin 15 Wire bump 20 Wiring board 21 Connection pad 22 Metal ball 23 Lands 24, 31, 41 Adhesive member 25 Sealing resin 26, 32 Product forming portion 30 Metal substrate 42 Wire 91 First surface 92 of first semiconductor chip Second surface 93 of first semiconductor chip Flat surface 100 Suction stages 102, 112 Adsorption hole 110 Bonding tool 120 Stage 121 Application sheet 131 Underfill material 130 Dispenser 140 Storage jig 150 Dispenser 160, 190 Bonding tool 170 Mounting tool 180 Dicing tape 181 Dicing blade 200 Function expansion chip

Claims (9)

Preparing a first semiconductor chip provided with a bump electrode on a first surface and a second semiconductor chip provided with a bump electrode on both sides;
The second semiconductor chip is stacked on the first surface of the first semiconductor chip, and the bump electrodes of the first semiconductor chip and the bump electrodes of the second semiconductor chip are electrically connected. Forming a chip stack by connecting to
The first semiconductor chip and the second semiconductor chip in a state where at least the outer periphery of the second surface opposite to the first surface of the first semiconductor chip is in close contact with the mounting surface. Filling the gap between them with sealing resin;
After the step of filling the sealing resin, a step of connecting and fixing the second semiconductor chip of the chip stack and the wiring board. Preparing a first semiconductor chip provided with a bump electrode on a first surface and a plurality of second semiconductor chips provided with a bump electrode on both sides;
Sequentially stacking the first semiconductor chip and the plurality of second semiconductor chips such that the second surface of the first semiconductor chip opposite to the first surface is directed outward; Forming a chip stack by electrically connecting the bump electrodes of the semiconductor chips adjacent to each other;
Filling a gap between the semiconductor chips adjacent to each other with a sealing resin in a state where at least the outer periphery of the second surface of the first semiconductor chip is in close contact with the mounting surface;
After the step of filling the sealing resin, a step of connecting and fixing the second semiconductor chip located at the end of the chip stack and the wiring board.   Filling the sealing resin in a state where the second surface of the first semiconductor chip is flat and the second surface of the first semiconductor chip is in close contact with the flat mounting surface. The method for manufacturing a semiconductor device according to claim 1, wherein:   In the step of filling the sealing resin, a liquid underfill material is supplied to the chip laminate in a state where the chip laminate is placed on a coating sheet, and the underfill material is thermally cured to The manufacturing method of the semiconductor device of any one of Claim 1 to 3 which forms sealing resin.   The method for manufacturing a semiconductor device according to claim 4, wherein the coating sheet has a poor wettability with respect to the liquid underfill material.   The method for manufacturing a semiconductor device according to claim 4, wherein the coating sheet is a peelable adhesive surface.   The method according to claim 1, further comprising a step of forming another sealing resin that covers the periphery of the chip stack on the wiring substrate after the step of connecting and fixing the second semiconductor chip and the wiring substrate. A manufacturing method of a semiconductor device given in any 1 paragraph.   Before the step of connecting and fixing the second semiconductor chip and the wiring board, the chip stack is picked up from the mounting surface, and the second surface of the first semiconductor chip is used as a support substrate. And forming another sealing resin that covers the periphery of the chip stack except for the surface of the chip stack opposite to the support substrate. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   9. The method for manufacturing a semiconductor device according to claim 1, wherein the second semiconductor chip and the wiring board are connected and fixed via another semiconductor chip. 10.

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