JP2012089191A - Semiconductor memory device - Google Patents

Abstract

An output latch failure may occur due to manufacturing variations.
A cell array in which a plurality of memory cells are arranged, a complementary bit line pair provided corresponding to a memory cell column, and a precharge for precharging the bit line pair to a predetermined potential before data reading. An output latch circuit for latching the output of the sense amplifier in a semiconductor memory device comprising: a circuit; and a sense amplifier connected to the bit line pair and detecting and amplifying data stored in the selected memory cell when activated A semiconductor memory device comprising: an output latch determination circuit that determines latch completion based on an output of the sense amplifier that performs an amplification operation and an output of the output latch circuit.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor memory device.

  In recent years, semiconductor wafers have been reduced in chip cost by increasing the diameter. However, transistor characteristics (threshold, on-current, etc.) vary greatly due to manufacturing variations due to miniaturization, and high yields that are not affected by variations due to characteristics variations are required. Similarly, in a static random access memory (SRAM) product, a high yield product that eliminates the influence of fluctuation due to characteristic variation is desired, and it is important to increase the yield.

  FIG. 10 shows a block configuration of a circuit of the conventional SRAM 1 disclosed in Patent Document 1. In FIG. FIG. 11 shows an operation timing chart in the prior art. As shown in FIG. 10, the conventional SRAM 1 includes a sense amplifier 13, data line pairs 11 and 12, an output voltage detection circuit 21, a NAND circuit 34, an inverter circuit 35, and an output latch circuit 14. .

  The output voltage detection circuit 21 is disposed in the vicinity of the sense amplifier 13. The output voltage detection circuit 21 has an AND circuit 33. The output voltage detection circuit 21 inputs the voltages of the complementary data line pairs 11 and 12. Then, it is detected that the voltage on the output terminal pair to the complementary data line pair 11 and 12 in the sense amplifier 13 has been established. When the output voltage detection circuit 21 detects that the output voltage of the data line pair 11, 12 of the sense amplifier 13 is fixed, it outputs a detection signal 22.

  The NAND circuit 34 inputs the detection signal 22 and the sense amplifier control signal 15 and outputs a signal 23. The inverter circuit 35 outputs an inverted signal of the signal 23 as the output latch control signal 18. The output latch circuit 14 is latch-controlled by an output latch control signal 18.

FIG. 11 shows a timing chart of the read operation of the conventional SRAM 1 configured as described above. The SRAM 1 activates the sense amplifier 13 by raising the sense amplifier control signal 15 to a high level at time t1 when the voltage difference between the data line pairs 11 and 12 is opened to some extent by the data read after the completion of precharge.

  Then, the potential of one of the data line pairs 11 and 12 connected to the sense amplifier 13 is suddenly lowered by the sense amplifier 13 in the activated state, and the potential difference between the data line pairs is opened.

  When the potential difference opens, the AND circuit 33 of the output voltage detection circuit 21 detects a mismatch between the levels of the output pairs of the data line pairs 11 and 12, that is, detects a detection signal at time t3 when it is detected that the output of the sense amplifier 13 has been established. 22 falls from the high level to the low level.

  The NAND circuit 34 receives the low level detection signal 22 and the high level sense amplifier control signal 15 and outputs a high level signal 23. The inverter circuit 35 inverts this signal 23 to obtain an output latch control signal 18.

  As described above, according to the conventional technique, the sense amplifier output voltage detection circuit 21 that detects that the voltage on the output terminal pair to the complementary data line pair 11 and 12 connected to the sense amplifier 13 is fixed is individually provided. Therefore, the wiring length through which the output latch control signal 18 propagates can be shortened, and the wiring load can be reduced. For this reason, the dullness of the waveform of the output latch control signal 18 can be suppressed. As a result, it is possible to reliably generate the output latch control signal 18 having a pulse width of a length necessary for latching output data without expecting an excessive margin.

JP 2002-133875 A

  However, this conventional technique has the following problem of erroneous reading due to an output latch failure. As described above, the SRAM 1 detects only the determination of the data line pair 11, 12 that is the output of the sense amplifier 13 by the output voltage detection circuit 21 (AND circuit 33) and generates the output latch control signal 18. In such a circuit configuration, when the output latch control signal generation unit composed of the output voltage detection circuit 21, the NAND circuit 34, and the inverter circuit 35 is affected by the characteristic variation, the time that the output latch control signal 18 assumes There is a possibility that it will work faster.

  For example, the transistor constituting the AND circuit 33 of the output voltage detection circuit 21 is affected by manufacturing variations, and the threshold value, which is one of the transistor characteristics, fluctuates. As shown in FIG. When the output latch control signal 18 changes faster than the design time shown by the dotted line, the pulse width of the output latch control signal 18 becomes narrow. Therefore, a sufficient data latch pulse cannot be generated as the output latch control signal 18, and the output latch circuit 14 cannot latch the output data, which may cause an output latch failure.

  According to one embodiment of the present invention, a cell array in which a plurality of memory cells are arranged, a complementary bit line pair provided corresponding to a memory cell column, and the bit line pair are precharged to a predetermined potential before data reading. An output for latching the output of the sense amplifier in a semiconductor memory device comprising: a precharge circuit configured to detect and a sense amplifier connected to the bit line pair and detecting and amplifying data stored in the selected memory cell when activated The semiconductor memory device includes a latch circuit, an output latch determination circuit that determines latch completion based on an output of the sense amplifier that performs an amplification operation, and an output of the output latch circuit.

  According to another aspect of the present invention, complementary first and second complementary circuits respectively provided corresponding to a cell array in which a plurality of memory cells are arranged and a first or second column column in which one is selected. In response to the bit line pair, the first precharge control signal, the first precharge circuit for precharging the first bit line pair to a predetermined potential before data reading, and the second precharge control signal Accordingly, the second precharge circuit for precharging the second bit line pair to a predetermined potential before data reading and the corresponding column column connected to the first bit line pair are selected. Is activated when the corresponding column column is selected and connected to the first bit line pair and the first sense amplifier for detecting and amplifying data stored in the selected memory cell when activated. Memory And a second sense amplifier for detecting and amplifying the data, and an output latch circuit for latching the output of the first or second sense amplifier in the selected column column, And an output latch determination circuit that determines latch completion based on the output of the first or second sense amplifier that performs the amplification operation of the column row and the output of the output latch circuit.

  The present invention includes an output latch determination circuit that determines latch completion based on an output of a sense amplifier that has performed an amplification operation and a latch output of an output latch circuit that latches the output of the sense amplifier. Since the latch output of the output latch circuit is used to determine the completion of latching, the output of the output latch circuit that has been reliably latched can be used as output data of the semiconductor memory device. For this reason, it is possible to prevent erroneous reading due to output latch failure.

  The present invention can prevent erroneous reading due to an output latch failure.

1 is a circuit configuration of a semiconductor memory device according to a first embodiment; 3 is a configuration of a control circuit according to the first exemplary embodiment. 3 is an operation timing chart of the semiconductor memory device according to the first embodiment; 3 is a circuit configuration of a semiconductor memory device according to a second embodiment; 3 is a configuration of a control circuit according to a second embodiment. 3 is a configuration of a control circuit according to a second embodiment. 3 is a configuration of a control circuit according to a second embodiment. 3 is a configuration of a control circuit according to a second embodiment. 6 is an operation timing chart of the semiconductor memory device according to the second embodiment. This is a circuit configuration of a conventional semiconductor memory device. 6 is an operation timing chart of a conventional semiconductor memory device.

  Embodiment 1 of the Invention

  Hereinafter, a specific first embodiment to which the present invention is applied will be described in detail with reference to the drawings. FIG. 1 shows the configuration of the semiconductor memory device 100 according to the first embodiment. The semiconductor memory device 100 is, for example, an SRAM circuit.

  As shown in FIG. 1, the semiconductor memory device 100 includes a memory cell array 101, a precharge circuit 102, a sense amplifier 103, an output latch circuit 104, an output latch determination circuit 105, clocked inverter circuits CIV106 and CIV107, , Inverter circuits IV108 and IV109, a bit line pair DLDT and DLDB, and a control circuit 110.

  The bit lines DLDT and DLDB constitute complementary bit line pairs, and the TRUE side becomes DLDT and the BAR side becomes DLDB.

  The precharge circuit 102 is activated in response to the precharge control signal SPC, and equalizes and precharges the bit lines DLDT and DLDB to a predetermined voltage (power supply voltage VDD in this example). Hereinafter, this predetermined voltage is referred to as a precharge voltage.

  The precharge circuit 102 includes PMOS transistors MP1 to MP3. The PMOS transistor MP1 is an equalizing transistor, and is connected between the bit line pair DLDT and DLDB. The PMOS transistor MP2 is a precharging transistor, and is connected between the bit line DLDT and the power supply terminal VDD. The PMOS transistor MP3 is a precharging transistor and is connected between the bit line DLDB and the power supply terminal VDD.

  The precharge control signal SPC is input to the gates of the PMOS transistors MP1 to MP3. The PMOS transistors MP1 to MP3 are turned on in response to the precharge control signal SPC, and the power supply terminal VDD and the bit line pair DLDT, DLDB are electrically connected. For this reason, the bit line pair DLDT, DLDB is precharged to the precharge voltage.

  The memory cell array 101 has a plurality of memory cells (not shown). The bit line pair DLDT, DLDB has a voltage corresponding to the data held in the selected memory cell among the plurality of memory cells. For example, when the selected memory cell holds “0”, the voltage of the bit line DLDT decreases from the precharge voltage, and the voltage of the bit line DLDB maintains the precharge voltage. Conversely, when the selected memory cell holds “1”, the voltage of the bit line DLDT maintains the precharge voltage, and the voltage of the bit line DLDB decreases from the precharge voltage.

  The sense amplifier (SA) 103 is connected to the bit line pair DLDT, DLDB. The sense amplifier 103 is activated in response to the sense amplifier activation signal SES, and amplifies the potential difference between the bit lines DLDT and DLDB.

  Clocked inverter circuit CIV106 has an input terminal connected to bit line DLDT and an output terminal connected to node QB. Further, the clocked inverter circuit CIV106 inputs the output latch control signal SESB and the output latch control inversion signal SESR to the clock input terminal.

  The clocked inverter circuit CIV 106 performs an inverter operation based on the output latch control signal SESB as a clock signal and the output latch control inverted signal SESR that is an inverted signal thereof. For example, when the output latch control signal SESB is at a high level (the output latch control inversion signal SESR is at a low level), the signal input to the input terminal is inverted and output to the node QB (hereinafter referred to as an ON state). When the output latch control signal SESB is at a low level (the output latch control inversion signal SESR is at a high level), the output terminal is set to a high impedance state (hereinafter referred to as an off state).

  Clocked inverter circuit CIV107 has an input terminal connected to bit line DLDB. The output terminal is open. The clocked inverter circuit CIV107 inputs the output latch control signal SESB and the output latch control inverted signal SESR to the clock input terminal. Similarly to the CIV 106, the clocked inverter circuit CIV107 performs an inverter operation based on the output latch control signal SESB as a clock signal and the output latch control inverted signal SESR that is an inverted signal thereof. The clocked inverter circuit CIV107 is a dummy element for matching the loads of the bit line DLDT and the bit line DLDB.

  Output latch circuit 104 is connected between nodes QB and QHLD. Output latch circuit 104 latches the potential level of node QB. The output latch circuit 104 includes an inverter circuit IV11 and a clocked inverter circuit CIV11.

  Inverter circuit IV11 has an input terminal connected to node QB, and an output terminal connected to node QHLD.

  Clocked inverter circuit CIV11 has an input terminal connected to node QHLD and an output terminal connected to node QB. Further, the clocked inverter circuit CIV11 receives the output latch control signal SESB and the output latch control inverted signal SESR as clock signals. For example, when the output latch control inversion signal SESR is at a high level (the output latch control signal SESB is at a low level), the signal input to the input terminal is inverted and output (hereinafter referred to as an ON state). When the output latch control inversion signal SESR is at a low level (the output latch control signal SESB is at a high level), the output terminal is set to a high impedance state (hereinafter referred to as an off state).

  Inverter circuit IV108 has an input terminal connected to node QHLD and an output terminal connected to node QHLDB. Inverter circuit IV109 has an input terminal connected to node QB. Inverter circuit IV109 is an output buffer, which buffers a signal applied to node QB and outputs it as data output signal Q. Note that a signal applied to the node QHLD is referred to as an output latch signal QHLD, and a signal applied to the node QHLDB is referred to as an output latch inversion signal QHLDB as necessary.

  The output latch determination circuit 105 generates an output latch completion determination signal QLEN according to the output latch signal QHLD from the output latch circuit 104 and the potential level of the bit line pair DLDT, DLDB. The output latch determination circuit 105 includes PMOS transistors MP4 to MP7 and NMOS transistors MN1 and MN2.

  The PMOS transistor MP4 is connected between the power supply terminal VDD and the node N1, and has a gate connected to the bit line DLDT. The PMOS transistor MP5 is connected between the power supply terminal VDD and the node N2, and has a gate connected to the bit line DLDB. The PMOS transistor MP6 is connected between the node N1 and the node QLEN, and has a gate connected to the node QHLD. The PMOS transistor MP7 is connected between the node N2 and the node QLEN, and has a gate connected to the node QHLDB.

  The NMOS transistor MN1 is connected between the node QLEN and the node N3, and has a gate connected to the bit line DLDT. The NMOS transistor MN2 is connected between the node N3 and the ground terminal GND, and has a gate connected to the bit line DLDB. A node QHLDB is an output node of the output latch determination circuit 105, and an output latch completion determination signal QLEN is output to the control circuit 110.

  The output latch completion determination signal QLEN is used to generate a trigger signal for reading output data output from the semiconductor memory device 100. Therefore, the value of the potential level of the data output signal Q when the output latch completion determination signal QLEN becomes valid (for example, high level) becomes the value of the output data of the semiconductor memory device 100 that has completed the latch.

  The control circuit 110 receives the output latch completion determination signal QLEN, the precharge trigger signal PCB, and the sense amplifier activation trigger signal SEIB, and outputs the output latch control signal SESB and the output latch control inverted signal SESR in response to them. The precharge control signal SPC and the sense amplifier activation signal SES are output.

  FIG. 2 shows the configuration of the control circuit 110. As shown in FIG. 2, the control circuit 110 includes a PMOS transistor MP21, an NMOS transistor MN21, inverter circuits IV21 to IV26, NOR circuits NOR21 and NOR22, a NAND circuit NAND21, and a clocked inverter circuit CIV21.

  Inverter circuit IV21 receives output latch completion determination signal QLEN at its input terminal, and its output terminal is connected to node QLENB. A signal applied to node QLENB is referred to as signal QLENB.

  The PMOS transistor MP21 is connected between the power supply terminal VDD and the node QLL, and has a gate connected to the node QLENB.

  The NMOS transistor MN21 is connected between the node QLL and the ground terminal GND, and a precharge trigger signal PCB is input to the gate.

  Inverter circuit IV22 has an input terminal connected to node QLL, and an output terminal connected to node QLLB. Signals applied to nodes QLL and QLLB are referred to as signals QLL and QLLB, respectively.

  Clocked inverter circuit CIV21 has an input terminal connected to node QLLB and an output terminal connected to node QLL. The clocked inverter circuit CIV21 inputs the signal QLLB and its inverted signal to the clock input terminal.

  The clocked inverter circuit CIV21 performs an inverter operation based on the signal QLLB and its inverted signal as a clock signal. For example, when the signal QLLB is at a high level, the signal input to the input terminal is inverted and output (ON state), and when the signal QLLB is at a low level, the output terminal is set to a high impedance state (OFF state).

  Inverter circuit IV23 has an input terminal connected to node QLLB and an output terminal connected to node ILEN. A signal applied to node ILEN is referred to as signal ILEN.

  In the NOR circuit NOR21, the signal ILEN is input to one input terminal, and the precharge trigger signal PCB is input to the other input terminal. Then, the NOR calculation result is output to the node IPC.

  Inverter circuit IV24 has an input terminal connected to node IPC and an output terminal connected to node IPCB. Signals applied to the nodes IPC and IPCB are referred to as signals IPC and IPCB, respectively.

  In the NOR circuit NOR22, the signal IPCB is input to one input terminal, and the sense amplifier activation trigger signal SEIB is input to the other input terminal. Then, the NOR calculation result is output to the node SES. When the signal applied to the node SES becomes the sense amplifier activation signal SES and becomes, for example, a high level, the sense amplifier 103 is activated.

  Inverter circuit IV25 has an input terminal connected to node SES and an output terminal connected to node SESB. Note that the signal applied to the node SESB is the output latch control signal SESB.

  In the NAND circuit NAND21, the signal IPCB is input to one input terminal, and the output latch control signal SESB is input to the other input terminal. Then, the NAND operation result is output as a precharge control signal SPC.

  The inverter circuit IV26 receives the output latch control signal SESB at the input terminal and outputs the output latch control inverted signal SESR from the output terminal.

  Hereinafter, an operation of the semiconductor memory device 100 according to the first embodiment will be described. FIG. 3 shows a timing chart for explaining the operation of the semiconductor memory device 100. A data read operation of the semiconductor memory device 100 will be described with reference to FIG. In the following description, the rise of each signal indicates a state in which the signal potential changes from the low level to the high level, and the fall indicates a state in which the signal potential changes from the high level to the low level.

  Here, a period T1 shown in FIG. 3 is a period from the start of reading of memory data from the memory cell array 101 to the determination of the output latch of the output latch node QHLD. A period T2 is an output latch completion determination period. A period T3 is a precharge / reset period from the completion of the output latch determination to the next cycle.

  As an initial operation, first, the precharge trigger signal PCB falls. For this reason, the signal IPC that is the output of the NOR circuit NOR21 rises, and the precharge control signal SPC rises to a high level. Therefore, the precharge of the bit line pair DLDT, DLDB is released. Then, depending on the value held in the selected memory cell of the memory cell array 101, the potential of one of the bit lines DLDT and DLDB is lowered.

  When the potential difference between the bit lines DLDT and DLDB is opened, the sense amplifier activation trigger signal SEIB falls. Therefore, the sense amplifier activation signal SES, which is the output of the NOR circuit NOR22, rises and the sense amplifier 103 is activated. When the sense amplifier 103 is activated, one of the bit lines DLDT and DLDB is fixed at a high level and the other is fixed at a low level.

  Also, the output latch control signal SESB falls and the output latch control inversion signal SESR rises due to the rise of the sense amplifier activation signal SES. Therefore, clocked inverter circuit CINV106 is turned on (conductive state), the potential level of bit line DLDT propagates to node QB, and data output signal Q is determined. At time t4, the output latch signal QHLD and the inverted output latch signal QHLDB are determined, and the output latch is completed.

  Since the output latch inversion signal QHLDB is determined, one of the PMOS transistors MP6 and MP7 is turned on. For example, when the bit line DLDT is fixed at a low level by activating the sense amplifier 103, the output latch inversion signal QHLDB is also at a low level, and the PMOS transistor MP6 is turned on. Since the bit line DLDT is at a low level, the PMOS transistor MP4 is turned on and the NMOS transistor MN1 is turned off. Therefore, the output latch completion determination signal QLEN rises to a high level at time t5.

  The output latch completion determination signal QLEN rising to the high level is used to generate a trigger signal for reading output data output from the semiconductor memory device 100. That is, in the example in which the bit line DLDT is at the low level, the low-level data output signal Q (value is “0”) is the value of the output data of the semiconductor memory device 100.

  Since the output latch completion determination signal QLEN becomes high level, the signal QLENB becomes low level, and the PMOS transistor MP21 is turned on. At this time, since the precharge trigger signal PCB is at a low level, the NMOS transistor MN21 is in an off state, the signal QLL is at a high level, and the signal QLLB is at a low level.

  Then, since the signal QLLB falls to the low level, the signal ILEN rises, and the output signal IPC from the NOR circuit NOR21 falls accordingly. As a result, the signal IPCB rises to a high level, and the NOR circuit NOR22 falls the sense amplifier activation signal SES to a low level. Therefore, the output latch control signal SESB rises and the output latch control inversion signal SESR falls. As a result, the clocked inverter circuit CIV106 is turned off, and the clocked inverter circuit CIV11 of the output latch circuit 104 is turned on. Since sense amplifier activation signal SES falls to a low level, sense amplifier 103 is deactivated.

  Since the output latch control signal SESB rises, the NAND circuit NAND21 falls the precharge control signal SPC at the same time as the clocked inverter circuit CIV11 is turned on. Therefore, the precharge circuit 102 is activated and precharges the bit line pair DLDT, DLDB to a high level (power supply voltage VDD).

  Then, the bit line pair DLDT and DLDB are precharged and both become high level, so that the PMOS transistors MP4 and MP5 are turned off, the NMOS transistors MN1 and MN2 are turned on, and the output latch completion determination signal QLEN is reset. A low level is reached, and a series of read operations are completed.

  As can be understood from the above operation, in the first embodiment, not only the output of the sense amplifier 103 but also the output latch signal QHLD and the output latch inversion signal QHLDB are determined, and the output latch determination circuit 105 determines the output latch completion. A signal QLEN is generated. The output latch completion determination signal QLEN is used to generate a read trigger signal for the data output signal Q. Therefore, the output of the output latch circuit 104 that has been reliably latched can be used as the output data of the semiconductor memory device 100. For this reason, it is possible to prevent erroneous reading due to output latch failure.

  Further, the output latch control signal SESB, the output latch control inversion signal SESR, and the precharge control signal SPC are generated from the determination of the output latch signal QHLD and the output latch inversion signal QHLDB. For this reason, the output latch control signal SESB, the output latch control inversion signal SESR, and the precharge control signal SPC are operated before the output latch is determined due to characteristic variations, and the clocked inverter circuits CINV106 and CINV11 are turned off, or the precharge circuit 102 Can be prevented from starting precharge, and output latch failure is prevented. Therefore, in the semiconductor memory device 100 of the first embodiment, it is possible to prevent the erroneous reading due to the output latch failure.

  Embodiment 2 of the Invention

  Hereinafter, a specific second embodiment to which the present invention is applied will be described in detail with reference to the drawings. The second embodiment is different from the first embodiment in that the semiconductor memory device is a multi-column type.

  FIG. 4 shows the configuration of the semiconductor memory device 200 according to the second embodiment. As shown in FIG. 4, the semiconductor memory device 200 includes a memory cell array 101, precharge circuits 102A and 102B, sense amplifiers 103A and 103B, an output latch circuit 204, an output latch determination circuit 105, and a clocked inverter circuit. CIV106A, CIV106B, CIV107A, CIV107B, inverter circuits IV108, IV109, bit line pairs DLDT0, DLDB0, bit line pairs DLDT1, DLDB1, and control circuits 211-214 are provided. In addition, the structure which attached | subjected the code | symbol same as FIG. 1 among the codes | symbols shown in FIG. 4 has shown the structure similar to or similar to FIG.

  The memory cell array 101 is a multiple column type, and a bit line pair DLDT0, DLDB0 and a bit line pair DLDT1, DLDB1 are connected to each other. In this example, the bit line pair in the lower column is set to DLDT0 and DLDB0, and the bit line pair in the upper column is set to DLDT1 and DLDB1.

  The precharge circuit 102A and the sense amplifier 103A are connected to the bit line pair DLDT0 and DLDB0 in the lower column, respectively. The precharge circuit 102A is the same as that of the first embodiment except that the precharge control signal SPC0 is input instead of the precharge control signal SPC, and the description of the configuration and the like is omitted. The sense amplifier 103A is the same as that in the first embodiment except that the sense amplifier 103A is activated in response to the sense amplifier activation signal SES0, and the description of the configuration and the like is omitted.

  The precharge circuit 102B and the sense amplifier 103B are connected to the bit line pair DLDT1 and DLDB1 in the upper column, respectively. The precharge circuit 102B is the same as that of the first embodiment except that the precharge control signal SPC1 is input instead of the precharge control signal SPC, and the description of the configuration and the like is omitted. The sense amplifier 103B is the same as that of the first embodiment except that the sense amplifier 103B is activated in response to the sense amplifier activation signal SES1, and the description of the configuration and the like is omitted.

  Clocked inverter circuit CIV106A has an input terminal connected to bit line DLDT0 and an output terminal connected to node QB. The clocked inverter circuit CIV106A inputs the output latch control signal SESB0 and the output latch control inversion signal SESR0 to the clock input terminal. Others are the same as those of the clocked inverter circuit CIV106 of the first embodiment.

  Clocked inverter circuit CIV107A has an input terminal connected to bit line DLDB0. The clocked inverter circuit CIV107A inputs the output latch control signal SESB0 and the output latch control inversion signal SESR0 to the clock input terminal. Others are the same as those of the clocked inverter circuit CIV107 of the first embodiment.

  Clocked inverter circuit CIV106B has an input terminal connected to bit line DLDT1, and an output terminal connected to node QB. Further, the clocked inverter circuit CIV106B inputs the output latch control signal SESB1 and the output latch control inverted signal SESR1 to the clock input terminal. Others are the same as those of the clocked inverter circuit CIV106 of the first embodiment.

  Clocked inverter circuit CIV107B has an input terminal connected to bit line DLDB1. The clocked inverter circuit CIV107B inputs the output latch control signal SESB1 and the output latch control inversion signal SESR1 to the clock input terminal. Others are the same as those of the clocked inverter circuit CIV107 of the first embodiment.

  The output latch circuit 204 includes an inverter circuit IV11, PMOS transistors MP11 to MP13, and NMOS transistors MN11 to MN13.

  Inverter circuit IV11 has an input terminal connected to node QB, and an output terminal connected to node QHLD.

  The PMOS transistor MP11 is connected between the power supply terminal VDD and the node N4, and the output latch control inversion signal SESR0 is input to the gate.

  The PMOS transistor MP12 is connected between the node N4 and the node N5, and the output latch control inversion signal SESR1 is input to the gate.

  The PMOS transistor MP13 is connected between the node N5 and the node QB, and has a gate connected to the node QHLD.

  NMOS transistor MN13 is connected between nodes N6 and QB, and has its gate connected to node QHLD.

  The NMOS transistor MP12 is connected between the node N6 and the node N7, and the output latch control signal SESB1 is input to the gate.

  The NMOS transistor MN11 is connected between the node N7 and the ground terminal GND, and the output latch control signal SESB0 is input to the gate.

  The PMOS transistor MP13 and the NMOS transistor MN13 form an inverter circuit. The PMOS transistors MP11 and MP12 and the NMOS transistors MN11 and MN12 have a switch function for supplying power to the inverter circuit. That is, when the PMOS transistors MP11 and MP12 and the NMOS transistors MN11 and MN12 are all turned on, the inverter circuit composed of the PMOS transistor MP13 and the NMOS transistor MN13 is also turned on.

  The control circuit 211 outputs a signal DLDT2 in response to signals applied to the bit lines DLDT0 and DLDT1. FIG. 5 shows the configuration of the control circuit 211. As shown in FIG. 5, the control circuit 211 includes a NAND circuit NAND31 and an inverter circuit IV31.

  NAND circuit NAND31 has one input terminal connected to bit line DLDT0 and the other input terminal connected to bit line DLDT1. Then, the NAND operation result of the signal applied to both terminals is output as a signal DLDT2B.

  The inverter circuit IV31 inputs the signal DLDT2B to the input terminal and outputs the inverted signal DLDT2 from the output terminal.

  The control circuit 212 outputs a signal DLDB2 in response to signals applied to the bit lines DLDB0 and DLDB1. FIG. 6 shows the configuration of the control circuit 212. As shown in FIG. 6, the control circuit 212 includes a NAND circuit NAND41 and an inverter circuit IV41.

  NAND circuit NAND41 has one input terminal connected to bit line DLDB0 and the other input terminal connected to bit line DLDB1. Then, the NAND operation result of the signal applied to both terminals is output as the output signal DLDB2.

  Inverter circuit IV41 receives signal DLDB2B at its input terminal and outputs its inverted output signal DLDB2 from its output terminal.

  In the output latch determination circuit 105, the output signal DLDT2 from the control circuit 211 is input to the gate of the PMOS transistor MP4, the output signal DLDB2 from the control circuit 212 is input to the gate of the PMOS transistor MP5, and the gate of the NMOS transistor MN1 is controlled. The output signal DLDT2 from the circuit 211 is input, and the output signal DLDB2 from the control circuit 212 is input to the gate of the NMOS transistor MN2. The rest is the same as in the first embodiment.

  The control circuit 213 receives the output latch completion determination signal QLEN, the precharge trigger signal PCB0, and the sense amplifier activation trigger signal SEIB0, and in response thereto, the output latch control signal SESB0 and the output latch control inversion signal SESR0. The precharge control signal SPC0 and the sense amplifier activation signal SES0 are output.

  FIG. 7 shows the configuration of the control circuit 213. As shown in FIG. 7, the control circuit 213 includes a PMOS transistor MP21A, an NMOS transistor MN21A, inverter circuits IV21A to IV26A, NOR circuits NOR21A and NOR22A, a NAND circuit NAND21A, and a clocked inverter circuit CIV21A.

  Inverter circuit IV21A receives output latch completion determination signal QLEN at its input terminal, and its output terminal is connected to node QLENB0. A signal applied to node QLENB0 is referred to as signal QLENB0.

  The PMOS transistor MP21A is connected between the power supply terminal VDD and the node QLL0, and has a gate connected to the node QLENB0.

  The NMOS transistor MN21A is connected between the node QLL0 and the ground terminal GND, and a precharge trigger signal PCB0 is input to the gate.

  Inverter circuit IV22A has an input terminal connected to node QLL0, and an output terminal connected to node QLLB0. Signals applied to nodes QLL0 and QLLB0 are referred to as signals QLL0 and QLLB0, respectively.

  Clocked inverter circuit CIV21A has an input terminal connected to node QLLB0 and an output terminal connected to node QLL0. The clocked inverter circuit CIV21A inputs the signal QLLB0 and its inverted signal to the clock terminal.

  The clocked inverter circuit CIV21A performs an inverter operation based on the signal QLLB0 as a clock signal and its inverted signal. For example, when the signal QLLB0 is at a high level, the signal input to the input terminal is inverted and output (ON state), and when the signal QLLB0 is at a low level, the output terminal is set to a high impedance state (OFF state).

  Inverter circuit IV23A has an input terminal connected to node QLLB0, and an output terminal connected to node ILEN0. A signal applied to node ILEN0 is referred to as signal ILEN0.

  In the NOR circuit NOR21A, the signal ILEN0 is input to one input terminal, and the precharge trigger signal PCB0 is input to the other input terminal. Then, the NOR calculation result is output to the node IPC0.

  Inverter circuit IV24A has an input terminal connected to node IPC0 and an output terminal connected to node IPCB0. Signals applied to the nodes IPC0 and IPCB0 are referred to as signals IPC0 and IPCB0, respectively.

  In the NOR circuit NOR22A, the signal IPCB0 is input to one input terminal, and the sense amplifier activation trigger signal SEIB0 is input to the other input terminal. Then, the NOR calculation result is output to the node SES0. When the signal applied to the node SES0 becomes the sense amplifier activation signal SES0 and becomes high level, for example, the sense amplifier 103A is activated.

  Inverter circuit IV25A has an input terminal connected to node SES0, and an output terminal connected to node SESB0. Note that the signal applied to the node SESB0 is the output latch control signal SESB0.

  In the NAND circuit NAND21A, the signal IPCB0 is input to one input terminal, and the output latch control signal SESB0 is input to the other input terminal. Then, the NAND operation result is output as a precharge control signal SPC0.

  The inverter circuit IV26A receives the output latch control signal SESB0 at its input terminal and outputs the output latch control inverted signal SESR0 from its output terminal.

  The control circuit 214 receives the output latch completion determination signal QLEN, the precharge trigger signal PCB1, and the sense amplifier activation trigger signal SEIB1, and in response thereto, the output latch control signal SESB1 and the output latch control inverted signal SESR1. The precharge control signal SPC1 and the sense amplifier activation signal SES1 are output.

  FIG. 8 shows the configuration of the control circuit 213. As shown in FIG. 8, the control circuit 213 includes a PMOS transistor MP21B, an NMOS transistor MN21B, inverter circuits IV21B to IV26B, NOR circuits NOR21B and NOR22B, a NAND circuit NAND21B, and a clocked inverter circuit CIV21B. Note that the control circuits 211 to 214 can be regarded as one control circuit.

  Inverter circuit IV21B receives output latch completion determination signal QLEN at its input terminal, and its output terminal is connected to node QLENB1. A signal applied to node QLENB1 is referred to as signal QLENB1.

  PMOS transistor MP21B is connected between power supply terminal VDD and node QLL1, and has its gate connected to node QLENB1.

  The NMOS transistor MN21B is connected between the node QLL1 and the ground terminal GND, and the precharge trigger signal PCB1 is input to the gate.

  Inverter circuit IV22B has an input terminal connected to node QLL1, and an output terminal connected to node QLLB1. Signals applied to nodes QLL1 and QLLB1 are referred to as signals QLL1 and QLLB1, respectively.

  Clocked inverter circuit CIV21B has an input terminal connected to node QLLB1, and an output terminal connected to node QLL1. Further, the clocked inverter circuit CIV21B inputs the signal QLLB1 and its inverted signal to the clock terminal.

  The clocked inverter circuit CIV21B performs an inverter operation based on the signal QLLB1 as a clock signal and its inverted signal. For example, when the signal QLLB1 is at a high level, the signal input to the input terminal is inverted and output (ON state), and when the signal QLLB1 is at a low level, the output terminal is set to a high impedance state (OFF state).

  Inverter circuit IV23B has an input terminal connected to node QLLB1, and an output terminal connected to node ILEN1. Note that a signal applied to the node ILEN1 is referred to as a signal ILEN1.

  In the NOR circuit NOR21B, the signal ILEN1 is input to one input terminal, and the precharge trigger signal PCB1 is input to the other input terminal. Then, the NOR calculation result is output to the node IPC1.

  Inverter circuit IV24B has an input terminal connected to node IPC1, and an output terminal connected to node IPCB1. Signals applied to the nodes IPC1 and IPCB1 are referred to as signals IPC1 and IPCB1, respectively.

  In the NOR circuit NOR22B, the signal IPCB1 is input to one input terminal, and the sense amplifier activation trigger signal SEIB1 is input to the other input terminal. Then, the NOR calculation result is output to the node SES1. When the signal applied to the node SES1 becomes the sense amplifier activation signal SES1, and becomes high level, for example, the sense amplifier 103B is activated.

  Inverter circuit IV25B has an input terminal connected to node SES1, and an output terminal connected to node SESB1. Note that the signal applied to the node SESB1 is the output latch control signal SESB1.

  In the NAND circuit NAND21B, the signal IPCB1 is input to one input terminal, and the output latch control signal SESB1 is input to the other input terminal. Then, the NAND operation result is output as the precharge control signal SPC1.

  The inverter circuit IV26B receives the output latch control signal SESB1 at the input terminal and outputs the output latch control inverted signal SESR1 from the output terminal.

  Hereinafter, the operation of the semiconductor memory device 200 according to the second embodiment will be described. FIG. 9 is a timing chart for explaining the operation of the semiconductor memory device 200. The data read operation of the semiconductor memory device 200 will be described with reference to FIG. However, the lower column is selected and the upper column is not selected. In the following description, the rise of each signal indicates a state in which the signal potential changes from the low level to the high level, and the fall indicates a state in which the signal potential changes from the high level to the low level.

  Here, a period T4 shown in FIG. 9 is a period from the start of reading the memory data from the memory cell array 101 to the determination of the output latch of the output latch node QHLD. Period T5 is an output latch completion determination period. A period T6 is a precharge / reset period from the completion of the output latch determination to the next cycle. In the operation of FIG. 9, the case where a lower column is selected as a premise will be described. Therefore, when the upper column is selected, the operation is performed by replacing the lower column with the upper column.

  As an initial operation, first, the precharge trigger signal PCB0 in the lower column falls. For this reason, the signal IPC0 that is the output of the NOR circuit NOR21A rises, and the precharge control signal SPC0 rises to a high level. Therefore, the precharge of the bit line pair DLDT0 and DLDB0 is released. Then, according to the value held in the selected memory cell in the lower column of the memory cell array 101, the potential of one of the bit lines DLDT0 and DLDB0 is lowered.

  When the potential difference between the bit lines DLDT0 and DLDB0 in the lower column opens, the sense amplifier activation trigger signal SEIB0 falls. For this reason, the sense amplifier activation signal SES0, which is the output of the NOR circuit NOR22A, rises and the sense amplifier 103A is activated. When the sense amplifier 103A is activated, one of the bit lines DLDT0 and DLDB0 is fixed at the high level and the other is fixed at the low level.

  Therefore, in the control circuit 211, the output DLDT2B of the NAND circuit NAND31 rises and the output DLDT2 of the inverter circuit IV31 falls.

  Further, the output latch control signal SESB0 falls and the output latch control inversion signal SESR0 rises due to the rise of the sense amplifier activation signal SES0. Therefore, clocked inverter circuit CINV 106A is turned on, the level of bit line DLDT0 is propagated to node QB, and data output signal Q is determined. However, the clocked inverter circuit CINV106B remains in the off state, and the output terminal maintains the high impedance state. At time t6, the output latch signal QHLD and the inverted output latch signal QHLDB are determined, and the output latch is completed.

  Since the output latch inversion signal QHLDB is determined, one of the PMOS transistors MP6 and MP7 is turned on. For example, when the bit line DLDT0 is fixed at the low level by activating the sense amplifier 103A, the output latch inversion signal QHLDB is also at the low level, and the PMOS transistor MP6 is turned on.

  Since the upper column is not selected, the bit line DLDT1 is at the precharge voltage (high level), and the bit line DLDT0 is at the low level, so that the output signal DLDT2 output from the control circuit 211 is at the low level. Since the signal DLDT2 is at a low level, the PMOS transistor MP4 is turned on and the NMOS transistor MN1 is turned off. Therefore, the output latch completion determination signal QLEN rises to a high level at time t7.

  The output latch completion determination signal QLEN rising to the high level is used to generate a trigger signal for reading output data output from the semiconductor memory device 200. That is, in the example in which the bit line DLDT0 is at the low level, the low-level data output signal Q (value is “0”) is the value of the output data of the semiconductor memory device 200.

  When the output latch completion determination signal QLEN becomes high level, the signal QLENB0 of the control circuit 213 becomes low level, and the PMOS transistor MP21A is turned on. At this time, since the precharge trigger signal PCB0 is at a low level, the NMOS transistor MN21A is in an off state, the signal QLL0 rises to a high level, and the signal QLLB0 falls to a low level.

  Since the signal QLLB0 falls to the low level, the signal ILEN0 rises, and in response thereto, the output signal IPC0 from the NOR circuit NOR21A falls. As a result, the signal IPCB0 rises to a high level, and the NOR circuit NOR22A causes the sense amplifier activation signal SES0 to fall to a low level. Therefore, the output latch control signal SESB0 rises and the output latch control inversion signal SESR0 falls. As a result, the clocked inverter circuit CIV106A is turned off.

  Further, the output latch control signal SESB1 from the control circuit 214 is high level, the output latch control inversion signal SESR1 is low level, the output latch control signal SESB0 is high level, and the output latch control inversion signal SESR0 is low level as described above. Therefore, the inverter circuit composed of the PMOS transistor MP13 and the NMOS transistor MN13 is turned on. Since sense amplifier activation signal SES0 falls to a low level, sense amplifier 103A is deactivated.

  Furthermore, since the output latch control signal SESB0 rises, the NAND circuit NAND21A falls the precharge control signal SPC0 at the same time as the inverter circuit composed of the PMOS transistor MP13 and the NMOS transistor MN13 is turned on. For this reason, the precharge circuit 102A is activated to precharge the bit line pair DLDT0, DLDB0 to a high level (power supply voltage VDD).

  Since the bit line pair DLDT0 and DLDB0 are precharged and become high level, high level signals DLDT2 and DLDB2 are output from the control circuits 211 and 212, respectively. Therefore, the PMOS transistors MP4 and MP5 are turned off, the NMOS transistors MN1 and MN2 are turned on, the output latch completion determination signal QLEN is reset to low level, and a series of reading operations is completed.

  Note that the upper column does not operate during the above series of operations. Accordingly, the sense amplifier activation trigger signal SEIB1, the precharge trigger signal PCB1, the output latch control signal SESB1, the precharge control signal SPC1, the bit line pair DLDT1, DLDB1, and the output signals DLDB2, DLDB2B from the control circuit 212 are always in the upper column. High level. The sense amplifier activation signal SES1 and the output latch control inversion signal SESR1 are always at a low level.

  As can be seen from the above operation, in the second embodiment, the output latch determination circuit 105 outputs not only the output of the sense amplifier of the selected column column but also the determination of the output latch signal QHLD and the output latch inversion signal QHLDB. A latch completion determination signal QLEN is generated. The output latch completion determination signal QLEN is used to generate a read trigger signal for the data output signal Q. Therefore, the output of the output latch circuit 104 that has been reliably latched can be used as the output data of the semiconductor memory device 200. For this reason, even in a semiconductor memory device having a plurality of columns, it is possible to prevent erroneous reading due to an output latch failure as in the first embodiment.

  Further, as described above, the output latch control signal SESB0, the output latch control inversion signal SESR0, and the precharge control signal SPC0 for the lower column are generated from the determination of the output latch signal QHLD and the output latch inversion signal QHLDB. For this reason, the output latch control signal SESB0, the output latch control inversion signal SESR0, and the precharge control signal SPC0 operate before the output latch is determined due to characteristic variations, and the clocked inverter circuit CINV106A is turned off or the precharge circuit 102A is precharged. Starting charging can be prevented and output latch failure is prevented. Therefore, even in a semiconductor memory device having a plurality of columns as in the second embodiment, it is possible to prevent erroneous reading due to an output latch failure as in the first embodiment.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. In the above example, the memory array cell is assumed to be SRAM, but it may be DRAM. In the second embodiment, the upper column and the lower column are two, but a plurality of column configurations may be used.

100, 200 Semiconductor memory device 101 Memory cell array 102, 102A, 102B Precharge circuit 103, 103A, 103B Sense amplifier 104 Output latch circuit 105 Output latch judgment circuit CIV106, CIV106A, CIV106B Clocked inverter circuit CIV107, CIV107A, CIV107B Clocked inverter Circuit CIV11 Clocked inverter circuit IV108, IV109 Inverter circuit DLDT, DLDB Bit line 110 Control circuit MP21, MP21A, MP21B PMOS transistor MN21, MN21A, MN21B NMOS transistors IV21-IV26 Inverter circuits IV21A-IV26A Inverter circuits IV21B-IV26B Inverter circuit NOR21, NOR22 NO Circuit NOR21A, NOR22A NOR circuit NOR21B, NOR22B NOR circuit NAND21, NAND21A, NAND21B NAND circuit MP4~MP7 PMOS transistor MN1, MN2 NMOS transistor MP11~MP13 PMOS transistor MN11~MN13 NMOS transistor 211 to 214 control circuit

Claims (13)

A cell array in which a plurality of memory cells are arranged;
Complementary bit line pairs provided corresponding to the memory cell columns;
A precharge circuit for precharging the bit line pair to a predetermined potential before data reading;
In a semiconductor memory device comprising a sense amplifier connected to the bit line pair and detecting and amplifying data stored in a selected memory cell when activated,
An output latch circuit for latching the output of the sense amplifier;
A semiconductor memory device comprising: an output latch determination circuit that determines latch completion based on an output of the sense amplifier that performs an amplification operation and an output of the output latch circuit. The output latch determination circuit includes first to sixth switch circuits,
The first and second switch circuits are connected in series between a first power supply terminal and a first node,
The first switch circuit is controlled to be turned on and off in accordance with one potential level of the bit line pair.
The second switch circuit is controlled to be turned on and off according to the output of the output latch circuit,
The third and fourth switch circuits are connected in series between the first power supply terminal and the first node,
The third switch circuit is controlled to be turned on / off according to the other potential level of the bit line pair,
The fourth switch circuit is controlled to be turned on and off according to the inverted output of the output latch circuit.
The fifth and sixth switch circuits are connected in series between the first node and a second power supply terminal,
The fifth switch circuit is controlled to be turned on and off in accordance with one potential level of the bit line pair.
The sixth switch circuit is controlled to be turned on / off according to the other potential level of the bit line pair,
The semiconductor memory device according to claim 1, wherein a determination result of the output latch determination circuit is output from the first node. Each of the first to fourth switch circuits is composed of a first conductivity type transistor,
The semiconductor memory device according to claim 2, wherein each of the fifth and sixth switch circuits includes a second conductivity type transistor. A control circuit;
The control circuit includes:
In response to a sense amplifier activation trigger signal, the sense amplifier is activated by a first control signal,
The precharge operation of the precharge circuit is stopped by a second control signal in response to the precharge trigger signal,
In response to the determination result of the output latch determination circuit, the sense amplifier is deactivated by the first control signal, and the precharge circuit is precharged by the second control signal. ,
4. The semiconductor memory device according to claim 1, wherein the output latch determination circuit resets a determination result of the output latch determination circuit according to a precharge voltage of the bit line pair. 5. A first clocked inverter circuit;
The first clocked inverter circuit is connected between the output of the sense amplifier and the output latch circuit, and controls activation or deactivation of the sense amplifier output from the control circuit. 5. The semiconductor memory device according to claim 4, wherein the semiconductor memory device is controlled to be conductive or nonconductive between the output of the sense amplifier and the output latch circuit in response to a third control signal based on the control signal. The output latch circuit includes a first inverter circuit and a second clocked inverter circuit, a second node connected to the output of the sense amplifier, and an inverted signal of the second node Is connected to the third node from which
The output of the first inverter circuit and the input of the second clocked inverter circuit are connected to a second node, and the output of the second clocked inverter circuit and the input of the first inverter circuit are third. Connected to
The second clocked inverter circuit includes the second node and the third node when the first clocked inverter circuit is turned off in response to the third control signal. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is controlled to conduct. A cell array in which a plurality of memory cells are arranged;
Complementary first and second bit line pairs respectively provided corresponding to the first or second column column of which one is selected,
A first precharge circuit for precharging the first bit line pair to a predetermined potential before data reading in response to a first precharge control signal;
A second precharge circuit for precharging the second bit line pair to a predetermined potential before data reading in response to a second precharge control signal;
A first sense amplifier connected to the first bit line pair and detecting and amplifying data stored in a selected memory cell at the time of activation when a corresponding column row is selected;
A semiconductor memory device comprising: a second sense amplifier connected to the second bit line pair and detecting and amplifying storage data of a selected memory cell when activated when a corresponding column column is selected;
An output latch circuit for latching the output of the first or second sense amplifier of the selected column row;
A semiconductor memory device comprising: an output latch determination circuit that determines latch completion based on an output of the first or second sense amplifier that performs an amplification operation of a selected column row and an output of the output latch circuit. A control circuit;
The control circuit includes:
A first control signal corresponding to one potential level of the first bit line pair and one potential level of the second bit line pair;
Generating a second control signal according to the other potential level of the second bit line pair and the other potential level of the second bit line pair;
The output latch determination circuit includes first to sixth switch circuits,
The first and second switch circuits are connected in series between a first power supply terminal and a first node,
The first switch circuit is controlled to be turned on and off according to the first control signal,
The second switch circuit is controlled to be turned on and off according to the output of the output latch circuit,
The third and fourth switch circuits are connected in series between the first power supply terminal and the first node,
The third switch circuit is controlled to be turned on and off according to the second control signal,
The fourth switch circuit is controlled to be turned on and off according to the inverted output of the output latch circuit.
The fifth and sixth switch circuits are connected in series between the first node and a second power supply terminal,
The fifth switch circuit is controlled to be turned on and off according to the first control signal,
The sixth switch circuit is controlled to be turned on and off according to the second control signal,
8. The semiconductor memory device according to claim 7, wherein a determination result of the output latch determination circuit is output from the first node. Each of the first to fourth switch circuits is composed of a first conductivity type transistor,
9. The semiconductor memory device according to claim 8, wherein each of the fifth and sixth switch circuits includes a second conductivity type transistor. The control circuit includes:
In response to the sense amplifier activation trigger signal, the first or second sense amplifier of the column column selected by the third control signal is activated,
In response to the precharge trigger signal, the precharge operation of the first or second precharge circuit in the column column selected by the fourth control signal is stopped,
According to the determination result of the output latch determination circuit, the third control signal deactivates the first or second sense amplifier of the selected column column, and the fourth control signal The first or second bit line pair is precharged by the first or second precharge circuit of the selected column column;
The semiconductor memory device according to claim 8, wherein the output latch determination circuit resets a determination result of the output latch determination circuit in accordance with the first and second control signals. A first and a second clocked inverter circuit;
The first clocked inverter circuit is connected between the output of the first sense amplifier and the output latch circuit, and the second clocked inverter circuit is connected to the output of the second sense amplifier and the output of the second sense amplifier. Connected to the output latch circuit,
Select according to a fifth control signal based on the third control signal that controls the activation or deactivation of the first or second sense amplifier of the selected column column output from the control circuit 11. The output of the first or second sense amplifier and the output latch circuit are controlled to be conductive by turning on the first or second clocked inverter circuit of the selected column column. The semiconductor memory device described in 1. The output latch circuit includes first and second inverter circuits, and seventh to tenth switch circuits, and a second node connected to the outputs of the first and second sense amplifiers And a third node from which an inverted signal of the second node is output,
The output of the first inverter circuit and the input of the second inverter circuit are connected to the second node, and the output of the second inverter circuit and the input of the first inverter circuit are connected to the third node. Connected with
The second inverter circuit is supplied with a voltage from the first power supply terminal via the seventh and eighth switch circuits connected in series, and the ninth and tenth connected in series. The voltage from the second power supply terminal is supplied via the switch circuit of
The seventh and ninth switch circuits are turned off when the first clocked inverter circuit is turned on according to the fifth control signal,
The eighth and tenth switch circuits are turned off when the second clocked inverter circuit is turned on according to the fifth control signal,
The seventh to tenth switch circuits are turned on when the first and second clocked inverter circuits are turned off in response to the fifth control signal. The semiconductor memory device described. Each of the seventh and eighth switch circuits is composed of a first conductivity type transistor,
The semiconductor memory device according to claim 12, wherein each of the ninth and tenth switch circuits includes a second conductivity type transistor.

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