JP2012089182A - Semiconductor memory device - Google Patents

Abstract

In a negative word line type semiconductor memory device, the potential of an unselected word line is stabilized.
In a semiconductor memory device (50) including at least one memory block (60), a first negative potential generating circuit (64) for outputting a first negative potential and a second negative potential are output. The second negative potential generating circuit (65), the first discharge path (25) between the word line (13) and the first negative potential in the memory block, the word line (13) and the second And a second discharge path (21) between the negative potential.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor memory device, and more particularly to a negative word line type semiconductor memory device.

  A negative word line type dynamic memory is known as a memory that suppresses channel leakage current of transistors constituting a dynamic memory cell and improves the charge retention characteristics of the memory cell. In particular, in a DRAM mixed system LSI in which a logic circuit, an analog circuit, and a dynamic memory (hereinafter referred to as DRAM) are mounted on the same silicon substrate, a DRAM for a logic circuit transistor or an analog circuit transistor is used. As a result, the process for forming the memory cell transistor is required to be made as low as possible and the cost is reduced, and the degree of freedom in forming the memory cell transistor is extremely limited.

  Therefore, in order to obtain the desired read / write characteristics and charge retention characteristics required for DRAM, means for controlling the gate voltage of the memory cell transistor to a negative potential and suppressing the channel leakage current include transistors for logic circuits and This is effective in obtaining the necessary characteristics as a DRAM while ensuring compatibility with the analog circuit transistor.

  FIG. 13 is a configuration diagram of an example of a conventional negative word line type DRAM (see, for example, Patent Document 1). There are four memory blocks MBa, MBb, MBc, and MBd on the same chip. Each memory block includes memory cell blocks 100a, 100b, 100c, and 100d, row selection system blocks 101a, 101b, 101c, and 101d, and a column decoder 102a. , 102b, 102c, 102d. Since it is a negative word line system, a negative potential is supplied to the source voltage of the transistor that drives the L level of the word line driving circuit of the row selection system blocks 101a, 101b, 101c, and 101d. Each memory block MBa, MBb, MBc, MBd decodes the address signal group Add to determine the memory block to be accessed, the row address, and the column address.

  The corresponding switch circuits 103a, 103b, 103c, and 103d are controlled by the block selection signals BSa, BSb, BSc, and BSd output from the block selection circuit 104, and negative as a negative potential signal supplied to the row selection system block. Switching control of the output Vbb1 of the potential generation circuit 105 or the output Vbb2 of the negative potential generation circuit 106 is performed.

  Here, a relationship of Vbb1 <Vbb2 is assumed. For example, when the memory block MBa is selected as the memory block to be accessed, the “disturb refresh” state is set and Vbb1 is supplied. Further, the other memory blocks (MBb, MBc, MBd) are not selected, and are in a “pause refresh” state, and Vbb2 is supplied.

  With such a configuration, compared to the case where the low negative potential Vbb1 is supplied to all the memory blocks, the low Vbb1 is supplied only to the selected block, and the high Vbb2 is supplied to the other non-selected blocks. Power consumption can be suppressed.

  However, in the conventional configuration, since the negative potential is switched in units of memory blocks, for example, when the memory block MBa is switched from the non-selected state to the selected state, it is necessary to discharge from the high negative potential Vbb2 to the low negative potential Vbb1. A large number of word line driving circuits to which negative potentials are supplied (for the number of word lines) exist and are connected as a common source, so that a capacitive load is very large. For this reason, the time to reach the predetermined low negative potential Vbb1 increases, and an inaccessible period occurs when the memory block is switched.

  Alternatively, in order to complete the transition to Vbb1 within a predetermined time, it is necessary to increase the current supply capability of the negative potential generating circuit 105. However, the circuit area of the negative potential generating circuit 105 and the power consumption are increased. Has the disadvantage of inviting.

  On the other hand, for example, when the memory block MBa is switched from the selected state to the non-selected state, the low negative potential Vbb1 is switched to the high negative potential Vbb2. In general, the negative potential generation circuit has a mechanism for raising the low negative potential to the high negative potential. It is not provided, and there is no choice but to wait for a predetermined potential due to the leak current. If the memory block in the “pause refresh” state remains at a low negative potential Vbb1, there is a disadvantage that the substrate current due to the electric field in the vicinity of the drain called GIDL (Gate Induced Drain Current) increases, leading to deterioration of charge retention characteristics. .

  Further, for example, in the selected memory block MBa, when the active word line is reset to the inactive state, if the word line charged to H level is discharged to a low negative potential Vbb1, the negative potential Vbb1 A phenomenon occurs in which the potential rises. This is because a common source potential for driving the L level of the plurality of word line driving circuits rises. In particular, there is a drawback that the L level of the adjacent word line rises, the channel leakage current increases, and the charge retention characteristics are deteriorated.

  FIG. 14 is a configuration diagram of an example of a conventional negative word line type word line driving circuit (see, for example, Patent Document 2). The word line driving circuit includes a three-input NAND gate 200, PMOS transistors 201 and 202, and NMOS transistors 203, 204, and 205. The output terminal NI of the NAND gate 200 is connected to the gate of the transistor 201, the source of the transistor 202, and the gate of the transistor 205. The source of the transistor 201 is connected to the power supply Vcc, and the drain is connected to the word line 13. The drain of the transistor 202 is connected to the drain of the transistor 203 and the gate of the MOS transistor 204, and the word line pull-down signal / WPDWN is supplied to the gate. The source and back gate of the transistor 203 are connected to the negative potential Vbb, and the gate is connected to the word line 13. The source and back gate of the transistor 204 are connected to Vbb, and the drain is connected to the word line 13. The source of the transistor 205 is connected to the power supply Vss, the drain is connected to the word line 13, and the back gate is connected to Vbb.

  The transistor 205 is a first pull-down circuit for lowering the potential of the active word line 13 from the Vcc level to the Vss level to make it inactive, and functions as a first discharge circuit. The transistor 204 is a second pull-down circuit for lowering the potential of the inactive word line 13 from the Vss level to the Vbb level, and functions as a second discharge circuit.

  When the word line 13 is reset, the node NI is first set to H level, the potential of the word line 13 is changed from Vcc to Vss, then / WPDLW is changed to L level, the transistor 204 is turned on, and the potential of the word line 13 is changed from Vss to Vbb. To discharge.

  By operating as described above, the charge of the word line 13 charged to Vcc is once discharged to Vss and then to Vbb, so that the capability of the negative potential generation circuit can be reduced. The circuit area and power consumption of the negative potential generating circuit can be reduced.

Japanese Patent Laid-Open No. 7-307091 Japanese Patent Laid-Open No. 10-241361

  The channel leak characteristic of the memory cell transistor is very sensitive to the gate voltage as shown in FIG. 15, and the channel leak current increases exponentially with changes in the gate voltage. Therefore, even when the potential of the word line 13 is discharged from Vss to Vbb, fluctuation of Vbb which is a common source occurs due to the discharge charge. That is, in the conventional semiconductor memory device shown in FIG. 14, Vbb is supplied to the word line 13 from the common negative potential generating circuit regardless of whether the word line 13 is selected or not. For this reason, a change in Vbb due to the reset operation of the selected word line 13 is recorded as noise on the unselected word line 13. In general, the current supply capability of the negative potential generating circuit is relatively small, and the output impedance is equivalently high. Furthermore, a negative potential is generated by using the charge pump circuit while detecting the potential level of Vbb. However, if the responsiveness to detect the potential level is poor, the changed Vbb is recovered to a predetermined potential. It will take time. As described above, when Vbb varies at the time of resetting the active word line, the negative potential level of the inactive word line is increased, and charge retention characteristics are deteriorated.

  In a negative word line type DRAM, in order to solve the above-described problem and to improve and stabilize the charge retention characteristic, the sum of leak current components with respect to the storage node of the memory cell (channel leak current and GIDL current of the memory cell transistor, It is important to set a bias condition that minimizes storage node junction leakage current, capacitor leakage current, and the like. In particular, it is indispensable to suppress the influence on the unselected word line due to the potential fluctuation when the word line having high sensitivity to the leakage current transitions from the active state to the inactive state.

  In view of the above, an object of the present invention is to stabilize the potential of an unselected word line in a negative word line type semiconductor memory device.

  In order to solve the above problems, the present invention has taken the following solutions. For example, in a semiconductor memory device including at least one memory block, a first negative potential generation circuit that outputs a first negative potential, a second negative potential generation circuit that outputs a second negative potential, and a memory The block includes a first discharge path between the word line and the first negative potential, and a second discharge path between the word line and the second negative potential.

  According to this, for example, the address-selected word line can be connected to the second negative potential, and the address non-selected word line can be connected to the first negative potential. The fluctuation of the second negative potential when transitioning to the logic L level can be prevented from propagating to the first negative potential, and the potential of the unselected word line can be stabilized.

  For example, the first negative potential generation circuit includes a reference potential generation circuit, a voltage detection circuit for comparing and detecting the output signal of the reference potential generation circuit and the first negative potential, an oscillator circuit for self-oscillation, and a voltage detection circuit And a first charge pump circuit that operates in conjunction with the output signal of the oscillator circuit, and performs a pumping operation asynchronously with the row address cycle of the memory block. The second negative potential generating circuit has a second charge pump circuit that operates in synchronization with the word line enable signal and outputs a second negative potential.

  According to this, a negative potential is generated intermittently in the negative potential generation circuit. That is, since a negative potential is generated only when necessary, power consumption of the semiconductor memory device can be reduced. Further, the second negative potential generating circuit does not require an oscillator or the like for generating a charge pump pulse, and the layout area can be reduced.

  Furthermore, the current supply capability of the second negative potential generation circuit may be higher than the current supply capability of the first negative potential generation circuit. In this case, the semiconductor memory device has switch means for connecting the output terminal of the first negative potential generating circuit and the output terminal of the second negative potential generating circuit during the operation preparation period. It may be.

  According to this, since the time until the output of the first negative potential generating circuit with low drive capability becomes the first negative potential is shortened during the operation preparation period of the semiconductor memory device, the semiconductor memory device is quickly activated. To do.

  Preferably, the first negative potential is supplied to the plurality of memory blocks. Since the current supply capability of the first negative potential generation circuit may be lower than the current supply capability of the second negative potential generation circuit, the first negative potential generation circuit supplies the first to a plurality of memory blocks. Negative potential can be supplied. Therefore, the number of first negative potential generating circuits can be reduced as much as possible, and thereby the circuit scale of the entire semiconductor memory device can be reduced.

  According to the present invention, in the negative word line type semiconductor memory device, the potential of the non-selected word line is stabilized and the leakage current of the memory cell can be suppressed. Thereby, the charge retention characteristics of the memory cell are improved.

1 is a configuration diagram of a main part of a semiconductor memory device according to an embodiment of the present invention. 2 is a timing chart of the word line driver of FIG. 4 is another timing chart of the word line driver of FIG. 1. 1 is a configuration diagram of a semiconductor memory device according to an embodiment. FIG. 5 is a configuration diagram of the negative potential generation circuit of FIG. 4. It is a block diagram which shows another example of FIG. FIG. 6 is another configuration diagram of the negative potential generation circuit 65 of FIG. 5. It is a block diagram of the semiconductor memory device which concerns on another embodiment. It is a block diagram which shows the structure of the switch means of FIG. FIG. 9 is a configuration diagram of the negative potential generation circuit 67 of FIG. 8. It is a block diagram of the pulse generation circuit of FIG. 11 is a timing chart of the negative potential generation circuit of FIG. 10. It is a block diagram of the conventional semiconductor memory device. It is a block diagram of the conventional word line drive circuit. It is a graph showing the channel leak characteristic of a memory cell.

  FIG. 1 is a configuration diagram of a main part of a semiconductor memory device according to an embodiment of the present invention. A plurality of the main parts are assembled to constitute a row address selection system circuit and a memory cell array of the semiconductor memory device.

  The memory cell 10 includes one NMOS transistor 11 and one capacitor 12. Access to the memory cell 10 is performed by controlling the word line 13 connected to the gate of the transistor 11. A low potential VBB is applied to the substrate potential of the transistor 11 of the memory cell 10. When the word line 13 is at the H level, writing and reading operations to the capacitor 12 are performed via the bit line 14. On the other hand, when the word line 13 is at the L level, the data written in the capacitor 12 is held.

  In the data holding state of the memory cell 10, the charge holding characteristic may be deteriorated when the bit line 14 is in the disturb refresh state where the L level is in the negative word line system in which the L level potential of the word line 13 is a negative potential. By adopting, channel leakage current of the transistor 11 can be suppressed.

  In the negative word line system, the threshold voltage of the transistor 11 can be set lower than in the normal word line system in which the L level potential of the word line 13 is the ground potential. That is, since the H level potential of the word line 13 necessary for fully writing the H level to the capacitor 12 can be set low, the power consumption of the boost power supply VPP that supplies the H level potential of the word line 13 is reduced. be able to. In addition, since the amount of channel injection for controlling the threshold value of the transistor 11 can be reduced, variation in threshold voltage can be suppressed.

  The word line driver 20 and the row decoder 30 have the functions of the row selection systems 101a to 101d shown in FIG. Based on the predecode signals XAn, XBn, and XCn, the row decoder 30 instructs the word line driver 20 to select and deselect the address of the word line 13 with the address selection signal AD and the address non-selection signal NAD. Further, based on the word line enable signals WDEN and XAn, XBn, and XCn, the word line driver 20 is instructed by the word line drive signal NWL whether to activate or deactivate the word line 13. The row decoder 30 is a decode circuit 31 to which XAn, XBn, and XCn are input, an inverter circuit 32 that logically inverts an output NAD of the decode circuit 31, a logical operation of the output AD of the inverter circuit 32 and WDEN, and outputs NWL The NAND circuit 33 can be configured.

The word line driver 20 drives the word line 13 according to the outputs NWL, AD, NAD of the row decoder 30. The word line driver 20 includes an inverter and discharge paths 21 and 25. The inverter can be composed of a PMOS transistor 22 and an NMOS transistor 23. The transistor 22 is controlled to conduct when NWL is at L level. As a result, the word line 13 is driven and the potential becomes VPP. The transistor 23 is conduction controlled when NWL is at H level. Therefore, word line 13 is activated when NWL is at L level, and its potential WL is at H level. On the other hand, when NWL is at H level, the word line 13 is inactivated and WL is at L level.

  Discharge path 21 is provided between word line 13 and negative potential VNB2. The discharge path 21 includes NMOS transistors 23 and 24, and pulls down the potential of the word line 13 to VNB2. The transistor 24 is conduction controlled when AD is at the H level. The discharge path 25 is provided between the word line 13 and VNB1. The discharge path 25 includes an NMOS transistor 26, and pulls down the potential of the word line 13 to VNB1 higher than VNB2. The transistor 26 is conduction controlled when NAD is at H level. As will be described later, VNB1 and VNB2 are output from different negative potential generation circuits.

  Next, the operation of the word line driver 20 will be described with reference to FIG. First, XAn, XBn, and XCn are generated based on the external address Xadd at the rising edge of the clock signal CLK. In the period of Rate1, when NAD is at H level by the combination of XAn, XBn, and XCn, AD is at L level. That is, the address of the word line 13 is not selected. From time t1 to t2, WDEN is at H level, but AD remains at L level and NWL remains at H level. Therefore, the transistor 24 is turned off, the transistor 26 is turned on, and the word line 13 is pulled down to VNB1 and is inactive. That is, the potential WL of the word line 13 is at the L level.

  When NAD transitions to L level according to the combination of XAn, XBn, and XCn during the period of Rate2, AD also transitions to H level. That is, the address of the word line 13 is selected. Accordingly, the transistor 26 is turned off at time t3. Then, the transistor 24 is turned on with a delay corresponding to the inversion operation of the inverter circuit 32, and WL becomes VNB2. Here, WL becomes VNB2, but the channel leakage current of the transistor 12 of the memory cell 10 tends to be suppressed when the gate potential is negative as shown in FIG. Therefore, VNB2 may be set to a potential that does not significantly increase with respect to the GIDL current.

  Returning to FIG. 2, at time t4, when WDEN changes to H level and NWL changes to L level, transistor 22 is turned on, transistor 23 is turned off, WL becomes H level, and word line 13 is activated. It becomes. At time t5, when NWL changes to the H level, the transistor 22 is turned off and the transistor 23 is turned on. Further, since AD is at the H level, the transistor 24 is on and WL becomes VNB2. At this time, the electric charge of the word line 13 charged to VPP flows into VNB2 all at once, causing a potential fluctuation of VNB2, but the other unselected word line 13 is connected to VNB1 and not connected to VNB2. Therefore, the potential of the unselected word line 13 does not fluctuate. Instead of discharging all the charges on the word line 13 to VNB2, it is also possible to discharge most of the charges to the ground potential and then discharge to VNB2.

  In the period of Rate 3, NAD transitions to the H level and AD transitions to the L level at time t6. As a result, the transistor 24 is turned off and WL becomes VNB1. Here, the timing at which NAD transitions to the H level is earlier than the timing at which AD transitions to the L level by an amount corresponding to the delay time of the inverter circuit 32. Therefore, the transistor 24 and the transistor 26 are simultaneously turned on for a period corresponding to the delay time. Since VNB2 <VNB1, VNB1 is slightly lowered, but the channel leakage current of the transistor 12 of the memory cell 10 is suppressed as described above. Further, since VNB2 never becomes higher than VNB1, there is no problem.

  Next, n1 and n2 indicated by WL in FIG. 2 will be described. n1 and n2 are noises generated in the word line when the negative potential VNB1 is supplied to the selected word line and the non-selected word line from only one negative potential generation circuit as in the conventional semiconductor memory device. In the conventional semiconductor memory device, as shown in FIG. 2, when WDEN, AD, and NAD transition from the H level to the L level, the L level potential of WDEN, AD, and NAD slightly increases. As a result, like n1 and n2, the potential of the non-selected word line temporarily changes in the vicinity of times t2, t3, t5, and t6. In particular, around time t5, WL changes from VPP to VNB1 due to the reset operation of the selected word line, so that the potential level of VNB1 changes more greatly. Noise is superimposed on the unselected word lines due to such potential fluctuation of VNB1.

  On the other hand, in the semiconductor memory device according to the present embodiment, VNB1 and VNB2 are supplied from different negative potential generation circuits, so that the above-described noise can be suppressed.

  As described above, since the negative potential level of the unselected word line 13 is stabilized, the leakage current of the memory cell 10 is suppressed, and the charge retention characteristics of the memory cell 10 are improved.

  It is desirable that the H level potential of NAD, AD, and NWL is VPP and the L level potential is VNB2. One of the purposes is to prevent a through current from flowing through the word line driver 20. Another object is to eliminate the influence on VNB1 by supplying the ground potential of the row decoder 30 to VNB2, and to supply more stable VNB1 to the unselected word line 13.

  In the present embodiment, VNB1 and VNB2 need only be output from different negative potential generation circuits, so VNB2> VNB1 may be satisfied, but VNB2 ≦ VNB1 is preferable. FIG. 3 shows a timing chart when VNB1 and VNB2 are equal. As shown in FIG. 3, it is only necessary that VNB2 is supplied to the selected word line 13 from time t3 to time t5 and from time t7 to time t8. Thus, even if VNB1 and VNB2 are equal, the potential of the unselected word line 13 can be stabilized.

  The row decoder 30 may include a level conversion function. For example, it may be configured to have a function of converting the output amplitude to a level from VNB2 to VPP with respect to the level from the ground potential VSS to the low power supply potential VDD.

  In the transistor 26, when the gate potential is VNB2, the source potential is VNB1, the drain potential is VPP, and VNB2 is higher than VNB1, a drain-source current is generated. However, by setting VNB2 <VNB1, there is no leakage current, and the H level potential can be stably supplied to the word line 13.

  FIG. 4 is a configuration diagram of a semiconductor memory device according to one embodiment. The semiconductor memory device 50 is represented by a logic circuit block 51 typified by digital signal processing and a microcontroller, an analog circuit block 52 typified by an AD converter, a DA converter, a PLL circuit, etc., and a DRAM. A plurality of memory blocks 60 and a single negative potential generating circuit 64 for supplying a negative potential VNB1 to each memory block 60 are mounted, which is a typical system-on-chip configuration. The memory block 60 is provided with one negative potential generating circuit 65 that supplies VNB2.

  Although not shown, the memory block 60 includes a plurality of memory cells arranged in a matrix, a plurality of word line drivers, and a plurality of row decoders. The memory block 60 includes a so-called SRAM interface that completes a write or read operation in synchronization with CLK. Note that the present invention is not limited to the SRAM interface, and other interfaces such as an SDRAM interface may be provided.

  As shown in FIG. 5, the negative potential generation circuit 64 can be composed of a reference potential generation circuit 70, a voltage detection circuit 71, an oscillator circuit 72, a pulse generation circuit 73, and a charge pump circuit 74.

  The reference potential generation circuit 70 generates a reference voltage VREF1. The voltage detection circuit 71 compares VREF1 and VNB1, and outputs a control signal PUMPEN1 when | VREF1 |> | VNB1 |. The oscillator circuit 72 generates a self-excited oscillation clock OSC1 when PUMPEN1 is enabled. The cycle of OSC1 is set relatively long with respect to the random access cycle to the memory block 60. Pulse generation circuit 73 outputs pulse signal PULS1 at a predetermined frequency when receiving OSC1. The charge pump circuit 74 outputs VNB1 when PULS1 is output from the pulse generation circuit 73.

  Although not shown in detail, the charge pump circuit 74 is assumed to be configured by a so-called Dickson type charge pump circuit that transfers charges using an n-layer PULS 1. Further, it is desirable that the amount of charge supplied by the charge pump circuit 74 in one pumping operation be as small as possible in order to suppress potential fluctuations with respect to VNB1. Then, the circuit area of the charge pump circuit 74 can be reduced.

  Here, VNB1 is an important parameter that determines the charge retention characteristics of the memory cell. Therefore, high voltage level accuracy is required for VNB1, and it is necessary to suppress potential fluctuations of VNB1 as much as possible. Therefore, in the present embodiment, the potential variation due to VNB2 can be blocked by generating VNB1 by the negative potential generation circuit 64. The current supply capability of the negative potential generation circuit 64 only needs to be sufficient to cover the leakage current of the word line driver, that is, not less than the total leakage current of each memory block 60. Further, since the negative potential generation circuit 64 does not need to cope with instantaneous current consumption, the allowable range for response is wide. Therefore, the power consumption of the negative potential generating circuit 64 and the circuit area can be reduced, and the degree of freedom of the arrangement position in the semiconductor memory device 50 can be improved.

  The negative potential generation circuit 65 can be composed of a pulse generation circuit 83 and a charge pump circuit 84. The pulse generation circuit 83 outputs the pulse signal PULS2 during the L period of WDEN. Although not shown in detail, for example, a one-shot pulse synchronized with the falling edge of WDEN can be applied to the pulse signal PULS2. The charge pump circuit 84 outputs VNB2 when receiving PULS2. The charge pump circuit 84 is set so that the amount of charge supplied in one pumping operation is larger than that of the charge pump circuit 74. Although not shown in detail, the charge pump circuit 84 is assumed to be configured by a so-called Dixon type charge pump circuit that transfers charges using n-layer PULS2.

  VNB2 is supplied when the active word line is reset. When the word line is reset, the memory cell transitions to a precharge state. The reset operation speed of the word line is one factor that determines the random access cycle. Since the number of word lines activated in each random access cycle is unique and the load current consumed is constant, the negative potential generation circuit 65 is synchronized with the reset timing of the word line in each random access cycle. It is desirable that VNB2 corresponding to the consumed charge can be supplied. In order to supply VNB2 so as to suppress the delay as much as possible following the reset timing of the word line, the current supply capability of the negative potential generation circuit 65 is increased, the negative potential generation circuit 65, the word line driver, It is necessary to reduce the wiring resistance between the two. Therefore, the current supply capability of the negative potential generation circuit 65 is made larger than the current supply capability of the negative potential generation circuit 64. Further, by providing the negative potential generating circuit 65 in the memory block 60, the supply path to each circuit to which VNB2 is supplied can be shortened, and the wiring resistance can be reduced. As a result, the supply path of VNB 2 can be optimized, optimal current supply capability and responsiveness can be ensured, and uniform characteristics can be obtained in the memory block 60.

  Such negative potential generation circuits 64 and 65 can improve and stabilize the charge retention characteristics of the memory block 60 and improve the responsiveness of supplying VNB2. The reference voltage generation circuit 70, the voltage detection circuit 71, and the oscillator circuit 72 may be omitted. In this case, the charge pump circuit 74 is operated in an event driven manner synchronized with the random access cycle. As a result, even if the negative potential generating circuit 65 is mounted in each memory block 60, the increase in circuit area is slight.

  In the configuration of FIG. 4, the number ratio of the memory block 60 and the negative potential generation circuit 64 is 4: 1, but is not limited to this, and may be 5: 1 or 10: 2. It may be arbitrarily set according to the relationship between the leakage current of the memory block 60 and the current supply capability of the negative potential generation circuit 64. The number ratio of the memory block 60 and the negative potential generation circuit 65 may not be 1: 1. For example, one negative potential generation circuit 65 may be mounted on two or more memory blocks 60. Preferably, the number of negative potential generation circuits 64 is smaller than the number of negative potential generation circuits 65. Furthermore, the current supply capability of the negative potential generating circuit 65 may be arbitrarily set for each corresponding memory block 60 according to the scale, the operating frequency, and the like.

  As described above, according to the present embodiment, the parasitic resistance component between the word line and the negative potential generating circuit 65 can be reduced, the driving load of the negative potential generating circuit 65 can be reduced, and the charge, which is a performance index as a DRAM. The holding characteristics can be stabilized.

  Note that by adopting the negative word line method, the substrate potential VBB of the transistor 11 of the memory cell 10 shown in FIG. 1 can be set to a relatively shallow potential. Therefore, as shown in FIG. VNB1 may be supplied as the substrate potential of the transistor 11. In this case, a circuit for generating VBB in the semiconductor memory device 50 can be omitted, and the circuit area can be reduced and the power consumption can be reduced. In addition, it becomes easy to share the substrate potential with VNB1, which is the potential of the unselected word line. Even in this way, the substrate potential of the memory cell 10 does not affect the VNB 1 because it has no large current path and is stable with a sufficient parasitic capacitance component.

-Modification of negative potential generation circuit-
FIG. 7 is a block diagram showing a modification of the negative potential generating circuit 65 of FIG. The negative potential generation circuit 66 can be composed of a reference potential generation circuit 80, a voltage detection circuit 81, an oscillator circuit 82, a pulse generation circuit 83, and a charge pump circuit 84.

  The reference potential generation circuit 80 generates a reference voltage VREF2. The voltage detection circuit 81 compares VREF2 and VNB2, and outputs a control signal PUMPEN2 when | VREF2 |> | VNB2 |. The oscillator circuit 82 generates a self-excited oscillation clock OSC2. The pulse generation circuit 83 receives OSC2, WDEN, and PUMPEN2, and outputs PULS2 in synchronization with the falling edge of WDEN when PUMPEN2 is enabled. The charge pump circuit 84 receives PULS2 and outputs VNB2.

  The negative potential generation circuit 66 operates the OSC 2 for a plurality of cycles during the L level period of WDEN using the oscillator circuit 82, but in synchronization with the falling edge of WDEN without using the oscillator circuit 82. The structure which generate | occur | produces PULS2 may be sufficient. In this case, the pumping cycle of the charge pump circuit 84 is set short with respect to the charge pump circuit 74.

  By adopting such a configuration, the output cycle of VNB2, which consumes a large amount of charge, can be accurately synchronized with the random access cycle of the DRAM, and the necessary amount of charge can be supplied as VNB2. On the other hand, as VNB1 with a small amount of consumed electric charge, it is sufficient to supply the amount of charge mainly determined by the leakage current characteristics of the MOS transistor. can do. Therefore, the response characteristic of the voltage detection circuit 71 can be delayed, and the current consumed by the negative potential generation circuit 64 can be suppressed.

  FIG. 8 is a configuration diagram of a semiconductor memory device according to another embodiment. Hereinafter, differences from the above embodiment will be described. The logic circuit block 51 and the analog circuit block 52 are omitted.

  The memory block 60 includes a memory cell array 90 composed of a plurality of memory cells 10, a word line driver block 91 composed of a plurality of word line drivers 20 and a row decoder 30, a negative potential generation circuit 67, and switch means 92. And. The negative potential generation circuit 64 supplies VNB 1 in common to the substrate potential of the memory cell array 90 in each memory block 60 and the word line driver block 91. The negative potential generation circuit 67 supplies VNB2 to the word line driver block 91.

  The switch means 92 is controlled according to the switch control signal NRST. Specifically, the switch unit 92 includes the output terminal of the negative potential generation circuit 64 and the output terminal of the negative potential generation circuit 67 during the operation preparation period from when the power of the semiconductor memory device 50 is turned on to when the operation starts. Is set to a conductive state, and is set to a non-conductive state after the operation is started. As shown in FIG. 9, for example, the switch means 92 includes an inverter circuit 92a and an NMOS transistor 92b. Thus, VNB1 is complemented with VNB2 when NRST is at the L level. In order to obtain a sufficient cut-off characteristic of the NMOS transistor 92b, the L level of the inverter circuit 92a is preferably VNB2.

  FIG. 10 is a block diagram according to the negative potential generating circuit of this embodiment. The negative potential generation circuit 67 uses a pulse generation circuit 85 instead of the pulse generation circuit 83 of FIG. In addition to WDEN, NRST is input to the pulse generation circuit 85.

  The pulse generation circuit 85 can be configured as shown in FIG. Specifically, the OR circuit 85c performs a logical operation on WDEN and a signal obtained by inverting the output of the delay element 85a that delays WDEN for a predetermined time by the inverter circuit 85b, and outputs a one-shot pulse signal WLRST synchronized with WDEN. The pulse width of WLRST is determined by the delay time of the delay element 85a. WLRST and NRST that becomes L level during a certain period after power-on are input to OR circuit 85f via inverter circuits 85d and 85e, respectively. Output signals PUMPEN3, OSC2, and PUMPEN2 of the OR circuit 85f are input to the AND circuit 85g. The AND circuit 85g outputs a pumping clock PUMPCK2 as a result of logical operation of PUMPEN3, OSC2, and PUMPEN2. The pulse generation unit 85h generates PULS2 for operating the charge pump circuit 84 when PMUPCK2 is output.

  The operation of the negative potential generating circuit 67 will be described with reference to FIG. When the power supply VDD is turned on at time t0, VDD gradually rises at time t1 and stabilizes at a predetermined potential. At time t1, the operation of the circuit is started in response to the VDD being turned on, and VREF2 and VNB2 are compared by the voltage detection circuit 81. Until VNB2 reaches a predetermined potential, PUMPEN2 is at H level. The oscillator circuit 82 performs self-excited oscillation and generates OSC2. In response to the fact that NRST that is at the L level for a certain period after the power is turned on is at the L level, PUMPEN3 becomes the H level. Therefore, PUMPCK2 is output from the AND circuit 85g. When PUMPCK2 is output, PULS2 is generated and a charge pump operation is performed.

  When VNB2 reaches a predetermined level at time t2, PUMPEN2 becomes L level. In response to PUMPEN2 becoming L level, PUMPCK2 is fixed to L level, and the pumping operation is stopped.

  At time t3, NRST becomes H level, and in response, PUMPEN3 becomes L level. When the time t3 is earlier than the time t2, the NRST becomes the H level without the VNB2 reaching the predetermined level, and the switch unit 92 is cut off. Desirably, time t3 is made later than time t2.

  After the time t3, the normal operation period of the negative potential generating circuit 67 is shown. NRST is at the H level, and the switch means 92 is in the OFF state. In response to WDEN becoming H level at time t4 and WDEN becoming L level at time t5, VNB2 is lifted. When the voltage detection circuit 81 detects the potential fluctuation of VNB2, PUMPEN2 becomes H level. In response to the falling edge of WDEN, WLRST is generated and PUMPEN3 becomes H level. The pulse width of WLRST is the same width as the period from time t5 to time t7.

  Since both PUMPEN2 and PUMPEN3 become H level at time t5, PUMPCK2 is supplied through OSC2, and the charge pump circuit 84 starts the pumping operation. When it is detected that the potential of VNB2 has reached a predetermined set voltage VREF2 at time t6, PUMPEN2 becomes L level and the pumping operation is stopped.

  The operation of the negative potential generating circuit 67 after time t3 operates independently in each memory block.

  Here, the negative potential generation circuit 64 always repeats the charge pump operation until VNB1 reaches VREF1, but the current supply capability is low and the load capacity of the memory block 60 is very large. Therefore, only the operation of the negative potential generating circuit 64 may take a very long time to bring VNB1 to a predetermined potential level. In this embodiment, VNB1 is commonly supplied to the substrate potential of each memory cell array 90 and each word line driver block 91. However, even if the configuration is such that each word line driver block 91 is supplied with VNB1 sufficiently large. Since the load capacity is connected, it is not a solution to shortening the time.

  Therefore, as described above, during the operation preparation period, each negative potential generation circuit 67 is also operated simultaneously, and VNB1 is supplemented with VNB2 via the switch means 92, so that the current supply capability of the negative potential generation circuit 64 is remarkably increased. Can be improved. That is, it is possible to greatly reduce the waiting time from when the power is turned on to when the operation of the memory block 60 starts. Although not shown in detail, it is desirable to set the potentials of VREF1 and VREF2 to be the same while the switch means 92 is on. Further, it is desirable that the potential at this time is adjusted to the one having a smaller absolute value during normal operation.

  As described above, according to the present embodiment, the operation preparation period can be shortened. That is, the semiconductor memory device 50 starts up quickly.

  Since the semiconductor memory device according to the present invention is excellent in the charge retention characteristics of the memory cell, it is useful for various electronic devices.

10 memory cell 13 word line 20 word line driver 21 discharge path (first discharge path)
23 NMOS transistor (second switch element)
24 NMOS transistor (first switch element)
25 Discharge path (second discharge path)
26 NMOS transistor (switch element)
50 Semiconductor memory device 60 Memory block 64 Negative potential generation circuit (second negative potential generation circuit)
65, 66, 67 Negative potential generation circuit (first negative potential generation circuit)
70 Reference Potential Generation Circuit 71 Voltage Detection Circuit 72 Pulse Generation Circuit 74 Charge Pump Circuit (Second Charge Pump Circuit)
84 Charge pump circuit (first charge pump circuit)

Claims (11)

A semiconductor memory device comprising at least one memory block,
A first negative potential generating circuit for outputting a first negative potential;
A second negative potential generating circuit for outputting a second negative potential;
A first discharge path between a word line in the memory block and the first negative potential;
A semiconductor memory device comprising a second discharge path between the word line and the second negative potential. The semiconductor memory device according to claim 1.
The first discharge path has a switch element whose conduction is controlled according to a decode signal of an address decoder,
2. The semiconductor memory device according to claim 1, wherein the logic L level potential of the decode signal is the second negative potential. The semiconductor memory device according to claim 1.
The second discharge path is:
A first switch element, one end of which is connected to the second negative potential and whose conduction is controlled according to a decode signal of an address decoder;
A second switch element connected between the other end of the first switch element and the word line and controlled to be conductive in accordance with a word line drive signal;
2. The semiconductor memory device according to claim 1, wherein a logic L level potential of the decode signal and the word line drive signal is the second negative potential. The semiconductor memory device according to claim 1.
The semiconductor memory device, wherein the second negative potential is equal to or lower than the first negative potential. The semiconductor memory device according to claim 1.
The semiconductor memory device, wherein the first negative potential is supplied to a plurality of memory blocks. The semiconductor memory device according to claim 5.
The semiconductor memory device, wherein the first negative potential is supplied as a substrate potential of each memory cell in the memory block. The semiconductor memory device according to claim 1.
A semiconductor memory device, wherein one of the second negative potential generation circuits is provided in each of a plurality of memory blocks. The semiconductor memory device according to claim 1.
The first negative potential generation circuit includes:
A reference potential generation circuit;
A voltage detection circuit for comparing and detecting an output signal of the reference potential generation circuit and a first negative potential;
An oscillator circuit that self-oscillates;
A first charge pump circuit that operates in response to the output signal of the oscillator circuit in response to the output signal of the voltage detection circuit;
Pumping operation asynchronously with the row address cycle of the memory block,
The semiconductor memory device, wherein the second negative potential generation circuit has a second charge pump circuit that operates in synchronization with a word line enable signal and outputs the second negative potential. The semiconductor memory device according to claim 8.
2. The semiconductor memory device according to claim 1, wherein a current supply capability of the second negative potential generation circuit is higher than a current supply capability of the first negative potential generation circuit. The semiconductor memory device according to claim 8.
A semiconductor memory device, wherein a pumping cycle of the first charge pump circuit is longer than a pumping cycle of the second charge pump circuit. The semiconductor memory device according to claim 9.
A semiconductor memory device comprising switch means for connecting an output terminal of the first negative potential generating circuit and an output terminal of the second negative potential generating circuit during an operation preparation period of the semiconductor memory device .

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