JP2012084564A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

[Problem] To keep the conventional equipment and processing process as much as possible and suppress the increase in cost, but easily and reliably process Ta-containing conductive materials as desired without generating difficult-to-removable residual deposits. A highly reliable semiconductor device is realized.
A Ta-containing layer, a TiN layer, and a layer capable of dry etching such as a polycrystalline silicon film are sequentially stacked on a semiconductor substrate, and the polycrystalline silicon film is dry-etched using the TiN layer as an etching stopper to have a predetermined shape. In addition, the TiN layer and the Ta-containing layer are wet-etched using SPM, APM or the like to leave a predetermined shape under the polycrystalline silicon film.
[Selection] Figure 8

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and is suitable for application to a field effect transistor (MIS-FET) or the like.

  In recent years, with the miniaturization of semiconductor devices typified by MIS-FETs, introduction of metal materials as gate electrode materials in place of semiconductor polycrystalline silicon has been studied. In the MIS-FET provided with a gate electrode (metal gate) using a metal material, the effective film thickness of the gate insulating film can be reduced, so that high performance is realized.

As a next-generation FET equipped with a metal gate, a metal-inserted polysilicon gate (Metal Inserted Poly-Si) using a high dielectric constant material for the gate insulating film and a gate electrode layered structure of a metal film and a polycrystalline silicon film Stacks: MIPS) FETs have been devised. Application of this MIPS-FET to a CMOS-FET is being studied. For example, it is conceivable to individually adjust the threshold voltage by inserting different types of metals into the gate electrodes of nMOS-FET and pMOS-FET.
In addition, the use of tungsten (W) or the like in place of the polycrystalline silicon in the MIPS-FET has been studied.

Zhibo Zhang, SC Song, Craig Huffman, Muhammad M. Hussain, Joel Barnett, Naim Moumen, Husam N. Alshareef, Prashant Majhi, Johnny H. Sim, Sang Ho Bae, and Byoung Hun Lee: Electrochemical and Solid-State Letters, 8 10 G271-G274 2005 Muhammad Mustafa Hussain, Naim Moumen ,, Joel Barnett, Jason Saulters, David Baker, and Zhibo Zhang: Electrochemical and Solid-State Letters, 8 12 G333-G336 2005 F. Ootsuka, Y. Tamura, Y. Akasaka, S. Inumiya, H. Nakata, M. Ohtsuka, T. Watanabe, M kitajima, Y. Nara and K. Nakamura: Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, Yokohama, 2006, pp. 1116-1117

However, the MIPS-FET has the following problems.
Many of the metal materials that are being studied for introduction into the gate electrode of MIPS-FET are chemicals used in the cleaning process of the semiconductor manufacturing process (sulfuric acid / hydrogen peroxide mixed solution, ammonia / hydrogen peroxide mixed solution, hydrochloric acid / peroxide). Vulnerable to hydrogen mixed solution.

  In the MIPS-FET manufacturing process, it is difficult to dry-etch the metal material of the gate electrode. As this metal material, in particular, a Ta-containing conductive material (TaN, TaSiN, TaC, TaCN, etc.) is used. However, when dry etching is performed, a large amount of residual deposits that are difficult to remove are generated on the resist. It adheres to the surface of the semiconductor substrate such as the side surface of the gate electrode. In addition, when performing gate processing, it is required to vertically process two types of conductive materials (polycrystalline silicon and metal, W and metal, etc.) having different properties by dry etching. Therefore, a significant change is required in the processing process by dry etching, and there is a problem that costs for development of a new processing process and development and introduction of the new equipment are required.

  The present invention has been made in view of the above-mentioned problems, and succeeds in existing equipment and processing processes as much as possible to suppress an increase in cost. An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same that can be processed as desired without causing the generation of defects.

  In one embodiment of a method for manufacturing a semiconductor device, a first layer made of a Ta-containing conductive material, a second layer made of TiN, and a third layer capable of dry etching are sequentially stacked above a semiconductor substrate. A step of patterning the third layer by dry etching using the second layer as an etching stopper, and the second layer and the first layer using the patterned third film as a mask. Wet etching to leave a part of the second layer and the first layer below the third layer.

  One aspect of the semiconductor device includes a semiconductor substrate and a gate electrode formed above the semiconductor substrate via a gate insulating film, and the gate electrode includes a first layer made of a Ta-containing conductive material; A second layer made of TiN and a third layer made of polycrystalline silicon are sequentially stacked.

  According to the above-described aspects, the conventional equipment and processing process are inherited as much as possible to suppress the increase in cost, but the Ta-containing conductive material is processed as desired without generating difficult-to-removable residual deposits. In addition, a highly reliable semiconductor device and a method for manufacturing the same can be realized easily and reliably.

It is a characteristic view which shows the result of having investigated about the film thickness dependence of the side etching rate with respect to SPM and APM about a TiN layer. It is a schematic sectional drawing which shows the manufacturing method of MIPS-CMOS by this embodiment in order of a process. FIG. 3 is a schematic cross-sectional view showing the MIPS-CMOS manufacturing method according to the present embodiment in the order of steps, following FIG. 2. FIG. 4 is a schematic cross-sectional view showing the MIPS-CMOS manufacturing method according to the present embodiment in the order of steps, following FIG. 3. FIG. 5 is a schematic cross-sectional view subsequent to FIG. 4 showing the MIPS-CMOS manufacturing method according to the present embodiment in the order of steps. FIG. 6 is a schematic cross-sectional view showing the MIPS-CMOS manufacturing method according to the present embodiment in the order of steps, following FIG. 5; 7 is a schematic cross-sectional view subsequent to FIG. 6 showing the MIPS-CMOS manufacturing method according to the present embodiment in the order of steps. FIG. FIG. 8 is a schematic cross-sectional view showing the MIPS-CMOS manufacturing method according to the present embodiment in the order of steps, following FIG. 7. It is a schematic sectional drawing which shows a mode that the TiN layer was laminated | stacked and formed on the Ta content layer. It is a schematic sectional drawing shown.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In the present embodiment, a CMOS-FET to which a MIPS-FET is applied as a semiconductor device (hereinafter simply referred to as MIPS-CMOS) is illustrated as an example. The configuration will be described together with the manufacturing method.

(Etching processing of components having conductive material containing Ta)
In the present embodiment, a Ta-containing conductive material (TaN, TaSiN, TaC, TaCN, etc.) is applied to the constituent members of the MIPS-FET. As a specific form of application, a layer made of TiN (hereinafter simply referred to as a TiN layer) is formed on a layer of a Ta-containing conductive material (hereinafter simply referred to as a Ta-containing layer), and on that layer. Assume a laminate in which a layer of a material that can be dry-etched (hereinafter simply referred to as an upper layer) is formed.

  As described above, when the Ta-containing conductive material is dry-etched, a large amount of residual deposits that are difficult to remove are generated and adhere to the surface of the semiconductor substrate such as the side surface of the gate electrode on the resist. Therefore, when the Ta-containing conductive material is deposited in the vicinity of the surface of the semiconductor substrate where the residual deposits have an adverse effect, dry etching is not suitable for the processing. On the other hand, the Ta-containing conductive material has a certain resistance to sulfuric acid / hydrogen peroxide mixed solution (SPM), ammonia / hydrogen peroxide mixed solution (APM), hydrochloric acid / hydrogen peroxide mixed solution (HPM), and the like. However, it is relatively easy to dissolve in APM. If the Ta-containing conductive material is wet-etched, it can be processed without causing residual deposits. For this reason, wet etching using APM as an etching solution is suitable for processing a Ta-containing conductive material.

  In general, TiN is considered extremely vulnerable to SPM, APM and the like. In this embodiment, if TiN is formed to be thin to some extent, the formed TiN layer has an etching rate in the horizontal direction (lateral direction) (side etching rate) with respect to SPM, APM, etc., in the vertical direction (vertical direction). We have found that it is extremely lower than In this embodiment, based on this fact, a TiN layer is provided between the Ta-containing layer and the upper layer to form a laminate.

For the TiN layer, the film thickness dependence of the side etching rate with respect to SPM and APM was examined. The experimental results are shown in FIG.
In this experiment, polycrystalline silicon was stacked on TiN deposited by sputtering, and the side etching rate of wet etching of the TiN layer was measured. As an etching solution, SPM is 96% sulfuric acid: 31% hydrogen peroxide solution = 4: 1, about 80 ° C., and APM is 29% ammonia water: 31% hydrogen peroxide water: water = 3: 3: 40, about Used as 60 ° C.

  From FIG. 1, it can be seen that both the SPM and APM have a significantly reduced side etching rate compared to the etching rate in the vertical direction (bulk). The degree of reduction in the side etching rate depends on the thickness of the TiN layer, and the thinner the thickness, the lower the dissolution rate. In particular, in an extremely thin TiN layer having a thickness of 10 nm or less, the dissolution rate is extremely slow, being several nm / min or less. It is difficult to form a TiN layer with a thickness of less than 0.5 nm due to the limitations caused by the film forming apparatus and the properties of TiN. From the above, by forming the TiN layer to a thickness of 0.5 nm to 10 nm, the side etch amount of the TiN layer can be suppressed to about several nm for an etching time of about 1 minute to 10 minutes. confirmed.

  In the TiN layer formed in the above laminate, it is required to wet-etch the Ta-containing layer and the TiN layer as desired while reliably holding the dry-etched upper layer. Therefore, in wet etching using SPM and / or APM, the TiN layer is preferably formed to a thickness of 0.5 nm to 5 nm, more preferably 0.5 nm to 2 nm.

  In addition, the upper layer is made of a material having a lower etching rate of dry etching than TiN. In this case, the TiN layer functions as an etching stopper when the upper layer is dry-etched. If there is no etching stopper, the Ta-containing layer is slightly over-etched by dry etching of the upper layer. At this time, a residual deposit of the Ta-containing layer is generated, and its adhesion to the vicinity of the surface of the semiconductor substrate is inevitable. In this embodiment, since the TiN layer functions as an etching stopper, the Ta-containing layer is covered with the TiN layer when the dry etching of the upper layer is completed. Therefore, the generation of residual deposits in the Ta-containing layer is prevented.

As described above, in the present embodiment, the TiN layer is formed to a thickness of 0.5 nm to 5 nm, more preferably 0.5 nm to 2 nm to form the stacked body.
First, the upper layer is dry-etched using the TiN layer as an etching stopper. At this time, the Ta-containing layer is protected by the TiN layer, and the occurrence of residual deposits on the Ta-containing layer is prevented.
Subsequently, the TiN layer and the Ta-containing layer are wet-etched using SPM, APM, or both solutions. When both liquids are used, first, most of the TiN layer and the resist material and etching products used during dry etching are removed by SPM. Furthermore, it is effective to remove most of the Ta-containing layer and the SPM liquid and particles remaining on the wafer by performing APM treatment. At this time, the amount of side etching of the TiN layer is small, and the Ta-containing layer (and TiN layer) remains in a desired shape while the upper layer is stably held.

Furthermore, the following facts were found in the experiment of FIG.
When SPM was used as the etching solution, it was confirmed that when the film thickness of the TiN layer was 5 nm or less, there was an offset time during which the TiN layer was hardly side-etched. This offset time was about 2 minutes.

In this embodiment, this fact may be used.
A TiN layer is formed to a thickness of 0.5 nm to 5 nm to form a stacked body.
First, the upper layer is dry-etched using the TiN layer as an etching stopper. At this time, the Ta-containing layer is protected by the TiN layer, and the occurrence of residual deposits on the Ta-containing layer is prevented. Subsequently, using the SPM, the etching time is set within about 2 minutes, and the TiN layer and a part of the Ta-containing layer are wet-etched. Further, the Ta-containing layer is almost peeled off by APM treatment for about 5 minutes. At this time, the TiN layer is hardly side-etched, and the Ta-containing layer (and the TiN layer) remains in a desired shape while the upper layer is securely held stably. Even if the etching time of the wet etching is set longer than the offset time of 2 minutes, if the etching time is about several minutes (about 10 minutes or less), the side etching rate reduction phenomenon shown in FIG. The side etch amount of the layer can be kept small.

(Specific embodiment)
Hereinafter, the MIPS-CMOS manufacturing method according to the present embodiment will be described in detail based on the above-described etching process of the constituent member having the Ta-containing layer.
2 to 8 are schematic cross-sectional views showing the MIPS-CMOS manufacturing method according to the present embodiment in the order of steps.

First, as shown in FIG. 2A, an element isolation structure 11 is formed on a silicon semiconductor substrate 10 by, for example, an STI (Shallow Trench Isolation) method.
Specifically, the P ⁻ -type silicon semiconductor substrate 10 is processed by lithography and dry etching to form an isolation groove 11 a in an element isolation region on the semiconductor substrate 10.
An insulator such as silicon oxide (SiO ₂ ) is deposited on the semiconductor substrate 10 by a CVD method or the like so as to fill the isolation trench 11a. The silicon oxide is polished until the surface of the semiconductor substrate 10 is exposed, and is planarized by, for example, chemical mechanical polishing (CMP). Thereby, the element isolation structure 11 formed by filling the isolation trench 11a with silicon oxide is formed. By forming the element isolation structure 11, an active region, here, a P-type active region 12 a and an N-type active region 12 b are defined on the semiconductor substrate 10.

Subsequently, as shown in FIG. 2B, an N-type well 13 is formed in the P-type active region 12a.
Specifically, an N-type impurity such as phosphorus (P) is ion-implanted only in the P-type active region 12a under the conditions of a dose amount of 5 × 10 ¹² / cm ² and an acceleration energy of 450 keV. An N-type well 13 is formed.

Subsequently, as shown in FIG. 2C, a gate insulating film 14 is formed.
Specifically, a high dielectric constant material such as HfSiON or HfO ₂ is deposited on the semiconductor substrate 10 to a thickness of about 1.5 nm to ₃ nm by a low pressure CVD (LPCVD) method or the like. As a result, the gate insulating film 14 is formed on the semiconductor substrate 10.
As the gate insulating film, instead of using a high dielectric constant material, an insulator such as silicon oxide or silicon oxynitride (SiON) is formed on the semiconductor substrate 10 with a film thickness of about 1 nm to 10 nm by a thermal oxidation method or a CVD method. It may be formed by depositing.

Subsequently, as shown in FIGS. 2D and 9A, a gate metal film 15 is formed.
More specifically, a Ta-containing conductive material, here TaN (Ta: N = 1: 1) for a P-type gate is formed on the gate insulating film 14 by a sputtering method or the like, with a film thickness of about 0.5 nm to 10 nm, here 3 nm. Deposit to a degree. Thereby, the TaN layer 15a is formed.
On the TaN layer 15a, TiN (Ti: N = 1: 1) is deposited by sputtering or the like to a film thickness of about 0.5 nm to 10 nm, here about 5 nm. Thereby, the TiN layer 15b is formed.
As described above, as shown in FIG. 9A, the gate metal film 15 in which the TiN layer 15b is laminated on the TaN layer 15a is formed. In FIG. 2D, for convenience of illustration, the gate metal film 15 is illustrated as a single layer.

Subsequently, as shown in FIG. 3A, a hard mask 16 is formed.
Specifically, on the gate metal film 15, a mask material for wet etching of the gate metal film 15, here, silicon nitride (SiN) is formed by raw material Si ₂ Cl ₆ + NH _{3 at} a temperature of 450 ° C. by LPCVD or the like. Under conditions, the film is deposited to a thickness of about 10 nm to 30 nm. Thereby, the hard mask 16 is formed.

Subsequently, as shown in FIG. 3B, a resist mask 17 is formed.
Specifically, a resist is applied on the hard mask 16, and the resist is processed by lithography. As a result, a resist mask 17 is formed above the semiconductor substrate 10 to cover the P-type active region 12a and expose the N-type active region 12b.

Subsequently, as shown in FIG. 3C, the hard mask 16 is dry-etched.
Specifically, the resist mask 17 is used, the TiN layer 15b of the gate metal film 15 is used as an etching stopper, and the hard mask 16 is patterned by dry etching, here, reactive ion etching (RIE). This RIE is performed by generating an inductively coupled plasma with a total pressure of 40 mTorr and an etching gas of CF ₄ / Ar mixed gas. As a result, the hard mask 16 has its portion on the N-type active region 12b removed and only the portion on the P-type active region 12a covered with the resist mask 17 remains. In the N-type active region 12b, the TiN layer 15b is exposed, and the TaN layer 15a of the gate metal film 15 is covered and protected by the TiN layer 15b. Therefore, the TaN layer 15a is not subjected to RIE, and the occurrence of TaN residual deposits is reliably prevented.

Subsequently, as shown in FIG. 3D, the resist mask 17 is removed.
More specifically, the resist mask 17 is removed by ashing using, for example, O ₂ plasma.

Subsequently, as shown in FIG. 4A, the gate metal film 15 is wet-etched.
Specifically, the gate metal film 15 is wet etched using the hard mask 16 using SPM and / or APM as an etchant. SPM is 96% sulfuric acid: 31% hydrogen peroxide solution = 4: 1 and is used at about 80 ° C. APM is 29% ammonia water: 31% hydrogen peroxide water: water = 3: 3: 40, and is used at about 60 ° C. The wet etching is performed for 1 minute to 2 minutes using SPM, and then performed for 52 minutes to 10 minutes using APM. Alternatively, APM is used for 5 minutes to 10 minutes. When APM is used as the etchant, the etching rate of the TaN layer 15a is about 1 nm / min.

  The TiN layer 15b has a very low side etching rate with respect to the etching solution. Accordingly, in this wet etching, the side etch amount of the portion of the TiN layer 15 b covered with the hard mask 16 is small, and the hard mask 16 is reliably held on the gate metal film 15. As a result, the gate metal film 15 remains in a desired shape following the hard mask 16 while the hard mask 16 is stably held without causing the generation of residual deposits of TaN.

Subsequently, as shown in FIGS. 4B and 9B, a gate metal film 18 is formed.
Specifically, a Ta-containing conductive material on the gate insulating film 14 including the hard mask 16, here, TaSiN for an N-type gate (Ta: Si: N = 1: 1.5 to 2.5: 1 to 3) Is deposited to a film thickness of about 0.5 nm to 10 nm, here about 1.5 nm by sputtering or the like. Thereby, the TaSiN layer 18a is formed.
On the TaSiN layer 18a, TiN (Ti: N = 1: 1) is deposited to a film thickness of about 0.5 nm to 10 nm, here about 5 nm by sputtering or the like. Thereby, the TiN layer 18b is formed.
As a result, as shown in FIG. 9B, the gate metal film 18 in which the TiN layer 18b is laminated on the TaSiN layer 18a is formed. In FIG. 4B, for convenience of illustration, the gate metal film 18 is illustrated as a single layer.

Subsequently, as shown in FIG. 4C, a hard mask 19 is formed.
More specifically, a mask material for wet etching of the gate metal film 18 on the gate metal film 18, here, SiN is formed by LPCVD or the like, with a raw material Si ₂ Cl ₆ + NH ₃ , a temperature of 450 ° C., and a film thickness of 10 nm. Deposits to about 30 nm. Thereby, the hard mask 19 is formed.

Subsequently, as shown in FIG. 4D, a resist mask 21 is formed.
Specifically, a resist is applied on the hard mask 19 and the resist is processed by lithography. As a result, a resist mask 21 that covers the N-type active region 12b and exposes the P-type active region 12a over the semiconductor substrate 10 is formed.

Subsequently, as shown in FIG. 5A, the hard mask 19 is dry-etched.
Specifically, the resist mask 21 is used, and the hard mask 19 is patterned by dry etching, here RIE, using the TiN layer 18b of the gate metal film 18 as an etching stopper. This RIE is performed by generating an inductively coupled plasma with a total pressure of 40 mTorr and an etching gas of CF ₄ / Ar. As a result, the hard mask 16 is removed from the portion on the P-type active region 12a, and only the portion on the N-type active region 12b covered with the resist mask 17 remains. In the P-type active region 12a, the TiN layer 18b is exposed, and the TaSiN layer 18a of the gate metal film 18 is covered and protected by the TiN layer 18b. Therefore, the TaSiN layer 18a is not subjected to RIE, and the occurrence of TaSiN residual deposits is reliably prevented.

Subsequently, as shown in FIG. 5B, the resist mask 21 is removed.
Specifically, the resist mask 21 is removed by ashing using, for example, O ₂ plasma.

Subsequently, as shown in FIG. 5C, the gate metal film 18 is wet-etched.
Specifically, the gate metal film 18 is wet-etched using the hard mask 19 using SPM and / or APM as an etchant. SPM is 96% sulfuric acid: 31% hydrogen peroxide solution = 4: 1 and is used at about 80 ° C. APM is 29% ammonia water: 31% hydrogen peroxide water: water = 3: 3: 40, and is used at about 60 ° C. The wet etching is performed for 1 minute to 2 minutes using SPM, and then performed for 10 minutes to 30 minutes using APM. Alternatively, APM is used for 10 minutes to 30 minutes. When APM is used as the etching solution, the etching rate of the TaSiN layer 18a is about 0.3 nm / min.

  The TiN layer 18b has a very low side etching rate with respect to the etching solution. Therefore, in this wet etching, the side etch amount of the TiN layer 18b in the portion covered with the hard mask 19 is small, and the hard mask 19 is reliably held on the gate metal film 18. Thereby, the gate metal film 18 remains in a desired shape following the hard mask 19 in a state where the hard mask 19 is stably held without causing generation of residual deposits of TaSiN.

Subsequently, as shown in FIG. 5D, the hard masks 16 and 19 are removed.
Specifically, the hard masks 16 and 19 are removed, for example, by dry etching using RIE or wet etching using dilute hydrofluoric acid.

Subsequently, as shown in FIG. 6A, a polycrystalline silicon film 22 is deposited.
Specifically, a polycrystalline silicon film 22 is deposited to a thickness of about 40 nm to 80 nm on the semiconductor substrate 10 so as to cover the gate metal films 16 and 18 by LPCVD or the like.

Subsequently, as shown in FIG. 6B, a hard mask 23, an antireflection film 24, and resist masks 25a and 25b are sequentially formed.
More specifically, a mask material for wet etching of the gate metal film 15 or 18 on the polycrystalline silicon film 22, here SiN is formed by the LPCVD method or the like under conditions of raw material Si ₂ Cl ₆ + NH ₃ and a temperature of 450 ° C. Deposited to a film thickness of about 30 nm to 70 nm. Thereby, the hard mask 23 is formed. The hard mask may be formed using SiO ₂ instead of SiN.

  After an antireflection film (BARC) 24 is formed on the hard mask 23, a resist is applied on the antireflection film 24, and the resist is processed by lithography. As a result, a resist mask 25 a is formed above the gate metal film 15 and a resist mask 25 b is formed above the gate metal film 18.

Subsequently, as shown in FIG. 6C, the antireflection film 24 is wet-etched and the resist masks 25a and 25b are slimmed.
Specifically, the antireflection film 24 is wet etched using the resist masks 25a and 25b. At this time, the resist masks 25a and 25b are also etched and slimmed into electrode shapes.

Subsequently, as shown in FIG. 6D, the hard mask 23 and the polycrystalline silicon film 22 are dry-etched.
Specifically, the resist masks 25a and 25b are used, and the hard mask 23 and the polycrystalline silicon film 22 are patterned by dry etching, here RIE, using the TiN layers 15b and 18b of the gate metal films 15 and 18 as etching stoppers. This RIE is performed by generating an inductively coupled plasma by using a mixed gas of O ₂ / CF ₄ / HBr / Cl ₂ with an etching gas at a total pressure of ₄ mTorr. As a result, only the portions of the hard mask 23 and the polycrystalline silicon film 22 covered with the resist masks 25a and 25b remain. In the P-type active region 12a, the TaN layer 15a of the gate metal film 15 is covered and protected by the TiN layer 15b. In the N-type active region 12b, the TaN layer 18a of the gate metal film 18 is covered and protected by the TiN layer 18b. Therefore, the TaN layers 15a and 18a are not RIE, and the occurrence of TaN and TaSiN residual deposits is reliably prevented.

Subsequently, as shown in FIG. 7A, the resist masks 25a and 25b and the antireflection film 24 are removed.
Specifically, the resist masks 25a and 25b and the antireflection film 24 are removed by ashing using, for example, O ₂ plasma.

Subsequently, as shown in FIG. 7B, the gate metal films 15 and 18 are wet-etched.
Specifically, the gate metal films 15 and 18 are wet-etched using SPM and / or APM as an etchant and using the polycrystalline silicon film 22 as a hard mask. SPM is 96% sulfuric acid: 31% hydrogen peroxide solution = 4: 1 and is used at about 80 ° C. APM is 29% ammonia water: 31% hydrogen peroxide water: water = 3: 3: 40, and is used at about 60 ° C. The wet etching is performed for 1 minute to 2 minutes using SPM, and then for 1 minute to 10 minutes using APM. Alternatively, APM is used for 1 to 10 minutes.

  The TiN layers 15b and 18b have a very low side etching rate with respect to the etching solution. Therefore, in this wet etching, the side etch amount of the portions of the TiN layers 15 b and 18 b covered with the hard mask 23 is small, and the hard mask 23 is reliably held on the gate metal films 15 and 18. As a result, the gate metal films 15 and 18 remain in a desired shape following the hard mask 23 in a state where the hard mask 23 is stably held without generating dry etching residue deposits of TaN and TaSiN.

Subsequently, as shown in FIG. 7C, the residue obtained by wet etching of the gate insulating film 14 and the slightly remaining metal gates 15a and 18a is dry-etched.
Specifically, using the hard mask 23 (and the polycrystalline silicon film 22) as a mask, the gate insulating film 14 is patterned by dry etching, here RIE. This RIE is performed by generating an inductively coupled plasma with a total pressure of 10 mTorr and an etching gas of BCl ₃ + Cl ₂ + Ar. As a result, only portions of the gate insulating film 14 covered with the gate metal films 15 and 18 remain. In this RIE, the hard mask 23 is also removed. As described above, on the semiconductor substrate 10, the gate electrode 20a having the MIPS structure via the gate insulating film 14 is formed on the P-type active region 12a, and the MIPS structure is formed on the N-type active region 12b by the gate insulating film 14. Each of the gate electrodes 20b is formed. The gate electrode 20a is formed by laminating a polycrystalline silicon film 22 on the gate metal film 15 in the P-type active region 12a. The gate electrode 20b is formed by laminating a polycrystalline silicon film 22 on the gate metal film 18 in the N-type active region 12b.

Subsequently, as shown in FIG. 7D, a first sidewall insulating film 26 is formed.
More specifically, an insulating film such as SiO ₂ is deposited on the entire surface of the semiconductor substrate 10 so as to cover the gate electrodes 20a and 20b. The entire surface of this SiO ₂ is subjected to anisotropic dry etching (etch back). As a result, SiO ₂ remains only on the side surfaces of the gate electrodes 20a and 20b, and the first sidewall insulating film 26 is formed.

Subsequently, as shown in FIG. 8A, extension regions 27a and 27b are formed.
Specifically, a resist mask that covers the N-type active region 12b and exposes the P-type active region 12a is formed, and an N-type impurity such as arsenic (As ⁺ ) is dosed into the P-type active region 12a using the resist mask. Ion implantation is performed under the conditions of 1 × 10 ¹⁵ / cm ² and acceleration energy of 3 keV, whereby extension regions 27 a are formed on both sides of the gate electrode 20 a of the P-type active region 12 a in the semiconductor substrate 10. The extension region 27 a is formed in alignment with the first sidewall insulating film 26. The resist mask is removed by ashing or the like.

A resist mask that covers the P-type active region 12a and exposes the N-type active region 12b is formed, and using this resist mask, a P-type impurity such as boron (B ⁺ ) is dosed to the N-type active region 12b at a dose of 1 × 10 ^15. Ion implantation is performed under the conditions of / cm ² and acceleration energy of 4 keV, whereby extension regions 27 a are formed on both sides of the gate electrode 20 b of the N-type active region 12 b in the semiconductor substrate 10. The extension region 27b is formed in alignment with the first sidewall insulating film 26. The resist mask is removed by ashing or the like.

Subsequently, as shown in FIG. 8B, a second sidewall insulating film 28 is formed.
Specifically, an insulating film such as SiO ₂ is deposited on the entire surface of the semiconductor substrate 10 so as to cover the gate electrodes 20a and 20b and the first sidewall insulating film 26. The entire surface of this SiO ₂ is etched back. As a result, SiO ₂ remains so as to cover only the first sidewall insulating film 26 of the gate electrodes 20a and 20b, and the second sidewall insulating film 28 is formed.

Subsequently, as shown in FIG. 8C, source / drain regions 29a and 29b are formed.
Specifically, a resist mask that covers the N-type active region 12b and exposes the P-type active region 12a is formed, and using this resist mask, an N-type impurity such as arsenic (As ⁺ is dosed to 5) in the P-type active region 12a. Ions are implanted under the conditions of × 10 ¹⁵ / cm ² and acceleration energy of 38 keV, whereby source / drain regions 29a are formed on both sides of the gate electrode 20a of the P-type active region 12a in the semiconductor substrate 10. Source / drain regions 29a is aligned with the second sidewall insulating film 28 and partially overlaps with the extension region 27a, and the resist mask is removed by ashing or the like.

A resist mask that covers the P-type active region 12a and exposes the N-type active region 12b is formed. Using this resist mask, a P-type impurity such as BF ₂ ⁺ is dosed to the N-type active region 12b at a dose of 3 × 10 ¹⁵ / cm. ^2. Ion implantation is performed under the condition of an acceleration energy of 18 keV, whereby source / drain regions 29b are formed on both sides of the gate electrode 20b of the N-type active region 12b in the semiconductor substrate 10. The source / drain region 29b is formed so as to be aligned with the second sidewall insulating film 28 and partially overlap with the extension region 27b. The resist mask is removed by ashing or the like.

Subsequently, as shown in FIG. 8D, a silicide film 31 is formed.
Specifically, a silicide metal such as Ni is deposited on the entire surface of the semiconductor substrate 10 by a sputtering method or the like, and the semiconductor substrate 10 is heat-treated. As a result, Ni and silicon, here, the polysilicon film 22 of Ni and the gate electrodes 20a and 20b, and Ni and the source / drain regions 29a and 29b are chemically reacted to be silicided.
Thereafter, unreacted Ni is removed by wet etching. Thus, the NiSi silicide film 31 is formed on the gate electrodes 20a and 20b and the source / drain regions 29a and 29b.

  Thereafter, various processes such as formation of an interlayer insulating film, contact holes, conductive plugs filling the contact holes, wirings connected to the conductive plugs, and the like are performed. Thus, a MIPS-CMOS having a P-type MIPS-FET in the P-type active region 12a and an N-type MIPS-FET in the N-type active region 12b is formed.

  As described above, according to the present embodiment, the TaN layer and the TaSiN layer, which are Ta-containing conductive materials, are difficult to remove, although the conventional equipment and processing processes are inherited as much as possible to suppress the cost increase. Thus, a highly reliable MIPS-CMOS can be realized easily and surely without causing any residual deposits.

  Hereinafter, various aspects of the semiconductor device and its manufacturing method will be collectively described as additional notes.

(Appendix 1) A step of sequentially laminating a first layer made of a Ta-containing conductive material, a second layer made of TiN, and a third layer that can be dry-etched above a semiconductor substrate;
Patterning the third layer by dry etching using the second layer as an etching stopper;
The second layer and the first layer are wet-etched using the patterned third film as a mask, and the second layer and a part of the first layer are left below the third layer. A method for manufacturing a semiconductor device, comprising the steps of:

  (Additional remark 2) The said 1st layer is formed in the film thickness of 0.5 to 10.0 nm, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.

  (Additional remark 3) The said 2nd layer is formed in the film thickness of 0.5 to 10.0 nm, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.

  (Appendix 4) The semiconductor according to any one of appendices 1 to 3, wherein the wet etching uses both SPM and APM or one selected from SPM and APM as an etchant. Device manufacturing method.

  (Additional remark 5) The said 3rd layer is a silicon layer, The manufacturing method of the semiconductor device of any one of Additional remark 1-4 characterized by the above-mentioned.

  (Additional remark 6) The said 3rd layer is a layer used as the mask of the said wet etching, The manufacturing method of the semiconductor device of any one of Additional remark 1-4 characterized by the above-mentioned.

(Appendix 7) a semiconductor substrate;
A gate electrode formed above the semiconductor substrate via a gate insulating film,
The gate electrode is formed by sequentially laminating a first layer made of a Ta-containing conductive material, a second layer made of TiN, and a third layer made of polycrystalline silicon. .

  (Supplementary note 8) The semiconductor device according to supplementary note 7, wherein the first layer is formed to a thickness of 0.5 nm to 10.0 nm.

  (Supplementary note 9) The semiconductor device according to supplementary note 7, wherein the second layer is formed to a thickness of 0.5 nm to 10.0 nm.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Element isolation structure 11a Isolation groove | channel 12a P-type active region 12b N-type active region 13 N-type well 14 Gate insulating film 15, 18 Gate metal film 15a TaN layer 15b, 18b TiN layer 16, 19, 23 Hard mask 17 , 21, 25a, 25b Resist mask 18a TaSiN layer 20a, 20b Gate electrode 22 Polycrystalline silicon film 24 Antireflection film 26 First sidewall insulating film 27a, 27b Extension region 28 Second sidewall insulating film 29a, 29b Source / Drain region 31 Silicide film

Claims (5)

A step of sequentially laminating a first layer made of a Ta-containing conductive material, a second layer made of TiN, and a third layer capable of being dry-etched over a semiconductor substrate;
Patterning the third layer by dry etching using the second layer as an etching stopper;
The second layer and the first layer are wet-etched using the patterned third film as a mask, and the second layer and a part of the first layer are left below the third layer. A method for manufacturing a semiconductor device, comprising the steps of:   The method for manufacturing a semiconductor device according to claim 1, wherein the second layer is formed to a thickness of 0.5 nm to 10.0 nm.   The method for manufacturing a semiconductor device according to claim 1, wherein the third layer is a silicon layer. A semiconductor substrate;
A gate electrode formed above the semiconductor substrate via a gate insulating film,
The gate electrode is formed by sequentially laminating a first layer made of a Ta-containing conductive material, a second layer made of TiN, and a third layer made of polycrystalline silicon. .   The semiconductor device according to claim 4, wherein the second layer is formed to a thickness of 0.5 nm or more and 10.0 nm or less.

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