JP2012079152A - Semiconductor device - Google Patents

Abstract

An object of the present invention is to prevent reverse engineering via a debug terminal.
A debugging terminal unit control circuit extracts an enabling routine R1 from a debugging program P1 executed by a CPU 4, and receives the receiving at a debugging terminal unit 2 based on the extracted enabling routine R1. The debug terminal unit 2 is controlled so as to input the debug input signal S4 to the CPU 4. As a result, when the debug program P1 is stored in the external memory 7a, the debug terminal unit 2 is enabled and the debug input signal S4 is sent to the CPU 4
However, when the debug program P1 is not stored in the external memory 7a, the debug terminal unit 2 is disabled and the debug input signal S4 is not input to the CPU 4. As a result, it is possible to prevent reverse engineering via the debug terminal unit 2 by invalidating the debug terminal unit 2 at the time of shipment.
[Selection] Figure 1

Description

In a SoC (System on Chip) having a debug terminal, the present invention relates to a semiconductor device that achieves both debugging convenience and prevention of reverse engineering via a debug terminal by a third party after product shipment.

Generally, in order to debug a SoC that is an integrated circuit that integrates a series of required functions (systems) on one semiconductor chip, the SoC is provided with a debug terminal.

FIG. 6 is a block diagram illustrating a configuration example of a conventional semiconductor device 300. As shown in FIG. 6, the semiconductor device 300 includes a SoC 1B, an external memory 7b, and the like. SoC1B
A debug terminal unit 2B, a CPU 4, an internal memory 5 and a functional circuit 6 are provided. The CPU 4, the internal memory 5, the functional circuit 6 and the external memory 7b are a system bus 1 provided in the SoC 1B.
0 are connected to each other and exchange data and the like via the system bus 10.

When the power-on reset signal S1 is input from the outside, the CPU 4 reads and executes the product program P2 stored in the external memory 7b. The power-on reset signal S1 is
It is a reset signal for each part in the SoC 1B, and is a signal for setting the circuit state immediately after turning on the power of the SoC 1B to a constant value.

The product program P2 is a program for operating the semiconductor device 300. When the CPU 4 executes the product program P2, for example, data necessary for the operation of the functional circuit 6 stored in the internal memory 5 is read and a predetermined algorithm is executed.

The debug terminal unit 2B is a terminal for exchanging a debug input signal S4 and a debug output signal S5 for controlling and observing the operation of the CPU 4 from the outside of the SoC 1B with a debug device (not shown).

FIG. 7 is a circuit diagram showing a configuration example of a conventional debug terminal unit 2B. As shown in FIG.
The debug terminal unit 2B includes an input buffer 21B and an output buffer 22B. The debug device (not shown) is connected to the input buffer 21B and the output buffer 22B.
The debug device is connected to the input buffer 21B and the output buffer 22B when performing verification, evaluation, debugging, failure analysis, and the like of the semiconductor device 300 and the like.

The input buffer 21B receives the debug input signal S4 from the debug device and receives the CPU 4
To enter. The output buffer 22B receives the debug output signal S5 from the CPU 4 and outputs it to the debug device.

With such a configuration, the debug device can control the operation of the CPU 4 and observe the state via the debug terminal unit 2B. For example, this observation is performed by stepping the product program P2,
For example, reference and rewriting of data at a specific address stored in the internal memory 5 and the external memory 7b, and reference and rewriting of a register (not shown) and an internal state in the CPU 4 are performed.

Thereby, the semiconductor device 300 can improve the work efficiency of debugging by executing the product program P2 while confirming the signal / state inside and outside the SoC 1B by using the debug terminal unit 2B.

As another conventional example, Patent Document 1 discloses a method for debugging a system LSI. This debugging method allows the system LSI to be debugged by allowing the system LSI to authenticate that the user is an authorized user using an IC card.

JP 2010-160765 A

By the way, according to the conventional semiconductor device 300, the work efficiency of debugging is improved, but the hardware of the product program P2 and SoC1B, which are important design assets, is connected to the debug terminal unit 2.
By using B, there is a possibility of analysis by a third party. That is, reverse engineering is possible via the debug terminal 2B.

In order to prevent such reverse engineering, it is conceivable to encrypt the product program P2. In this case, it is possible to prevent the product program P2 from being directly analyzed, but even if the product program P2 is encrypted, when the CPU 4 executes the product program P2, the encrypted product program P2 is decrypted and executed. Therefore, the decoding result of the product program P2 is obtained via the debug terminal unit 2B, and the operation of the product program P2 and S
The hardware structure of oC1B is analyzed.

In order to prevent this, it is conceivable that the debug terminal portion 2B is not mounted. In this case, since the product program P2 cannot be executed while checking the signal / state inside and outside the SoC 1B, there is a problem that debugging work becomes difficult.

Further, it is conceivable to manufacture two types of semiconductor devices, a semiconductor device mounting the debug terminal portion 2B and a semiconductor device not mounting the debug terminal portion 2B. For example, when performing a debugging operation, a semiconductor device equipped with a debugging terminal portion 2B is used. After the debugging operation is completed, a debugging terminal portion 2B reflecting a debugging result of the semiconductor device equipped with the debugging terminal portion 2B is used. Ship semiconductor devices that are not installed to customers. In this case, two types must be designed and manufactured, which causes a problem that the manufacturing cost of the semiconductor device increases.

Although the above-mentioned Patent Document 1 can solve these problems, there is a problem that the manufacturing cost further increases because an IC card or an authentication circuit is used.

Therefore, the present invention solves the above-described problems, improves the work efficiency of debugging, can prevent the operation of the program, the hardware structure of the semiconductor device and the like from being analyzed from the debug terminal unit, And it aims at providing the semiconductor device which can reduce manufacturing cost.

In order to solve the above-described problem, a semiconductor device according to the present invention is connected to a debug device that generates a debug input signal for executing debugging, and is generated by the debug device in the semiconductor device debugged by the debug device. A processor that reads a debug program from a memory in which a debug program including a debug terminal unit that receives the debug input signal and an enabling routine that enables the debug terminal unit is stored in advance, and the processor The enable terminal is extracted from the debug program executed in step 1, and the debug terminal is enabled so that the debug input signal received at the debug terminal is input to the processor based on the extracted enable routine. And a debug terminal control unit It is.

The semiconductor device according to the present invention is connected to a debugging device that generates a debug input signal for executing debugging, and is debugged by the debugging device. Based on this assumption, the debug terminal unit receives a debug input signal generated by the debug device. The processor reads and executes the debugging program from a memory in which a debugging program including an enabling routine for enabling the debugging terminal unit is stored in advance. And
The debug terminal unit control unit extracts an activation routine from the debugging program executed by the processor, and inputs a debug input signal received by the debug terminal unit to the processor based on the extracted activation routine. Enable the debug terminal as follows.

Thus, when the debug program is stored in the memory, the debug terminal portion is enabled and the debug input signal is input to the processor. However, when the debug program is not stored in the memory, the debug terminal portion is Disabled and no debug input signal is input to the processor. That is, whether or not the semiconductor device can be debugged is determined depending on whether or not a debugging program is stored in the memory.

For example, before shipping the semiconductor device to a customer, a memory in which a debugging program is stored is mounted, and the debugging terminal portion is enabled by the debugging program in the memory so that debugging can be performed. When the debugging is completed, a product program for operating the semiconductor device is stored instead of the debugging program stored in the memory. Then, the debug terminal portion becomes invalid, and after the semiconductor device is shipped to the customer, debugging by the customer becomes impossible.

According to the semiconductor device of the present invention, it is possible to improve the convenience of debugging work by enabling the debug terminal part at the time of debugging, and from the debug terminal part by invalidating the debug terminal part at the time of shipment. It is possible to prevent the program operation and the hardware structure of the semiconductor device from being analyzed. Then, it is not necessary to design and manufacture two types as in the prior art, and since no IC card or authentication circuit is used, the manufacturing cost of the semiconductor device can be reduced.

1 is a block diagram illustrating a configuration example (during debugging) of a semiconductor device according to a first embodiment; It is a block diagram which shows the structural example (at the time of shipment) of the semiconductor device which concerns on 1st Embodiment. It is a circuit diagram which shows the structural example of a debug terminal part. It is a block diagram which shows the structural example of a debug terminal part control circuit. It is a block diagram which shows the structural example of the semiconductor device which concerns on 2nd Embodiment. It is a block diagram which shows the structural example of the conventional semiconductor device. It is a circuit diagram which shows the structural example of the conventional debug terminal part.

A semiconductor device will be described below as an example of an embodiment of the present invention with reference to the drawings.

<First Embodiment>
[Configuration Example of Semiconductor Device 100]
As shown in FIGS. 1 and 2, the semiconductor device 100 according to the present embodiment includes the SoC 1 and an external memory 7a or 7b. The SoC 1 includes a debug terminal unit 2, a debug terminal unit control circuit 3, a CPU 4, an internal memory 5, and a functional circuit 6, which are formed on one semiconductor substrate. Further, the SoC 1 can receive the power-on reset signal S1 from the outside, and each part in the SoC 1 is reset by the power-on reset signal S1.

The debug terminal unit 2 is connected to the debug terminal unit control circuit 3 and the CPU 4. The debug terminal unit control circuit 3, CPU 4, internal memory 5, functional circuit 6 and external memories 7a and 7b are
Each is connected to the system bus 10 and exchanges data and the like via the system bus 10.

The external memory 7a stores a debugging program P1 (FIG. 1) including an enabling routine R1 for enabling the debug terminal unit 2, and the external memory 7b stores a product program P2 (FIG. 2) for operating the SoC1. Remember.

The debug program P1 includes a test program for debugging work and an enabling routine R1, in addition to processing procedures, initial data, and algorithms necessary for realizing the required specification function of SoC1. The validation routine R1 is a program that validates the debug terminal function of the debug terminal unit 2. The product program P2 includes a processing procedure, initial data, an algorithm, and the like necessary for realizing the required specification function of the SoC 1, similarly to a part of the debugging program P1.

The external memory 7a is detachably attached to the SoC 1 and can be exchanged with the external memory 7b. For example, when debugging SoC1, the external memory 7a in which the debugging program P1 is stored is attached to the SoC1. And when SoC1 debugging is complete,
The external memory 7a is removed and the external memory 7b in which the product program P2 is stored is stored in the SoC.
Attach to 1.

The debug terminal unit 2 is a terminal connected to the outside. For example, the debug terminal unit 2 is connected to a debug device that generates a debug input signal S4 for executing debugging and exchanges the debug input signal S4. The debug output signal S5 is exchanged with the CPU 4 that generates the debug output signal S5 for executing debugging. Debug input signal S4 and debug output signal S5
Is a signal for controlling / observing the operation of the CPU 4 from the debug device.

With this debug input signal S4 and debug output signal S5, the debug device, for example, executes step execution of the debug program P1, references or rewrites data at a specific address stored in the internal memory 5 and the external memory 7a, Reference and rewrite of a register and an internal state (not shown) are performed.

The CPU 4 is an example of a processor, and reads and sequentially executes the debugging program P1 stored in the external memory 7a or the product program P2 stored in the external memory 7b. Further, the CPU 4 generates the debug output signal S5 and outputs it to the debug terminal unit 2 as described above.

The debug terminal unit control circuit 3 is an example of the debug terminal unit control unit.
Is to control. For example, the debug terminal unit control circuit 3 extracts the validation routine R1 from the debugging program P1 executed by the CPU 4, and based on the extracted validation routine R1, the debug received by the debug terminal unit 2 The debug terminal unit 2 is validated so as to input the input signal S4 to the CPU 4. Also, the debug terminal unit control circuit 3 generates a debug output signal S received by the debug terminal unit 2 based on the extracted enabling routine R1.
The debug terminal 2 is enabled so that 5 is output to the debug device.

The internal memory 5 holds temporary data necessary for the operation of the CPU 4 and the functional circuit 6.
The internal memory 5 may store all or part of the product program P2 executed by the CPU 4. In this case, the CPU 4 reads and executes the product program P2 stored in the internal memory 5.

The functional circuit 6 realizes the required specifications of SoC1. As described above, the functional circuit 6
Data necessary for the above operation is stored in the internal memory 5, and the functional circuit 6 operates when the CPU 4 reads and executes the data. In the present embodiment, the functional circuit 6 is included in the SoC 1.
However, the present invention is not limited to this, and a plurality of them may be provided.

[Configuration example of debug terminal unit 2]
Next, a configuration example of the debug terminal unit 2 will be described. As shown in FIG. 3, the debug terminal unit 2 includes an input buffer with enable (hereinafter referred to as “input buffer 21”) and an output buffer with enable (hereinafter referred to as “output buffer 22”). The input buffer 21 and the output buffer 22 are connected to the debug terminal unit control circuit 3, the CPU 4, and a debug device that is an external device.

The input buffer 21 is controlled by a debug terminal unit control signal S3 output from the debug terminal unit control circuit 3. For example, the input buffer 21 receives the debug input signal S4 from the debug device. At this time, the input buffer 21 indicates that the debug terminal control signal S3 is Hi.
In this case, the debug input signal S4 is passed and inputted to the CPU 4, and when the debug terminal control signal S3 is Low, the debug input signal S4 is cut off.

The debug device performs operation control of the CPU 4, rewriting data of specific addresses stored in the internal memory 5 and the external memory 7a, and rewriting registers and internal states in the CPU 4 from the outside of the SoC 1 by a debug input signal S4.

The output buffer 22 is controlled by a debug terminal unit control signal S3 output from the debug terminal unit control circuit 3. For example, the output buffer 22 sends the debug output signal S5 to the CPU.
4 is received. At this time, when the debug terminal control signal S3 is Hi, the output buffer 22 passes the debug output signal S5 and outputs it to the debug device. When the debug terminal control signal S3 is Low, the output buffer 22 cuts off the debug output signal S5. To do.

The debug device uses the debug output signal S5 to monitor the state of the CPU 4, refer to the data of the specific address stored in the internal memory 5 and the external memory 7a, and refer to the registers and internal state in the CPU 4 from outside the SoC 1.

Thus, the debug terminal unit 2 passes / cuts off the debug input signal S4 and the debug output signal S5 based on the debug terminal unit control signal S3 output from the debug terminal unit control circuit 3.

[Configuration example of debug terminal control circuit 3]
Next, a configuration example of the debug terminal unit control circuit 3 will be described. As shown in FIG. 4, the debug terminal unit control circuit 3 includes an I / F 31, an address decoder 32, a data decoder 33, and a flip-flop 34.

The I / F 31 receives various signals output from the CPU 4 via the system bus 10. For example, when the CPU 4 reads out and executes the debugging program P1 from the external memory 7a and outputs the enabling signal S2 based on the enabling routine R1 to the debugging terminal unit control circuit 3, the I / F 31 receives the enabling signal S2. Receive. Then, the I / F 31 outputs the received enable signal S2 to the address decoder 32 and the data decoder 33.

An address decoder 32 and a data decoder 33 are connected to the I / F 31. The address decoder 32 and the data decoder 33 receive the enable signal S2 from the I / F 31, and determine a value to be written in the flip-flop 34 based on the received enable signal S2.

A flip-flop 34 is connected to the address decoder 32 and the data decoder 33. The flip-flop 34 holds the debug terminal unit control signal S3 and outputs the debug terminal unit control signal S3 to the debug terminal unit 2.

Based on the values written in the address decoder 32 and the data decoder 33, the flip-flop 34 activates the debug terminal unit control signal S3 Hi, that is, the debug terminal function of the debug terminal unit 2.

Further, when the flip-flop 34 is reset by the power-on reset signal S1, the debug terminal unit control signal S3 is set to Low, that is, the debug terminal function of the debug terminal unit 2 is disabled.

In this manner, the debug terminal unit control circuit 3 realizes an operation in which the CPU 4 changes the value of the debug terminal unit control signal S3 by writing specific data at a specific address.

[Operation Example of Semiconductor Device 100]
Next, an operation example of the semiconductor device 100 will be described. For the explanation of the operation example, the following (i)
Assume ~ (iv).
(i) The address decoder 32 permits the flip-flop 34 to write a value only when the value 0x12345678 is input from the system bus 10.
(ii) The data decoder 33 sets the input of the flip-flop 34 to Hi only when the value 0x9a is input from the system bus 10. For other values, flip-flop 34 input is set to Low.
To.
(iii) The flip-flop 34 takes in the input value and outputs it to the debug terminal unit 2 as the debug terminal unit control signal S3 only when value writing is permitted by the address decoder 32. The debug terminal control signal S3 is held until the next value fetching permission.
(iv) The content of the enabling routine R1 of the debugging program P1 is an instruction code of the CPU 4 that executes the operation “write value 0x9a to address 0x12345678”.

[Example of operation during debugging]
First, an operation example during the debugging operation of the semiconductor device 100 illustrated in FIG. 1 will be described. When the semiconductor device 100 is debugged, it is assumed that the external memory 7a in which the debugging program P1 including the validation routine R1 is stored is installed.

When the semiconductor device 100 is powered on, the SoC 1 is reset by receiving the power-on reset signal S1. At this time, since the flip-flop 34 is also in the reset state (see FIG. 4), the value of the debug terminal unit control signal S3 is Low, and the debug terminal function of the debug terminal unit 2 is in an invalid state.

When the power-on reset signal S1 is in the reset state and when the power-on reset signal S1 is in the released state when the power-on reset signal S1 is in the released state, The program P1 is read and executed. When the enabling routine R1 is executed by the CPU 4 in this process, the value of the debug terminal control signal S3 becomes Hi in the following operation sequence (1) to (3), and the debug terminal function of the debug terminal 2 is It becomes valid.

(1) The CPU 4 reads the instruction code “write value 0x9a to address 0x12345678” of the activation routine R1.
(2) The CPU 4 executes an operation for writing the value 0x9a to the address 0x12345678 to the debug terminal unit control circuit 3.
(3) Hi is written into the flip-flop 34.

If a debug device is connected to the debug terminal unit 2 in the above-described state, a debug operation can be performed.

[Example of operation at shipment]
Next, the operation at the time of shipment of the semiconductor device 100 shown in FIG. 2 will be described. Semiconductor device 1
At the time of shipment of 00, it is assumed that the debugging operation of the semiconductor device 100 is completed and the external memory 7b in which the product program P2 not including the activation routine R1 is stored is mounted instead of the external memory 7a. .

As in the debugging operation described above, SoC1 is reset when the power-on reset signal S1 is input when the semiconductor device 100 is powered on. At this time, since the flip-flop 34 of the debug terminal unit control circuit 3 is also in the reset state, the value of the debug terminal unit control signal S3 is Low, and the debug terminal function of the debug terminal unit 2 is in an invalid state.

When the power-on reset signal S1 is released, the CPU 4 reads and executes the product program P2 stored in the external memory 7b. In the execution of the product program P2, the debug terminal unit control signal S3 does not become Hi, and the debug terminal function of the debug terminal unit 2 holds an invalid state.

Even if a debugging device is connected to the debugging terminal unit 2 in such a state, it is impossible to analyze the debugging work and the hardware of the product program P2 and SoC1. As described above, the semiconductor device 100 operates differently at the time of debugging and at the time of shipment.

As described above, the semiconductor device 100 according to the first embodiment is connected to the debug device that generates the debug input signal S4 for executing debugging, and is debugged by this debug device. On the premise of this, the debug terminal unit 2 receives the debug input signal S4 generated by the debug device. The CPU 4 reads and executes the debugging program P1 from the external memory 7a in which the debugging program P1 including the enabling routine R1 for enabling the debugging terminal unit 2 is stored in advance. Then, the debug terminal unit control circuit 3 extracts the validation routine R1 from the debug program P1 executed by the CPU 4, and based on the extracted validation routine R1, the debug terminal unit 2 receives the debug. The debug terminal unit 2 is validated so as to input the input signal S4 to the CPU 4.

Thus, when the debugging program P1 is stored in the external memory 7a,
When the debug terminal 2 is enabled and the debug input signal S4 is input to the CPU 4, but the debug program P1 is not stored in the external memory 7a, for example, the external memory 7b in which the product program P2 is stored is stored. When installed, the debug terminal section 2 is disabled and the debug input signal S4 is not input to the CPU 4. That is, whether or not the semiconductor device 100 can be debugged is determined by whether or not the external memory 7a is installed (whether or not the debugging program P1 is stored).

Further, the CPU 4 generates a debug output signal S5 for executing debugging. The debug terminal unit 2 receives the debug output signal S5 generated by the CPU 4. Then, the debug terminal unit control circuit 3 controls the debug terminal unit 2 so as to output the debug output signal S5 received by the debug terminal unit 2 to the debug device based on the extracted enabling routine R1.

Thus, when the debugging program P1 is stored in the external memory 7a,
The debug terminal 2 is enabled and the debug output signal S5 is output to the debug device.
When the debug program P1 is not stored in the external memory 7a, for example, when the external memory 7b in which the product program P2 is stored is mounted, the debug terminal unit 2
Becomes invalid and the debug output signal S5 is not output to the debug device.

As a result, it is possible to improve the convenience of the debugging work by enabling the debug terminal part 2 at the time of debugging work, and by disabling the debugging terminal part 2 at the time of shipment,
Analysis of the operation of the product program P2 and the hardware structure of the semiconductor device 100 from the debug terminal unit 2 can be prevented (reverse engineering can be prevented). Then, it is not necessary to design and manufacture two types as in the prior art, and since no IC card or authentication circuit is used, the manufacturing cost of the semiconductor device can be reduced.

In the present embodiment, the debug signal is cut off using the enable buffer shown in FIG. 3 as the configuration of the debug terminal unit. However, the present invention is not limited to this, and an AND gate or an OR gate may be used. In this case, the debug terminal function can be invalidated by fixing the logic level to Low or Hi.

In addition, as shown in FIG. 4, the debug terminal unit control circuit is configured to change the value of the debug terminal unit control signal by writing one value to one address, but this is not limitative. Instead, the value of the debug terminal unit control signal may be changed by sequentially writing the value to a single address multiple times.

Furthermore, the product program stored in the external memory may or may not be encrypted. When the product program is encrypted, the debug terminal portion is invalid, so that it is impossible for a third party to analyze the decryption process on the SoC 1, the process procedure of the product program, the initial data, and the algorithm. . Further, when the product program is not encrypted, the product program may be directly read from the external memory and analyzed by a third party. However, since the activation routine is not included in the product program, no means for activating the debug terminal unit is known. The analysis of the SoC program is difficult unless it is executed by the SoC and monitored through the debug terminal.

<Second Embodiment>
In the second embodiment, a semiconductor device 200 in which the memory write terminal portion 8 is provided in the internal memory 5 described in the first embodiment and the contents of the internal memory 5 can be rewritten will be described. The same names and reference numerals as those of the first embodiment have the same functions, and thus description thereof is omitted.

As shown in FIG. 5, the semiconductor device 200 does not include the external memories 7a and 7b described in the first embodiment and is configured only by the SoC 1A. SoC1A is a debug terminal 2
, A debug terminal unit control circuit 3, a CPU 4, an internal memory 5, a functional circuit 6, and a memory write terminal unit 8.

The memory write terminal unit 8 is an example of an external terminal that can be externally connected, and is connected to the internal memory 5. The memory write terminal unit 8 is a terminal that enables the program stored in the internal memory 5 to be rewritten from the outside. However, the memory write terminal unit 8 cannot read the program.

During debugging, a debugging program P1 including an enabling routine R1 is stored in the internal memory 5 via the memory write terminal unit 8. Then, the CPU 4 can read out and execute the debugging program P1 stored in the internal memory 5 and enable the debug terminal unit 2 in the same manner as the operation of the semiconductor device 100 described above.

At the time of product shipment, a product program P2 that does not include the activation routine R1 is stored in the internal memory 5 via the memory write terminal unit 8. Then, the CPU 4 can read and execute the product program P2 stored in the internal memory 5, and can maintain the invalidation of the debug terminal unit 2 in the same manner as the operation of the semiconductor device 100 described above.

As described above, according to the semiconductor device 200 according to the second embodiment, the memory write terminal portion 8 in which the program of the internal memory 5 can be rewritten is provided, so that the external memories 7a and 7b as in the semiconductor device 100 described above. It is not necessary to facilitate the two types of memories, and it is not necessary to secure a space for the external memories 7a and 7b, so that the manufacturing cost can be reduced as compared with the semiconductor device 100.

1,1A, 1B SoC
2 Debug terminal section 3 Debug terminal section control circuit 4 CPU
DESCRIPTION OF SYMBOLS 5 Internal memory 6 Functional circuit 7a, 7b External memory 8 Memory write terminal part 10 System bus 21 Input buffer with enable 22 Output buffer with enable 31 I / F
32 Address decoder 33 Data decoder 34 Flip-flop 100,200 Semiconductor device P1 Debug program P2 Product program R1 Enable routine S1 Power-on reset signal S2 Enable signal S3 Debug terminal control signal S4 Debug input signal S5 Debug output signal

Claims (6)

In a semiconductor device that is connected to a debug device that generates a debug input signal for executing debugging and is debugged by the debug device,
A debug terminal unit for receiving a debug input signal generated by the debug device;
A processor that reads and executes a debugging program from a memory in which a debugging program including an activation routine for activating the debug terminal unit is stored in advance;
The enabling routine is extracted from the debugging program executed by the processor, and based on the extracted enabling routine, the debug input signal received at the debug terminal unit is input to the processor. A semiconductor device comprising: a debug terminal unit control unit that activates the debug terminal unit. The processor generates a debug output signal for performing debugging;
The debug terminal unit receives a debug output signal generated by the processor,
The debug terminal unit control unit extracts the validation routine from a debugging program executed by the processor, and outputs a debug output signal received by the debug terminal unit based on the extracted validation routine. The semiconductor device according to claim 1, wherein the debug terminal unit is validated so as to be output to the debug device. The debug terminal unit control unit includes:
Based on an enabling routine extracted from the debugging program, generating a debug terminal part control signal for enabling the debug terminal part, and outputting the generated debug terminal part control signal to the debug terminal part The semiconductor device according to claim 1 or 2. The debug terminal section is
When the debug terminal unit control signal is received from the debug terminal unit control unit, the debug input signal is input to the processor and / or the debug output signal is output to the debug device. The semiconductor device according to claim 1. The debug terminal unit, the processor, and the debug terminal unit control unit are formed on one semiconductor substrate,
5. The memory according to claim 1, wherein the memory is detachably attached to the semiconductor substrate and can be exchanged for a product memory storing a product program for operating the semiconductor device. The semiconductor device described. The debug terminal unit, the processor, the debug terminal unit control unit, and the memory are
Formed on one semiconductor substrate,
The memory is provided with an externally connectable external terminal to which a product program for operating the semiconductor device is input,
5. The semiconductor device according to claim 1, wherein the memory can rewrite the stored debugging program into the product program input to the external terminal. 6.

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