JP2012074608A - Wiring formation method - Google Patents

Abstract

Provided is a wiring forming method capable of maintaining high adhesion without deteriorating adhesion between a lower wiring layer and a wiring seed layer.
A wiring forming method for forming an upper wiring layer and a communication wiring layer on an object to be processed in which a lower wiring layer, an insulating barrier layer, an interlayer insulating film, and an upper wiring layer are sequentially laminated. The pretreatment step of forming the communication hole 9B with the insulating barrier layer left, filling the sacrifice hole in the communication hole, and forming the pattern mask 62 for forming the trench 9A, and the trench formation step of forming the trench An ashing step for ashing the sacrificial film 60 and the pattern mask, a barrier layer forming step for forming the barrier layer 10 by heat treatment in the trench and the communication hole, and a barrier layer at the bottom of the communication hole by anisotropic etching, An anisotropic etching process for removing the insulating barrier layer and a wiring seed layer forming process for forming the wiring seed layer 12 are included.
[Selection] Figure 2

Description

  The present invention relates to a wiring forming method, and more particularly to a wiring forming method for forming a thin film wiring on an object to be processed such as a semiconductor wafer.

  In general, to manufacture a semiconductor device, a semiconductor device is repeatedly subjected to various processes such as film formation, patterning, and dry etching to manufacture a desired device. The line width and hole diameter are becoming more and more finer than ever. In recent years, the wiring layer has a multi-wiring structure such as an eight-layer structure. Furthermore, as the wiring material and the embedding material, there is a tendency to use copper that is very low in electrical resistance and inexpensive because it is necessary to reduce the electrical resistance by miniaturizing various dimensions (Patent Document 1). When copper is used as the wiring material or the embedding material, in general, in consideration of adhesion with the lower layer, tantalum metal (Ta), titanium (Ti), tantalum nitride film (TaN), A titanium nitride film (TiN) or the like is used as the barrier layer.

  In order to fill the recess, first, in the plasma sputtering apparatus, a thin wiring seed layer made of a copper film is formed on the entire wafer surface including the entire wall surface in the recess, and then the copper plating is applied to the entire wafer surface. By applying the treatment, the inside of the recess is completely embedded. After that, the excess copper thin film on the wafer surface is removed by polishing by CMP (Chemical Mechanical Polishing) or the like (Patent Document 2).

  This point will be described with reference to FIG. FIG. 5 is a view showing a conventional embedding process of a recess of a semiconductor wafer. The semiconductor wafer W is made of, for example, a silicon substrate, and the lower insulating film 2, the lower wiring layer 4, the insulating barrier layer 6 for preventing diffusion, and the interlayer insulating film 8 are sequentially stacked on the surface. The lower wiring layer 4 is made of copper, for example, and is previously patterned and embedded. The insulating barrier layer 6 is formed of, for example, a SiCN film, the lower insulating film 2 is formed of, for example, a SiCN film, and the interlayer insulating film 8 is a low dielectric constant material such as a SiOC film or a NCS (Nano Clustering Silicon) film. Etc. are formed. On the surface of the interlayer insulating film 8 formed on the semiconductor wafer W, there is a recess corresponding to a via hole, a through hole, a trench, or the like, which is a target of a single damascene structure, a dual damascene structure, a three-dimensional mounting structure, or the like. 9 is formed, and the insulating barrier layer 6 is dry-etched at the bottom of the recess 9 to expose the lower wiring layer 4 (see FIG. 5A).

  Specifically, the recess 9 includes a trench (groove) 9A having an elongated cross-section formed on the surface of the interlayer insulating film 8 and a communication hole 9B formed in a part of the bottom of the trench 9A. This communication hole 9B becomes a via hole or a through hole. The lower wiring layer 4 is exposed at the bottom of the communication hole 9B, and is electrically connected to a further lower wiring layer and an element such as a transistor. Note that elements such as transistors are not shown. With the miniaturization of the design rule, the recess 4 has a very small width or inner diameter of about 50 nm, for example, and an aspect ratio of about 2 to 4, for example.

  First, a barrier layer 10 made of, for example, a Ta / TaN film is formed on the surface of the semiconductor wafer W substantially uniformly including the inner surface of the recess 9 by a plasma sputtering apparatus (see FIG. 5B). Next, a wiring seed layer 12 made of a thin copper film is formed as a metal film over the entire wafer surface including the surface in the recess 9 by a plasma sputtering apparatus (see FIG. 5C). Next, the recess 9 is filled with a metal film 14 made of, for example, a copper film by performing a copper plating process on the wafer surface (see FIG. 5D). As a result, the communication wiring layer 16 is formed in the communication hole 9A, and the upper wiring layer 18 is formed in the trench 9B. Here, the communication wiring layer 16 and the upper wiring layer 18 are integrally formed. Thereafter, the excess metal film 14, the wiring seed layer 12 and the barrier layer 10 on the wafer surface are removed by polishing using the above-described CMP process or the like (see FIG. 5E).

JP 2000-077365 A JP 2006-148075 A

  Recently, there has been a demand for further miniaturization of the line width and hole diameter, and for example, the current line width and hole diameter of about 50 nm are required to be reduced to about 20 to 30 nm. Further, the aspect ratio is further increased by reducing the thickness of each layer, and for example, it tends to be required up to about 10.

  In the case of such a miniaturized dimension, the step coverage characteristic is not so good in the film forming process by sputtering with high directivity, so a thin film is formed on the surface in the recess 9. At this time, there is a concern that the thin film is not sufficiently deposited on the side wall or the like in the recess 9. Therefore, instead of film formation by sputtering, a barrier layer 10 in the recess 9 is formed by CVD (Chemical Vapor Deposition) processing with high step coverage or ALD (Atomic Layer Deposition) processing in which, for example, source gas and reaction gas are alternately flowed. It is conceivable to form a thin film.

  However, in the case of the CVD process or the ALD process, impurities are present because various film forming gases are used, unlike the high-vacuum and clean sputtering process. For this reason, there is a concern that the interface between the lower wiring layer 4 made of a Cu film and the barrier layer 10 is contaminated by the impurities, the reliability of the interface is impaired, and the adhesion is lowered.

  In order to improve the operation speed of the semiconductor device, a low-k material which is a so-called low dielectric constant material is used for the purpose of reducing the capacitor of the interlayer insulating film, and the dielectric constant is further lowered. For this reason, bubbles have been included in the low-k material, that is, a large number of pores (porous). In this case, when the barrier film is formed by using the CVD process or the ALD process having a good step coverage in a state where the low-k material containing the pores (porous) is used as the interlayer insulating film 8. Then, the film forming gas penetrates into the porous layer, and the adhesion between the interlayer insulating film 8 and the barrier layer is deteriorated. For example, there is no effect of the barrier layer of the wiring layer such as Cu, and the insulating performance of the interlayer insulating film is reduced. There was also a concern that it would cause a decline.

  The present invention has been devised to pay attention to the above problems and to effectively solve them. The present invention is a wiring forming method that can maintain high adhesion without deteriorating the adhesion between a lower wiring layer and a wiring seed layer.

  According to the first aspect of the present invention, a lower wiring layer, an insulating barrier layer, an interlayer insulating film, and an upper wiring layer are sequentially laminated on a target object, and a metal film is embedded in a communication hole formed in the interlayer insulating film. In the wiring forming method of forming a communication wiring layer for electrically connecting the upper wiring layer and the lower wiring layer, a sacrificial film is embedded in the communication hole with the insulating barrier layer left, and the interlayer insulating film A pre-processing step of forming a pattern mask with a photoresist on the sacrificial film to form a trench for the upper wiring layer in the interior; and a dry process for the object to be processed using the pattern mask as a mask in a vacuum processing chamber. A trench forming step of forming the trench in the interlayer insulating film by performing an etching process; and assembling the sacrificial film and the pattern mask in a vacuum processing chamber. An ashing step to be removed, a barrier layer forming step for forming a barrier layer on the entire surface including the surface in the trench and the surface in the communication hole in the vacuum processing chamber by ALD or CVD processing, and in the vacuum processing chamber. An anisotropic dry etching step of removing the barrier layer and the insulating barrier layer formed at the bottom of the communication hole by performing anisotropic dry etching to expose the lower wiring layer, and vacuum processing And a wiring seed layer forming step of forming a wiring seed layer over the entire surface including the surface in the trench and the surface in the communication hole.

  As described above, the lower wiring layer, the insulating barrier layer, the interlayer insulating film, and the upper wiring layer are sequentially laminated, and the metal film is embedded in the communication hole formed in the interlayer insulating film, so that the upper wiring layer and the lower layer are embedded. In a wiring forming method for forming a communication wiring layer that conducts with a wiring layer, when forming a barrier layer by heat treatment, the lower wiring layer is covered with an insulating barrier layer, and thereafter anisotropic drying is performed. The bottom layer of the communication hole and the insulating barrier layer are removed by the etching process to expose the lower layer wiring layer, and then the wiring seed layer is formed. Therefore, the lower layer wiring layer and the wiring seed in contact therewith are formed. Adhesion with the layer can be greatly improved.

  According to a fourth aspect of the present invention, a lower wiring layer, an insulating barrier layer, an interlayer insulating film, and an upper wiring layer are sequentially laminated on a workpiece, and a metal film is embedded in a communication hole formed in the interlayer insulating film. In the wiring forming method for forming a communication wiring layer for conducting the upper wiring layer and the lower wiring layer, the communication hole is formed with the insulating barrier layer left, and the interlayer insulating film is formed in the interlayer insulating film. A pretreatment step of forming a pattern mask made of a metal-containing material for forming the trench for the upper wiring layer, and a dry etching process on the object to be processed in the vacuum processing chamber using the pattern mask as a mask A trench is formed on the entire surface including the trench forming step of forming the trench in the interlayer insulating film, and the surface in the trench and the surface in the communication hole in the vacuum processing chamber. A barrier layer forming step of forming a barrier layer by D or CVD processing, and the barrier layer and the insulating barrier layer formed at the bottom of the communication hole by performing anisotropic dry etching in a vacuum processing chamber. An anisotropic dry etching process that removes and exposes the lower wiring layer, and a wiring seed layer formation that forms a wiring seed layer over the entire surface including the surface in the trench and the surface in the communication hole in a vacuum processing chamber A wiring formation method comprising: a step.

  As described above, the lower wiring layer, the insulating barrier layer, the interlayer insulating film, and the upper wiring layer are sequentially laminated, and the metal film is embedded in the communication hole formed in the interlayer insulating film, so that the upper wiring layer and the lower layer are embedded. In a wiring forming method for forming a communication wiring layer that conducts with a wiring layer, when forming a barrier layer by heat treatment, the lower wiring layer is covered with an insulating barrier layer, and thereafter anisotropic drying is performed. The bottom layer of the communication hole and the insulating barrier layer are removed by the etching process to expose the lower layer wiring layer, and then the wiring seed layer is formed. Therefore, the lower layer wiring layer and the wiring seed in contact therewith are formed. Adhesion with the layer can be greatly improved.

According to the wiring forming method of the present invention, the following excellent effects can be exhibited.
A lower wiring layer, an insulating barrier layer, an interlayer insulating film, and an upper wiring layer are sequentially laminated, and a metal film is embedded in a communication hole formed in the interlayer insulating film to form the upper wiring layer and the lower wiring layer. In the wiring forming method for forming the conductive wiring layer to be conducted, when the barrier layer is formed by heat treatment, the lower wiring layer is covered with an insulating barrier layer, and thereafter the communication is performed by anisotropic dry etching. The barrier layer at the bottom of the hole and the insulating barrier layer are removed to expose the lower wiring layer, and then the wiring seed layer is formed, so that the lower wiring layer and the wiring seed layer in contact with the lower wiring layer are in close contact with each other Can greatly improve the performance.

It is a schematic block diagram which shows an example of the processing system for enforcing the principal part of the wiring formation method which concerns on this invention. It is process drawing which shows 1st Example of the wiring formation method which concerns on this invention. It is process drawing which shows 1st Example of the wiring formation method which concerns on this invention. It is process drawing which shows the principal part of 2nd Example of the wiring formation method of this invention. It is a figure which shows the conventional embedding process of the recessed part of a semiconductor wafer.

Hereinafter, an embodiment of a wiring forming method according to the present invention will be described with reference to the accompanying drawings.
First, before explaining the wiring forming method of the present invention, a processing system for carrying out the main part of the wiring forming method of the present invention will be described. FIG. 1 is a schematic configuration diagram showing an example of a processing system for carrying out the main part of the wiring forming method according to the present invention. As shown in FIG. 1, the processing system 20 includes a first common transfer chamber 22 and a second common transfer chamber 24. Both common transfer chambers 22 and 24 are formed in a substantially heptagon shape, and the inside is in a vacuum atmosphere.

  In the first and second common transfer chambers 22 and 24, there are provided first and second transfer arms 26 and 28 which can be bent and stretched, respectively. On one end side of the first common transfer chamber 22, a pair of load lock chambers 30, 32 that can be evacuated and returned to atmospheric pressure are provided in parallel via gate valves G, respectively. The opposite sides of the pair of load lock chambers 30 and 32 are connected to one side of the air-side transfer chamber 34 that is horizontally long via a gate valve G, respectively. A plurality of, in the illustrated example, three ports 36 are provided on the other side of the atmosphere-side transfer chamber 34, and a semiconductor wafer W that is an object to be processed to be carried into and out of the processing system 20 is accommodated in the port 36. A cassette container is placed.

  An orienter 39 for aligning the wafer W is provided at one end in the longitudinal direction of the atmosphere-side transfer chamber 34. In the atmosphere-side transfer chamber 34, an atmosphere-side transfer arm 38 that is movable in the longitudinal direction is provided, and a wafer is provided between the port 36, the orienter 39, and the load lock chambers 30 and 32. W can be delivered.

  On the other hand, the first and second common transfer chambers 22 and 24 are connected via a relay chamber 40 having a gate valve G interposed at one end and relaying the wafer. The first common transfer chamber 22 is connected to first and fourth vacuum processing chambers 42 and 48 via gate valves G, respectively. Further, between the first and second common transfer chambers 22 and 24, second and fifth vacuum processing chambers 44 and 50 are connected to both ends thereof via gate valves G, respectively. The second and fifth vacuum processing chambers 44 and 50 are provided in parallel so that the relay chamber 40 is sandwiched therebetween.

  The second common transfer chamber 24 is connected to third, sixth and seventh vacuum processing chambers 46, 52 and 54 through gate valves G, respectively. The first and fourth vacuum processing chambers 42 and 48 are accessible by the first transfer arm 26. Further, the third, sixth and seventh vacuum processing chambers 46, 52 and 54 are accessible by the second transfer arm 28. Further, the second and fifth vacuum processing chambers 44 and 50 and the relay chamber 40 are both accessible from the opposite sides of the first and second transfer arms 26 and 28.

  In the first vacuum processing chamber 42, a process of forming a trench by dry etching using plasma and removing a resist mask by ashing is performed. In the second vacuum processing chamber 44, a sealing process for sealing holes (porous) in the interlayer insulating film is performed. In the third vacuum processing chamber 46, a barrier layer is formed by heat treatment such as CVD processing or ALD processing. Here, as will be described later, a TaCN film is used as the barrier layer.

In the fourth vacuum processing chamber 48, the barrier layer and the insulating barrier layer formed at the bottom of the communication hole which is a recess are removed by anisotropic dry etching using plasma. In the fifth vacuum processing chamber 50, a cleaning process is performed using plasma such as Ar gas or H ₂ gas in order to clean the bottom of the communication hole by plasma processing. In the sixth and seventh vacuum processing chambers 52 and 54, a wiring seed layer is formed. Here, for example, a laminated film of a Ru film and a Cu film is used as the wiring seed layer. In the sixth vacuum processing chamber 52, a Ru film is formed, and in the seventh vacuum processing chamber 54, a Cu film is formed. It comes to form. That is, the dry etching process and the film forming process can be performed through a vacuum. Therefore, since the inside of the communication hole or trench is not exposed to the atmosphere, the treatment can be performed in vacuum without moisture or oxidation. In addition, the example of arrangement | positioning of each said vacuum processing chamber is only an example, and is not limited to this, What kind of arrangement | positioning form may be employ | adopted.

  The entire processing system 20 is connected to and controlled by a system control unit 56 such as a computer. The system control unit 56 has a storage medium 58 for storing a computer-readable program. The storage medium 58 includes, for example, a flexible disk, a CD (Compact Disc), a hard disk, a flash memory, or a DVD.

<Wiring formation method>
Next, the wiring forming method of the present invention performed using the processing system 20 configured as described above will be described with reference to FIGS. FIG. 2 is a process diagram showing a first embodiment of a wiring forming method according to the present invention, and FIG. 3 is a process diagram showing a first embodiment of the wiring forming method according to the present invention.

  First, the semiconductor wafer W is made of, for example, a silicon substrate or the like. As shown in FIG. 2A, a lower insulating film 2, a lower wiring layer 4, and an insulating barrier layer 6 for preventing diffusion are formed on the surface of the wafer W. And the interlayer insulation film 8 is laminated | stacked one by one. The lower wiring layer 4 is made of copper, for example, and is previously patterned and embedded. The insulating barrier layer 6 is formed of, for example, a SiCN film, and the lower insulating film 2 and the interlayer insulating film 8 are low dielectric constant materials having a relative dielectric constant of, for example, 3 or less. This is formed of, for example, a SiOC film, a NCS (Nano Clustering Silica) film, a SiCOH film, a SiCN film, or the like. Here, the low dielectric constant material contains a large number of pores in order to reduce the capacitor.

  For this semiconductor wafer W, in the processing step, as shown in FIG. 2B, the interlayer insulating film 8 is subjected to dry etching processing by applying photolithography to form a communication hole 9B. Keep it. In this case, the insulating barrier layer 6 is left at the bottom of the communication hole 9B, and the lower wiring layer 4 made of the Cu film is not exposed. Further, as shown in FIG. 2C, a sacrificial film 60, which is an organic flat film, is applied to the entire surface of the wafer W with a predetermined thickness so that the entire inside of the communication hole 9B is embedded with the sacrificial film 60 and the surface. Flatten the whole. The sacrificial film 60, which is an organic flat film, is made of a C, H, F-based organic material. Then, a photoresist is applied on the sacrificial film 60, and a pattern mask 62 for forming a trench is formed by patterning the photoresist. The pretreatment process is completed by the above processing.

  When the pretreatment process is completed as described above, the semiconductor wafer W is transferred to the processing system 20 described with reference to FIG. 1, and each process described below is continuously performed in the processing system 20. Will be done. In the processing system 20, the wafer W is transferred between the vacuum processing chambers in a vacuum atmosphere.

First, the wafer W is taken into the system from the port 36 of the processing system 20 by the atmosphere-side transfer arm 38, aligned and oriented by the orienter 39, and then vacuumed inside through the load locks 30 and 32. It is transported into the atmosphere. The wafer W is first transferred to the first vacuum processing chamber 42, where a trench formation step as shown in FIG. 2D is performed. In this trench formation process, the wafer W is subjected to a dry etching process using the pattern mask 62 as a mask, whereby the interlayer insulating film 8 is scraped halfway in the thickness direction, thereby forming the trench (groove) 9A. It is formed. In this dry etching process, a fluorocarbon gas such as CF ₄ gas is used as a dry etching gas, and this dry etching gas is activated by plasma generated by, for example, high frequency power.

After the trench 9A is formed in this way, the ashing process is continued in the first vacuum processing chamber 42. In this ashing process, the supply of the dry etching gas is stopped and a plasma forming gas such as O ₂ or CO ₂ is supplied to generate plasma, and the pattern mask 62 and the communication hole 9B made of photoresist are generated. The sacrificial film 60 having embedded therein is ashed and removed. Thereby, as shown in FIG. 2 (E), the recess 9 including the trench 9A and the communication hole 9B is completely formed. In this case, the insulating barrier layer 6 at the bottom of the communication hole 9B has not been removed, and the lower wiring layer 4 is not exposed. The trench process and the ashing process may be performed in separate vacuum processing chambers. In this case, the wafer W is transferred in a vacuum atmosphere.

  When the ashing process is completed as described above, the wafer W is then transferred to the second vacuum processing chamber 44 via the vacuum transfer, and the second vacuum processing chamber 44 is shown in FIG. The sealing process is performed as described above. In this sealing step, the porous surface of the interlayer insulating film 8 made of a low dielectric constant material is sealed. Specifically, for example, this gas is adhered to the wafer surface by heat treatment while flowing a silane-based gas such as Hexamethyl Disilazane (HMDS), and sealing is performed. Alternatively, instead of the heat treatment, for example, methane gas may be flowed to generate plasma, so that pores (porous) are methylated and sealed.

  As a result, the porous surface of the interlayer insulating film 8 is sealed, so that it is possible to prevent the infiltration of the film forming gas during the subsequent ALD film formation or CVD film formation. And the barrier layer have good adhesion. Note that the sealing step and the second vacuum processing chamber 44 can be omitted when a low dielectric constant material having no pores is used as the interlayer insulating film 8.

  When the sealing process is completed as described above, the wafer W is then transferred to the third vacuum processing chamber 46 through a vacuum, and the third vacuum processing chamber 46 is shown in FIG. Thus, a barrier layer forming step is performed. In this barrier layer forming process, the sputtering apparatus is not used, and the barrier layer 10 is heat-treated by CVD film formation having excellent step coverage or ALD film formation by alternately flowing a source gas and a reactive gas. To form. Since the CVD film forming method and the ALD film forming method are excellent in step coverage, the barrier layer is formed on the entire surface of the wafer W, that is, the entire inner surface including the entire inner surface of the trench 9A and the bottom surface of the communication hole 9B. 10 is formed with a sufficient thickness.

Here, as the barrier layer 10, for example, a TaCN film can be used. In order to form this TaCN film, for example, TAIMATA (registered trademark) can be used as the source gas, and for example, H ₂ plasma can be used as the reactive gas. When the barrier layer 10 is formed, since the surface of the underlying interlayer insulating film 8 has already been sealed as described above, the film forming gas such as the source gas or the reaction gas does not soak into the porous. Therefore, the characteristics of the interlayer insulating film 8 can be maintained high. Further, since the lower wiring layer 4 is covered with the insulating barrier layer 6, the deposition gas does not directly contact the lower wiring layer 4.

  When the barrier layer forming step is completed as described above, the wafer W is then transferred to the fourth vacuum processing chamber 48 via a vacuum, and FIG. An anisotropic dry etching process is performed as shown. In this anisotropic dry etching process, the barrier layer 10 and the insulating barrier layer 6 formed at the bottom of the communication hole 9B are removed, and the lower wiring layer 4 made of a Cu film is formed at the bottom of the communication hole 4B. To expose.

In this anisotropic dry etching process, a dry etching process is performed by generating plasma using a CF-based gas such as CF ₄ as a dry etching gas. In dry etching, a bias power of a high frequency power is applied to a mounting table that holds the wafer W so that gas ions are drawn from the surface of the wafer W from the vertical direction, thereby performing anisotropic dry etching. Etching is performed. As a result, the barrier layer 10 and the insulating barrier layer 6 located at the bottom of the communication hole 4B are effectively removed as described above because dry etching can be performed through vacuum without being exposed to the atmosphere as in the prior art. It will be.

When the anisotropic dry etching process is completed as described above, the wafer W is then transferred to the fifth vacuum processing chamber 50 through a vacuum, and the process shown in FIG. The cleaning process is performed as shown in FIG. In this cleaning step, the residue present on the bottom surface in the communication hole 9B is removed to clean the bottom surface. Specifically, cleaning is performed by generating plasma while supplying H ₂ gas. This cleaning step and the fifth vacuum processing chamber 50 can be omitted when the cleanliness of the bottom of the communication hole 9B is high.

  When the cleaning process is completed as described above, the wafer W is then sequentially transferred to the sixth vacuum processing chamber 52 and the seventh vacuum processing chamber 54 via a vacuum, as shown in FIG. A wiring seed layer forming step is performed. In this wiring seed layer forming step, the wiring seed layer 12 is formed on the entire wafer surface, that is, the entire inner surface of the trench 9A and the entire inner surface including the bottom of the communication hole 9B. In this case, as described above, since the lower wiring layer 4 made of the Cu film is exposed at the bottom of the communication hole 9B, the lower wiring layer 4 and the wiring seed layer 12 are in direct contact with each other at the bottom. Will be joined.

Here, as the wiring seed layer 12, a laminated film of a Ru film and a Cu film is used here. Therefore, a Ru film is formed in the sixth vacuum processing chamber 52, and then a seventh film is formed via a vacuum. A Cu film is formed in the vacuum processing chamber 54. In the sixth vacuum processing chamber 52, for example, Ru ₃ (CO) ₁₂ is used as a source gas, and this is carried by a carrier gas made of CO, for example, and a Ru film can be formed by CDV processing. In the seventh vacuum processing chamber 54, a Cu film can be formed by plasma sputtering (PVD), or a Cu film can be formed by CVD processing or ALD processing using a Cu-containing organic source gas.

  When the wiring seed layer forming process is completed as described above, the wafer W is taken out of the processing system 20 and the process proceeds to the next plating process. In this plating step, as shown in FIG. 3C, a copper plating process is performed on the wiring seed layer 12 on the surface of the wafer so that the inside of the recess 9 including the communication hole 9B and the trench 9A is made of, for example, a metal made of a copper film. The film 14 is embedded. As a result, the communication wiring layer 16 is formed in the communication hole 9A, and the upper wiring layer 18 is formed in the trench 9B. Here, the communication wiring layer 16 and the upper wiring layer 18 are integrally formed. Thereafter, the process proceeds to a CMP process as shown in FIG. 3D, and the excess metal film 14, the wiring seed layer 12 and the barrier layer 10 on the wafer surface are removed by polishing using the above-described CMP process or the like. It will be.

  The wiring formation is completed as described above. Thus, when the barrier layer 10 is formed by the ALD method or the CVD method, since the lower wiring layer 4 made of the Cu film at the bottom of the communication hole 9B is covered with the insulating barrier layer 6, the ALD method or the CVD method is used. The surface of the lower wiring layer 4 is not exposed to the source gas or the like when performing the method. Then, the barrier layer 10 and the insulating barrier layer 6 at the bottom of the communication hole 9B are removed by dry etching to expose the lower wiring layer 4, and then the wiring seed layer 12 is formed. Adhesion with the wiring seed layer 12 can be maintained high.

  As described above, according to the present invention, the lower wiring layer 4, the insulating barrier layer 6, the interlayer insulating film 8, and the upper wiring layer 18 are sequentially stacked, and the communication holes 9 B formed in the interlayer insulating film 8 are formed. In the wiring forming method of forming the interconnecting wiring layer 16 that embeds a metal film and makes the upper wiring layer 18 and the lower wiring layer 4 conductive, when the barrier layer 10 is formed by heat treatment, the lower wiring layer 4 Then, the insulating barrier layer 6 is covered, and thereafter the barrier layer 6 and the insulating barrier layer 6 at the bottom of the communication hole 9B are removed by anisotropic dry etching to expose the lower wiring layer 4, and thereafter Since the wiring seed layer 12 is formed, the adhesion between the lower wiring layer 4 and the wiring seed layer 12 in contact with the lower wiring layer 4 can be greatly improved.

In the case where the interlayer insulating film 8 is formed of a low dielectric constant material including pores, a sealing step is performed as shown in FIG. 2F after the ashing step to seal the pores. Therefore, even if an ALD method or a CVD method having excellent step coverage is performed in the subsequent process, it is possible to prevent the deposition gas or the like from entering the porous body. As a result, it is possible to prevent the relative dielectric constant of the interlayer insulating film 8 from being lowered, and this film characteristic can be maintained high.
Furthermore, since the trench 9A is formed in the vacuum atmosphere in the first vacuum processing chamber 42, the trench 9A is not directly exposed to the atmosphere, but faces the trench 9A. It is possible to prevent the surface of the interlayer insulating film 8 from absorbing moisture from the atmosphere. Therefore, the film characteristics of the interlayer insulating film 8 can be kept higher by this amount.

<Second embodiment>
Next, a second embodiment of the wiring forming method of the present invention will be described. In the previous first embodiment, the sacrificial film 60 is embedded in the communication hole 9B in the pretreatment step, and this is removed by ashing after trench formation in the first vacuum processing chamber. In the embodiment, the sacrificial film which is an organic flat film is not used and the ashing process is omitted. FIG. 4 is a process diagram showing the main part of the second embodiment of the wiring forming method of the present invention. The same components as those shown in FIGS. 2 and 3 are denoted by the same reference numerals, and the description thereof is omitted.

  In the second embodiment, an etching stopper film 70 and a mask pattern 72 made of a metal-containing material are sequentially formed in advance on the interlayer insulating film 8 as shown in FIG. A communication hole 9B is formed. The etching stopper film 70 functions as an etching stopper when the mask pattern 72 is formed by patterning. The mask pattern 72 functions as a mask for forming a trench later. The etching stopper film 70B is made of, for example, a TEOS film. The mask pattern 72 is made of, for example, a TiN film.

  If the wafer W is formed as shown in FIG. 4A in the preprocessing step, the wafer W is loaded into the processing system 20 shown in FIG. Then, a trench forming process is performed on the wafer W in the first vacuum processing chamber 42. That is, as shown in FIG. 4B, by performing a dry etching process using the mask pattern 72 as a mask here, the interlayer insulating film 8 is partially removed in the thickness direction to form a trench 9A. Thereafter, since there is no photoresist on the wafer, the wafer is transported through a vacuum atmosphere without performing an ashing process, and the process proceeds to a sealing process as shown in FIG.

  The subsequent processing is the same as in the case of the first embodiment shown in FIGS. 2 (G) to 2 (H) and FIGS. 3 (A) to 3 (D). The mask pattern 72 made of the TiN film and the etching stopper film 70 may be removed by CMP processing or may be left. In the case of the second embodiment, the same effects as those of the first embodiment can be exhibited. In the case of the second embodiment, the ashing process among the processes performed in the processing system 20 can be omitted as compared with the case of the first embodiment.

  In each of the above embodiments, a case where a TaCN film is used as the barrier layer 10 has been described as an example. However, the barrier layer 10 is not limited thereto, and the barrier layer 10 may be a Ti film, a TiN film, a Ta film, a TaN film, A single layer structure or a laminated structure of one or more films selected from the group consisting of a TaCN film, a W (tungsten) film, a WN film, and a Zr film can be used.

  In each of the above embodiments, the case where a laminated film of a Ru film and a Cu film is used as the wiring seed layer has been described as an example. However, the present invention is not limited thereto, and the wiring seed layer includes a Cu film, a Ru film, One film selected from the group consisting of a laminated film of a Ru film and a Cu film, a Co film, and a laminated film of a Co film and a Cu film can be used. In this case, in addition to the pure Cu film, the Cu film includes a Cu alloy film (Al, Mn, Mg, Sn, Pb, Zn, Pt, Au, Ag, Ni, Co, etc. are contained in Cu), A Cu film to which impurities such as Si, C, P, and B are added is included.

  Although the semiconductor wafer is described as an example of the object to be processed here, the semiconductor wafer includes a silicon substrate and a compound semiconductor substrate such as GaAs, SiC, GaN, and the like, and is not limited to these substrates. The present invention can also be applied to glass substrates, ceramic substrates, and the like used in display devices.

2 Lower insulating film 4 Lower wiring layer 6 Insulating barrier layer 8 Interlayer insulating film 9 Recess 9A Trench (groove)
9B communication hole 10 barrier layer 12 wiring seed layer 16 communication wiring layer 18 upper wiring layer 20 processing system 22, 24 common transfer chamber 42-54 vacuum processing chamber 60 sacrificial film 62 mask pattern 72 mask pattern of metal-containing material W semiconductor wafer ( Processed object)

Claims (10)

A lower wiring layer, an insulating barrier layer, an interlayer insulating film, and an upper wiring layer are sequentially laminated on the object to be processed, and a metal film is embedded in a communication hole formed in the interlayer insulating film, so that the upper wiring layer and the lower layer are embedded. In the wiring formation method of forming a communication wiring layer that conducts with the wiring layer,
A sacrificial film is embedded in the communication hole with the insulating barrier layer left, and a pattern mask is formed on the sacrificial film with a photoresist to form a trench for the upper wiring layer in the interlayer insulating film. A pretreatment step to form;
A trench forming step of forming the trench in the interlayer insulating film by performing a dry etching process on the object to be processed using the pattern mask as a mask in a vacuum processing chamber;
An ashing step of ashing and removing the sacrificial film and the pattern mask in a vacuum processing chamber;
A barrier layer forming step of forming a barrier layer on the entire surface including the surface in the trench and the surface in the communication hole in a vacuum processing chamber by ALD or CVD;
An anisotropic dry etching step of exposing the lower wiring layer by removing the barrier layer and the insulating barrier layer formed at the bottom of the communication hole by performing anisotropic dry etching in a vacuum processing chamber When,
A wiring seed layer forming step of forming a wiring seed layer over the entire surface including the surface in the trench and the surface in the communication hole in a vacuum processing chamber;
A wiring formation method comprising: The interlayer insulating film is made of a low dielectric constant material having a porosity, and a sealing process for sealing the porous in a vacuum processing chamber between the ashing process and the barrier layer forming process is vacuumed from the ashing process. The wiring forming method according to claim 1, wherein the wiring forming method is performed via a wiring. The wiring formation method according to claim 1, wherein the trench formation step and the ashing step are performed in the same vacuum processing chamber. A lower wiring layer, an insulating barrier layer, an interlayer insulating film, and an upper wiring layer are sequentially laminated on the object to be processed, and a metal film is embedded in a communication hole formed in the interlayer insulating film, so that the upper wiring layer and the lower layer are embedded. In the wiring formation method of forming a communication wiring layer that conducts with the wiring layer,
A pre-processing step of forming the communication hole with the insulating barrier layer left, and forming a pattern mask made of a metal-containing material for forming the trench for the upper wiring layer in the interlayer insulating film; ,
A trench forming step of forming the trench in the interlayer insulating film by performing a dry etching process on the object to be processed using the pattern mask as a mask in a vacuum processing chamber;
A barrier layer forming step of forming a barrier layer on the entire surface including the surface in the trench and the surface in the communication hole in a vacuum processing chamber by ALD or CVD;
An anisotropic dry etching step of exposing the lower wiring layer by removing the barrier layer and the insulating barrier layer formed at the bottom of the communication hole by performing anisotropic dry etching in a vacuum processing chamber When,
A wiring seed layer forming step of forming a wiring seed layer over the entire surface including the surface in the trench and the surface in the communication hole in a vacuum processing chamber;
A wiring formation method comprising: The interlayer insulating film is made of a low dielectric constant material having a porous material, and a sealing process for sealing the porous material in a vacuum processing chamber is performed between the trench forming process and the barrier layer forming process. The wiring forming method according to claim 4. 6. A cleaning process for cleaning a bottom surface of the communication hole in a vacuum processing chamber between the anisotropic dry etching process and the wiring seed layer forming process. The wiring formation method of description. The wiring seed layer is made of one film selected from the group consisting of a Cu film, a Ru film, a laminated film of a Ru film and a Cu film, a Co film, and a laminated film of a Co film and a Cu film. The wiring formation method according to any one of claims 1 to 6. The barrier layer is a single layer structure or a laminated structure of one or more films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a TaCN film, a W (tungsten) film, a WN film, and a Zr film. The wiring forming method according to claim 1, further comprising: The said to-be-processed object between the said each vacuum processing chamber is performed by conveying the to-be-processed object through the inside of a vacuum atmosphere, The Claim 1 thru | or 8 characterized by the above-mentioned. Wiring formation method. The plating process for performing a plating process for filling the trench and the communication hole and the CMP process for removing an extra layer on the object to be processed are performed after the wiring seed layer forming process. Item 10. The wiring forming method according to any one of Items 1 to 9.

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