JP2012073148A - Fault diagnosis equipment, fault diagnosis method, and fault diagnosis program - Google Patents

Abstract

When discrepancies occur between actual measurement and simulation results, not only the number of paths that cause discrepancies but also the magnitude of the discrepancy in time is evaluated.
In the present invention, a delay time spent when a digital signal propagates through a fault propagation path from a fault candidate extracted by backward tracking of a circuit to a scan circuit (SFF) existing on the output side of the candidate is obtained. If a failure candidate with a delay of a path whose measured test result is unsuccessful is larger than that of a path that has passed, it is determined that the failure is a true failure, and if the magnitude relationship is reversed (mismatched), A fault candidate with a statistically small temporal reversal is determined to be a true fault. A path with a large delay has a smaller time margin in circuit operation than a path with a small delay, and the test result is likely to fail when a delay fault occurs. Therefore, a failure candidate whose pass / failure of the actually measured test result and the delay time follow the above is highly likely to be a true failure.
[Selection] Figure 7

Description

  The present invention relates to a failure diagnosis apparatus, and more particularly to an integrated circuit failure diagnosis apparatus.

  Due to the miniaturization of wiring and transistors, even a minute defect that did not cause a problem in the past is increasingly causing a delay fault. Further, the delay fault has a problem that it is difficult to specify the fault location as compared with the stuck-at fault that has been the object of fault diagnosis.

  Since the stuck-at fault propagates only according to the logical expression expressed by the circuit, the circuit is moved to the input side (upstream) along the fault propagation path based on the test result Pass / Fail information. It was possible to diagnose the fault location by going back (back tracing).

  However, in the case of a delay fault, the test result also changes depending on the timing margin of the test path. For example, in a path with a large timing margin, even in a scan-flip-flop (SFF: scan circuit) existing on the output side (downstream) of a delay fault location, if the delay fault is slight, the test result is Pass. In some cases.

  That is, in the stuck-at fault diagnosis algorithm using the backtrace, it is considered that there is no failure on the input side (upstream) of the location where the test result is Pass (pass), and therefore the location of the delay failure cannot be diagnosed correctly.

  A test of a logic circuit using a scan circuit is performed by applying a test digital signal (test pattern) to a circuit chip and observing a response to the digital signal with an SFF. At this time, the case where the observation result in the SFF matches the simulation is called “Pass”, and the case where the observation result does not match is called “Fail”. If the test results in all SFFs are Pass (pass), it is determined that the chip is a non-defective product.

[Non-Patent Document 1]
Non-Patent Document 1 “Delay Fault Diagnosis Method Considering Detectable Delay Fault Size (The IEICE Transactions D, Vol. J92-D No. 7 pp. 984-993, 2009/7)” A method for specifying a location where a delay fault has occurred in a circuit is disclosed.

[Flow of processing in the method of Non-Patent Document 1]
FIG. 1 is a flowchart of processing in this method, and the procedure is as follows.

(1) Step S1
First, the circuit area (failure candidate) where the communication failure is estimated to be estimated is roughly estimated by back tracing the circuit back to the input side (upstream) from the SFF where the test result is Fail (fail). To extract.

  FIG. 2 schematically shows this estimation method. As shown in FIG. 2, when there are a plurality of SFFs whose test result is “Fail”, the common part of the circuit area estimated by backward tracking is a failure candidate.

(2) Step S2
Next, when a delay fault occurs in the above-described fault candidate, the minimum value of the delay amount that can be detected with the Fail pattern that is a test pattern at that time is calculated.

(3) Step S3
Then, Pass (Fail) / Fail (Fail) of the circuit response when the test pattern is applied with the minimum delay fault inserted in the circuit is calculated by simulation.

(4) Step S4
Next, the simulation result of the circuit response is compared with the test result of the actual chip, and the degree of coincidence is calculated.

(5) Step S5
Next, the degree of coincidence is similarly calculated for a pass pattern that is a test pattern in which no failure occurs in the actual chip test (actual measurement).

(6) Step S6
Then, a harmonic average of the degree of coincidence with the fail (fail) pattern and the degree of coincidence with the pass (pass) pattern is calculated, and a portion having the maximum value is determined as a true failure.

  Note that the behavior of the SFF when a delay fault is inserted into the above fault candidates is classified as follows.

(1) TFSF (Test Fail Simulation Fail)
The test result is “Fail” in both the actual chip test and the simulation.

(2) TPSF (Test Pass Simulation Fail)
The test result of the actual chip test is Pass (pass), and the test result of simulation is Fail (fail).

(3) TPSP (Test Pass Simulation Pass)
The test result is Pass in both the actual chip test and simulation.

(4) TFSP (Test Fail Simulation Pass)
The test result of the actual chip test is “Fail”, and the test result of the simulation is “Pass”.

(5) TFSPD (Test Fail Simulation Pass with D Propagation)
The test result of the actual chip test is Fail (fail), and the test result of simulation is Pass (pass), but the influence of the delay increase due to the failure candidate reaches Flip-Flop (FF).

  FIG. 3 shows the relationship between the above classifications. FIG. 3 shows the relationship between the SFF whose actual chip test result is “Fail” and the SFF whose simulation test result is “Fail”. When it matches, it becomes 0 except TFSF.

Based on this, the degree of coincidence SCF is calculated from the following equation (1).
SFC = (ΣTFSF + ΣTFSPD) / (ΣTFSP + ΣTFSF + ΣTPSF) (1)

  In addition, the Σ symbol in the equation (1) means that the number of SFFs included in each of the above classifications is added to all the test patterns in which the test result includes Fail (failure).

  In Non-Patent Document 1, the test result of the actual chip test is “Fail”, whereas the simulation test result is “Pass”, and even in the SFF where the test results are inconsistent, When the influence of the delay fault inserted into the SFF reaches the SFF, it is classified as TFSPD and handled as having no contradiction in the test results. Therefore, the numerator of formula (1) includes TFSPD.

  The problem with the technology described in Non-Patent Document 1 is that only the number of SFFs in which the pass / fail test results are inconsistent between the actual test and the simulation is used when estimating the failure location. The delay amount is not taken into consideration.

  As described above, in the technique described in Non-Patent Document 1, the test result of the actual chip test is “Fail”, whereas the test result of the simulation is “Pass”, and the test result is inconsistent. Even in the SFF, if the influence of the delay fault inserted in the simulation reaches the SFF, it is classified as TFSPD and handled as having no contradiction in the test result.

  For this reason, even when the timing margin of the path from the failure candidate to the SFF that has failed (Fail) is large and delay failure is unlikely to occur, if the influence of the delay is propagated, it is treated as inconsistent. End up. As a result, an incorrect candidate may be determined as a true failure.

  FIG. 4 shows a case where an erroneous candidate is determined as a true failure. In this example, Fail (fail) occurs in SFF1 and SFF2 in the actual chip test. Further, the nets A and B are extracted as failure candidates by tracing the circuit back to the input side (upstream). Furthermore, when a simulation is performed by embedding a failure in the net A, Fail (fail) is reproduced in SFF1, but the test result of SFF2 is Pass (pass), which is inconsistent with actual measurement.

  On the other hand, when the simulation is performed for the net B in the same manner, the failure (failure) is reproduced in SFF1 and SFF2, but the failure (failure) is found in SFF3 that was not actually failed (failure). It has occurred.

  At this time, when the failure location is specified by the technique described in Non-Patent Document 1, first, the SFF2 Pass when the failure is inserted into the net A is classified as TFSPD, and the actual measurement and the simulation are not contradictory. Treated as a thing. Therefore, the degree of coincidence SCF (A) when the delay fault is assumed in the net A is 1. On the other hand, when a failure is inserted into the net B, the number of SFFs that have failed (failed) in the simulation (number of failures) is 3, whereas the number of SFFs that have failed (failed) in the actual measurement is 3 Since the number (Fail number) is 2, the degree of coincidence SCF (B) is 2/3. That is, it is determined that the net A having the highest matching degree SCF is a true failure.

  However, if the path from the net A to the SFF 2 has a large timing margin, it can be said that a delay fault is unlikely to occur in the path, so it may be an error to point out the net A as a true fault. high.

  Also, as shown in FIG. 5, when a fault is inserted in net B, if the input transition of SFF3 and the timing of measurement are in conflict, the test result in the simulation is “Fail”. However, due to the influence of delay calculation errors and manufacturing variations, it is fully conceivable that the actual test result will be Pass. That is, the net B is more likely to be a true failure than the net A under the above conditions.

  In this way, the technique described in Non-Patent Document 1 may point out an erroneous failure point because the test result Pass (Fail) / Fail (Fail) is the same between the simulation and the actual measurement. This is because, when there is a mismatch between Pass (pass) / Fail (fail), it is not considered whether it is a slight difference or a large difference in timing. Even if there are few mismatches, if the difference in timing is large, it should not be considered a true failure. On the other hand, if the timing difference is small even in a place where there are many unmatched places, it can be considered that the candidate is a true failure.

Delay Fault Diagnosis Method Considering Detectable Delay Fault Size (The Institute of Electronics, Information and Communication Engineers Journal D, Vol. J92-D No. 7 pp. 984-993, 2009/7)

  In the present invention, a failure propagation path from a failure candidate extracted by backward tracking of a circuit to a Scan-Flip-Flop (SFF) existing on the candidate output side (downstream), and a delay time spent when a digital signal propagates A failure candidate whose delay of the path whose actual test result is “Fail” is greater than that of the path whose path is “Pass” is determined to be a true failure. If a reverse (mismatch) occurs in the magnitude relationship, a failure candidate whose temporal reversal is statistically small is determined to be a true failure.

  A path with a large delay has a smaller time margin in circuit operation than a path with a small delay, and it is considered that the test result is likely to fail (fail) when a delay fault occurs. A failure candidate whose magnitude relationship between Pass / Fail and delay time of the above conforms to the above is highly likely to be a true failure. In the present invention, such a relationship between the delay time and the test result is used.

  In addition, in the present invention, when a mismatch occurs between the actual measurement and the simulation result, not only the number of paths where the mismatch occurs, but also the temporal magnitude relationship of the mismatch is evaluated. If it is smaller, the failure candidate is determined as a true failure.

  The fault diagnosis apparatus of the present invention includes a means for obtaining a candidate for a delay fault point by performing backward tracing back to the input side starting from a scan circuit whose test result has failed in an integrated circuit test, Means for extracting a fault propagation path from a fault location candidate to a scan circuit existing on the output side of the fault candidate, means for calculating a delay time when a digital signal propagates through the fault propagation path, and fault propagation path The boundary value of the delay time of the pass path and the fail path is calculated by means of grouping (classifying and grouping) into a pass path where the test result passes and a fail path where the test result fails. Means for extracting a passing route having a delay time larger than the boundary value and a failing route having a delay time smaller than the boundary value as a marginal route; A means for calculating the degree of coincidence from either the number of paths or the variation in delay value, and a means for selecting a fault candidate having the best degree of coincidence and outputting the selected fault candidate as a true fault It comprises.

  The failure diagnosis method of the present invention is a failure diagnosis method implemented by a computer, and in the integrated circuit test, the circuit is traced back to the input side starting from a scan circuit that has failed the test result. , Obtaining a delay fault location candidate, extracting the fault propagation path from the delay fault location candidate to the scan circuit existing on the output side of the fault candidate, and when the digital signal propagates through the fault propagation path Calculating the delay time to spend, grouping (classifying, grouping) the failure propagation path into a pass path where the test result passes and a fail path where the test result fails, Calculating the boundary value of the delay time of the failed path, and the passing path having a delay time larger than the boundary value and the reject path having a delay time smaller than the boundary value Select a failure candidate that has the best match, and calculate the matching score from either the number of marginal routes or the number of marginal routes and the variation in delay value. Outputting the candidate as a true fault.

  The fault diagnosis program of the present invention is a program for causing a computer to execute the processing in the above fault diagnosis method. The failure diagnosis program of the present invention can be stored in a storage device or a storage medium.

  In the present invention, even when there is a slight discrepancy in time between the actual measurement and the simulation test result, since the statistical evaluation of the time discrepancy is performed, the location of the delay fault is correctly pointed out. can do. Therefore, it is possible to avoid the problem of misdiagnosis that has occurred in the existing technology.

10 is a flowchart showing a procedure of delay fault diagnosis processing according to Non-Patent Document 1. It is a schematic diagram for demonstrating the process which calculates | requires the candidate of a delay fault location in the nonpatent literature 1. FIG. It is a schematic diagram for demonstrating the method of calculating | requiring the coincidence degree of the measurement result and simulation test result in a nonpatent literature 1. It is a figure for demonstrating the problem of the method of a nonpatent literature 1. FIG. It is a figure for demonstrating the influence which it has on a test result when a delay fault generate | occur | produces in a circuit. It is a block diagram which shows the structural example of the failure diagnosis apparatus of this invention. It is a figure shown from a viewpoint of the flow of data in 1st Embodiment of this invention. It is a flowchart which shows the procedure of the process of 1st Embodiment of this invention. It is a figure for demonstrating how to obtain | require the propagation path of a delay fault in 1st Embodiment of this invention. In the first embodiment of the present invention, the true failure location is determined from the relationship between the path delay from the failure candidate to the Scan-Flip-Flop (SFF) and the test result Pass / Fail (fail) in the SFF. It is a figure for demonstrating the method to estimate. In the first embodiment of the present invention, the possibility that the fault is a true fault is determined from the relationship between the delay of the path from the fault candidate to the SFF and the test result Pass (Fail) / Fail (Fail) in the SFF. It is a flowchart of the process which shows the procedure for calculating | requiring the matching degree shown. In 2nd Embodiment of this invention, it is a schematic diagram for demonstrating the example for calculating | requiring the boundary value of the delay of a Pass (pass) path | pass and a Fail (failure | failure) path | route. It is a figure for demonstrating the table | surface which matched the name (identification information) of a delay fault propagation path, the test result of a delay fault propagation path, and the delay value from a failure location to SFF. It is a figure for demonstrating the calculation example 1 of the residual sum of squares between the delay value of a marginal path | route, and a boundary value. It is a figure for demonstrating the calculation example 2 of the residual sum of squares between the delay value of a marginal path | route, and a boundary value. It is a figure which shows the relationship between the delay value of the path | route in FIG. 12, and the temporal operation margin of each path | route, and shows that the temporal operation margin is influenced by the measurement timing of SFF. It is a flowchart which shows the procedure of the process of 3rd Embodiment of this invention. It is a figure for demonstrating the three-dimensional histogram (no duplication) used by 3rd Embodiment of this invention. It is a figure for demonstrating the three-dimensional histogram (with duplication) used by 3rd Embodiment of this invention. It is a block diagram which shows the example of a failure diagnosis system structure using the failure diagnosis apparatus of this invention.

<First Embodiment>
Hereinafter, a first embodiment of the present invention will be described with reference to the accompanying drawings.
FIG. 6 shows a configuration example of the failure diagnosis apparatus of the present invention. FIG. 7 shows a data flow in the failure diagnosis apparatus of the present invention.

  The failure diagnosis apparatus according to the present invention includes an input device 10, a storage device 20, an arithmetic processing device 30, a read-only memory 40, and an output device 50.

  The input device 10 inputs circuit connection information 21, circuit delay information 22, test pattern information 23, and test result information 24, and stores each input information in the storage device 20.

  The storage device 20 includes circuit connection information 21, circuit delay information 22, test pattern information 23, test result information 24, circuit operation information 25, failure candidate list 26, failure propagation path list 27, and failure propagation. The path delay information 28 and the matching degree information 29 are held.

  The circuit connection information 21 is information describing the connection relation of circuit elements inside the integrated circuit to be diagnosed.

  The circuit delay information 22 is information in which a delay time spent when a digital signal propagates between the circuit elements is described.

  The test pattern information 23 is pattern information of a test signal for confirming that the circuit operates normally, and represents a signal waveform (digital signal waveform for test) applied to the circuit during the test.

  The test result information 24 is a circuit response when the test pattern is applied to the circuit, and stores information on whether or not the circuit has operated as expected. At this time, the case where the circuit operation is as expected is referred to as “Pass”, and the case where the circuit operation is different from the expectation is referred to as “Fail”.

  The circuit operation information 25 is information describing the operation of each net in the circuit when there is no failure in the circuit.

  The failure candidate list 26 is information in which a list of failure candidates extracted by scanning the circuit back to the input side (upstream) from the Scan-Flip-Flop (SFF) whose test result is Fail (failed) is described. is there.

  The failure propagation path list 27 is information in which a list of failure propagation paths from each failure candidate included in the failure candidate list 26 to the SFF located on the candidate output side (downstream) is described.

  The failure propagation path delay information 28 is information in which a delay time spent when a digital signal propagates through each failure propagation path included in the failure propagation path list 27 is described.

  The degree of coincidence information 29 is information describing the possibility that each failure candidate is a true failure.

  The arithmetic processing device 30 includes a circuit simulation unit 31, a circuit retroactive treatment unit 32, a failure propagation path extraction unit 33, a delay calculation unit 34, a coincidence calculation unit 35, and a diagnosis unit 36.

  The circuit simulation unit 31 refers to the circuit connection information 21 and the test pattern information 23, obtains the operation of each net in the circuit during the test pattern travel by simulation, and generates the circuit operation information 25 as a result.

  The circuit retroactive processing unit 32 refers to the circuit connection information 21 and the test result information 24, extracts a failure candidate by tracing the circuit back to the input side (upstream) from the SFF whose test result is Fail (fail), A failure candidate list 26 is generated.

  The failure propagation path extraction unit 33 extracts a failure propagation path from each failure candidate included in the failure candidate list 26 to the SFF located on the candidate output side (downstream), and generates a failure propagation path list 27.

  The delay calculation unit 34 refers to the circuit delay information 22, obtains a delay time spent when the digital signal propagates through each fault propagation path included in the fault propagation path list 27, and generates delay information 28 on the fault propagation path. .

  The coincidence calculation unit 35 obtains the possibility that each failure candidate is a true failure from the relationship between the test result information 24 and the delay information 28 of the failure propagation path, and generates the coincidence information 29.

  The diagnosis unit 36 refers to the coincidence degree information 29 and selects a failure candidate that has the highest possibility of a true failure. Here, the diagnosis unit 36 notifies the output device 50 of the selected failure candidate. The diagnosis unit 36 may store the selected failure candidate in the storage device 20.

  The read-only memory 40 stores a program 41 that is executed by the arithmetic processing unit 30. The arithmetic processing unit 30 reads the program 41 from the read-only memory 40 and operates to thereby match the circuit simulation unit 31, the circuit retroactive unit 32, the failure propagation path extraction unit 33, and the delay calculation unit 34. It functions as the degree calculation unit 35 and the diagnosis unit 36, and realizes diagnosis processing.

  The program 41 is a failure diagnosis program.

  The output device 50 outputs the failure candidate selected by the diagnosis unit 36 as a failure diagnosis result 51.

[Hardware example]
As an example of the failure diagnosis apparatus of the present invention, a computer such as a PC (personal computer), a thin client terminal / server, a workstation, a mainframe, and a supercomputer is assumed. The failure diagnosis apparatus of the present invention is not limited to a terminal or a server, but may be a relay device or a peripheral device. The failure diagnosis apparatus of the present invention may be an expansion board mounted on a computer or a virtual machine (Virtual Machine (VM)) built on a physical machine. However, actually, it is not limited to these examples.

  Examples of the input device 10 include an I / O board, a keyboard and a keypad, a keypad on the screen, a touch panel, a tablet, a reading device that reads an IC chip and a storage medium, and the like. The input device 10 may be an interface (I / F) for acquiring information from an external input device or storage device.

  Examples of the storage device 20 and the read-only memory 40 include a semiconductor storage device such as a RAM (Random Access Memory), a ROM (Read Only Memory), an EEPROM (Electrically Erasable and Programmable Read Only Memory), a flash memory, etc. An auxiliary storage device such as a drive (Drive) or SSD (Solid State Drive), or a removable disk such as a DVD (Digital Versatile Disk) or an SD memory card (Secure Digital memory card) or a storage medium (media) may be considered.

  As an example of the arithmetic processing unit 30, a CPU (Central Processing Unit), a microprocessor (microprocessor), a microcontroller, or a semiconductor integrated circuit (Integrated Circuit (IC)) having a dedicated function can be considered.

  Examples of the output device 50 include a display device such as an LCD (Liquid Crystal Display), a PDP (Plasma Display), an organic EL display (Organic Electroluminescence Display), or a printing device such as a printer that prints output contents on paper. . The output device 50 may be an interface (I / F) for outputting information to an external display device or storage device. Note that the output device 50 may be the storage device 20.

  The input device 10, the storage device 20, the arithmetic processing device 30, the read-only memory 40, and the output device 50 may be independent computers.

  However, actually, it is not limited to these examples.

[Diagnostic procedure]
With reference to FIG. 8, the procedure of the diagnostic process of this embodiment is demonstrated.

(1) Step S101
The input device 10 stores circuit connection information 21, circuit delay information 22, test pattern information 23, and test result information 24 in the storage device 20.

(2) Step S102
The circuit simulation unit 31 executes circuit simulation based on the circuit connection information 21 and the test pattern information 23, obtains the operation of each net in the circuit when the test pattern is applied to the circuit, and generates circuit operation information 25. .

(3) Step S103
Next, the circuit retroactive processing unit 32 refers to the circuit connection information 21 and the test result information 24, starts the SFF whose test result is “Fail” (failed), and starts the circuit along the fault propagation path on the input side ( A primary failure candidate is derived by tracing back (upstream) to generate a failure candidate list 26. Here, the point where the traces overlap is set as the primary failure candidate.

(4) Step S104
Next, the failure propagation path extraction unit 33 refers to the failure candidate list 26, extracts a failure propagation path from the primary failure candidate to the SFF located on the candidate output side (downstream), and displays the failure propagation path list 27. Generate.

  For example, as shown in FIG. 9, in a circuit composed of seven nets from NET1 to NET7, the operation of the circuit in a certain test pattern is the value in parentheses in FIG. 9, and the rise (rising) transition of NET2 Let us consider the case where a delay fault occurs.

  When tracing how this delay fault propagates to the output side (downstream) of the circuit, two paths “NET2-NET4-NET6” and “NET2-NET4-NET7” are extracted. For the route of “NET2-NET4-NET5”, 0 is input to NET1, and the logical transition is not transmitted to the SFF, so this route is not extracted.

  The failure propagation path extraction unit 33 extracts the propagation path of the delay fault in this way, and generates the failure propagation path list 27. Further, as described above, this processing requires information on each net in the circuit when each test pattern is applied. This information is stored in the circuit operation information 25.

(5) Step S105
The delay calculation unit 34 refers to the circuit delay information 22, calculates a delay time spent when the digital signal propagates through each failure propagation path included in the failure propagation path list 27, and generates delay information 28 on the failure propagation path. To do.

  The circuit delay information 22 describes a delay time spent when a digital signal propagates between circuit elements in the integrated circuit. The delay calculation unit 34 calculates the delay time of each route by integrating these delay times.

  The circuit delay information 22 itself can be generated using existing integrated circuit design software. The existing integrated circuit design software includes a function for outputting the circuit delay information 22 in a format called “Standard Delay Format (SDF)”. The computer executes such integrated circuit design software and outputs circuit delay information 22.

(6) Step S106
The coincidence calculation unit 35 compares the test result information 24 with the delay information 28 of the failure propagation path, and generates coincidence information 29 for each failure candidate.

  The degree of coincidence is a parameter indicating the possibility (likelihood: likelihood) that the failure candidate under consideration is a true failure.

  FIG. 10 is a diagram illustrating a method for calculating the degree of coincidence. In this example, the degree of coincidence is set to 1 if the delay of the path that is passed (pass) is smaller than the delay of the failure propagation path that results in an actual test result of Fail (fail). If the above is not followed, the degree of coincidence is reduced in the range of 0 to 1 depending on the degree. Note that 0 is the worst value and 1 is the best value.

  This is because a path with a long delay time for signal propagation has a smaller temporal operation margin than a path with a short delay, so the test result is likely to fail (fail). This is based on the fact that there is a high possibility of being a candidate.

  In the example of FIG. 10, the degree of coincidence is set to a value in the range of 0 to 1, and the state with the highest degree of coincidence is represented by the degree of coincidence = 1, but is not limited to this. If the degree of coincidence expresses the likelihood (likelihood) of a failure candidate obtained from the correspondence between the magnitude of the delay and the test result Pass (Fail) / Fail (Fail), the range of the degree of coincidence value is arbitrary. Good.

(7) Step S107
The diagnosis unit 36 refers to the coincidence information 29, selects a failure candidate having the largest coincidence, and outputs the failure diagnosis result 51 as a place where there is a high possibility of a true failure.

  The diagnosis unit 36 accumulates the degree of coincidence when the test result is “Fail” in a plurality of test patterns, and performs the diagnosis similarly using the accumulated result S. In addition, when the number of patterns used for diagnosis is N, a method in which a candidate having the smallest “S ÷ N” is pointed out as a true failure is also conceivable.

[Matching degree calculation process]
With reference to FIG. 11, a detailed procedure of the degree-of-match calculation process will be described.

(1) Step S201
The degree-of-match calculation unit 35 checks whether there is a location where the test result is “Fail” (non-failure path) in the SFF that is not included in the fault propagation path starting from the fault candidate (other than the fault propagation path). .

(2) Step S202
The coincidence degree calculation unit 35 sets the coincidence degree of the candidate to 0 when there is a location where the test result is Fail (fail).

(3) Step S203
The coincidence calculation unit 35 confirms whether the test result is Fail (fail) for all the SFFs included in the failure propagation path and all the other SFFs are Pass (pass).

(4) Step S204
The coincidence calculation unit 35, when all the SFFs included in the failure propagation path have a test result of “Fail” and the other SFFs all have a test result of “Pass”, the coincidence degree of the candidate Is 1. However, if this is true for all the test patterns, there is a high possibility that the diagnosis result is a stuck-at fault, and this is output as a warning message.

(5) Step S205
When the degree of coincidence is not determined in step S201 and step S203 described above, the coincidence degree calculation unit 35 indicates that Pass (Fail) / Fail (failure) is included in the test result of the SFF included in the failure propagation path of the failure candidate. If both are present and the test results of other SFFs are Pass (pass), first, as shown in FIG. 12A, the failure propagation path is classified into a Pass (pass) path and a Fail (fail) path. To do.

  The Pass path is a fault propagation path whose test result in the SFF at the path end is Pass. The Fail (failed) path is a failure propagation path whose test result in the SFF at the path end is Fail (failed).

  The coincidence calculation unit 35 refers to the signal propagation delay time T of the Pass (pass) path and the Fail (fail) path, and determines the boundary value of the delay time of the Pass (fail) path and the Fail (fail) path. .

  Here, a Fail route having a delay amount smaller than the boundary value and a Pass route having a delay amount larger than the boundary value are referred to as a marginal route.

  The coincidence calculation unit 35 determines the boundary value so that the sum of squares of the residual between the delay of the marginal path and the boundary value (residual sum of squares) becomes as small as possible.

(6) Step S206
The coincidence calculation unit 35 changes the subsequent processing depending on whether or not a marginal route exists.

(7) Step S207
The coincidence calculation unit 35 sets the coincidence to 1 when there is no marginal route.

(8) Step S208
When there is a marginal route, the coincidence calculation unit 35 determines the coincidence based on the number of marginal routes and the delay distribution (variation).

For example, the following method can be considered as a method for calculating the degree of coincidence.
The coincidence calculation unit 35 compares the delay variation (process variation) caused by the process variation with the delay variation (standard deviation) of the marginal path, and if the delay variation of the marginal path is sufficiently small, the coincidence degree is calculated. Set to 1. If the degree is the same, the degree of coincidence is set to 0.5. If the delay variation of the marginal path is larger, the matching degree is set to zero.

  This is a calculation method paying attention to the cause of the marginal path. If the delay calculation accuracy is sufficiently high, a marginal path is not generated originally, but a marginal path is generated because the actual delay does not match the calculated value due to the influence of process variations. Based on this concept, if the delay variation of the marginal path is smaller than the process variation, it can be said that the discrepancy between the magnitude of the delay and the pass / fail of the test result is small.

  It should be noted that the cause of the marginal path may be the influence of delay calculation errors. Therefore, the delay calculation accuracy of the marginal path may be compared with the delay calculation accuracy. Alternatively, a value obtained by summing the calculation accuracy of the process variation and the delay variation of the marginal path may be used as the comparison target.

  The degree of coincidence calculation unit 35 has a small number of paths when there is a place where the test result is Fail (fail) in an SFF that is not included in the failure propagation path, or where a marginal path exists. In such a case, the degree of coincidence may be recalculated after removing them.

  This is a remedy for a case where a small number of paths disturb the magnitude relationship between the test result Pass / Fail and the delay. Regarding the number that can be removed, there are a method of setting an arbitrary number of about 10 and a method of setting a few percent to 10% of the number of original Pass (pass) paths and Fail (fail) paths.

[Calculation method of boundary value]
Next, an example of calculating the boundary value will be described with reference to FIGS. 12B to 12D.

  FIG. 12B is a table in which the name (identification information) of the delay fault propagation path, the test result of the delay fault propagation path, and the delay value from the fault location to the SFF are associated with each other. In this embodiment, it is assumed that eight delay fault propagation paths are generated from a single fault candidate. For convenience, the names of the routes are A to H. Moreover, the test result of each path | route and the delay value from a failure location to SFF are as FIG. 12B shows.

  Here, when the test results of the paths A to H are compared with the delay value, the delay value of the Pass path is larger than that of the Fail path (Fail (fail) than the Pass path). There are four routes (routes C, D, E, and F) where the delay value of the route is small).

  Further, the boundary value is classified as a marginal route by classifying a Pass route having a delay value larger than the boundary value and a Fail route having a delay value smaller than the boundary value, and the delay value and boundary value of the marginal route. Is defined such that the residual sum of squares is minimized.

  Therefore, the boundary value is considered to be a value close to the delay values of the paths C, D, E, and F.

  Therefore, when the residual sum of squares is calculated when the boundary values are the delay values (17, 16, 14, 11) of the paths C, D, E, and F, the values are as shown in FIG. 12C.

  According to FIG. 12C, the residual sum of squares is the smallest when the boundary value is 14, and the residual sum of squares is the next smallest when the boundary value is 16. From this, it is considered that the boundary value at which the residual sum of squares is minimum exists in the range of 14 to 16. Therefore, when searching for the boundary value at which the residual sum of squares has the minimum value in this range, the boundary value = 14.5 is obtained.

  Although the boundary value calculation method as described above is an example in which the boundary value is obtained by simple iterative calculation, the residual sum of squares is minimized by a well-known iterative calculation method such as the golden section method. A method for obtaining the boundary value is also considered.

[Reason for problem solving]
In the method of Non-Patent Document 1, a circuit simulation is performed in a state where a delay fault is inserted into a fault candidate, and the degree of coincidence is high by comparing the actual measurement and the test result of the simulation (Pass) / Fail (fail). The failure candidate is determined to be a true candidate. At this time, only the number of matching points and non-matching points in the test result Pass / Fail (failure) is the subject of comparison. It is not considered whether it is a big difference or not. For this reason, as shown in FIG. 4, an erroneous location may be determined as a failure location.

  Even if there are few mismatches, if the timing difference is large, it should not be considered a true failure. On the other hand, even when there are many unmatched parts, if the timing difference is small, it may be due to the influence of process variations or delay calculation errors, and the candidate may be a true candidate.

  Therefore, in the present invention, first, the delay time spent when the digital signal is propagated along the path from the failure candidate to the SFF is calculated. It is considered that a path having a large delay is more likely to cause a delay fault than a path having a small delay. For this reason, in the present invention, the delay of the route having a measured test result of “Fail” is larger than the delay of the route having “Pass”, or the reversal (mismatch) of the magnitude relationship is statistically small. The failure candidate is determined to be a true failure.

  According to the above procedure, even when a slight discrepancy in time occurs as shown in FIG. 4 between the actual measurement and the simulation test result, the present invention statistically evaluates the temporal discrepancy. Therefore, it is possible to correctly point out the location of the delay fault.

<Second Embodiment>
In the first embodiment, the signal propagation delay time of the path from the failure candidate to the SFF is obtained, and the failure location is diagnosed from the magnitude. This is a diagnostic method based on the assumption that a delay fault is more likely to occur in a path with a large delay because the temporal operation margin is smaller.

  However, it is considered that the above estimation is valid only when the signal measurement timings in the SFF are the same, as shown in FIG. If signal measurement is performed at the same timing in all SFFs, the “delay + margin” is always a constant value as shown in FIG.

  However, in an actual circuit, the signal measurement timing of the SFF often varies as shown in FIG. 13B due to the influence of clock skew. As described above, when the signal measurement timing varies, as shown in FIG. 13B, the margin of a path with a large delay may be larger than that of a path with a small delay. For this reason, if the coincidence calculation step S106 and the diagnosis step S107 in FIG. 8 are performed using this delay information, there is a possibility that a portion different from the true failure is output as a diagnosis result.

  Therefore, a method for correcting clock skew is proposed as a second embodiment of the present invention. In this method, the clock skew is corrected when the delay time of the fault propagation path is calculated in step S105 of FIG. That is, when the measurement timing of the SFF at the end of the fault propagation path is earlier than the reference, the difference is added to the delay time of the path. Conversely, if the SFF measurement timing is later than the reference, the difference is subtracted from the path delay information. Then, the calculation result is used for the coincidence calculation in step S106 in FIG.

  According to the above procedure, even when there are variations in the signal measurement timing in the SFF, the correction result of the delay value of each fault propagation path correctly reflects the time margin of each path and the ease of occurrence of the delay fault. It becomes a value, and the true fault position can be correctly determined.

[Significance of this embodiment]
In the first embodiment, diagnosis is performed without considering the variation in the signal measurement timing in the SFF as described above, using only the delay of the path from the failure candidate to the SFF, and considering that a path having a large delay is likely to cause a delay fault. Do. In this case, it is considered that the time margin cannot be correctly evaluated, and a portion different from the true failure may be output as a diagnosis result.

  On the other hand, in this embodiment, when calculating the delay of the fault propagation path from the fault candidate to the SFF, the signal measurement timing variation correction in the SFF is performed. That is, when the measurement timing of the SFF at the end of the failure propagation path is earlier than the reference, the difference is added to the signal propagation delay time of the path. Conversely, if the SFF measurement timing is later than the reference, the difference is subtracted from the signal propagation delay time of the path.

  By this processing, the delay value correction effect becomes a value that accurately reflects the time margin of each path and the likelihood of delay failure, and the above-described problems can be avoided.

<Third Embodiment>
A method using a three-dimensional histogram of the number of fault propagation paths will be described as a third embodiment of the present invention.

[Diagnostic procedure]
With reference to FIG. 14, the procedure of the diagnostic process of this embodiment is demonstrated.
As shown in FIG. 14, the processing procedure of the third embodiment is the same as that of the first embodiment (step S <b> 301 to step S <b> 305 in FIG. 14) from the data input process to the delay value calculation process of the failure propagation path. S101 to step S105).

(1) Step S301
The input device 10 stores circuit connection information 21, circuit delay information 22, test pattern information 23, and test result information 24 in the storage device 20.

(2) Step S302
The circuit simulation unit 31 executes circuit simulation based on the circuit connection information 21 and the test pattern information 23, obtains the operation of each net in the circuit when the test pattern is applied to the circuit, and generates circuit operation information 25. .

(3) Step S303
Next, the circuit retroactive processing unit 32 refers to the circuit connection information 21 and the test result information 24, starts the SFF whose test result is “Fail” (failed), and starts the circuit along the fault propagation path on the input side ( A primary failure candidate is derived by tracing back (upstream) to generate a failure candidate list 26. Here, the point where the traces overlap is set as the primary failure candidate.

(4) Step S304
Next, the failure propagation path extraction unit 33 refers to the failure candidate list 26, extracts a failure propagation path from the primary failure candidate to the SFF located on the candidate output side (downstream), and displays the failure propagation path list 27. Generate.

(5) Step S305
The delay calculation unit 34 refers to the circuit delay information 22, calculates a delay time spent when the digital signal propagates through each failure propagation path included in the failure propagation path list 27, and generates delay information 28 on the failure propagation path. To do.

  The steps so far are the same as steps S101 to S105 in FIG.

(6) Step S306
Next, the degree-of-match calculation unit 35 refers to the test result information 24 and the delay information 28 of the fault propagation path, and creates a three-dimensional histogram of the number of fault propagation paths as shown in FIG.

  First, as shown in FIG. 15 (a), the number of paths with the delay time as a class for the number of paths for which the actual test result is Pass (pass) and the number of paths for which Fail (fail) is detected. Create a histogram for.

  Here, there is no overlap in the Pass and Fail plots in FIG. 15A, that is, the boundary value with the delay of the Pass and Fail paths. If it can be separated into a reference, this corresponds to a state where there is no marginal path in the first embodiment, and it can be said that there is a high possibility that the failure is a true failure.

  Therefore, next, the histogram of FIG. 15A is created for each test pattern, and this is rotated 90 degrees and synthesized to obtain a three-dimensional histogram as shown in FIG. 15B. In FIG. 15B, the vertical axis represents the delay time class, and the color shading represents the number of paths. Also, the area hatched with the upper right diagonal line is an area corresponding to the Fail (fail) path, and the area hatched with the lower right diagonal line is an area corresponding to the Pass (pass) path. The horizontal axis corresponds to the test pattern, but the patterns are arranged in ascending order of the boundary value of delay between the Pass (pass) path and the Fail (fail) path (calculated in step S203 in FIG. 11).

  FIG. 15B is a diagram in which the histogram of FIG. 15A is aligned over the entire test pattern so that the overlap between the Pass path and the Fail path is easily identified. A failure candidate with a small is likely to be a true failure.

  Therefore, in this embodiment, a three-dimensional histogram shown in FIG. 15B is created for each failure candidate.

(7) Step S307
In the three-dimensional histogram of FIG. 15B, the diagnosis unit 36 determines a candidate having a small overlap between the pass (fail) region and the fail (fail) region as a place where the possibility of a true failure is high. The result 51 is output.

  For example, in FIG. 15B, since there is no overlap between the Pass (fail) region and the Fail (fail) region over the entire test pattern, the failure candidate that outputs this three-dimensional histogram may be a true failure. high.

  On the other hand, in FIG. 16, there is an overlap (pass-hatched area in the figure) between the Pass area and the Fail area. The candidate is less likely to be a true failure compared to FIG.

  When determining the size of the overlap between the pass area and the fail area, it may be determined simply from the size of the area of the overlapped area, but the frequency of each area (color density) ) Is considered as the height, and the volume in which the pass (pass) region and the fail (fail) region overlap may be used as a comparison target. Alternatively, a three-dimensional histogram as shown in FIG. 15B is displayed on the screen for each failure candidate, and the failure analysis engineer visually determines the size of the overlap.

[Significance of this embodiment]
The significance of the present embodiment is that various information for determining whether or not a failure candidate is a true failure is visualized so that they can be grasped in a short time.

  From the three-dimensional histogram of FIG. 15, for example, it is possible to determine whether the ratio of the number of paths of the Pass (pass) path and the Fail (fail) path and the boundary values thereof are constant for the entire test pattern. Is possible.

  It is also possible to determine whether a large number of marginal paths are generated in some test patterns or whether a marginal path is generated little by little in the entire test pattern.

<Fourth embodiment>
Below, 4th Embodiment of this invention is described with reference to an accompanying drawing.
With reference to FIG. 17, a failure diagnosis system using the failure diagnosis apparatus of the present invention will be described.

[overall structure]
The fault diagnosis system includes an ATPG (Automatic Test Pattern Generator) 100, an LSI (Large Scale Integration) tester 200, a circuit under test 300, and a fault diagnosis device 400.

  The ATPG 100 generates test pattern information 23 based on the circuit connection information 21 according to the ATPG program.

  The LSI tester 200 applies a test pattern to the circuit under test 300 based on the test pattern information 23, performs a circuit test, and outputs test result information 24.

  The circuit under test 300 is an integrated circuit chip that is diagnosed by this failure diagnosis system.

  The failure diagnosis apparatus 400 estimates a failure location based on the circuit connection information 21, the test pattern information 23, the test result information 24, and the circuit delay information 22 according to the failure diagnosis program, and outputs a failure diagnosis result 51.

  The failure diagnosis apparatus 400 is a failure diagnosis apparatus according to the present invention. That is, the failure diagnosis apparatus 400 includes the input device 10, the storage device 20, the arithmetic processing device 30, the read-only memory 40, and the output device 50 described in the first embodiment of the present invention.

  The failure diagnosis program is the same as the program 41 described in the first embodiment of the present invention.

[Overall operation]
The operation of this failure diagnosis system will be described below.

  First, the ATPG 100 operates normally when a test signal pattern for confirming whether the circuit operates normally and a test signal is applied to the circuit based on the circuit connection information 21 according to the ATPG program. An expected value of the signal pattern output from the (non-failed) circuit is generated, and the test signal pattern and the expected value of the signal pattern are output as the test pattern information 23.

  At this time, when generating the test signal, the ATPG 100 desirably generates the test signal so that it can be confirmed that all elements and wirings constituting the circuit operate normally, but this is not possible. In such a case, the test signal is generated so that the ratio of elements and wiring that cannot be tested is minimized.

  Next, the LSI tester 200 applies a test pattern to the circuit under test 300 based on the test pattern information 23 and compares the output of the circuit under test 300 with an expected value to determine whether the circuit operates normally. To test.

  If the output of the circuit under test 300 is different from the expected value, the LSI tester 200 provides information such as the pattern in which the difference has occurred and the output signal terminal name, or the SFF name in which the difference has been detected, as the test result information 24. Output as.

  Next, the failure diagnosis apparatus 400 estimates the failure location based on the circuit connection information 21, the test pattern information 23, the test result information 24, and the circuit delay information 22 according to the failure diagnosis program, and displays the failure diagnosis result 51. Output.

  The circuit delay information 22 is generated in advance at the circuit design stage.

[result]
If the cause of the failure is clarified from the failure diagnosis result 51, the manufacturing process of the integrated circuit is improved based on the cause, and the occurrence probability of the failure is reduced.

  Moreover, in order to grasp the detailed cause of failure, exposure of a failure location using a FIB (Focused Ion Beam) apparatus or an electron microscope such as a SIM (Scanning Ion Microscope) was used. In some cases, the manufacturing process may be improved after a more detailed analysis such as observing the failure location.

[Significance of this embodiment]
The significance of the fourth embodiment is that the failure location is automatically estimated from the circuit test result, and the manufacturing process can be improved from the diagnosis result.

  In addition, it can be said that the manufacturing cost can be reduced by improving the manufacturing yield and reducing the occurrence rate of defective products.

[Summary]
As described above, Non-Patent Document 1 performs a circuit simulation in a state where a delay fault is inserted into a fault candidate, and compares the actual measurement and the test result of the simulation (Pass) / Fail (fail). This is a method of determining a failure candidate having a high degree of coincidence as a true candidate. At this time, the comparison is made only with the number of coincidence points and non-coincidence points of Pass (Fail) / Fail (failure) of the test result, and the time size of the disagreement is not considered. For this reason, an erroneous location may be determined as a true failure.

  On the other hand, in the present invention, the delay time spent when the digital signal propagates the path from the failure candidate to the SFF is calculated, and the delay of the path whose test result is “Fail” is “Pass”. A fault candidate that is larger than the delay of a certain path is determined to be a true fault.

  Alternatively, even if a reversal occurs in the magnitude relationship, a failure candidate whose statistical reversal is statistically small is determined to be a true failure.

  As described above, in the present invention, the misdiagnosis occurring in the existing technology can be avoided by evaluating the inconsistency temporally.

[Features of the present invention]
(1) In a test of an integrated circuit, the arithmetic processing unit performs a backward tracking that traces the circuit back to the input side (upstream) from the SFF whose test result is “Fail” (failure), thereby identifying a delay fault location. Perform the required failure diagnosis process. At this time, the arithmetic processing unit extracts a failure propagation path from each failure candidate to the SFF existing on the output side (downstream) of the candidate. The arithmetic processing unit calculates a delay time that is spent when the digital signal propagates through the failure propagation path. Further, the arithmetic processing device compares the delay of the path whose test result in the SFF is “Fail” with the delay of the path which is “Pass”, and the delay of the path which is “Fail” is A failure candidate that is larger than the delay of the path that is Pass is determined to be a true failure.

  (2) The arithmetic processing unit groups the failure propagation path from the failure candidate to the SFF on the output side (downstream) of the candidate into a Fail path where the test result is Fail. Divide). Further, the arithmetic processing unit calculates a boundary value of the delay time between the Pass (pass) route and the Fail (fail) route. Further, the arithmetic processing device extracts a Pass route having a delay time larger than the boundary value and a Fail route having a delay time smaller than the boundary value as a marginal route. In addition, the arithmetic processing unit calculates the degree of coincidence from the number of marginal paths or the variation in delay values. The arithmetic processing unit selects a failure candidate having the best degree of coincidence, and outputs this as a true failure from the output device.

  (3) When the number of marginal routes is 0, the arithmetic processing unit sets the matching degree as the best value.

  (4) The arithmetic processing unit calculates the delay variation of the marginal path. Further, the arithmetic processing device compares the delay variation due to process variation, the delay calculation accuracy, or the total value thereof with the delay variation of the marginal path, and calculates the degree of coincidence according to the comparison result. .

  (5) The arithmetic processing unit is sufficient if the delay variation of the marginal path is significantly smaller (than a predetermined range) as compared with delay variation due to process variation, delay calculation accuracy, or the total value thereof. If the degree of coincidence is the best value, conversely, the degree of coincidence is the worst value if it is significantly larger (than the predetermined range), and the degree of coincidence is between the best value and the worst value if the degree is the same (within the predetermined range) And

  (6) When there is a location where the test result is Fail (failed) in the SFF that is not included in the failure propagation path of the failure candidate, the arithmetic processing unit sets the matching degree of the failure candidate as the worst value. .

  (7) The arithmetic processing unit has a test result of “Fail” (fail) in an arbitrary small number of marginal paths and SFFs not included in the output propagation path (downstream) of an arbitrary small number of fault candidates. The degree of coincidence is recalculated after removing the existing part.

  (8) The arithmetic processing unit calculates a result S obtained by accumulating the degree of coincidence for any N test patterns, and points out a candidate having the largest “S ÷ N” as a true failure.

  (9) When the arithmetic processing unit calculates the failure propagation path signal propagation delay time from the failure candidate to the SFF existing on the output side (downstream) of the candidate, the measurement timing of the SFF at the path end is earlier than the reference The difference is added to the delay time of the route, and conversely, if it is late, the difference is subtracted from the delay time of the route, and the delay value corrected by the above procedure is used for the subsequent diagnosis.

  (10) The arithmetic processing unit delays the number of paths of the Pass (pass) path where the actual test result is Pass and the Fail path which is Fail (fail). Generate a histogram of the number of routes with time as the class. In addition, the arithmetic processing unit converts the number of paths of each class in the histogram into color shades (expressed by color shades). Further, the arithmetic processing unit creates the converted histogram for each test pattern, and generates a three-dimensional histogram by combining the results. The arithmetic processing unit generates and outputs the above three-dimensional histogram for each failure candidate.

  (11) The arithmetic processing unit determines that the area where the pass area and the fail area of the three-dimensional histogram overlap or the frequency (color density) of each area is the height, and the pass area and the fail area. (Fail) A volume where regions overlap is obtained, and a fault candidate having a small area or volume is output as a diagnosis result.

  The present invention is different from the conventional one in that it is a diagnostic method focusing on the magnitude of the delay value of the fault propagation path. That is, as shown in FIG. 10, the proposed method calculates the signal propagation delay time for each failure propagation path from the failure candidate to the SFF located downstream from the circuit perspective, and the failure (fail) path is calculated. If the delay amount is larger than the Pass path, the corresponding candidate is diagnosed as a true failure.

<Appendix>
Part or all of the above-described embodiments can be described as in the following supplementary notes. However, actually, it is not limited to the following description examples.

(Appendix 1)
In a test of an integrated circuit, a failure for which a candidate for a delay fault is obtained by performing backward tracing back to the input side starting from a Scan-Flip-Flop (SFF) whose test result is Fail (fail) A diagnostic program,
Means for extracting a failure propagation path from each failure candidate to the SFF existing on the output side of the candidate, and storing the result in a storage device;
Means for calculating a delay time spent when a digital signal propagates through the failure propagation path, and storing the result in a storage device;
The failure propagation paths are grouped (classified and grouped) into a Pass path where the test result is Pass and a Fail path where the test result is Fail. Means for storing in a storage device;
Means for calculating a boundary value of a delay time of the Pass (pass) path and a Fail (fail) path;
Means for extracting a Pass path having a delay time larger than the boundary value and a Fail path having a delay time smaller than the boundary value as a marginal path;
Means for calculating the degree of coincidence from the number of marginal paths or the variation in delay value and storing the result in a storage device;
Means for selecting a fault candidate having the best degree of coincidence, and outputting this as a true fault from the output device;
A failure diagnosis apparatus comprising:

(Appendix 2)
The failure diagnosis device according to appendix 1,
A failure diagnosis apparatus, further comprising means for calculating the boundary value so that a sum of squares of residuals between the delay value of the marginal path and the boundary value is minimized.

(Appendix 3)
The failure diagnosis device according to appendix 1 or 2,
A fault diagnosis apparatus further comprising means for setting the degree of coincidence to the best value when the number of marginal paths is zero.

(Appendix 4)
The failure diagnosis device according to any one of appendices 1 to 3,
Means for calculating the delay variation of the marginal path;
Means for comparing delay variation due to process variation, delay calculation accuracy, or a total value thereof, and delay variation of the marginal path;
Means for calculating the degree of coincidence according to the comparison result;
A failure diagnosis device further comprising:

(Appendix 5)
The failure diagnosis apparatus according to appendix 4, wherein
If the delay variation of the marginal path is significantly smaller (than the predetermined range) compared to the delay variation due to process fluctuation, delay calculation accuracy, or the total value thereof, the coincidence degree is set to the best value and vice versa. If it is larger than (predetermined range), the degree of coincidence is the worst value, and if it is comparable (within the predetermined range), the degree of coincidence is further set to the intermediate value between the best value and the worst value. .

(Appendix 6)
The failure diagnosis apparatus according to any one of appendices 1 to 5,
A fault diagnosis apparatus, further comprising means for setting the degree of coincidence of the fault candidate as the worst value when there is a location where the test result is rejected in the scan circuit not included in the fault propagation path of the fault candidate.

(Appendix 7)
The failure diagnosis device according to any one of appendices 1 to 6,
Means to recalculate the degree of coincidence after removing the points where the test result is not acceptable in the scan circuit that is not included in the failure propagation path on the output side of any small number of marginal paths and any small number of fault candidates A failure diagnosis device further comprising:

(Appendix 8)
The failure diagnosis apparatus according to any one of appendices 1 to 7,
Means for calculating a result S obtained by accumulating the degree of coincidence for any N test patterns;
Means to point out the candidate with the largest S ÷ N as a true failure;
A failure diagnosis device further comprising:

(Appendix 9)
The failure diagnosis apparatus according to any one of appendices 1 to 8,
When calculating the signal propagation delay time of the fault propagation path from the fault candidate to the scan circuit existing on the output side of the candidate, if the measurement timing of the scan circuit at the end of the path is earlier than the reference, the difference is calculated as the delay time of the path Means for adding to
Conversely, if it is slow, means to subtract it from the delay time of the route,
A failure diagnosis program further comprising means for using the delay value corrected by the above procedure for subsequent diagnosis.

(Appendix 10)
The failure diagnosis device according to any one of appendices 1 to 9,
A means for creating a histogram of the number of paths with the delay time as a class for the number of paths for which the actual test result has passed and the number of paths for which the test has failed,
Means for converting the number of paths of each class of the histogram into shades of color;
Means for generating a transformed histogram for each test pattern and generating a three-dimensional histogram by combining the results;
And a means for generating and outputting the three-dimensional histogram for each fault candidate.

(Appendix 11)
The failure diagnosis device according to appendix 10, wherein
Means for determining the area where the pass area and the fail area of the three-dimensional histogram overlap, or the frequency (color shading) of each area as high, and determining the volume where the pass area and the fail area overlap;
A failure diagnosis apparatus further comprising means for outputting a failure candidate having a small area or volume where the overlap occurs as a diagnosis result.

  As mentioned above, although embodiment of this invention was explained in full detail, actually, it is not restricted to said embodiment, Even if there is a change of the range which does not deviate from the summary of this invention, it is included in this invention.

DESCRIPTION OF SYMBOLS 10 ... Input device 20 ... Storage device 21 ... Circuit connection information 22 ... Circuit delay information 23 ... Test pattern information 24 ... Test result information 25 ... Circuit operation information 26 ... Fault candidate list 27 ... Fault propagation path list 28 ... Fault propagation path list Delay information 29 ... Matching degree information 30 ... Arithmetic processing unit 31 ... Circuit simulation part 32 ... Circuit retrogression processing part 33 ... Fault propagation path extraction part 34 ... Delay calculation part 35 ... Matching degree calculation part 36 ... Diagnosis part 40 ... Read-only memory 41 ... Program (Failure diagnosis program)
50 ... Output device 51 ... Failure diagnosis result 100 ... ATPG (Automatic Test Pattern Generator)
DESCRIPTION OF SYMBOLS 200 ... LSI (Large Scale Integration) tester 300 ... Circuit under test 400 ... Failure diagnosis device

Claims (11)

In the integrated circuit test, starting from a scan circuit that has failed the test result, the circuit traces back to the input side, and a means for obtaining a candidate for a delay fault location;
Means for extracting a fault propagation path from a candidate for a delayed fault location to a scan circuit existing on the output side of the fault candidate;
Means for calculating a delay time spent when a digital signal propagates through the failure propagation path;
Means for grouping the fault propagation paths into a pass path where the test result passes and a fail path where the test result fails;
Means for calculating a boundary value of a delay time of the pass path and the fail path;
Means for extracting a passing path having a delay time larger than the boundary value and a failing path having a delay time smaller than the boundary value as a marginal path;
Means for calculating the degree of coincidence from the magnitude of either the number of paths of the marginal path or the variation of the delay value;
A failure diagnosis apparatus comprising: means for selecting a failure candidate having the best degree of coincidence, and outputting the selected failure candidate as a true failure. The failure diagnosis device according to claim 1,
The fault diagnosis apparatus further comprising means for calculating a boundary value that minimizes a sum of squares of residuals between the delay value of the marginal path and the boundary value when calculating the boundary value. The failure diagnosis device according to claim 1 or 2,
When the number of marginal routes is 0, means for making the degree of coincidence the best value;
If the number of marginal paths is not 0, means for calculating the delay variation of the marginal paths;
Means for comparing delay variation due to process variation, delay calculation accuracy, and the total value thereof, and delay variation of the marginal path;
If the delay variation of the marginal path is smaller than a predetermined range, means for making the matching degree the best value;
If the delay variation of the marginal path is larger than a predetermined range, means for making the coincidence the worst value,
If the delay variation of the marginal path is within a predetermined range, the fault diagnosis apparatus further comprises means for setting the degree of coincidence between the best value and the worst value. The fault diagnosis apparatus according to any one of claims 1 to 3,
A fault diagnosis apparatus further comprising means for setting the degree of coincidence of a fault candidate as a worst value when there is a location where a test result is rejected in a scan circuit not included in the fault propagation path of the fault candidate. The fault diagnosis apparatus according to any one of claims 1 to 4,
There is a means to eliminate the test results that are not included in the scan circuit that is not included in the failure propagation path on the output side of any small number of marginal paths and any small number of fault candidates, and to recalculate the degree of coincidence. A failure diagnosis device further provided. The fault diagnosis apparatus according to any one of claims 1 to 5,
Means for calculating a result S obtained by accumulating the degree of coincidence for any N test patterns;
And a means for pointing out a candidate having the largest S ÷ N as a true failure. The fault diagnosis apparatus according to any one of claims 1 to 8,
Means for calculating the signal propagation delay time of the fault propagation path from the fault candidate to the scan circuit existing on the output side of the fault candidate;
If the measurement timing of the scan circuit at the end of the path is earlier than the reference, a means for adding the difference between the measurement timing and the reference to the delay time of the path and correcting the delay value of the marginal path;
When the measurement timing of the scan circuit at the end of the path is later than the reference, a means for subtracting the difference between the measurement timing and the reference from the delay time of the path and correcting the delay value of the marginal path;
And a means for using the corrected delay value for subsequent failure diagnosis. The fault diagnosis apparatus according to any one of claims 1 to 7,
A means for creating a histogram of the number of paths with the delay time as a class for the number of paths for which the actual test result has passed and the number of paths for which the test has failed,
Means for converting the number of paths of each class of the histogram into shades of color;
Means for creating the converted histogram for each test pattern;
Means for combining the histograms created for each of the test patterns to generate a three-dimensional histogram;
And a means for generating and outputting the three-dimensional histogram for each fault candidate. The failure diagnosis apparatus according to claim 8,
Means for determining the volume where the pass area and the fail area of the three-dimensional histogram overlap each other and the density of the color of each area as a height, and determining the volume where the pass area and the fail area overlap;
A failure diagnosis apparatus further comprising means for outputting a failure candidate having a small area or volume in which an overlap between the pass region and the fail region is small as a diagnosis result. A failure diagnosis method performed by a computer,
In the integrated circuit test, starting from the scan circuit that failed the test result, tracing back to the input side of the circuit, obtaining a candidate for a delay fault location,
Extracting a fault propagation path from a candidate for a delayed fault location to a scan circuit existing on the output side of the fault candidate;
Calculating a delay time spent when a digital signal propagates through the failure propagation path;
Grouping the failure propagation path into a pass path where the test result passes and a fail path where the test result fails;
Calculating a boundary value of a delay time of the pass path and the fail path;
Extracting a passing path having a delay time larger than the boundary value and a failing path having a delay time smaller than the boundary value as a marginal path;
Calculating the degree of coincidence from the magnitude of either the number of routes of the marginal route or the variation of the delay value;
Selecting a fault candidate having the best degree of coincidence, and outputting the selected fault candidate as a true fault. In a test of an integrated circuit, starting from a scan circuit that has failed the test result, tracing back to the input side of the circuit, obtaining a delay fault candidate,
Extracting a fault propagation path from a candidate for a delayed fault location to a scan circuit existing on the output side of the fault candidate;
Calculating a delay time spent when a digital signal propagates through the failure propagation path;
Grouping the failure propagation path into a pass path where the test result passes and a fail path where the test result fails;
Calculating a boundary value of a delay time of the pass path and the fail path;
Extracting a pass route having a delay time larger than the boundary value and a fail route having a delay time smaller than the boundary value as a marginal route;
Calculating the degree of coincidence from the magnitude of either the number of paths of the marginal path or the variation of the delay value;
A fault diagnosis program for causing a computer to execute a step of selecting a fault candidate having the best degree of coincidence and outputting the selected fault candidate as a true fault.

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