JP2012069718A - Semiconductor device and manufacturing method therefore - Google Patents

Abstract

A semiconductor device capable of easily selecting a material for a sealing film is provided.
A semiconductor device wafer having a plurality of connection terminals formed on a semiconductor substrate, and a first insulation provided with an opening that covers the surface of the semiconductor device wafer and exposes the connection terminals. A plurality of rewirings 30 formed on the first insulating film 14 and having one end face connected to the connection terminal 12, and a plurality of columnar electrodes 21 formed on the other end face of the rewiring 30; A second insulating film 15 covering a side surface of the rewiring 30; and a sealing film 22 that seals the rewiring 30 and the second insulating film 15 and exposes the surface of the columnar electrode 21. This is a semiconductor device 1B.
[Selection] Figure 18

Description

  The present invention relates to a semiconductor device such as a WLP (Wafer Level Package) and a method for manufacturing the semiconductor device.

  Some semiconductor devices have a structure as shown in FIG. An insulating film 114 is provided on the surface of the semiconductor device wafer 110 on which the connection pads 112 are provided, and an opening 114 a is provided in the insulating film 114 at a portion corresponding to the central portion of the connection pads 112. A rewiring 130 is formed on the surface of the insulating film 114 and in the opening 114a. The rewiring 130 includes a main layer 119 and an electroplating seed layer 116, and the main layer 119 is connected to the connection pad 112 through the electroplating seed layer 116. A columnar electrode 121 is provided at the end of the rewiring 130, and the rewiring 130 and the insulating film 113 are sealed with the sealing film 122. The columnar electrode 121 is exposed from the sealing film 122, and a solder terminal 123 is provided on the surface of the columnar electrode 121. The semiconductor device 101 is connected to a circuit board (not shown) via the solder terminal 123 (see, for example, Patent Document 1).

JP 2007-287048 A

  By the way, the sealing film is required to play a role such as protection from physical external force, shielding humidity, shielding external light, etc., having a thermal expansion coefficient close to that of a semiconductor substrate, heat resistance, chemical resistance, and the like. Furthermore, since the sealing film is in contact with the rewiring, it is necessary to select a material that does not cause a metal migration phenomenon forming the rewiring. For this reason, it is very difficult to select and evaluate the material of the sealing film.

  The subject of this invention is providing the semiconductor device which can select the material of a sealing film easily.

  In order to solve the above-described problems, according to the first aspect of the present invention, a semiconductor device wafer having a plurality of connection terminals formed on the surface of a semiconductor substrate, the surface of the semiconductor device wafer being covered and the connection terminals being A first insulating film provided with an opening to be exposed; a plurality of rewirings formed on a surface of the first insulating film and having one end connected to the connection terminal; and formed on a surface of the other end of the rewiring. A plurality of columnar electrodes; a second insulating film that covers at least a side surface of the rewiring; and a sealing film that seals the rewiring and the second insulating film and exposes the surface of the columnar electrode. A semiconductor device is provided.

  According to another aspect of the present invention, a semiconductor device wafer having a plurality of connection terminals formed on a surface of a semiconductor substrate, and an opening that covers the surface of the semiconductor device wafer and exposes the connection terminals is provided. An insulating film; a plurality of rewirings formed on a surface of the first insulating film and having one end connected to the connection terminal; a plurality of columnar electrodes formed on a surface of the other end of the rewiring; and the first There is provided a semiconductor device comprising: a second insulating film that covers the insulating film and the rewiring; and a sealing film that seals the second insulating film and exposes a surface of the columnar electrode. The

  According to another aspect of the present invention, a first insulating film that covers the surface of the semiconductor device wafer having a plurality of connection terminals formed on the surface of the semiconductor substrate and has an opening that exposes the connection terminals is provided, A first electroplating seed layer was provided on the exposed surface of the connection terminal and the first insulating film, and then a rewiring resist was formed on the surface of the seed layer, and rewiring was formed by electrolytic plating. Later, the rewiring resist and the first electroplating seed layer under the rewiring resist are removed, and then an opening that covers the surface of the first insulating film and the rewiring and exposes one end of the rewiring is formed. A second insulating film is formed, a second electroplating seed layer is provided on the exposed surface of the rewiring and the second insulating film, and a columnar electrode is formed on the second insulating film. Forming a resist for After the columnar electrode is formed by deplating, the columnar electrode resist and the second electrolytic plating seed layer thereunder are removed, and then the surface of the columnar electrode is formed on the second insulating film. A method for manufacturing a semiconductor device is provided, in which a sealing film that is flush with the surface is formed.

  According to another aspect of the present invention, a first insulating film that covers the surface of the semiconductor device wafer having a plurality of connection terminals formed on the surface of the semiconductor substrate and has an opening that exposes the connection terminals is provided, A second insulating film is provided at a position on the surface of the first insulating film where no rewiring is formed, and then an electroless plating catalyst layer is formed on the exposed connection terminals and the surface of the first insulating film. Then, a rewiring is formed on the electroless plating catalyst layer by an electroless plating method, and then an electroplating seed layer covering the rewiring and the surface of the second insulating film is formed, Next, a columnar electrode resist is formed on the electrolytic plating seed layer, and after the columnar electrode is formed by an electrolytic plating method, the columnar electrode resist and the underlying electrolytic plating seed layer are removed. The rewiring On top of the fine the second insulating film, a method of manufacturing a semiconductor device characterized by forming a sealing film having a surface flush with the surface of the columnar electrode.

Preferably, a rewiring is further provided between the second insulating film and the sealing film.
Preferably, the second insulating film is a material that does not cause a migration phenomenon of the material forming the rewiring.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can select the material of a sealing film easily can be provided.

1 is a plan view showing a semiconductor device 1A according to a first embodiment of the present invention. It is II-II arrow sectional drawing of FIG. It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. It is sectional drawing which shows the semiconductor device 1B which concerns on the modification of this embodiment. It is sectional drawing which shows 1C of semiconductor devices which concern on the 2nd Embodiment of this invention. It is explanatory drawing of the manufacturing method of 1 C of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 C of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 C of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 C of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 C of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 C of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 C of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 C of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 C of semiconductor devices. It is explanatory drawing of the manufacturing method of 1 C of semiconductor devices. It is sectional drawing of WLP of the Example after a HAST test. It is sectional drawing of WLP of the comparative example after a HAST test. It is sectional drawing which shows the conventional semiconductor device 101. FIG.

[First Embodiment]
FIG. 1 is a plan view showing a semiconductor device 1A according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II in FIG. As shown in FIGS. 1 and 2, the semiconductor device 1 </ b> A is formed by forming rewirings 30, columnar electrodes 21, solder terminals 23, and the like on the surface of a semiconductor device wafer 10.
As shown in FIG. 1, a semiconductor device wafer 10 includes a semiconductor substrate 11 made of silicon or the like, a plurality of connection pads 12 made of a conductive material such as metal, and a passivation film 13 made of an insulating material such as silicon oxide. , Etc.

  On the surface of the semiconductor substrate 11, LSIs and wirings are formed. The connection pad 12 is connected to the wiring on the silicon substrate 11. The passivation film 13 is formed on the surface of the semiconductor substrate 11 and covers LSI, wiring, and the like. The passivation film 13 is provided with an opening 13a for exposing the connection pad 12. As shown in FIGS. 1 and 2, the opening 13 a is smaller than the connection pad 12.

  A first insulating film 14 made of epoxy resin, polyimide resin, or the like is formed on the surface of the passivation film 13. For the first insulating film 14, a high-functional plastic material such as polyimide (PI) or polybenzoxazole (PBO), a plastic material such as epoxy, phenol, or silicon, or a composite material thereof may be used. it can.

  The first insulating film 14 is provided with an opening 14 a that exposes the connection pad 12. The opening 14a can be formed by a laser, for example. As shown in FIGS. 1 and 2, the opening 14a of the first insulating film 14 is smaller than the opening 13a of the passivation film 13, and the connection pad 12 and the first insulating film 14 are in close contact with each other at the outer periphery of the opening 14a. .

The rewiring 30 includes an electroplating seed layer 16A, a main layer 19, and the like.
An electroplating seed layer 16A made of copper or the like is formed on a part of the surface of the first insulating film 14 and on the connection pad 12 exposed from the opening 14a. The electroplating seed layer 16A preferably has a thickness of 200 nm to 2000 nm. One end of the electroplating seed layer 16A is connected to the connection pad 12 through the openings 13a and 14a.
A main layer 19 made of a conductive material such as copper is formed on the surface of the electroplating seed layer 16A. The main layer 19 preferably has a thickness of 1 μm to 10 μm. A columnar electrode 21 made of a conductive material such as copper is formed on the upper surface of the end of the main layer 19 opposite to the connection pad 12.

  The laminate of the electroplating seed layer 16A and the main layer 19 connects the connection pads 12 and the columnar electrodes 21 corresponding to each other, and the other electroplating seed layer 16A and the main layer 19 respectively. They are arranged so as to be electrically insulated from the laminate.

  A second insulating film 15 is formed on the surfaces of the rewiring 30 and the first insulating film 14. The material for forming the second insulating film is required to be a material that does not cause a metal migration phenomenon that forms the main layer 19 in the rewiring 30. Such materials include high-functional plastic materials such as polyimide (PI) and polybenzoxazole (PBO), plastic materials such as epoxy, phenol, and silicon, or composite materials thereof.

  The second insulating film 15 is provided with an opening 15 a that exposes a connection portion between the rewiring 19 and the columnar electrode 21. The opening 15a can be formed by a laser, for example. An electroplating seed layer 18 is formed in the inside and the outer periphery of the opening 15a. A columnar electrode 21 is formed on the seed layer 18 for electrolytic plating.

  The sealing film 22 is provided on the surface of the second insulating film 15 so that the upper surface of the columnar electrode 21 is exposed when the surface thereof is substantially flush with the surface of the columnar electrode 21. The sealing film 22 is made of a composite (composite material) of an epoxy resin and a silica filler. The sealing film 22 protects the electroplating seed layer 18 and the columnar electrode 21 from the side surfaces, and protects the second insulating film 15 from the upper part thereof. On the surface of each columnar electrode 21, a substantially spherical solder terminal 23 for connection to the connection pad 12 of the semiconductor substrate 11 is provided. The solder terminals 23 are electrically connected to each other by contacting the circular upper surface of the columnar electrode 21.

Next, a method for manufacturing the semiconductor device 1A will be described with reference to FIGS.
First, as shown in FIG. 3, the first insulating film 14 is formed on the surface of the semiconductor device wafer 10.
Next, as shown in FIG. 4, an electroplating seed layer 16A that covers the entire surface of the first insulating film 14 and the entire surface of the connection pad 12 is formed by vapor deposition such as sputtering.

Next, as shown in FIG. 5, a rewiring resist 17 is formed at a position where the main layer 19 is not formed.
Next, as shown in FIG. 6, a main layer 19 is formed in a portion where the rewiring resist 17 is not formed by electrolytic plating using the seed layer 16A for electrolytic plating as a cathode.
Thereafter, as shown in FIG. 7, the rewiring resist 17 is removed.

Next, as shown in FIG. 8, the electroplating seed layer 16 </ b> A where the main layer 19 is not formed is removed by etching. At this time, the surface of the main layer 19 is also etched, but the main layer 19 is sufficiently thick as compared with the electroplating seed layer 16A, and thus has no effect.
Next, as shown in FIG. 9, the second insulating film 15 is formed on the main layer 19 and the first insulating film 14.
Next, as shown in FIG. 10, an electroplating seed layer 18 is formed to cover the entire surface of the second insulating film 15 and the entire surface of the main layer 19 exposed from the opening 15a.

Next, as shown in FIG. 11, an opening 20 a is formed at the position of the columnar electrode 21 by pasting and patterning a dry film to be the columnar electrode resist 20 on the upper surface of the electroplating seed layer 18.
Next, as shown in FIG. 12, columnar electrodes 21 are formed in the openings 22a by electrolytic plating using the electroplating seed layer 18 as a cathode.
Next, as shown in FIG. 13, the columnar electrode resist 20 is removed.
Thereafter, as shown in FIG. 14, the electroplating seed layer 18 in the portion where the columnar electrode 21 is not formed is removed by etching. At this time, a part of the columnar electrode 21 is also etched, but the columnar electrode 21 is sufficiently thick as compared with the seed layer 18 for electroplating, and thus has no influence.

Next, as shown in FIG. 15, a resin to be the sealing film 22 is applied by a printing method to form the sealing film 22.
Next, as shown in FIG. 16, by grinding the surface of the sealing film 22, the upper surface of the columnar electrode 21 is exposed so that the surface of the sealing film 22 is substantially flush with the surface of the columnar electrode 21. .
Thereafter, a substantially spherical solder terminal 23 is formed on the upper surface of the columnar electrode 21 and diced. Thus, the semiconductor device 1A is formed.

  Thus, according to the present invention, since the rewiring 30 is covered with the second insulating film 15, the rewiring 30 and the sealing film 22 do not contact each other. Therefore, the migration phenomenon of the metal forming the rewiring 30 does not occur, and a short circuit of the rewiring 30 can be prevented. For this reason, the wiring density of the rewiring 30 can be increased. Further, since the rewiring 30 and the sealing resin 22 do not come into contact with each other, any material can be selected as the material of the sealing film 22.

  In addition, since the rewiring 30 is formed and then covered with the second insulating film 15 and then the columnar electrode resist 20 is formed, the generation of bubbles due to the unevenness of the rewiring 30 can be prevented during dry film lamination. . Moreover, the influence with respect to the rewiring 30 of the dust originating in a dry film can be prevented.

<Modification>
FIG. 17 is a cross-sectional view showing a semiconductor device 1B according to a modification of the present embodiment. In this modification, the opening 15 a of the second insulating film 15 is formed smaller than the columnar electrode 21. Further, the electroplating seed layer 18 is provided not only in the inside and the outer periphery of the opening 15a of the second insulating film 15 but also in other portions, and a main layer 24 is further provided on the electroplating seed layer 18. It has been. The columnar electrode 21 is formed on the rewiring 40.

  In this modification, since the opening 15a of the second insulating film 15 is formed smaller than the columnar electrode 21, the rewiring 40 connected to the columnar electrode 21 and the other rewiring 40 are more adjacent to each other. And more rewirings 40 can be arranged. Moreover, in addition to the rewiring 40 covered with the second insulating film 15, the rewiring 40 can be provided also on the second insulating film, and the wiring density can be further increased.

[Second Embodiment]
FIG. 18 is a cross-sectional view showing a semiconductor device 1C according to the second embodiment of the present invention. In addition, about the structure similar to 1st Embodiment, the same code | symbol is attached | subjected and description is omitted.
The semiconductor device 1C according to the present embodiment is different from the semiconductor device 1A according to the first embodiment as follows.

  That is, in the semiconductor device 1 </ b> C, the electroless plating catalyst layer 16 </ b> B is formed below the main layer 19 instead of the electrolytic plating seed layer 16 </ b> A. The electroless plating seed layer 16B is formed, for example, by applying and drying a liquid material (catalyst solution) such as an aqueous solution containing Pd by an inkjet method or the like. Alternatively, after the first insulating film 14 and the second insulating film 15 have different surface wettability and adsorptivity so that the affinity of the catalyst solution with respect to the first insulating film 14 is higher, The semiconductor device wafer 10 on which the first insulating film 14 and the second insulating film 15 are formed may be formed by immersing in a catalyst solution and drying.

The second insulating film 15 is formed only on the first insulating film 14 and is not formed on the main layer 19. In the present embodiment, the second insulating film 15 needs to be patterned. For this reason, the second insulating film 15 is formed using a photosensitive resin. The thickness of the second insulating film 15 is preferably about 5 to 15 μm.
The electroplating seed layer 18 is provided only between the main layer 19 and the columnar electrode 21, and the sealing film 22 is formed on the second insulating film 15 and the main layer 19.

Next, a method for manufacturing the semiconductor device 1C will be described with reference to FIGS.
First, as in the first embodiment, as shown in FIG. 3, a first insulating film 14 is formed on the surface of the semiconductor device wafer 10.

Next, as shown in FIG. 19, a photosensitive resin for forming the second insulating film 15 is applied on the first insulating film 14 and patterned to form the second insulating film 15. At this time, the second insulating film 15 is left only at a position where the rewiring 30 is not formed.
Next, as shown in FIG. 20, an electroless plating seed layer 16 </ b> B is formed in a portion where the second insulating film 15 is not formed.
Next, as shown in FIG. 21, the main layer 19 is formed on the electroless plating seed layer 16B by electroless plating.
Next, as shown in FIG. 22, an electroplating seed layer 18 is formed on the entire surface of the second insulating film 15 and the main layer 19.

Next, as shown in FIG. 23, an opening 20a is formed at the position of the columnar electrode 21 by attaching a dry film to be the columnar electrode resist 20 on the upper surface of the electroplating seed layer 18 and patterning.
Next, as shown in FIG. 24, columnar electrodes 21 are formed in the openings 22a by electrolytic plating using the electroplating seed layer 18 as a cathode.
Next, as shown in FIG. 25, the columnar electrode resist 20 is removed.
Thereafter, as shown in FIG. 26, the electroplating seed layer 18 in the portion where the columnar electrode 21 is not formed is removed by etching.

Next, as shown in FIG. 27, a resin to be the sealing film 22 is applied by a printing method to form the sealing film 22.
Next, as shown in FIG. 28, by grinding the surface of the sealing film 22, the upper surface of the columnar electrode 21 is exposed so that the surface of the sealing film 22 is substantially flush with the surface of the columnar electrode 21. .
Thereafter, a substantially spherical solder terminal 23 is formed on the upper surface of the columnar electrode 21 and diced. Thus, the semiconductor device 1C is formed.

  Thus, according to the present embodiment, the adjacent rewiring 19 is partitioned by the second insulating film 15 made of a material that does not cause the metal migration phenomenon forming the rewiring 30, so that the adjacent rewiring 19 Short circuit between each other can be prevented. For this reason, the wiring density of the rewiring 19 can be increased. In addition, the semiconductor device can be formed with a smaller number of processes than in the first embodiment.

In the present embodiment, the rewiring 30 includes the seed layer 16A for electroplating or the catalyst layer 16B for electroless plating and the main layer 19. However, the rewiring 30 may include at least the main layer 19. It ’s fine.
Moreover, according to the modification of this embodiment, although the rewiring 40 was provided with the seed layer 18 for electroplating and the main layer 24, it should just be provided with the main layer 24 at least.

Hereinafter, reliability tests performed on the examples of the present invention will be described together with comparative examples.
<Example>
A first insulating film (first insulating film) is formed on the upper surface of the Si substrate of the semiconductor device wafer, and two rewirings are formed adjacent to each other above the first insulating film. The rewiring was covered with a second insulating film (second insulating film), and the upper part of the second insulating film was sealed with a sealing resin to form a WLP. PI was used for the first and second insulating films. Copper (Cu) was used for rewiring. As the sealing resin, a sealing material in which a silica filler was dispersed in an epoxy resin was used.

<Comparative example>
An insulating film is formed on the upper surface of the Si substrate of the semiconductor device wafer, two rewirings are formed adjacent to each other on the insulating film, and the two rewirings are sealed with a sealing resin to form a WLP. did. PI was used for the insulating film. Copper (Cu) was used for rewiring. As the sealing resin, a sealing material in which a silica filler was dispersed in an epoxy resin was used.

<HAST test>
HAST (Highly Accelerated Temperature and Humidity Stress Test) was performed on the WLPs of Examples and Comparative Examples as a reliability test in an accelerated environment with a moisture-resistant bias. A bias voltage of 3.5 V was applied between the two rewirings for 500 hours in an environment where the temperature was 130 ° C. and the humidity was 85%.

<Result>
FIG. 29 is a sectional view of the example after the HAST test, and FIG. 30 is a sectional view of the comparative example. 29, the left side rewiring is on the high voltage side (High), and the right side rewiring is on the low voltage side (Low). In FIG. 30, the left side rewiring is on the low voltage side (Low), and the right side rewiring is on the right side. Is the high voltage side (High).

  As shown in FIG. 29, in the example, since the wiring is covered with the first and second insulating films, the shape of the rewiring is not affected even after the HAST test. On the other hand, as shown in FIG. 30, in the comparative example, since the rewiring was in contact with the sealing resin, elution (migration) of Cu occurred in the rewiring on the high voltage side. In addition, the insulation film between the two rewirings was broken due to the short circuit.

1A, 1B Semiconductor device 10 Semiconductor device wafer 11 Semiconductor substrate 12 Connection pad 13 Passivation films 13a, 14a, 15a, 20a Opening 14 First insulating film 15 Second insulating film 16A Electroplating seed layer 16B Electroless plating catalyst layer 19 Main layer 20 Columnar electrode resist 21 Columnar electrode 22 Sealing film 23 Solder terminal 30 Rewiring

Claims (10)

A semiconductor device wafer having a plurality of connection terminals formed on a semiconductor substrate;
A first insulating film that covers the surface of the semiconductor device wafer and is provided with an opening that exposes the connection terminal;
A plurality of rewirings formed on the first insulating film and having one end surface connected to the plurality of connection terminals,
A plurality of columnar electrodes formed on the other end surface of the rewiring;
A second insulating film covering a side surface of the rewiring;
A sealing film that seals the rewiring and the second insulating film and exposes the surface of the columnar electrode;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein a seed layer for electrolytic plating is formed between the plurality of columnar electrodes and the rewiring layer.   The semiconductor device according to claim 2, wherein the second insulating film further covers an upper surface of the rewiring and an upper surface of the first insulating film.   The semiconductor device according to claim 2, wherein the second insulating film is not provided on an upper surface of the rewiring.   The semiconductor device according to claim 1, further comprising a rewiring between the second insulating film and the sealing film.   6. The semiconductor device according to claim 1, wherein the second insulating film is a material that does not cause a migration phenomenon of the material forming the rewiring. Forming a first insulating film that covers the surface of a semiconductor device wafer on which a plurality of connection terminals are formed on a semiconductor substrate and has an opening that exposes the connection terminals;
Forming a plurality of rewirings each having one end face connected to the plurality of connection terminals on the first insulating film;
Forming a second insulating film on top of the first insulating film so as to cover at least a side surface of the rewiring having an opening exposing the other end surface of the rewiring;
Forming a columnar electrode on the opening of the second insulating film on the other end surface of the rewiring;
Forming a sealing film whose surface is flush with the surface of the columnar electrode on the rewiring and the second insulating film;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 7, wherein the second insulating film further covers an upper surface of the rewiring and an upper surface of the first insulating film.   The method of manufacturing a semiconductor device according to claim 7, wherein a rewiring is further formed between the second insulating film and the sealing film.   The method for manufacturing a semiconductor device according to claim 7, wherein the second insulating film is a material that does not cause a migration phenomenon of the material forming the rewiring.