JP2012068765A - Memory controller, flash memory system with memory controller, and control method of flash memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the efficiency reduction of access processing based on inter-block transfer by reducing the frequency of inter-block transfer.SOLUTION: Data given from a host system is written in a physical page within a physical block being managed as a write destination block. The number of physical pages storing invalid data therein within the physical block is counted and a physical block having the greatest number of pages is specified. Valid data being stored in that physical block is transferred to a physical page within a physical block being managed as a transfer destination block. Different physical blocks are selected for the physical block being managed as the write destination block and the physical block being managed as the transfer destination block.

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method, and more particularly, when converting a logical address given from a host system into a physical address in the flash memory, an address in page units. The present invention relates to a memory controller that controls access to a flash memory by performing conversion. In the management of the data storage destination in this memory controller or the like, the physical block is allocated by allocating the data storage destination given from the host system and the data storage destination copied (transferred) in the flash memory to different physical blocks. Improves processing efficiency when creating empty blocks.

  In recent years, the market for storage devices using nonvolatile semiconductor memories such as small memory cards and SSDs (Solid State Drives) is expanding. These products are equipped with a nonvolatile memory and a memory controller for controlling the nonvolatile memory. By the control by the memory controller, these storage devices can be used without requiring special software or hardware circuits in a system in which a conventional HDD is used. For example, in the access from the host system to the HDD, the address of the write destination is specified in units of sectors (in units of 512 bytes), and the data corresponding to each address is written to the sector corresponding to each address. Therefore, a storage device using a non-volatile semiconductor memory needs to cope with such data writing in sectors.

  In such a storage device, a NAND flash memory (hereinafter referred to as a flash memory) is usually used as a nonvolatile memory. However, this flash memory has various limitations such as a limitation in erasure processing and writing processing, and a limitation on the number of rewrites.

  For example, a flash memory cannot be rewritten by overwriting, so the data write destination must be an erased area. That is, when the data write destination area is not in the erased state, the data write destination area must be in the erased state before data writing is performed. This data erasure processing unit is a physical block, and this physical block is composed of a plurality of physical pages. This physical page is a processing unit for data writing. For example, each physical block is composed of 64, 128, or 256 physical pages. Each physical page includes a user area of 4 sectors (2048 bytes), 8 sectors (4096 bytes), or 16 sectors (8192 bytes).

  As described above, since data cannot be overwritten in the flash memory, when data is rewritten, normally, new data is written on a physical page different from old data. Further, when there is no empty page in the physical block in which the old data is written, the new data is written in an empty page in another physical block. When such data rewriting is performed, a plurality of data having the same address given from the host system exist until the old data is erased. Therefore, when there are a plurality of data with the same address, only the latest data is treated as valid data, and the other data is treated as invalid data.

  When this invalid data increases, the free capacity of the flash memory decreases. However, if there is a physical page in which valid data is stored, erase processing cannot be performed on the physical block to which the physical page belongs, so the valid data in the physical block is transferred to another physical block. Then, after all the data in the physical block becomes invalid data by this data transfer, the erasure process is performed on the physical block. With the increase in capacity of NAND flash memory, the effect of this inter-block transfer on the performance of the storage device cannot be ignored. In other words, since the block size of the NAND flash memory has increased and the writing time has become longer, this inter-block transfer time has become longer, which has a greater effect on the performance of the storage device.

Japanese Patent Laid-Open No. 08-115252 JP 2005-222550 A

  In order to suppress the influence of inter-block transfer, in Reference 1, all data is given read / write frequency information, further memory use information, memory specific information, etc. are given, and based on these information, the host The physical address to which data given by the system is written is specified. In such a case, information to be managed increases, and the management becomes complicated.

  In Reference 2, when inter-block transfer is performed, the time effect when inter-block transfer is executed in each physical block is calculated, and a physical block with less influence is selected and inter-block transfer is executed. ing. In this way, the time required for inter-block transfer can be shortened, but the burden for calculating temporal effects and the like increases.

  Accordingly, the present invention provides a memory controller, a flash memory system including the memory controller, and a flash memory control method capable of reducing the frequency of inter-block transfer and suppressing the efficiency of access processing based on inter-block transfer. The purpose is to do.

A memory controller according to the first aspect of the present invention comprises:
A logical page including one or a plurality of logical sectors to which a logical address given by the host system is assigned is defined, and a physical block including a plurality of physical pages which are processing units of write processing is a processing unit of erasing processing. A memory controller that controls access to a flash memory,
An empty block search means for searching for an erased physical block in the flash memory,
Write destination management means for managing the physical block in the erased state detected by the empty block search means as a write destination block;
The physical of the storage destination in the physical block is stored so that the data is stored in the physical page in the physical block managed as the write destination block by the write destination management unit in the order from the first page to the last page. Write destination instruction means for indicating a page;
Writing means for writing data given from the host system to the physical page instructed by the writing destination instruction means;
Transfer destination management means for managing a physical block in the erased state detected by the empty block search means as a transfer destination block;
A transfer source specifying means for counting the number of physical pages in which invalid data in the physical block is stored, and specifying a physical block having the largest number of pages;
The physical storage in the physical block is stored in the physical page in the physical block managed as the transfer destination block by the transfer destination management unit so that data is stored in the order from the first page to the last page. A transfer destination instruction means for indicating a page;
Transfer means for transferring valid data stored in the physical block specified by the transfer source specifying means to the physical page specified by the transfer destination indicating means,
The write destination management means newly manages another physical block as the write destination block when data is stored in all physical pages in the physical block managed as the write destination block,
The transfer destination management means newly manages another physical block as the transfer destination block when data is stored in all physical pages in the physical block managed as the transfer destination block,
The physical block managed as the write destination block by the write destination management unit and the physical block managed as the transfer destination block by the transfer destination management unit are different physical blocks.

A memory controller according to the first aspect of the present invention comprises:
A free block management means for managing the number of erased physical blocks in the flash memory;
The transfer of valid data by the transfer means is preferably executed when the number of blocks becomes a predetermined value or less.

A flash memory system according to the second aspect of the present invention comprises:
A memory controller according to the first aspect of the present invention;
A flash memory controlled by the memory controller is provided.

A control method of a flash memory according to the third aspect of the present invention includes:
A logical page including one or a plurality of logical sectors to which a logical address given by the host system is assigned is defined, and a physical block including a plurality of physical pages which are processing units of write processing is a processing unit of erasing processing. A flash memory control method for controlling access to a certain flash memory,
An empty block search step for searching for an erased physical block in the flash memory; and
A write destination management step for managing the physical block in the erased state detected by the empty block step as a write destination block;
A writing step of writing data provided from the host system in the order from the first page to the last page in the physical page in the physical block managed as the write destination block from the write destination management step;
A transfer destination management step of managing the erased physical block detected by the empty block search step as a transfer destination block;
A transfer source specifying step of counting the number of physical pages in which invalid data in the physical block is stored, and specifying a physical block having the largest number of pages;
The physical pages in the physical block managed as the transfer destination block by the transfer destination management step are stored in the physical block specified by the transfer source specifying means in the order from the first page to the last page. A transfer step for transferring data,
In the write destination management step, when data is stored in all physical pages in the physical block managed as the write destination block, another physical block is newly managed as the write destination block,
In the transfer destination management step, when data is stored in all physical pages in the physical block managed as the transfer destination block, another physical block is newly managed as the transfer destination block,
The physical block managed as the write destination block by the write destination management step and the physical block managed as the transfer destination block by the transfer destination management step are different physical blocks.

A control method of a flash memory according to the third aspect of the present invention includes:
A free block management step for managing the number of erased physical blocks in the flash memory;
The transfer of valid data in the transfer step is preferably executed when the number of blocks becomes a predetermined value or less.

  According to the present invention, in the management of the storage area in the flash memory, the physical address of the physical page that becomes the write destination of the data given from the host system and the physical page that becomes the transfer destination of the data transferred by inter-block transfer Physical addresses are managed using separate pointers. By managing the storage area, data given from the host system and data transferred by inter-block transfer are stored in different physical blocks. Here, since data transferred by inter-block transfer has a high probability of being data with low rewrite frequency, data with low rewrite frequency and data with high rewrite frequency are efficiently separated. Then, by separating the data with low rewrite frequency from the data with high rewrite frequency, the frequency with which data with low rewrite frequency is subject to inter-block transfer can be kept low.

  For each physical block, the number of physical pages storing invalid data is managed, and a physical block with a large number of pages is preferentially selected as a transfer source for inter-block transfer. By selecting the transfer source physical block for inter-block transfer in this way, it is possible to shorten the processing time required for making the transfer source physical block free block.

FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present embodiment. FIG. 2 is a diagram showing the correspondence between the logical address on the host system side and the physical address in the flash memory. FIG. 3 is a diagram illustrating an address conversion table. FIG. 4 shows an empty block table. FIG. 5 is a diagram illustrating a physical block counter table. FIG. 6 is a diagram showing an invalid data page table. FIG. 7 is a flowchart for explaining a writing process for writing data given from the host system into the flash memory. FIG. 8 is a flowchart for explaining an inter-block transfer process for transferring data between physical blocks.

  As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a memory controller 3 that controls the flash memory 2. The memory controller 3 is connected to the flash memory 2 via the internal bus 14.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 is composed of a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

As shown in FIG. 1, the memory controller 3 includes a microprocessor 6, a host interface block 7, an SRAM 8, a buffer memory 9, a flash memory interface block 10, an error correction block 11, and a ROM (Read Only Memory) 12.
Hereinafter, each functional block will be described.

  The host interface block 7 controls transmission / reception of data, address information, status information, external commands and the like performed with the host system 4. That is, the flash memory system 1 captures data supplied from the host system 4 via the host interface block 7. The flash memory system 1 supplies data and the like to the host system 4 via the host interface block 7. The external command is a command for the host system 4 to instruct the flash memory system 1 to execute processing.

  The host interface block 7 includes a command register R1, a sector number register R2, and an LBA register R3. Information given from the host system 4 is written in the command register R1, the sector number register R2, and the LBA register R3. External commands such as a write command and a read command are written in the command register R1. In the sector number register R2, the number of sectors of data to be written or read is written. In an LBA (Logical Block Address) register R3, an LBA corresponding to a logical sector from which writing or reading is started is written. The LBA is an address assigned to a logical sector having a capacity of 512 bytes.

  An SRAM (Static Random Access Memory) 8 is a volatile memory that temporarily stores information necessary for controlling the flash memory 2. Various tables necessary for accessing the flash memory 2 are held in the SRAM 8 and updated on the SRAM 8. When a table necessary for accessing the flash memory 2 is not held in the SRAM 8, the table is created on the SRAM 8. However, when the table is stored in the flash memory 2, the stored table is read from the flash memory 2 and held in the SRAM 8. The various tables include an address conversion table, a search table, a defective block table, and the like. In the present invention, the address conversion table is a table for managing the correspondence between logical pages and physical pages. In addition to the above tables, the present invention stores two pointer information for writing data from the host system and for data transfer destinations between blocks. The bad block table is a table for managing bad blocks.

  The buffer memory 9 is a volatile memory that temporarily holds data read from the flash memory 2 or data to be written to the flash memory 2.

  The flash memory interface block 10 controls transmission / reception of data, address information, status information, internal commands and the like performed with the flash memory 2. Here, the internal command is a command for the memory controller 3 to instruct the flash memory 2 to execute processing, and the flash memory 2 operates in accordance with the internal command given from the memory controller 3.

  When the error correction block 11 writes data to the flash memory 2, the error correction block 11 encodes the data into an error correcting code (ECC) of the BCH code and reads the encoded data from the flash memory 2. The encoded data is decoded. That is, data written to the flash memory 2 is encoded into a BCH code to which redundant bits are added and written to the flash memory 2, and the encoded data (data to which redundant bits are added) is read. When decrypted, it is decrypted. In this decoding, bit errors up to a predetermined number of bits are corrected according to the number of redundant bits added at the time of encoding. In addition to the correction function based on the BCH code, the error correction block 11 has a detection function for detecting that a bit error having the number of bits exceeding the correction capability of the correction function has occurred.

  The ROM 12 is a non-volatile storage element for storing firmware necessary for controlling the flash memory 2. Note that only the minimum firmware necessary for starting up the flash memory system 1 may be stored in the ROM 12, and other firmware may be stored in the flash memory 2.

  The microprocessor 6 reads firmware from the ROM 12 or the flash memory 2 and operates according to the firmware. The functional blocks included in the memory controller 3 are controlled by the microprocessor 6.

  The flash memory 2 is a NAND flash memory, and includes a register and a memory cell array in which a plurality of memory cells are two-dimensionally arranged. The memory cell array includes a plurality of memory cell groups and word lines. Here, the memory cell group is a group in which a plurality of memory cells are connected in series. Each word line is for selecting a specific memory cell in the memory cell group. Data is written from the register to the selected memory cell or data is read from the selected memory cell to the register between the selected memory cell and the register via the word line. The flash memory includes a memory cell composed of SLC (Single Level Cell) type memory cells and a memory cell composed of MLC (Multi Level Cell) type memory cells.

  In the NAND flash memory, a data read operation and a data write operation are performed in units of pages, and a data erase operation is performed in units of blocks (physical blocks). Each physical block is composed of a plurality of pages (physical pages), and each physical page is composed of a user area and a redundant area. The user area is an area for mainly storing data given from the host system 4, and the redundant area is an area for mainly storing additional data such as logical address information, block status (flag) information, ECC, and the like. It is.

  The logical address information is information for specifying a logical page corresponding to the physical page related to the information. The block status (flag) is a flag indicating whether the physical block related to the information is a defective block (a physical block in which data cannot be normally written). The defective blocks include an initial defective block and a late defective block. The initial defective block is a defective block detected before shipment. A late defective block is a defective block generated during use. For an initial defective physical block, a block status (flag) indicating a defective block is written by the manufacturer. Some manufacturers also write a block status (flag) indicating the initial defective physical block in the user area.

  Next, an address conversion procedure and a write control method will be described. In the present invention, as shown in FIG. 2, address conversion for associating a logical address on the host system side with a physical address in the flash memory is performed in units of pages. Accordingly, a logical page including a plurality of logical sectors (512 bytes) which are access units of the host system is defined, and the correspondence between the logical page and the physical page is managed in this logical page unit. In the present embodiment, a flash memory composed of physical pages having a user area of 8 sectors (4096 bytes) is used. Therefore, the logical page is composed of 8 logical sectors.

  The logical page number (LPN) is a serial number assigned to the logical page. The physical block address (PBA) corresponds to an address assigned to the physical block in the flash memory. The physical page number (PPN) is a serial number in each physical block assigned to a physical page in each physical block. Note that a physical page number (PPN) connected to the lower side of the physical block address (PBA) corresponds to a physical page address (PPA) assigned to a physical page in the flash memory.

  The conversion from the logical page number (LPN) to the physical page address (PPA) is performed using an address conversion table as shown in FIG. This address conversion table is configured by an area in which a physical page address (PPA) corresponding to each logical page number (LPN) is stored. The physical page address (PPA) includes a bit indicating a physical block address (PBA) and a bit indicating a physical page number (PPN) in the physical block. In this embodiment, each logical page number (LPN) is composed of a 23-bit area. Of the 23-bit area, the upper 15 bits correspond to the physical block address (PBA), and the lower 8 bits correspond to the physical page number (PPN).

  In this embodiment, the physical page address (PPA) of the data write destination given from the host system is managed based on the write pointer (WP), and the physical page address of the transfer destination when data is transferred between physical blocks. (PPA) is managed based on the transfer pointer (TP). In addition, a physical block that is a write destination of data given from the host system and a physical block that is a transfer destination when data is transferred between the physical blocks are managed by different physical locks. Therefore, the physical block to which the physical page of the physical page address (PPA) indicated by the write pointer (WP) belongs and the physical block to which the physical page of the physical page address (PPA) indicated by the transfer pointer (TP) belong are The physical blocks are different from each other.

  When write data and information such as LBA are given from the host system, the physical page address (PPA) of the physical page of the write destination is acquired by the write pointer (WP). Then, data given from the host system is written to the physical page of the physical page address (PPA). As the data is written, the address conversion table is updated. In this address conversion table, the physical page address (PPA) of the area is written in the area corresponding to the logical page number (LPN) of the written data. The logical page number (LPN) corresponding to the data to be written is obtained based on LBA or the like given from the host system.

  When inter-block transfer is performed, a physical page address (PPA) of a transfer destination physical page is acquired by a transfer pointer (TP). Then, the transfer source data is transferred to the physical page of the physical page address (PPA).

  An empty block, which is an erased physical block or a physical block in which no valid data is stored, is managed using an empty block table as shown in FIG. In this empty block table, each physical block in the flash memory is assigned to one bit on the table. The logical value (“0” or “1”) of each bit indicates whether or not the physical block assigned to that bit corresponds to an empty block. In this example, a logical value “0” indicates that it corresponds to an empty block, and a logical value “1” indicates that it does not correspond to an empty block. A 1-byte (8-bit) area is assigned to each address on the empty block table. In the entire table, an area of 2048 bytes from address # 0 to address # 2047 is used as an area for this empty block table. For example, eight physical blocks of physical block addresses (PBA) # 0 to # 7 are allocated to 8 bits from the least significant bit to the most significant bit of address # 0. Eight physical blocks from physical block addresses (PBA) # 8 to # 15 are assigned to 8 bits from the least significant bit to the most significant bit of address # 1, respectively. Similarly, physical blocks from physical block addresses (PBA) # 16 to # 16383 are sequentially assigned.

  The write pointer (WP) sequentially specifies the physical page address (PPA) of the physical page in the physical block assigned as the write destination of the data given from the host system from the first page to the last page. The transfer pointer (TP) sequentially specifies the physical page address (PPA) of the physical page in the physical block assigned as the transfer destination when transferring data between the physical blocks from the first page to the last page.

  Therefore, for the physical block assigned as the designation target of the write pointer (WP) or transfer pointer (TP), the logical value of the bit on the empty block table corresponding to the physical block changes from “0” to “1”. Be changed.

  All the valid data stored in the transfer-source physical block of the inter-block transfer is transferred to the transfer-destination physical block, so that the transfer-source physical block becomes an empty block. When the transfer-source physical block becomes an empty block, the logical value of the bit on the empty block table corresponding to the transfer-source physical block is changed from “1” to “0”.

  The number of physical pages storing invalid data in the physical block is managed by a physical block counter table as shown in FIG. In the physical block counter table, for each physical block, the value of the number of physical pages in which invalid data in the physical block is stored is held. Here, invalid data refers to data replaced by new data. When data given from the host system is written to the physical page at the physical page address (PPA) indicated by the write pointer (WP), the data replaced by the data becomes invalid data. That is, when data is written and there is old data corresponding to the same logical page as the data, the old data changes from valid data to invalid data. Therefore, when data is written, the number of physical pages in which invalid data is stored in the physical block in which the old data is stored increases by one. Thus, when the number of pages of physical pages storing invalid data in a physical block increases, the value of the number of pages held in the physical block counter table is updated.

  In the present embodiment, one physical block is composed of 64 physical pages. Accordingly, the value of the number of physical pages in which invalid data held in the physical block counter table is stored varies from “0” to “64”. Since the physical block with the page number value of “64” does not store valid data, it is erased and handled as an empty block.

  A physical page in which invalid data in each physical block is stored is managed by an invalid data page table as shown in FIG. In this invalid data page table, each physical page in the flash memory is assigned to one bit on the table. The logical value (“0” or “1”) of each bit indicates whether or not the data stored in the physical page assigned to the bit corresponds to invalid data. In this example, data indicating that the logical value “0” is stored does not correspond to invalid data, and data indicating that the logical value “1” is stored corresponds to invalid data. That is, when no data is stored in the physical page or valid data is stored, the logical value of the bit corresponding to the physical page is “0”, and invalid data is stored in the physical page. In this case, the logical value of the bit corresponding to the physical page becomes “1”. A 1-byte (8-bit) area is assigned to each address on the invalid data page table. In the entire table, an area of 524288 bytes from address # 0 to address # 524287 is used as an area for this invalid data page table. For example, 8 physical pages from physical page number (PPN) # 0 to # 7 in the physical block of physical block address (PBA) # 0 are added to 8 bits from the least significant bit to the most significant bit of address # 0. Are assigned to each. Eight physical pages from physical page number (PPN) # 8 to # 15 in the physical block of physical block address (PBA) # 0 are respectively included in the 8 bits from the least significant bit to the most significant bit of address # 1. Assigned. In this way, the physical pages in the physical blocks having physical block addresses (PBA) # 0 to # 16383 are sequentially allocated.

Next, a writing process for writing data given from the host system into the flash memory will be described with reference to FIG.
Step 1:
One page of data provided from the host system is written to the physical page at the physical page address (PPA) indicated by the write pointer (WP).
Step 2:
It is determined whether or not the physical page at the physical page address (PPA) indicated by the write pointer (WP) is the last physical page in the physical block. If it is determined that the physical page of the physical page address (PPA) indicated by the write pointer (WP) is the last physical page in the physical block, the process proceeds to step 3. If it is determined that the physical page at the physical page address (PPA) indicated by the write pointer (WP) is not the last physical page in the physical block, the process proceeds to step 6.
Step 3:
An empty block search using an empty block table is performed.
Step 4:
The physical page address (PPA) corresponding to the first physical page in the physical block detected by the empty block search in step 3 is set in the write pointer (WP).
Step 5:
Update the free block table. That is, the logical value of the bit corresponding to the physical block detected by the empty block search in step 3 is changed from “0” to “1”.
Step 6:
The value of the physical page address (PPA) set in the write pointer (WP) is incremented. That is, the value of the physical page address (PPA) set in the write pointer (WP) is changed to the physical page address (PPA) of the next physical page.

  As described above, data given from the host system is sequentially written from the first physical page to the last physical page in the physical page in the physical block assigned as the write destination of the data given from the host system. . When data is written to all physical pages, a new physical block (empty block) is newly assigned as a data write destination given from the host system.

  In addition, when data given from the host system is written to a physical page in the physical block of the write destination, if there is old data corresponding to the same logical page number (LPN) as that data, that is, the data is When there is data that becomes invalid data by being written, the physical block counter table and the invalid data page table are updated.

  In updating the physical block counter table, the value of the number of pages corresponding to the physical block to which the physical page storing the invalid data is stored, that is, the physical page storing the invalid data in the physical block. A value indicating the number of pages is incremented. As described above, when there is data that becomes invalid data by writing data given from the host system, the value of the number of pages corresponding to the physical block to which the physical page storing the data belongs increases by one.

  In the update of the invalid data page table, when there is data that becomes invalid data by writing the data given from the host system, the logical value of the bit corresponding to the physical page storing the data is changed from “0”. It is changed to “1”.

Next, an inter-block transfer process for transferring data between physical blocks will be described with reference to FIG. This inter-block transfer process is a process performed to make a transfer source physical block into an empty block, and is performed when the number of empty blocks in the flash memory becomes equal to or less than a predetermined number.
With reference to the physical block counter table, the value indicating the number of physical pages in which invalid data is stored is the most “64”.
Identify physical blocks close to. Further, the number of physical pages in which valid data in the physical block is stored is obtained. If the value indicating the number of physical pages in which invalid data is stored is n, the number of physical pages in which valid data is stored is 64-n.
Step 2:
By referring to the invalid data page table, a physical page in which valid data in the physical block identified in step 1 is stored is identified. Then, the valid data for one page in the physical block identified in step 1 is transferred (copied) to the physical page at the physical page address (PPA) indicated by the transfer pointer (TP).
Step 3:
It is determined whether or not the physical page at the physical page address (PPA) indicated by the transfer pointer (TP) is the last physical page in the physical block. If it is determined that the physical page of the physical page address (PPA) indicated by the transfer pointer (TP) is the last physical page in the physical block, the process proceeds to step 4. If it is determined that the physical page of the physical page address (PPA) indicated by the transfer pointer (TP) is not the last physical page in the physical block, the process proceeds to step 7.
Step 4:
An empty block search using an empty block table is performed.
Step 5:
The physical page address (PPA) corresponding to the first physical page in the physical block detected by the empty block search in step 4 is set in the transfer pointer (TP).
Step 6:
Update the free block table. That is, the logical value of the bit corresponding to the physical block detected by the empty block search in step 4 is changed from “0” to “1”.
Step 7:
The value of the physical page address (PPA) set in the transfer pointer (TP) is incremented. That is, the value of the physical page address (PPA) set in the transfer pointer (TP) is changed to the physical page address (PPA) of the next physical page.
Step 8:
If there is a physical page in which valid data is stored in the physical block identified in step 1, return to step 2; if there is no physical page in which valid data is stored, transfer between blocks. End the process. That is, after the data corresponding to the number of physical pages in which valid data is stored is transferred, the inter-block transfer process is terminated.

  In this way, the data transferred by the inter-block transfer process is sequentially written from the first physical page to the last physical page on the physical page in the physical block assigned as the transfer destination. When data is written to all physical pages, a new physical block (empty block) is newly allocated as a transfer destination of data transferred by the inter-block transfer process.

  Further, after the inter-block transfer process is completed, the transfer source physical block is erased, and the physical block counter table and the invalid data page table are updated accordingly. In the update of the physical block counter table, the value indicating the number of physical pages in which invalid data in the transfer source physical block is stored is reset to “0”. In updating the invalid data page table, the logical value of the bit corresponding to each physical page in the transfer source physical block is reset to “0”.

  The data transferred by the inter-block transfer process has a high probability of being data with a low rewrite frequency. By making the blocks different physical blocks, data with relatively low rewrite frequency and data with relatively high rewrite frequency are efficiently separated. In this way, data with relatively low rewrite frequency and data with relatively high rewrite frequency are stored separately in different physical blocks, so that the number of times that inter-block transfer processing is executed and the transfer between the blocks The total amount of data transferred by processing is reduced.

  Although the embodiment of the present invention has been described above, this is an example for explaining the present invention, and the scope of the present invention is not limited to this embodiment. Of course, various modifications can be made without departing from the scope of the present invention.

  For example, the present invention is also effective in a flash memory system having a plurality of channel buses for accessing a plurality of flash memories. A plurality of physical blocks respectively selected from a plurality of flash memories connected to each channel are defined as one virtual block. Furthermore, a plurality of physical pages respectively included in a plurality of physical blocks constituting the virtual block are defined as one virtual page. The present invention can also be applied to such a virtual space. In that case, the address conversion from the LBA space of the host system to the physical address in the flash memory is performed in units of virtual pages. That is, one logical page is assigned to one virtual page. Therefore, the size of the logical page matches the total value of the user data area of the virtual page.

  The present invention can be applied to an information storage (recording) device mounted on or built in an electronic device such as a personal computer or a digital still camera that handles various digital information.

1 ... flash memory system, 2 ... flash memory, 3 ... memory controller

Claims (5)

A logical page including one or a plurality of logical sectors to which a logical address given by the host system is assigned is defined, and a physical block including a plurality of physical pages which are processing units of write processing is a processing unit of erasing processing. A memory controller that controls access to a flash memory,
An empty block search means for searching for an erased physical block in the flash memory,
Write destination management means for managing the physical block in the erased state detected by the empty block search means as a write destination block;
The physical of the storage destination in the physical block is stored so that the data is stored in the physical page in the physical block managed as the write destination block by the write destination management unit in the order from the first page to the last page. Write destination instruction means for indicating a page;
Writing means for writing data given from the host system to the physical page instructed by the writing destination instruction means;
Transfer destination management means for managing a physical block in the erased state detected by the empty block search means as a transfer destination block;
A transfer source specifying means for counting the number of physical pages in which invalid data in the physical block is stored, and specifying a physical block having the largest number of pages;
The physical storage in the physical block is stored in the physical page in the physical block managed as the transfer destination block by the transfer destination management unit so that data is stored in the order from the first page to the last page. A transfer destination instruction means for indicating a page;
Transfer means for transferring valid data stored in the physical block specified by the transfer source specifying means to the physical page specified by the transfer destination indicating means,
The write destination management means newly manages another physical block as the write destination block when data is stored in all physical pages in the physical block managed as the write destination block,
The transfer destination management means newly manages another physical block as the transfer destination block when data is stored in all physical pages in the physical block managed as the transfer destination block,
The memory controller, wherein the physical block managed as the write destination block by the write destination management means and the physical block managed as the transfer destination block by the transfer destination management means are different physical blocks. A free block management means for managing the number of erased physical blocks in the flash memory;
2. The memory controller according to claim 1, wherein transfer of valid data by the transfer means is executed when the number of blocks becomes a predetermined value or less. Memory controller according to claim 1 or 2,
A flash memory system comprising a flash memory controlled by the memory controller. A logical page including one or a plurality of logical sectors to which a logical address given by the host system is assigned is defined, and a physical block including a plurality of physical pages which are processing units of write processing is a processing unit of erasing processing. A flash memory control method for controlling access to a certain flash memory,
An empty block search step for searching for an erased physical block in the flash memory; and
A write destination management step for managing the physical block in the erased state detected by the empty block step as a write destination block;
A writing step of writing data provided from the host system in the order from the first page to the last page in the physical page in the physical block managed as the write destination block from the write destination management step;
A transfer destination management step of managing the erased physical block detected by the empty block search step as a transfer destination block;
A transfer source specifying step of counting the number of physical pages in which invalid data in the physical block is stored, and specifying a physical block having the largest number of pages;
The physical pages in the physical block managed as the transfer destination block by the transfer destination management step are stored in the physical block specified by the transfer source specifying means in the order from the first page to the last page. A transfer step for transferring data,
In the write destination management step, when data is stored in all physical pages in the physical block managed as the write destination block, another physical block is newly managed as the write destination block,
In the transfer destination management step, when data is stored in all physical pages in the physical block managed as the transfer destination block, another physical block is newly managed as the transfer destination block,
Control of a flash memory, wherein the physical block managed as the write destination block by the write destination management step and the physical block managed as the transfer destination block by the transfer destination management step are different physical blocks Method. A free block management step for managing the number of erased physical blocks in the flash memory;
5. The flash memory control method according to claim 4, wherein the transfer of valid data in the transfer step is executed when the number of blocks becomes a predetermined value or less.

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