JP2012064855A - Semiconductor device - Google Patents

Abstract

A highly reliable semiconductor device is provided.
In a semiconductor device, a circuit board includes a metal circuit having terminal mounting portions having a chip mounting portion and an uneven portion. The semiconductor chip 11 is connected to the chip mounting part 34 via the first solder layer 12. The electrode terminals 16, 20, and 24 are arranged on the terminal mounting portions via the second solder layers 17, 21, and 25, which have one end facing the surface of the metal circuit 32 substantially in parallel and buried so as to fill the uneven portion 35. It is joined to 36 a, 36 b and 36 c and is electrically connected to the semiconductor chip 11.
[Selection] Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device.

  In the power semiconductor device, the power semiconductor element is soldered to the chip mounting portion of the metal circuit using the circuit board having the metal circuit, and the power semiconductor element is soldered to the terminal mounting portion of the metal circuit. It is pulled out by the electrode terminal.

  In power semiconductor devices, the amount of heat generated during energization is increasing as the degree of integration increases. As a result, there is a problem that fatigue of the solder joint portion increases and reliability of the semiconductor device is impaired.

  As a method for inspecting this fatigue life, there is a TFT test (Thermal Fatigue Test). When the power semiconductor element generates heat due to energization, the temperature of the metal circuit, solder joint, electrode terminal, etc. around the power semiconductor element rises.

  In particular, since the upper and lower surfaces of the solder joint are fixed, when the temperature rises, a compressive stress is generated due to thermal expansion. As the temperature decreases, the compressive stress is released.

  Due to the repeated generation and release of the compressive stress, the solder joint is fatigued and becomes brittle. When the solder joint becomes brittle, a solder crack is generated, resulting in an electrically open state.

JP 2007-96004 A

  The present invention provides a highly reliable semiconductor device.

  According to one embodiment, in the semiconductor device, the circuit board includes a metal circuit having a chip mounting portion and a terminal mounting portion having an uneven portion. The semiconductor chip is connected to the chip mounting portion via a first solder layer. One end of the electrode terminal is opposed to the surface of the metal circuit substantially in parallel, and is joined to the terminal mounting portion via a second solder layer stacked so as to fill the uneven portion, and is electrically connected to the semiconductor chip. Connected.

1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. FIG. 2A is a plan view of the circuit board according to the first embodiment, FIG. 2A is a plan view thereof, and FIG. 2B is a cross-sectional view taken along the line AA in FIG. . FIG. 6 is a diagram for explaining an assembly process of the semiconductor device according to the first embodiment. FIG. 4A is a plan view of the circuit board according to the first embodiment, FIG. 4B is a plan view thereof, and FIG. 4B is cut along the line BB in FIG. Sectional drawing. FIG. 5A is a plan view of the circuit board according to the first embodiment, FIG. 5B is a plan view thereof, and FIG. 5B is cut along the line CC in FIG. 5A and viewed in the direction of the arrow. Sectional drawing. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to a second embodiment. FIG. 10 is a cross-sectional view showing another main part of the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing another main part of the semiconductor device according to the second embodiment. FIG. 9 is a cross-sectional view showing the main parts of a semiconductor device according to Example 3;

  Embodiments of the present invention will be described below with reference to the drawings.

  The semiconductor device according to this example will be described with reference to FIGS. 1 is a cross-sectional view showing a semiconductor device of this embodiment, FIG. 2 is a view showing a circuit board, FIG. 2 (a) is a plan view thereof, and FIG. 2 (b) is an AA line in FIG. 2 (a). It is sectional drawing which cut | disconnected along and was seen in the arrow direction.

  In the semiconductor device 10 of the present embodiment, a power semiconductor chip, for example, an IGBT (Insulated Gate Bipolar Transistor), a power MOS transistor, and an electrode terminal electrically connected to the semiconductor chip are placed on a circuit board having a metal circuit. Yes. The semiconductor chip is mounted on the chip mounting portion of the metal circuit, and the electrode terminals are mounted on the terminal mounting portion of the metal circuit.

  First, the circuit board will be described. As shown in FIG. 2, the circuit board 30 has a metal circuit 32 formed on the first surface 31a of the insulating substrate 31, and a metal circuit 33 formed on the second surface 31b opposite to the first surface 31a. Yes.

  The metal circuit 32 is divided into three parts. A metal circuit 32 a including a chip mounting portion 34 and a terminal mounting portion 36 a having a concavo-convex portion 35 is formed in the central portion of the insulating substrate 31. Formed on both ends of the insulating substrate 31 are a metal circuit 32b having a terminal placement portion 36b having an uneven portion 35 so as to sandwich the metal circuit 32a, and a metal circuit 32c having a terminal placement portion 36c having an uneven portion 35. Has been.

  The metal circuit 33 is a single metal film, and is provided for soldering the circuit board 30 to a heat sink described later.

  A semiconductor chip is soldered to the chip mounting portion 34. Electrode terminals that are electrically connected to the semiconductor chip are soldered to the terminal mounting portions 36a, 36b, and 36c.

  The insulating substrate 31 is an alumina ceramic substrate, for example. The metal circuits 32 and 33 are, for example, aluminum foil.

  The uneven portion 35 is a groove having a V-shaped cross section. The width and depth of the groove are, for example, about 0.3 mm and about 0.5 mm. The concavo-convex portion 35 is formed, for example, by pressing using a mold having a V-shaped cross section and a stripe-shaped convex portion.

  Next, returning to FIG. 1, the semiconductor device of this embodiment will be described. As shown in FIG. 1, in the semiconductor device 10, the semiconductor chip 11 is mounted on the chip mounting portion 34 of the metal circuit 32a. The semiconductor chip 11 is, for example, a vertical IGBT, and the collector electrode is bonded to the chip mounting portion 34 of the metal circuit 32 a via the solder layer (first solder layer) 12.

  A heat sink 14 is bonded to a metal circuit 33 via a solder layer 13 on a circuit board 30 on which the semiconductor chip 11 is mounted. A fin-type heat dissipation plate 15 is further attached to the heat dissipation plate 14. The heat radiation of the semiconductor chip 11 when energized is dissipated into the atmosphere by the two heat sinks 14 and 15.

  One end portion of the electrode terminal 16 is bent to face the surface of the metal circuit 32a substantially in parallel with the terminal mounting portion via a solder layer (second solder layer) 17 (not shown) that is stacked so as to fill the uneven portion 35. It is joined to 36a. The other end of the electrode terminal 16 is bent and fixed to the bus bar 19 by a bolt / nut 18.

  One end of the electrode terminal 20 is bent to face the surface of the metal circuit 32b substantially parallel to the terminal mounting portion 36b via a solder layer (second solder layer) 21 that is stacked so as to fill the uneven portion 35. It is joined. The other end of the electrode terminal 20 is bent and fixed to the bus bar 23 with bolts and nuts 22.

  One end of the electrode terminal 24 is bent so as to face the surface of the metal circuit 32c substantially parallel to the terminal mounting portion 36c via a solder layer (second solder layer) 25 stacked so as to fill the uneven portion 35. It is joined.

  The emitter electrode of the semiconductor chip 11 is connected to the metal circuit 32 b via a plurality of wires 28. The base electrode of the semiconductor chip 11 is connected to the metal circuit 32 c through the wire 29.

  The circuit board 30 is housed in a synthetic resin case 40 with the heat sink 14 exposed. The case 40 is hermetically sealed by a synthetic resin terminal holder 41. The electrode terminals 16, 20, 24 pass through the terminal holder 41.

  The semiconductor device 10 of the present embodiment is configured to increase the effective thickness of the solder layers 17, 21, and 25 that join the electrode terminals 16, 20, and 24 to the terminal mounting portions 36a, 36b, and 36c. Yes.

  The solder layer 21 is stacked so as to fill the uneven portion 35 and joins the electrode terminal 20 to the terminal mounting portion 36b. As a result, the effective thickness t1 of the solder layer 21 can be made larger than the apparent thickness t2 in accordance with the depth of the uneven portion 35 (t1> t2).

  Here, the apparent thickness is a distance between the lower surface (second surface) of the bent one end of the electrode terminal 20 and the upper surface (first surface) of the metal circuit 32b. The effective thickness is obtained by adding the product of coefficients according to the depth of the uneven portion 35 and the cross-sectional shape of the uneven portion 35 to the apparent thickness.

  Furthermore, since the solder is stored in the concavo-convex portion 35, it is possible to prevent the solder from spreading outside the terminal placement portion 36b. The same applies to the solder layers 17 and 25.

  As a result, it is possible to effectively increase the thickness of the solder layers 17, 21, and 25 without increasing the height from the circuit board 30. For example, the thickness of the solder layer required for suppressing metal fatigue is about 100 μm. Even if the apparent thickness of the solder layers 17, 21 and 25 is set to about 30 μm, a sufficient effective thickness can be secured.

  Furthermore, even when the apparent thickness of the solder layers 17, 21 and 25 varies, sufficient robustness can be ensured.

  By effectively increasing the thickness of the solder layers 17, 21, 25, metal fatigue of the solder layers 17, 21, 25 due to heat generation of the semiconductor chip 11 during energization is reduced. It is possible to prevent solder cracks from being generated due to metal fatigue of the solder layers 17, 21, 25 and reaching an electrically open state.

  Next, an assembly process of the semiconductor device 10 will be described. FIG. 3 is a diagram for explaining an assembly process of the semiconductor device 10. 3A is a perspective view showing a state in which the case 40 is mounted on the heat radiating plate 14, and FIG. 3B is a perspective view showing the electrode terminals 16, 20, 24 fixed to the terminal holder 41. Since the electrode terminal 16 is hidden behind the terminal holder 41, it is not shown in FIG.

  First, as shown in FIG. 3C, the circuit board 30 having the metal circuits 32 a, 32 b, and 32 c and having the semiconductor chip 11 soldered to the metal circuit 32 a is attached to the heat radiating plate 14.

  Next, as shown in FIG. 3 (d), the electrode terminals 16, 20, 24 attached to the terminal holder 41 are soldered to the metal circuits 32 a, 32 b, 32 c of the circuit board 30.

  Thereafter, the case 40 is attached to the heat sink 14 so that the circuit board 30 is accommodated in the case 40. Thereafter, a resin (not shown) is filled in the case 40, and the circuit board 30 and the semiconductor chip 11 are sealed with the resin.

  After the assembly, the semiconductor device 10 was subjected to 10,000 cycles of the TFT test. The TFT test condition is, for example, room temperature to 120 ° C. After the TFT test, the semiconductor device 10 was disassembled to investigate whether or not solder cracks occurred in the solder layers 17, 21, and 25.

  As a result, almost no solder cracks were observed (approximately 0/10000 pcs), and it was confirmed that metal fatigue was suppressed.

  As described above, in the semiconductor device of this embodiment, the terminal mounting portions 36a, 36b, and the electrode mounting portions 36a, 36b, and the electrode layers 16, 20, and 25 are formed so as to fill the uneven portion 35. 36c.

  As a result, the effective thickness t1 of the solder layers 17, 21, 25 can be increased. Metal fatigue of the solder layers 17, 21, 25 due to heat generation of the semiconductor chip 11 during energization is reduced, and solder cracks are generated in the solder layers 17, 21, 25 to prevent an electrical open state from being reached. Can do. Therefore, the semiconductor device 10 having sufficient reliability can be obtained.

  Here, the case where the concavo-convex portion is a groove has been described. However, the present invention is not limited to this, and other shapes such as holes and through holes may be used.

  4A and 4B are diagrams showing a circuit board provided with a metal circuit in which the concavo-convex portion is a hole. FIG. 4A is a plan view thereof, and FIG. 4B is along a line BB in FIG. It is sectional drawing which cut | disconnected and looked at the arrow direction. As shown in FIG. 4, the circuit board 50 includes metal circuits 32 a, 32 b, and 32 c in which the uneven portion 51 is a hole. When the concavo-convex portion is a hole, the coefficient corresponding to the cross-sectional shape is larger than the V-shape, so that there is an advantage that the effective thickness increases.

  FIG. 5 is a diagram showing a circuit board provided with a metal circuit in which the concavo-convex portion is a through hole, FIG. 5 (a) is a plan view thereof, and FIG. 5 (b) is taken along line CC in FIG. It is sectional drawing which cut | disconnected and looked in the arrow direction. As shown in FIG. 5, the circuit board 55 includes metal circuits 32a, 32b, and 32c in which the concavo-convex portion 56 is a through hole. In the case where the concavo-convex portion is a through-hole, the coefficient corresponding to the cross-sectional shape is larger than the V-shape, and thus there is an advantage that the effective thickness is further increased.

  A semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view showing the semiconductor device of this example. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. This embodiment differs from the first embodiment in that an uneven portion is formed on the electrode terminal.

  That is, as shown in FIG. 6, in the semiconductor device 60 of the present embodiment, a power semiconductor chip 61, for example, an IGBT and electrode terminals 62 and 63 electrically connected to the semiconductor chip 61, and an electrode terminal 64 (not shown) are provided in the circuit. It is placed on the substrate 65. The circuit board 65 is basically the same as the circuit board 30 except that the unevenness is not formed on the terminal mounting portion.

  Metal circuits 66a, 66b, and 66c are formed on the insulating substrate 31 of the circuit board 65. The semiconductor chip 61 is placed on the chip mounting portion of the metal circuit 66a. The back surface of the semiconductor chip 61 is bonded to the chip mounting portion of the metal circuit 66 a through the solder layer 12.

  One end of the electrode terminal 64 is bent to face the surface of the metal circuit 66a substantially parallel to the metal circuit 66a via a solder layer (second solder layer) (not shown) that covers the one end so as to fill the uneven portion 67. It is joined to the terminal mounting part. The other end of the electrode terminal 64 (not shown) is bent and connected to a bus bar (not shown) by bolts and nuts (not shown).

  One end of the electrode terminal 62 is bent so as to face the surface of the metal circuit 66 c substantially parallel to the metal circuit 66 c via a solder layer (second solder layer) 68 covering the one end so as to fill the uneven portion 67. It is joined to the terminal mounting part. The other end of the electrode terminal 62 is bent and connected to the bus bar 70 by a bolt / nut 69.

  One end of the electrode terminal 63 is bent so as to face the surface of the metal circuit 66b substantially parallel to the metal circuit 66b via a solder layer (second solder layer) 71 that covers the one end so as to fill the uneven portion 67. It is joined to the terminal mounting part. The other end of the electrode terminal 63 is bent and connected to the bus bar 73 by a bolt / nut 72.

  The collector electrode of the semiconductor chip 61 is directly bonded to the metal circuit 66a. The base electrode of the semiconductor chip 61 is connected to the metal circuit 66 c through the wire 74. The emitter electrode of the semiconductor chip 61 is connected to the metal circuit 66 b through the wire 75.

  The semiconductor device 60 of this embodiment is configured to increase the bonding area between the electrode terminals 62 and 63 and the solder layers 68 and 71.

  The electrode terminals 62 and 63 have, for example, a width of 5 mm and a thickness of 6 mm. The uneven portion 67 is formed by pressing using, for example, a mold. The uneven portions 67 are desirably formed in a dispersed manner.

  By increasing the bonding area between the electrode terminals 62 and 63 and the solder layers 68 and 71, the stress applied to the electrode terminals 62 and 63 due to heat generation of the semiconductor chip 11 during energization is relieved, and solder cracks are generated in the solder layers 68 and 71. It is possible to prevent the occurrence of an electrical open state. This is because the overall stress is reduced by locally concentrating the stress on the uneven portion 67. The same applies to the electrode terminal 64 (not shown), and the description thereof is omitted.

  As described above, in the semiconductor device 60 of the present embodiment, since the electrode terminals 62 and 63 have the concavo-convex portions 67, the bonding area with the solder layers 68 and 71 increases. As a result, stress concentrates locally on the concavo-convex portion 67 and the overall stress is reduced.

  It is possible to prevent solder cracks from occurring in the solder layers 68 and 71 and reaching an electrically open state. Therefore, the semiconductor device 60 having sufficient reliability can be obtained.

  Here, the case where the concavo-convex portion is rectangular has been described, but the present invention is not limited to this, and other forms such as a triangular shape and a dome shape may be used.

  FIG. 7 is a cross-sectional view showing a case where the electrode terminal having a triangular uneven portion is soldered. As shown in FIG. 7, the electrode terminal 81 has a triangular uneven portion 82.

  FIG. 8 is a cross-sectional view showing a case where an electrode terminal having an uneven portion having a dome shape is soldered. As shown in FIG. 8, the electrode terminal 91 is formed with a dome-shaped uneven portion 92.

  A semiconductor device according to Example 3 of the present invention will be described with reference to FIG. FIG. 9 is a cross-sectional view showing the main part of the semiconductor device of this embodiment. The present embodiment is an example in which the first embodiment and the second embodiment are combined.

  That is, as shown in FIG. 9, in the semiconductor device of this example, the terminal mounting portion 36 c of the metal circuit 32 c is formed with the uneven portion (first uneven portion) 35, and the electrode terminal 62 is formed with the uneven portion ( A second concavo-convex portion 67 is formed.

  The uneven portion 35 increases the effective thickness of the solder layer 68 between the upper surface of the metal circuit 32 c and the lower surface of the electrode terminal 62, and the uneven portion 67 increases the contact area between the electrode terminal 62 and the solder layer 68.

  Due to the synergistic effect of the concavo-convex portion 35 and the concavo-convex portion 67, it is possible to increase the effect of preventing a solder crack from occurring in the solder layer 68 due to heat generation of the semiconductor chip 11 during energization and reaching an electrically open state. It is.

  As described above, in the semiconductor device of this embodiment, the uneven portion 35 is formed in the terminal mounting portion 36 c of the metal circuit 32 c, and the uneven portion 67 is formed in the electrode terminal 62. As a result, the synergistic effect of the concavo-convex portion 35 and the concavo-convex portion 67 increases the effect of preventing solder cracks from occurring in the solder layer 68 due to heat generation of the semiconductor chip 11 during energization and reaching an electrically open state. To do.

  The above-described embodiments are merely exemplary and are not intended to limit the scope of the invention. Indeed, the novel devices described herein may be embodied in a variety of other forms, and various omissions may be made in the form of devices described herein without departing from the spirit or spirit of the invention. Replacements and changes may be made. The appended claims and their equivalents or equivalent methods are intended to include such forms or modifications as would fall within the scope and spirit or spirit of the present invention.

10, 60 Semiconductor device 11, 61 Semiconductor chip 12, 13, 17, 21, 25, 68, 71 Solder layer 14, 15 Heat sink 16, 20, 24, 62, 63, 81, 91 Electrode terminals 18, 22, 69, 71 Bolt / Nut 19, 23, 70, 73 Busbar 28, 29, 74, 75 Wire 40 Case 41 Terminal holder 30, 50, 55, 65 Circuit board 31 Insulating board 32, 33, 66 Metal circuit 34 Chip placement Portions 35, 51, 56, 67, 82, 92 Uneven portion 36a, 36b, 36c Terminal mounting portion

Claims (5)

A circuit board including a metal circuit having a chip mounting portion and a terminal mounting portion having an uneven portion;
A semiconductor chip connected to the chip mounting portion via a first solder layer;
One end is opposed to the surface of the metal circuit substantially in parallel, and is joined to the terminal mounting portion via a second solder layer stacked so as to fill the uneven portion, and is electrically connected to the semiconductor chip. Electrode terminals,
A semiconductor device comprising: A circuit board including a metal circuit having a chip mounting portion and a terminal mounting portion;
A semiconductor chip connected to the chip mounting portion via a first solder layer;
Having a concavo-convex portion, one end facing the surface of the metal circuit substantially in parallel, and being joined to the terminal placement portion via a second solder layer covering the one end so as to fill the concavo-convex portion; An electrode terminal electrically connected to the semiconductor chip;
A semiconductor device comprising: A circuit board including a metal circuit having a chip mounting portion and a terminal mounting portion having a first uneven portion;
A semiconductor chip connected to the chip mounting portion via a first solder layer;
The one end portion has a second uneven portion, and the one end portion faces substantially parallel to the surface of the metal circuit, and is arranged so as to fill the first uneven portion, and fills the second uneven portion. An electrode terminal joined to the terminal mounting portion via a second solder layer covering the electrode and electrically connected to the semiconductor chip;
A semiconductor device comprising:   4. The semiconductor device according to claim 1, wherein the uneven portion or the first uneven portion is one of a groove, a hole, and a through hole.   4. The semiconductor device according to claim 2, wherein the concavo-convex portion or the second concavo-convex portion has any one of a rectangular shape, a triangular shape, and a dome shape in cross section.

Images