JP2012059153A - Design support apparatus, design support method, design support program, and manufacturing method of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve readability of circuit descriptions of an RTL.SOLUTION: A design support apparatus has: operation combination means for generating a circuit description of a first RTL on the basis of a circuit description of an operation level; parameter name generation means which generates, for a parameter included in the circuit description of the first RTL, a parameter name based on a parameter name of a corresponding parameter in an arithmetic expression substituted to the parameter or the circuit description of the operation level and records in storage means information of correspondence between the parameter name of the parameter included in the circuit description of the first RTL and the parameter name generated for the parameter; and circuit description output means for outputting the circuit description of the first RTL and a second RTL circuit description obtained by replacing the parameter name of the first RTL circuit description with the parameter name generated by the parameter name generation means.

Description

  The present invention relates to a design support apparatus, a design support method, a design support program, and a method for manufacturing a semiconductor integrated circuit, and more particularly to a design support apparatus, a design support method, a design support program, and a design support apparatus for generating an RTL circuit description by a behavioral synthesis method. The present invention relates to a method for manufacturing a semiconductor integrated circuit.

  In recent years, a behavioral synthesis (or high-level synthesis) method has attracted attention as semiconductor integrated circuits become larger in scale and have a shorter TAT (Turn Around Time). The behavioral synthesis method is a method for automatically generating a RTL (Register Transfer Level) circuit description from a circuit description at a high abstraction level such as ANSI-C, SystemC, or UML (Unified Modeling Language).

  There is no concept of register (holding of signal value), sharing of arithmetic unit, and time in the circuit description of the operation level. On the other hand, in the RTL circuit description, there are concepts of registers, sharing of arithmetic units, and time. When a designer manually designs an RTL circuit description, the concepts of register, computing unit sharing, and time are all determined and described by the designer.

  FIG. 1 is a diagram showing a design flow of RTL circuit description of manual design by a conventional designer.

  Based on the design specification p1, a design specification p2 and an operation level circuit description p3 are created. The design specification p1 is a summary of what kind of semiconductor integrated circuit is desired to be created. For example, the design specification p1 includes operating conditions, included functions, register specifications, and the like. The design specifications are further embodied, and what is described as a document or electronic data is the design specifications p2 and the circuit description p3 of the operation level. The circuit description p3 at the operation level is generally created for each function of the design specification p1 mainly for function verification.

  FIG. 2 is a diagram illustrating an example of the circuit description of the behavior level. The circuit description of the operation level shown in the figure is an example described in ANSI-C language. As is clear from the figure, there is basically no concept of the parallelism of operations and the time required for operations in the circuit description at the operation level.

  In a conventional RTL circuit description design by a designer, the designer analyzes and understands the design specification p2 and the operation level circuit description p3, and creates the RTL circuit description by hand design. For this reason, the designer can arbitrarily determine signal names and register names in the RTL circuit description.

  FIG. 3 is a diagram illustrating an example of RTL circuit description created by hand design. The circuit description in the figure is an example described using Verilog HDL. The circuit description of the RTL shown in the figure is functionally equivalent to the circuit description of the operation description shown in FIG. However, the RTL circuit description can describe the concept of parallelism and time. For example, in FIG. 3, the calculation of b + c and e + f is performed in the same cycle (parallelization), and the calculation of a * d is performed in the next cycle.

  On the other hand, according to the behavioral synthesis method, an RTL circuit description is generally automatically generated by a behavioral synthesis tool. FIG. 4 is a diagram showing a design flow of RTL circuit description using the behavioral synthesis method.

  The design specification p6 and the design specification p7 are the same as the design specification p1 or the design specification p2 in FIG. The behavioral level circuit description p8 is equivalent to the behavioral level circuit description p3 of FIG. However, there may be description restrictions depending on the behavioral synthesis tool used in behavioral synthesis p9, and a behavioral level circuit description p8 may be created separately for behavioral synthesis. In the behavioral synthesis p9, information on the behavioral level circuit description p8 and the design specification p7 is input to the behavioral synthesis tool, and an RTL circuit description p10 is generated by the behavioral synthesis tool. Since the behavioral synthesis method is a known technique, the details thereof are omitted. When the behavioral synthesis tool is used, the signal name and the register name in the circuit description p10 of the RTL are determined by the behavioral synthesis tool. Therefore, the signal or register name used in the circuit description p8 at the operation level and the signal or register name used in the circuit description p10 of the RTL basically do not match.

  FIG. 5 is a diagram illustrating an example of RTL circuit description generated by the behavioral synthesis method. The circuit description of the RTL shown in the figure is functionally equivalent to the circuit description of the operation description shown in FIG. The RTL circuit description shown in the figure is equivalent to the RTL circuit description shown in FIG. 3 except that the signal names are different.

  As described above, in the RTL circuit description generated by the behavioral synthesis method, the internal signal name or register name is determined by the behavioral synthesis tool and may be completely different from the behavioral level circuit description.

  The difference that occurs between the behavioral circuit description and the RTL circuit description by using the behavioral synthesis method will be described more specifically.

  FIG. 6 is a diagram illustrating an example of generating an RTL circuit description in which an operation is performed in two cycles by the behavioral synthesis method. In the example shown in the figure, the concept of time (clock) that is not at the operation level is introduced in the circuit description of the RTL.

  FIG. 7 is a diagram illustrating an example of generating an RTL circuit description in which an operation is performed in one cycle by a behavioral synthesis method. In the example shown in the figure, the signals a and d existing in the circuit description at the behavior level are not present in the RTL.

  FIG. 8 is a diagram illustrating an example in which a signal that does not exist in the behavioral circuit description appears in the RTL circuit description by the behavioral synthesis method. In the example shown in the drawing, a signal d1 that does not exist in the circuit description at the operation level is included in the circuit description of the RTL.

  FIG. 9 is a diagram illustrating an example in which an operation is converted into a state machine by a behavioral synthesis method and an example in which registers are shared. In the example shown in the figure, new signals (current_state, next_state) are added by creating a state machine. In addition, since the calculation of a = b * c and the calculation of d = e * f are not performed at the same time, the signal (register) a is shared between the case where the current_state is s1 and the case where s2.

  As described above, in the RTL circuit description output by the behavioral synthesis method, addition or deletion of signals not included in the behavioral description, calculation timing control (state machine), or sharing of registers (signals) may be performed. is there. As a result, the circuit is optimized, and effects such as reduction of the chip area and improvement of the processing speed can be obtained. However, the correspondence between the behavioral level and the circuit description of the RTL becomes difficult to understand, and the latter readability is lowered.

  For example, comparing FIG. 2 and FIG. 3, since the signal names are the same, the readability is high and debugging is easy. Comparing FIG. 2 and FIG. 5, it is difficult to distinguish at a glance whether the variable a in FIG. 2 is h or i in FIG. As a result, the readability of the RTL circuit description is reduced.

  The poor readability of the RTL circuit description generated by the behavioral synthesis method and the incompatibility of the correspondence with the behavioral level circuit description contribute to the spread of the behavioral synthesis method. It is thought that there is.

  Due to the poor readability of the RTL circuit description, the first problem is that the ease of debugging of the RTL circuit description generated by the behavioral synthesis technique is reduced. For example, when the logic verification pattern fails in the RTL circuit description generated by the behavioral synthesis method, the correspondence between the behavioral level source circuit description and the RTL circuit description generated by the behavioral synthesis method is determined. Is difficult. As a result, compared with the case where a circuit designer creates a circuit description of RTL by hand design, much man-hours are required for debugging.

  The second problem is that rework and man-hours when the design specifications are changed in the latter half of the design become very large. There is a method of performing behavioral synthesis again when the behavioral description is modified in the design specifications in the latter half of the design, and redoing all the steps after the behavioral synthesis step.

  FIG. 10 is a diagram showing a design flow using a general semiconductor integrated circuit behavioral synthesis method.

  From the determination of the design specification p11 to the creation of the mask data p20, five operations of a design specification p12 creation process, a behavioral synthesis process p14, a logic synthesis process p16, a DFT (Design For Test) process p18, and a layout process p19 There is a process.

  For example, when a specification change occurs in the layout process p19 and re-operational synthesis is performed, it is necessary to return to the behavioral synthesis process p14 and redo all of the logic synthesis process p16, the DFT process p17, and the layout process p19.

  Also, there is a method of analyzing the RTL circuit description generated by the behavioral synthesis method and finding the description corresponding to the corrected part of the behavioral level circuit description to correct the RTL circuit description. It takes a lot of man-hours due to poor readability of the circuit description. The same problem occurs in the RTL design flow by hand design. However, since the designer manually creates the RTL circuit description by hand, the correspondence between the specification change location and the RTL circuit description is not possible. Easy to understand. Therefore, analysis and correction can be performed in a much shorter time than the RTL design flow by the behavioral synthesis method.

  The present invention has been made in view of the above points, and provides a design support apparatus, a design support method, a design support program, and a method for manufacturing a semiconductor integrated circuit that can improve the readability of an RTL circuit description. With the goal.

  In order to solve the above-described problem, the present invention relates to behavioral synthesis means for generating a first RTL circuit description based on a behavioral level circuit description, and variables included in the first RTL circuit description. , A variable name is generated based on an arithmetic expression assigned to the variable or a variable name of a corresponding variable in the circuit description of the behavior level, and a variable name of the variable included in the circuit description of the first RTL Variable name generation means for recording correspondence information with the variable name generated for the variable in the storage means, the first RTL circuit description, and the variable name of the first RTL circuit description is the variable name generation means. Circuit description output means for outputting the second RTL circuit description replaced by the variable name generated by

  In such a design support apparatus, the readability of the RTL circuit description can be improved.

  According to the present invention, readability of an RTL circuit description can be improved.

It is a figure which shows the design flow of the circuit description of RTL of the hand design by the conventional designer. It is a figure which shows the example of the circuit description of a behavior level. It is a figure which shows the example of the circuit description of RTL produced by hand design. It is a figure which shows the design flow of the circuit description of RTL using the behavioral synthesis method. It is a figure which shows the example of the circuit description of RTL produced | generated by the behavioral synthesis method. It is a figure which shows the example which produced | generated the circuit description of RTL by which an operation is performed in 2 cycles with the behavioral synthesis method. It is a figure which shows the example which produced | generated the circuit description of RTL by which an operation is performed in 1 cycle with a behavioral synthesis method. It is a figure which shows the example which the signal which does not exist in the circuit description of a behavior level appears in the circuit description of RTL by the behavioral synthesis method. It is a figure which shows the example which made the state machine operation by the behavioral synthesis method, and the example where a register is shared. It is a figure which shows the design flow using the behavioral synthesis method of the general semiconductor integrated circuit. It is a figure which shows the hardware structural example of the design assistance apparatus in embodiment of this invention. It is a figure which shows the function structural example of the design assistance apparatus in embodiment of this invention. It is a figure for demonstrating an example of the process sequence of the production | generation process of the RTL circuit description which a design support apparatus performs. It is a figure which shows the example of correspondence information. It is a figure which shows the example of the RTL circuit description for debugging using the variable name of the 1st example. It is a figure which shows the example of the RTL circuit description for debugging using the variable name of the 2nd example. It is a figure which shows the example of the RTL circuit description for debugging using the variable name of the 3rd example. It is a figure which shows the method of grasping | ascertaining the correspondence of the RTL circuit description for debugging and the RTL circuit description for mounting based on the number of lines. It is a figure which shows the method of grasping | ascertaining the correspondence of the debugging RTL circuit description and the mounting RTL circuit description based on the appearance order of a variable.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 11 is a diagram illustrating a hardware configuration example of the design support apparatus according to the embodiment of the present invention. 11 includes a drive device 100, an auxiliary storage device 102, a memory device 103, a CPU 104, an interface device 105, a display device 106, and an input device, which are mutually connected by a bus B. 107.

  A program for realizing processing in the design support apparatus 10 is provided by a recording medium 101 such as a CD-ROM. When the recording medium 101 on which the program is recorded is set in the drive device 100, the program is installed from the recording medium 101 to the auxiliary storage device 102 via the drive device 100. However, the program need not be installed from the recording medium 101 and may be downloaded from another computer via a network. The auxiliary storage device 102 stores the installed program and also stores necessary files and data.

  The memory device 103 reads the program from the auxiliary storage device 102 and stores it when there is an instruction to start the program. The CPU 104 realizes functions related to the design support apparatus 10 according to a program stored in the memory device 103. The interface device 105 is used as an interface for connecting to a network. The display device 106 displays a GUI (Graphical User Interface) or the like by a program. The input device 107 includes a keyboard and a mouse, and is used for inputting various operation instructions.

  FIG. 12 is a diagram illustrating a functional configuration example of the design support apparatus according to the embodiment of the present invention. In the figure, the design support apparatus 10 includes a behavioral synthesis unit 121, a variable name generation unit 122, a correspondence information storage unit 123, a circuit description output unit 124, and the like. Each of these units is realized by processing executed by the CPU 104 by a program installed in the design support apparatus 10.

  The behavioral synthesis unit 121 generates an RTL (Register Transfer Level) circuit description by a behavioral synthesis method based on the design specification d1 and the behavioral level circuit description d2. The design specification d1 and the behavior level circuit description d2 are data generated based on the design specification of the semiconductor integrated circuit. The design specification is a summary of what kind of semiconductor integrated circuit is desired to be created. For example, the design specifications include operating conditions, functions included, register specifications, and the like. The design specifications are further embodied, and what is described as a document or electronic data is the design specifications d1 and the behavior level circuit description d2. The behavior level circuit description d2 is created for each function of the design specification mainly for function verification. The design specification d1 and the behavior level circuit description d2 are stored in the auxiliary storage device 102, for example.

  The variable name generation unit 122 relates to at least some of the variables included in the RTL circuit description generated by the behavioral synthesis unit 121, and the variable of the corresponding variable in the arithmetic expression or behavior level circuit description d2 assigned to the variable. A variable name based on the name is generated, and correspondence information 123A between the variable name included in the RTL circuit description and the variable name generated for the variable is recorded in the correspondence information storage unit 123. In the present embodiment, the variable name is a name given to a signal, a register, or the like in the circuit description. That is, the variable name is a generic name for the signal name or register name in the circuit description.

  The correspondence information storage unit 123 stores the correspondence information 123A using the auxiliary storage device 102, for example.

  The circuit description output unit 124 outputs (records) two RTL circuit descriptions, for example, the mounting RTL circuit description d3 and the debugging RTL circuit description d4, to the auxiliary storage device 102, for example. The circuit description output unit 124 outputs an unprocessed RTL circuit description generated by the behavioral synthesis unit 121 as a mounting RTL circuit description d3. The circuit description output unit 124 also includes a debug RTL circuit description in which variables included in the RTL circuit description generated by the behavioral synthesis unit 121 are replaced with variables generated by the variable name generation unit 122. Output as d4.

  Therefore, the mounting RTL circuit description d3 and the debugging RTL circuit description d4 basically have different variable names. That is, the variable name included in the mounting RTL circuit description d3 is arbitrarily given depending on the convenience or specification of the behavioral synthesis unit 121. On the other hand, the variable name included in the debug RTL circuit description d4 is generated using the variable name included in the behavior level circuit description d2. The mounting RTL circuit description d3 is an RTL circuit description generated for the purpose of being actually used in a later design process. The debug RTL circuit description d4 is an RTL circuit description generated for the purpose of debugging the RTL circuit description.

  Hereinafter, the processing procedure of the design support apparatus 10 will be described. FIG. 13 is a diagram for explaining an example of a processing procedure of RTL circuit description generation processing executed by the design support apparatus.

  For example, when a user inputs an RTL circuit description generation instruction via the input device 107, the behavioral synthesis unit 121 reads the behavior level circuit description d2 and the design specification d1 into the memory device 103 (S101). Subsequently, the behavioral synthesis unit 121 generates a mounting RTL circuit description d3 in the memory device 103 based on the read behavior level circuit description d2 and the design specification d1 (S102). The generation logic of the mounting RTL circuit description d3 may be the same as a known behavioral synthesis tool.

  Subsequently, the variable name generation unit 122 generates a variable name for the variable included in the mounting RTL circuit description d3 based on the corresponding variable name in the arithmetic expression or behavior level circuit description d2 assigned to the variable. (S103). Details of the generated variable names will be described later. Since the behavioral synthesis unit 121 generates the mounting RTL circuit description d3 based on the behavioral level circuit description d2, it recognizes the correspondence between the variables in the behavioral level circuit description d2 and the variables in the mounting RTL circuit description d3. ing. Therefore, based on the recognition by the behavioral synthesis unit 121, the variable name generation unit 122 grasps the correspondence between the two and generates a variable name.

  Subsequently, the variable name generation unit 122 generates correspondence information 123A between the variable name of the variable in the RTL circuit description and the variable name generated for the variable, and the generated correspondence information 123A is stored in the correspondence information storage unit 123. Record (S104).

  FIG. 14 is a diagram illustrating an example of the correspondence information 123A. This figure shows correspondence information 123A between the debugging RTL circuit description d4 and the mounting RTL circuit description d3.

  The correspondence information 123A is information for holding a correspondence between the variable name of the debugging RTL circuit description d4 and the variable name of the mounting RTL circuit description d3. In the example of FIG. 14, the left side of the equal sign (=) is the variable name of the debugging RTL circuit description d4, and the right side is the variable name of the mounting RTL circuit description d3. In this case, the variable name on the left side and the variable name on the right side correspond to each other (being for the same signal or register).

  Specifically, n__b_c in the debugging RTL circuit description d4 and x of the mounting RTL circuit description d3, n__e_f in the debugging RTL circuit description d4, y of the mounting RTL circuit description d3, and the debugging RTL circuit description d4 Each of n_b_c_e_f and z of the mounting RTL circuit description d3 corresponds to each other.

  The correspondence information 123A shown in FIG. 14 is merely an example. Accordingly, the format of the correspondence information 123A is not limited to connecting the variable name in the debugging RTL circuit description d4 and the variable name in the mounting RTL circuit description d3 with an equal sign (=). For example, the right side and the left side may be interchanged. The equal sign may be replaced by other characters such as a space or a colon. Furthermore, the correspondence information 123A may not be generated as an ASCII file.

  Subsequently, the circuit description output unit 124 generates a copy of the mounting RTL circuit description d3 in the memory device 103, and sets the variable name included in the copy to the correspondence information 123A stored in the correspondence information storage unit 123. On the basis of the variable name generated by the variable name generation unit 122. As a result, the debugging RTL circuit description d4 is generated in the memory device 103 (S105).

  Subsequently, the circuit description output unit 124 outputs the mounting RTL circuit description d3 and the debugging RTL circuit description d4 to the auxiliary storage device 102 (S106).

  In the above description, the debug RTL circuit description d4 is generated by replacing the variable name with respect to the copy of the mounting RTL circuit description d3. However, the mounting RTL circuit description d3 and the debugging RTL circuit description d4 may be generated in parallel by the behavioral synthesis unit 121. In this case, the behavioral synthesis unit 121 assigns the variable name of the behavior level circuit description d2 or the variable name to the variable name generation unit 122 each time a variable name is assigned to the mounting RTL circuit description d3. The arithmetic expression including the variable name of the variable of the mounting RTL circuit description d3 corresponding to the variable or the arithmetic expression including the variable name may be input. The variable name generation unit 122 generates a variable name of the variable of the debugging RTL circuit description d4 corresponding to the input variable of the mounting RTL circuit description d3 based on the input variable name or the arithmetic expression, The data is output to the combining unit 121. The behavioral synthesis unit 121 generates a debugging RTL circuit description d4 in parallel with the mounting RTL circuit description d3 using the output variable name.

  In the subsequent steps, debugging is performed using the debugging RTL circuit description d4. Further, the mounting RTL circuit description d3 is used for the actual manufacture of the semiconductor integrated circuit. That is, a circuit is created on the semiconductor substrate based on the mounting RTL circuit description d3 and the like.

  Next, an example of variable names generated by the variable name generation unit 122 will be described. Here, it is assumed that the contents of the behavior level circuit description d2 are as shown in FIG.

  In the first example, the variable name generation unit 122 sets the variable name for the operation level as much as possible for the debug RTL circuit description d4.

  As a result, the debug RTL circuit description d4 based on the behavior level circuit description d2 having the contents of FIG. 2 is as shown in FIG. 15, for example.

  FIG. 15 is a diagram illustrating an example of the debugging RTL circuit description d4 using the variable names of the first example.

  In the example shown in the figure, the variable name of the behavior level circuit description d2 is used as it is. As a result, comparison with the behavior level circuit description d2 is facilitated. That is, the readability is improved. For the mounting RTL circuit description d3, there is no restriction on the variable name, so the content as shown in FIG. 5 is output, for example.

  Next, a second example will be described. FIG. 16 is a diagram illustrating an example of the debug RTL circuit description d4 using the variable names of the second example. The debugging RTL circuit description d4 shown in the figure is also based on the behavior level circuit description d2 having the contents of FIG.

  In FIG. 16, variable names not included in the behavior level circuit description d2, such as h_b_plus_c and j_h_multi_i, are included. The variable name h__b_plus_c has a meaning before and after two consecutive underscores (__). Before the two consecutive underscores (__) is a variable name uniquely determined by the behavioral synthesis unit 121 (for example, a variable name output to the mounting RTL circuit description d3). After the two consecutive underscores (__), the variable name generation unit 122 generates a variable based on which variable indicates the operation result of which variable. . That is, the variable name of the variable is generated by combining (connecting) the variable name constituting the arithmetic expression assigned to the variable and the character string indicating the operator.

  Specifically, in h_b_plus_c, h is a variable name determined by the behavioral synthesis unit 121. b_plus_c is generated by the variable name generation unit 122 based on the arithmetic expression b + c. Similarly, in i_e_plus_f, i is a variable name determined by the behavioral synthesis unit 121. e_plus_f is generated by the variable name generation unit 122 based on an arithmetic expression e + f. In j__h_multi_j, j is a variable name determined by the behavioral synthesis unit 121. h_multi_j is generated by the variable name generation unit 122 based on an arithmetic expression h__b_plus_c * i__e_plus_f.

  Note that this example is an example, and other characters may be used as the delimiter. Other characters may be used as long as the name indicating the operation can be distinguished.

  According to the second example, the variable name of the behavior level circuit description d2 and the variable name of the debug RTL circuit description d4 do not necessarily match. However, just by looking at the variable name, the variable name is assigned to which variable. It is possible to determine what calculation result is to be stored. As a result, the readability of the debug RTL circuit description d4 can be improved.

  Next, a third example will be described. FIG. 17 is a diagram illustrating an example of the debug RTL circuit description d4 using the variable names of the third example. The debugging RTL circuit description d4 shown in the figure is also based on the behavior level circuit description d2 having the contents of FIG.

  In the example of the figure, the variable name starts with n__. The character string after n__ is generated by the variable name generation unit 122 by combining (connecting) the variable names included in the arithmetic expression assigned to the variable.

  For example, the variable name n__b_c indicates that an arithmetic expression including the variable b and the variable c is substituted. If the variable name that is the assignment source is known, it is easy to specify that the variable to which both b and c are related at the operation level is a.

  This example is an example, and the prefix character string may not be n__. Also, other characters may be used as delimiters.

  According to the third example, the variable name of the behavior level circuit description d2 and the variable name of the debugging RTL circuit description d4 do not necessarily match, but by just looking at the variable name, the variable name is assigned to which variable. It is possible to determine whether or not to store a calculation result based on it. As a result, the readability of the debug RTL circuit description d4 can be improved.

  As described above, according to the present embodiment, both the mounting RTL circuit description d3 and the debugging RTL circuit description d4 are generated, and the readability is improved only for the debugging RTL circuit description d4. Processing is applied. For example, the variable name included in the behavior level circuit description d2 and the variable name based on the arithmetic expression are intentionally included in the debug RTL circuit description d4. As a result, the readability of the RTL circuit description can be improved by using the debug RTL circuit description d4 for debugging. On the other hand, regarding the mounting, an increase in memory consumption can be suppressed by using the mounting RTL circuit description d3. That is, in order to improve readability, variable names tend to be longer. If the variable name becomes long, the amount of memory consumption increases, which may lead to a shortage of memory and an increase in execution time in the subsequent process. Therefore, in the subsequent process, by using the mounting RTL circuit description d3, it is possible to avoid the occurrence of such inconveniences (side effects associated with improved readability).

  Further, since the correspondence information 123A is output, it is possible to make debugging work and the like more efficient using the correspondence information 123A. For example, when debugging is performed using the debugging RTL circuit description d4 and the result is reflected in the mounting RTL circuit description d3, the correction location in the mounting RTL circuit description d3 can be easily determined based on the correspondence information 123A. Can be identified. As a result, it is possible to reduce the number of rework steps.

  As described above, according to the present embodiment, the readability of the RTL circuit description generated by the behavioral synthesis method can be improved, and debugging can be facilitated and the response to the design specification change can be facilitated. .

  Note that the correspondence between the debugging RTL circuit description d4 and the mounting RTL circuit description d3 can be performed based on the number of lines of both.

  FIG. 18 is a diagram illustrating a method of grasping the correspondence between the debug RTL circuit description and the mounting RTL circuit description based on the number of lines.

  Since the difference between the debugging RTL circuit description d4 and the mounting RTL circuit description d3 is basically a variable name, there is a high possibility that the same function is expressed in the same line. Therefore, when a line that needs to be corrected is found using the debugging RTL circuit description d4, the correction portion in the mounting RTL circuit description d3 may be specified based on the number of lines in the line. For example, when it is found that the correction is required on the 18th line of the debugging RTL circuit description d4, the correction may be performed on the 18th line of the mounting RTL circuit description d3.

  Further, the correspondence between the debug RTL circuit description d4 and the mounting RTL circuit description d3 may be achieved based on the order in which the variables appear.

  FIG. 19 is a diagram showing a method of grasping the correspondence between the debug RTL circuit description and the mounting RTL circuit description based on the order of appearance of variables.

  Since the difference between the debugging RTL circuit description d4 and the mounting RTL circuit description d3 is basically a variable name, the appearance order of variables for the same signal or register is basically the same. Therefore, when a variable that needs to be corrected is found in the debugging RTL circuit description d4, the correction location of the mounting RTL circuit description d3 may be specified based on the appearance order of the variable. For example, in the figure, n__b_c of the debug RTL circuit description d4 corresponds to x of the mounting RTL circuit description d3 because it is the left side of the multiplication (*).

  As described above, even when the correspondence information 123A is not used, when the debug operation is performed based on the debug RTL circuit description d4 and the correction portion becomes clear, the correction portion of the mounting RTL circuit description d3 can be specified. it can. However, by using the correspondence information 123A, it is possible to grasp the correspondence between the two more easily.

  As mentioned above, although the Example of this invention was explained in full detail, this invention is not limited to such specific embodiment, In the range of the summary of this invention described in the claim, various deformation | transformation・ Change is possible.

DESCRIPTION OF SYMBOLS 10 Design support apparatus 100 Drive apparatus 101 Recording medium 102 Auxiliary storage apparatus 103 Memory apparatus 104 CPU
105 interface device 106 display device 107 input device 121 behavior synthesis unit 122 variable name generation unit 123 correspondence information storage unit 124 circuit description output unit B bus d1 design specification d2 behavior level circuit description d3 mounting RTL circuit description d4 debugging RTL circuit Description

JP 2007-27267 A JP 2006-285333 A

Claims (10)

Behavioral synthesis means for generating a first RTL circuit description based on the behavioral level circuit description;
For a variable included in the circuit description of the first RTL, a variable name is generated based on an arithmetic expression assigned to the variable or a variable name of a corresponding variable in the circuit description of the behavior level, and the first Variable name generation means for recording, in a storage means, correspondence information between variable names of variables included in the RTL circuit description and variable names generated for the variables;
Circuit description output means for outputting the circuit description of the first RTL and the second RTL circuit description in which the variable name of the first RTL circuit description is replaced by the variable name generated by the variable name generation means And a design support apparatus.   The design support apparatus according to claim 1, wherein the variable name generation unit generates a variable name by combining variable names constituting the arithmetic expression.   The design support apparatus according to claim 2, wherein the variable name generation unit generates a variable name by combining character strings indicating operators constituting the arithmetic expression. A behavioral synthesis procedure for generating a first RTL circuit description based on the behavioral level circuit description;
For a variable included in the circuit description of the first RTL, a variable name is generated based on an arithmetic expression assigned to the variable or a variable name of a corresponding variable in the circuit description of the behavior level, and the first A variable name generation procedure for recording correspondence information between a variable name included in the RTL circuit description and a variable name generated for the variable in a storage unit;
Circuit description output procedure for outputting the first RTL circuit description and the second RTL circuit description in which the variable name of the first RTL circuit description is replaced by the variable name generated in the variable name generation procedure Design support method in which the computer executes.   The design support method according to claim 4, wherein the variable name generation procedure generates a variable name by combining variable names constituting the arithmetic expression.   The design support method according to claim 5, wherein the variable name generation procedure generates a variable name by combining character strings indicating operators constituting the arithmetic expression. A behavioral synthesis procedure for generating a first RTL circuit description based on the behavioral level circuit description;
For a variable included in the circuit description of the first RTL, a variable name is generated based on an arithmetic expression assigned to the variable or a variable name of a corresponding variable in the circuit description of the behavior level, and the first A variable name generation procedure for recording correspondence information between a variable name included in the RTL circuit description and a variable name generated for the variable in a storage unit;
Circuit description output procedure for outputting the first RTL circuit description and the second RTL circuit description in which the variable name of the first RTL circuit description is replaced by the variable name generated in the variable name generation procedure Design support program that causes a computer to execute.   The design support program according to claim 7, wherein the variable name generation procedure generates a variable name by combining variable names constituting the arithmetic expression.   The design support program according to claim 8, wherein the variable name generation procedure generates a variable name by combining character strings indicating operators constituting the arithmetic expression. A semiconductor integrated circuit manufacturing method for manufacturing a semiconductor integrated circuit using a semiconductor integrated circuit design support method executed by a computer,
The design support method includes:
A behavioral synthesis procedure for generating a first RTL circuit description based on the behavioral level circuit description;
For a variable included in the circuit description of the first RTL, a variable name is generated based on an arithmetic expression assigned to the variable or a variable name of a corresponding variable in the circuit description of the behavior level, and the first A variable name generation procedure for recording correspondence information between a variable name included in the RTL circuit description and a variable name generated for the variable in a storage unit;
Circuit description output procedure for outputting the first RTL circuit description and the second RTL circuit description in which the variable name of the first RTL circuit description is replaced by the variable name generated in the variable name generation procedure A method for manufacturing a semiconductor integrated circuit.

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