JP2012058664A - Light-emitting panel, and manufacturing method of light-emitting panel - Google Patents

Abstract

An object of the present invention is to reduce the disconnection at the intersection with the lower wiring of the upper wiring and improve the yield.
A lower wiring Ld formed on an upper portion of a substrate 2, an insulating layer 31 covering the lower wiring Ld, and an upper wiring La formed on the insulating layer 31 so as to intersect the lower wiring Ld. The light emitting panel 10 includes pixel transistors 11 to 13 connected to the lower wiring Ld and the upper wiring La, and an organic EL element 40 to which power is supplied by the pixel transistors 11 to 13. A protrusion along the lower wiring Ld is formed on the upper surface of the insulating layer 31 and above the lower wiring Ld, and the width of the upper wiring La changes at least on the inclined surface 31B of the protrusion.
[Selection] Figure 8

Description

  The present invention relates to a light emitting panel and a method for manufacturing the light emitting panel.

  An organic electroluminescence element (organic EL element) has a laminated structure in which, for example, an electron injection layer, a light emitting layer, and a hole injection layer are interposed between a cathode electrode and an anode electrode. When a forward bias voltage is applied between the anode electrode and the cathode electrode, electrons are injected from the electron injection layer into the light emitting layer, holes are injected from the hole injection layer into the light emitting layer, and electrons and positive ions are injected into the light emitting layer. The holes cause recombination and the light emitting layer emits light.

  The light emitting layer and the hole injection layer are made of an organic compound, and are formed by applying an organic compound solution obtained by dissolving these materials in a solvent onto the electrode of each pixel and drying it. In color displays, in order to prevent color mixing, a partition is formed between adjacent pixels to prevent mixing of organic compound solutions.

  In an active matrix organic EL display panel, a switching element is disposed in each pixel, and a scanning line, a signal line, a common power line, and the like that are disposed vertically and horizontally are connected to the switching element, and the organic element provided in each pixel The current supplied to the EL element is controlled (see, for example, Patent Document 1).

JP 2007-234391 A

  By the way, the wiring such as the scanning line connected to the switching element or the common power supply line intersects with the wiring such as the scanning line through the insulating film, and the upper wiring and the wiring due to the step of the insulating film due to the thickness of the lower wiring. Adhesion with the insulating film is reduced. Then, a developer or a stripping solution for photoresist for patterning the metal layer serving as the upper wiring may permeate from the boundary line between the upper wiring and the insulating film, and the yield may be reduced due to disconnection.

  It is an object of the present invention to reduce the disconnection at the intersection with the lower wiring of the upper wiring and to improve the yield.

  In order to solve the above problems, according to an aspect of the present invention, a first wiring formed on an upper portion of a substrate, the first wiring and a peripheral region of the first wiring are covered, and the first wiring An insulating layer having an inclined surface from the upper part to the upper part of the peripheral region, and formed on the upper part of the insulating layer so as to intersect the first wiring, and in the inclined surface, the width from the upper part of the first wiring to the upper part of the peripheral region And a second wiring formed so as to be gradually narrowed. A light-emitting panel is provided.

It is preferable that the width of the second wiring is gradually changed above the side surface of the first wiring.
Preferably, the pixel transistor includes a pixel transistor connected to the first wiring and the second wiring, and a light emitting element to which power is supplied by the pixel transistor.
The first wiring is preferably formed of a metal layer common to the gate electrode of the pixel transistor, and the second wiring is formed of a metal layer common to the source / drain electrodes of the pixel transistor.

  According to another aspect of the present invention, the first wiring is formed on the substrate, covers the first wiring and the peripheral area of the first wiring, and is inclined from the upper part of the first wiring to the upper part of the peripheral area. Forming an insulating layer, and intersecting the first wiring on the insulating layer, and forming the second wiring so that the width gradually decreases from the top of the first wiring to the top of the peripheral region on the inclined surface. A method for manufacturing a light emitting panel is provided.

  It is preferable to form a pixel transistor connected to the first wiring and the second wiring and a light emitting element to which power is supplied by the pixel transistor.

  According to the present invention, it is possible to reduce the disconnection at the intersection with the lower wiring of the upper wiring and improve the yield.

1 is a schematic plan view of an organic EL display panel 10. FIG. 3 is a circuit diagram of one pixel PX in the organic EL display panel 10. FIG. It is a top view which shows one pixel PX. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3. It is a VV arrow sectional view of Drawing 3. FIG. 6 is a cross-sectional view taken along the line VI-VI in FIG. 3. It is a VII-VII arrow sectional view of Drawing 1. FIG. 4 is a schematic perspective view for illustrating a positional relationship between a signal line Ld and a common power supply line La intersecting in a portion VIII in FIG. 3. It is IX arrow line view of FIG. It is sectional drawing for demonstrating the manufacturing process of the organic electroluminescent display panel 10 in the same cross section as FIG. It is sectional drawing for demonstrating the manufacturing process of the organic electroluminescent display panel 10 in the same cross section as FIG. It is sectional drawing for demonstrating the manufacturing process of the organic electroluminescent display panel 10 in the same cross section as FIG. It is sectional drawing for demonstrating the manufacturing process of the organic electroluminescent display panel 10 in the same cross section as FIG. It is sectional drawing for demonstrating the manufacturing process of the organic electroluminescent display panel 10 in the same cross section as FIG. It is sectional drawing for demonstrating the manufacturing process of the organic electroluminescent display panel 10 in the same cross section as FIG. It is sectional drawing for demonstrating the manufacturing process of the organic electroluminescent display panel 10 in the same cross section as FIG. It is sectional drawing for demonstrating the manufacturing process of the organic electroluminescent display panel 10 in the same cross section as FIG.

  The best mode for carrying out the present invention will be described below with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples. Further, in the following description, the term electroluminescence is abbreviated as EL.

  FIG. 1 is a schematic plan view of an organic EL display panel 10 according to the first embodiment of the present invention. In the organic EL display panel 10, red, blue, and green pixels PX form one dot pixel, and such pixels are arranged in a matrix form over the entire display area. When attention is paid to the horizontal arrangement in FIG. 1, red pixels PX, blue pixels PX, and green pixels PX are repeatedly arranged in this order. When attention is paid to the vertical arrangement in FIG. 1, the same colors are arranged in a line.

In the organic EL display panel 10, a plurality of signal lines Ld, scanning lines Ls, and a common power supply line La are provided in order to output various signals to the pixels PX. The scanning line Ls and the signal line Ld extend in directions orthogonal to each other. In FIG. 1, the signal line Ld extends in the vertical direction, and the scanning line Ls and the common power supply line La extend in the horizontal direction.
Terminals PLd, PLs, and PLa are provided at the ends of the signal line Ld, the scanning line Ls, and the common power supply line La, respectively. Further, a cathode PL terminal PLc common to the pixels PX is provided.

  FIG. 2 is a circuit diagram of switching elements in one pixel PX of the organic EL display panel 10. The pixel PX includes a pixel circuit PC and an organic EL element 40 having three n-channel transistors 11, 12, 13 and a capacitor CS. The three n-channel transistors 11, 12, 13 and the capacitor CS supply the power supplied from the common power supply line La to the organic EL element 40 in accordance with the input signals of the signal line Ld and the scanning line Ls.

  3 is a plan view showing one pixel PX, FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3, FIG. 5 is a cross-sectional view taken along arrow V-V in FIG. 3, and FIG. 3 is a sectional view taken along the arrow VI-VI in FIG. 3, and FIG. 7 is a sectional view taken along the arrow VII-VII in FIG. The vertical and horizontal directions in FIGS. 1 and 3 correspond to each other.

As shown in FIGS. 3 to 7, the first electrode CS <b> 1 of the capacitor CS is provided on the transparent insulating substrate 2. The first electrode CS1 is made of a transparent conductive film. Such a first electrode CS1 is, for example, tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO) or cadmium-tin oxide. An object (CTO) can be formed and patterned by using a photolithography method and an etching method.

On the insulating substrate 2, gate electrodes 11G, 12G, 13G of the transistors 11, 12, 13 and a signal line Ld are provided. As shown in FIG. 3, the gate electrodes 11G and 12G are integrally formed. Further, as shown in FIGS. 3 and 4, the gate electrode 13G is formed so as to partially overlap the first electrode CS1.
The gate electrodes 11G, 12G, and 13G and the signal line Ld are formed by patterning a metal thin film (gate metal) such as Al, AlTi, AlTiNd, or MoNb.

The gate electrodes 11G, 12G, and 13G, the first electrode CS1, and the signal line Ld are covered with a common gate insulating film 31. The gate insulating film 31 can be formed by depositing an inorganic insulator such as SiO ₂ , SiN, or SiON by a CVD method or a sputtering method.

  As shown in FIG. 4, a contact hole 31a is formed in the gate insulating film 31 at a portion above the first electrode CS1 and overlapping the source electrode 11S of the transistor 11. Further, as shown in FIG. 5, a contact hole 31b is formed in a portion overlapping the drain electrode 12D of the transistor 12 above the signal line Ld. Similarly, as shown in FIG. 3, a contact hole 31 c is formed in the portion above the gate electrode 12 </ b> G of the transistor 12 and overlapping the scanning line Ls.

  As shown in FIGS. 3 to 7, a semiconductor film 21, a channel protective film 22, and an n-type semiconductor film 23 are sequentially formed on the upper surface of the gate insulating film 31. On the upper surface of the n-type semiconductor film 23, source electrodes 11S, 12S, 13S and drain electrodes 11D, 12D, 13D, scanning lines Ls, and a common power supply line La of the transistors 11, 12, 13 are provided. The source electrodes 11S, 12S, and 13S, the drain electrodes 11D, 12D, and 13D, the scanning line Ls, and the common power supply line La are made of a common metal layer (drain metal).

  The semiconductor film 21 is formed above the source electrodes 11S, 12S, 13S, the drain electrodes 11D, 12D, 13D, the scanning line Ls, the common power supply line La, and the gate electrodes 11G, 12G, 13G. Yes. The semiconductor film 21 is formed by patterning amorphous silicon (a-Si) or the like.

The channel protective film 22 is formed above the semiconductor film 21 and above the gate electrodes 11G, 12G, and 13G. The channel protective film 22 is formed by patterning an inorganic insulator such as SiO ₂ , SiN, or SiON.
The n-type semiconductor film 23 is formed on the upper surface of the semiconductor film 21 and is provided so as to partially overlap the channel protective film 22.

  The common power supply line La is formed in the horizontal direction between the pixel electrodes 41 arranged in a matrix. The common power supply line La is formed integrally with the drain electrodes 11D and 13D of the transistors 11 and 13. The drain electrodes 11D and 13D are formed so as to partially overlap the gate electrodes 11G and 13G.

  The scanning line Ls is formed between the pixel electrodes 41 arranged in a matrix in the horizontal direction in parallel with the common power supply line La. A part of the scanning line Ls is formed at a position where the gate electrode 12G overlaps. A part of the scanning line Ls is formed in the contact hole 31c, whereby the scanning line Ls and the gate electrode 12G are electrically connected.

  FIG. 8 is a schematic perspective view for illustrating the positional relationship between the signal line Ld and the common power supply line La intersecting in the section VIII of FIG. 3, and FIG. 9 is a view taken along arrow IX of FIG. As shown in FIGS. 8 and 9, the gate insulating film 31 covers the signal line Ld provided on the upper portion of the insulating substrate 2. A common power supply line La is provided above the gate insulating film 31 so as to intersect the signal line Ld.

As shown in FIGS. 8 and 9, the gate insulating film 31 is raised along the portion where the signal line Ld is present at the lower portion. The gate insulating film 31 is generally continuous from the flat surface 31A without the signal line Ld to the flat surface 31C on the signal line Ld by the inclined surface 31B, and along the signal line Ld by the inclined surface 31B and the flat surface 31C. A ridge is formed. The inclined surface 31B may be a curved surface continuous with the flat surface 31A and the flat surface 31C.
The common power supply line La is continuously formed on the flat surface 31A, the inclined surface 31B, and the flat surface 31C so as to get over the raised portion of the gate insulating film 31.

As shown in FIG. 8, the common power supply line La is formed wider on the flat surface 31C than on the flat surface 31A. For this reason, the common power line La has a narrower width on the flat surface 31A side and a wider width on the flat surface 31C side on the inclined surface 31B.
Further, the common power supply line La starts to widen from the front of the inclined surface 31B in the direction from the flat surface 31A to the inclined surface 31B. For this reason, as shown in FIGS. 8 and 9, the length of the signal line Ld in the width direction of the portion where the width of the common power supply line La changes is longer than the width of the protrusion.
Further, the common power supply line La starts to become narrower from the front of the inclined surface 31B in the direction from the flat surface 31C to the inclined surface 31B. For this reason, as shown in FIGS. 8 and 9, the length in the width direction of the signal line Ld of the widest portion of the common power supply line La is shorter than the width of the signal line.
A crossing portion between the signal line Ld and the scanning line La has a similar structure.

  Here, when the width of the common power supply line La (or the scanning line Ls) is uniform, the common power supply line La (or the scanning line Ls) and the gate are caused by the step of the gate insulating film 31 depending on the thickness of the signal line Ld. The gradient of the boundary line with the insulating film 31 becomes steep, and the adhesion with the gate insulating film 31 decreases. That is, when the width of the common power supply line La (or the scanning line Ls) is uniform, the gradient of the boundary line between the common power supply line La (or the scanning line Ls) and the gate insulating film 31 (between the boundary line and the horizontal plane). The angle between them coincides with the inclination (inclination angle) of the gate insulating film 31. Then, a developing solution or a photoresist stripping solution for patterning the metal layer (drain metal layer) serving as the scanning line Ls and the common power supply line La is soaked from the boundary line with the gate insulating film 31 and disconnected. As a result, the yield may decrease.

  On the other hand, in the present embodiment, as shown in FIG. 8, the portion where the width of the common power supply line La (or the scanning line Ls) changes follows the inclined surface 31 </ b> B of the gate insulating film 31. For this reason, the common power supply line La (or the scanning line Ls) and the gate insulating film 31 can be compared with the case where the common power supply line La (or the scanning line Ls) is made to follow the inclined surface 31B by a portion having a uniform width. The gradient of the boundary line becomes gentle. That is, in this embodiment, the gradient of the boundary line between the common power supply line La (or the scanning line Ls) and the gate insulating film 31 (the angle between the boundary line and the horizontal plane) is the inclination (tilt) of the gate insulating film 31. Smaller than the angle). Therefore, the adhesion with the gate insulating film 31 is improved and the yield is improved.

The source electrode 11S is formed so that one end overlaps the gate electrode 11G and the other end overlaps the first electrode CS1. As shown in FIG. 4, the source electrode 11S is electrically connected to the first electrode CS1 by forming a part of the source electrode 11S in the contact hole 31a.
The drain electrode 12D is formed so as to partially overlap the signal line Ld. As shown in FIG. 5, the drain electrode 12D is electrically connected to the signal line Ld by forming a part of the drain electrode 12D in the contact hole 31b.

The source electrodes 12S and 13S are formed so as to partially overlap the gate electrodes 12G and 13G.
Over the source electrodes 12S and 13S, the second electrode CS2 of the capacitor CS is formed so as to partially overlap. The second electrode CS2 also serves as the pixel electrode 41 of the organic EL element 40.

The pixel electrode 41 is formed by patterning a transparent conductive film using a photolithography method and an etching method. Examples of such conductive films include tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), or cadmium-tin oxide. A thing (CTO) can be used.
The pixel electrode 41 of the organic EL element 40 also serves as the second electrode CS2 of the capacitor CS, and is arranged in a matrix.

The semiconductor film 21, the channel protective film 22, the n-type semiconductor film 23, the source electrodes 11S, 12S, 13S, the drain electrodes 11D, 12D, 13D, the second electrode CS2 (pixel electrode 41), the scanning line Ls, and the common power line La These are covered with a common interlayer insulating film 32. The interlayer insulating film 32 can be formed by depositing an inorganic insulator such as SiO ₂ , SiN, or SiON by a CVD method or a sputtering method.

  Further, as shown in FIGS. 4 and 6, an opening 33 is formed in the interlayer insulating film 32 to expose at least a part of the pixel electrode 41. By forming the opening 33, the interlayer insulating film 32 is formed in a mesh shape so as to sew between the pixel electrodes 41 and overlaps with a part of the outer edge of the pixel electrode 41 to surround the pixel electrode 41.

The outer edge of the pixel electrode 41, the scanning line Ls, and the auxiliary common power supply line sLa are covered with a common interlayer insulating film 32.
The stacked structure from the insulating substrate 2 to the interlayer insulating film 32 is the transistor array panel 100.

A mesh-like partition wall 6 is formed on the interlayer insulating film 32. At least a part of the pixel electrode 41 is exposed from the opening 8 of the partition wall 6.
The partition wall 6 is made of, for example, a positive photosensitive resin such as polyimide, and is sufficiently thicker than the electrodes of the transistors 11, 12, and 13, the signal line Ld, the scanning line Ls, and the common power supply line La. . The partition wall 6 is formed by applying a photosensitive resin on the transistor array panel 100 and patterning it using a photomask.

  A hole injection layer 42 is provided on the pixel electrode 41 and the partition 6 exposed from the opening 8 and the opening 33. The hole injection layer 42 has a function of injecting holes from the pixel electrode 41 toward the carrier transport layer 43. The hole injection layer 42 can be formed by sputtering a transition metal oxide such as molybdenum oxide, vanadium oxide, tungsten oxide, titanium oxide, or the like. In particular, molybdenum oxide is preferable.

  A carrier transport layer 43 and a light emitting layer 44 are formed in this order in the opening 8 and the opening 33 above the hole injection layer 42. The carrier transport layer 43 is made of PEDOT as a conductive polymer and PSS as a dopant, and the light emitting layer 44 is made of a conjugated polymer such as a polyphenylene vinylene light emitting material or a polyfluorene light emitting material. When the subpixel is red, the light emitting layer 44 emits red light. When the subpixel is green, the light emitting layer 44 emits green light. When the subpixel is blue, the light emitting layer 44 emits blue light. So set each material. The laminated structure of the carrier transport layer 43 and the light emitting layer 44 is an organic EL layer.

  The carrier transport layer 43 and the light emitting layer 44 are formed by a wet coating method (for example, an ink jet printing method). In this case, an organic compound-containing liquid containing PEDOT and PSS that becomes the carrier transport layer 43 is applied to the pixel electrode 41 to form a film, and then an organic compound-containing liquid containing a conjugated polymer light-emitting material that becomes the light-emitting layer 44 is formed. Apply and form a film. Since the thick partition walls 6 are provided, it is possible to prevent the organic compound-containing liquid applied to the adjacent pixel electrodes 41 from being mixed beyond the partition walls 6.

  An electron transport layer may be further provided on the light emitting layer 44. The organic EL layer may have a two-layer structure including a light emitting layer and an electron transport layer formed on the pixel electrode 41, and the combination of the carrier transport layer and the light emitting layer can be arbitrarily set. Further, in these layer structures, a laminated structure in which an interlayer that restricts carrier transport between appropriate layers may be interposed, or another laminated structure may be used.

  Above the hole injection layer 42 where the carrier transport layer 43 and the light emitting layer 44 are not formed, and above the light emitting layer 44, the electron injection layer 45 serving as a part of the cathode C of the organic EL element 40 was solid. The film is formed on one side. The electron injection layer 45 is made of a material having a work function lower than that of the pixel electrode 41. For example, the electron injection layer 45 is made of at least one of alkali metals or alkaline earth metals such as indium, magnesium, calcium, lithium, and barium, or rare earth metals. It is formed to a thickness of 1 to 10 nm from a simple substance or an alloy containing it. Alternatively, the electron injection layer 45 may have a stacked structure in which layers of the above various materials are stacked.

On the top of the electron injection layer 45, for example, a counter electrode (second electrode) that becomes a part of the cathode C formed by vapor phase deposition of a conductive material such as aluminum, chromium, silver, or a palladium-silver alloy. 46 is formed.
The organic EL element 40 is formed by sequentially laminating the pixel electrode 41, the hole injection layer 42, the organic EL layer (carrier transport layer 43 and light emitting layer 44), the electron injection layer 45, and the counter electrode 46.

  As shown in FIG. 7, the counter electrode 46 is formed on the gate insulating film 31 on the gate insulating film 31 through the contact hole 32 e provided in the interlayer insulating film 32 in the outer peripheral portion of the transistor array panel 100. 23 is connected to the wiring 26 formed through the wiring 23. The wiring 26 is made of a metal layer common to the source electrodes 11S, 12S, and 13S, the drain electrodes 11D, 12D, and 13D, the scanning line Ls, and the common power supply line La.

The wiring 26 is connected to a pad layer 14P formed on the insulating substrate 2 through a contact hole 31d formed in the gate insulating film 31. The pad layer 14P is formed by patterning the gate metal in the same manner as the gate electrodes 11G, 12G, and 13G and the signal line Ld.
Further, the wiring 26 is connected to the pad layer 39 through a contact hole 32f formed in the interlayer insulating film 32 in the contact hole 31d. The pad layer 39 is made of, for example, an alloy containing at least Al, such as Al, AlTi, AlTiNd, copper or silver, and an alloy containing copper or silver. For example, a metal film having a thickness of about 200 to 500 nm is formed by sputtering. After film formation, it can be formed by etching using a photosensitive resist.
The pad layer 39 is exposed by the contact hole 33b formed in the interlayer insulating film 32 in the contact hole 32f. This exposed portion is connected to external wiring.

As shown in FIGS. 4 to 7, a passivation film 47 is formed on the upper surface of the counter electrode 46 in the transistor array panel 100 in which the organic EL element 40 is formed. The passivation film 47 can be formed by sputtering alumina (Al ₂ O ₃ ), SiAlON, or the like, for example.

  The sealing material 3 is applied to the upper surface of the passivation film 47, and the organic EL element 40 is sealed by bonding the insulating substrate 2 and the counter substrate 9 together by the sealing material 3, thereby forming the organic EL display panel 10. The Since the organic EL element 40 has a bottom emission type light emitting structure, the light emitted from the organic EL layer 42 is transmitted through the pixel electrode 41 and the insulating substrate 2 to the other surface side of the insulating substrate 2 (FIGS. 4 to 7). (Downward).

Next, the manufacturing process of the organic EL display panel 10 will be described with reference to FIGS.
First, as shown in FIG. 10, the first electrode CS1 is formed by forming a transparent electrode film and patterning it.
Next, as shown in FIG. 11, a gate metal layer is formed of a metal such as Al, AlTi, AlTiNd, and patterned to form gate electrodes 11G, 12G, 13G, a first electrode CS1, a signal line Ld, and a pad layer 14P. Form.

Next, as shown in FIG. 12, a gate insulating film 31 and a semiconductor film 21 are sequentially formed on one surface. Next, an inorganic insulator such as SiO ₂ , SiN, and SiON is formed on the semiconductor film 21 and patterned to form the channel protective film 22.

  Next, as shown in FIG. 13, an n-type semiconductor film 23 is formed on the entire surface. Next, contact holes 31 a to 31 c are formed in the gate insulating film 31 by performing dry etching.

  Next, the drain metal layer is formed on the entire surface, and is patterned together with the semiconductor film 21 and the n-type semiconductor film 23 as shown in FIG. 14, so that the source electrodes 11S, 12S, 13S, and the drain electrodes 11D, 12D, 13D are formed. The scanning line Ls, the common power supply line La, and the wiring 26 are formed.

  Next, as shown in FIG. 15, a transparent electrode film is formed and patterned to form the second electrode CS2 (pixel electrode 41).

  Next, as shown in FIG. 16, an interlayer insulating film 32 is formed on the entire surface, patterned, and dry-etched to form openings 33 and contact holes 32e and 32f.

  Next, as shown in FIG. 17, a positive photosensitive resin material such as polyimide is applied, and the partition wall 6 is formed by performing exposure and development processing.

  Thereafter, a hole injection layer 42, a carrier transport layer 43, a light emitting layer 44, an electron injection layer 45, a counter electrode 46, and a passivation film 47 are sequentially formed, and the sealing material 3 is applied and bonded to the counter substrate 9. Thus, the organic EL display panel 10 is completed.

  In the above embodiment, the width of the scanning line Ls and the common power supply line La on the inclined surface 31B of the gate insulating film 31 is changed, so that the boundary line between the scanning line Ls and the common power supply line La and the gate insulating film 31 is changed. Decrease the slope. Therefore, the adhesion with the gate insulating film 31 can be improved, the disconnection of the scanning lines Ls and the common power supply line La can be reduced, and the yield can be improved.

  The present invention is not limited to the above embodiment, and various improvements and design changes may be made without departing from the spirit of the present invention. For example, in the above-described embodiment, the present invention is applied to the scanning line Ls and the common power supply line La provided above the signal line Ld. However, the present invention is applied by further providing a wiring above the scanning line Ls and the common power supply line La. May be. In the above embodiment, a display device such as an EL display panel has been described. However, the present invention is not limited to this, and may be applied to an exposure device such as a printer head.

CS capacitor CS1 first electrode CS2 second electrode Ld signal line (lower wiring)
Ls scanning line (upper wiring)
La Common power line (upper wiring)
PX pixel PLd, PLs, PLa Terminal 2 Substrate 3 Sealing material 6 Partition 8 Opening 9 Counter substrate 10 Organic EL display panels 11, 12, 13 Transistors 11D, 12D, 13D Drain electrodes 11G, 12G, 13G Gate electrodes 11S, 12S, 13S source electrode 14P pad layer 21 semiconductor film 22 channel protective film 23 n-type semiconductor film 24 scanning line connection layers 25a, 25b, 25c, 25d conductive layer 26 wiring 31 gate insulating films 31a-31c, 32e, 32f contact hole 32 interlayer insulation Film 33 Opening 40 Organic EL Element 41 Pixel Electrode (Second Electrode)
42 hole injection layer 43 carrier transport layer 44 light emitting layer 45 electron injection layer 46 counter electrode 47 passivation film 100 transistor array panel

Claims (6)

A first wiring formed on the top of the substrate;
An insulating layer covering the first wiring and the peripheral area of the first wiring, and having an inclined surface from the upper part of the first wiring to the upper peripheral area;
A second wiring formed on the insulating layer so as to intersect the first wiring, and formed so that the width gradually decreases from the first wiring upper part to the peripheral area upper part on the inclined surface;
A light-emitting panel comprising:   The light emitting panel according to claim 1, wherein the width of the second wiring is gradually changed above the side surface of the first wiring. A pixel transistor connected to the first wiring and the second wiring;
The light emitting panel according to claim 1, further comprising: a light emitting element to which electric power is supplied by the pixel transistor. The first wiring is formed of a metal layer common to the gate electrode of the pixel transistor,
4. The light-emitting panel according to claim 1, wherein the second wiring is formed of a metal layer common to the source / drain electrodes of the pixel transistor. 5. First wiring is formed on the substrate,
Covering the first wiring and the peripheral area of the first wiring, forming an insulating layer that is inclined from the upper part of the first wiring to the upper peripheral area,
The second wiring is formed on the insulating layer so as to intersect with the first wiring and so that the width gradually decreases from the upper part of the first wiring to the upper part of the peripheral region on the inclined surface. Panel manufacturing method.   6. The method of manufacturing a light-emitting panel according to claim 5, wherein a pixel transistor connected to the first wiring and the second wiring and a light-emitting element to which power is supplied by the pixel transistor are formed.

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