JP2012058351A - Image display device - Google Patents

Abstract

An image display device that suppresses flickering with the naked eye while suppressing consumption of resources such as power consumption.
An image display device includes a plurality of pixel circuits each including a light emitting element and lighting using the light emitting element, a lighting period control unit that controls each of the pixel circuits to light at a predetermined period, A lighting time determining unit that determines a length of time for lighting each of the pixel circuits within a predetermined period. The lighting period control unit causes the pixel circuits to light during one lighting period that is continuous for the length of time in the predetermined period when the length of time is equal to or longer than a predetermined length, When the length of the pixel circuit is shorter than the predetermined length, the pixel circuits are turned on during a plurality of lighting periods in which the sum of the predetermined periods is the time length.
[Selection] Figure 11

Description

  The present invention relates to an image display device, and more particularly to an image display device using a light emitting element.

  In recent years, image display devices using light emitting elements such as organic EL display devices have been actively developed. The image display apparatus needs to change the brightness of the screen in order to cope with a change in external light. However, if the brightness is changed by directly changing the signal indicating the display gradation (gradation signal), the gradation expression becomes rough (dynamic range becomes narrow). This is because the gradation signal is generated by the DA converter. For this reason, a technology has been developed in which the brightness of the screen is changed while ensuring the dynamic range by controlling the length of the lighting period of each pixel. In this technique, if one vertical scanning period is set to 60 Hz, for example, and one continuous lighting period is set within the vertical scanning period, flicker is observed with the naked eye. In order to suppress this flickering, Patent Document 1 discloses an image display device in which the lighting period within one vertical scanning period is divided into a plurality of times to shorten the lighting cycle and thereby suppress flickering.

  Patent Document 2 describes an image display device that sets the number of subframes in a frame period in accordance with the ratio of a light emission period to a non-light emission period. Patent Document 3 describes an image display device that determines a light emission mode according to an average luminance level of a screen and controls the number and length of lighting periods according to the light emission mode.

JP 2009-186884 A JP 2006-030516 A JP 2009-192753 A

  As a condition for flickering to be recognized by the naked eye, the lighting cycle and brightness are generally known. However, in an image display device that controls the length of the lighting period, a frequency (cycle that is lower than the critical frequency theoretically calculated from the brightness is used. In some cases, flicker is not recognized. Even in that case, if a plurality of lighting periods are uniformly used, unnecessary power is consumed and an unnecessary load is applied to the circuit.

  The present invention has been made in view of the above problems, and an object thereof is to provide an image display apparatus that suppresses the recognition of flickering with the naked eye while suppressing the consumption of resources such as power consumption. .

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) A plurality of pixel circuits each including a light emitting element that is lit using the light emitting element, a lighting period control unit that controls each of the pixel circuits to light at a predetermined period, and within the predetermined period, A lighting time determination unit that determines a length of time for lighting each pixel circuit, and the lighting period control unit includes the predetermined period when the length of the time is equal to or longer than a predetermined length. Each of the pixel circuits is lit in one lighting period that is continuous for the length of time, and when the length of time is shorter than the predetermined length, the sum of the predetermined periods becomes the length of time. An image display device characterized in that each of the pixel circuits is lit during a lighting period.

(2) In (1), when the length of time is shorter than the predetermined length, the lighting period control unit determines the last lighting period from the start of the first lighting period in the predetermined period. An image display device, wherein the pixel circuit is turned on so that a period until the end is within the predetermined length.

(3) In (1) or (2), each of the pixel circuits is a plurality of lighting patterns having an arrangement of lighting periods in the predetermined cycle, and any one of a plurality of lighting patterns having different arrangements from each other. Accordingly, the lighting period control unit controls the pixel circuits to light up according to the corresponding lighting pattern.

(4) In (3), the plurality of pixel circuits are arranged in a first direction, and the corresponding lighting pattern is different between each pixel circuit and one of the pixel circuits adjacent to the pixel circuit. A characteristic image display device.

(5) In (4), the corresponding lighting pattern is different between the even-numbered pixel circuits and the odd-numbered pixel circuits.

(6) The image display device according to any one of (3) to (5), wherein the number of the lighting patterns is two.

(7) In (6), a plurality of lighting shift registers, each provided corresponding to the lighting pattern, for controlling lighting of the pixel circuit corresponding to the lighting pattern based on control of the lighting period control unit, An image display device comprising:

(8) In (7), a plurality of lighting control lines provided corresponding to each of the plurality of pixel circuits, and a plurality of lighting control connection switches respectively corresponding to any of the plurality of lighting control lines, In addition, each pixel circuit includes a driving transistor that controls a light emission amount of the light emitting element, and a lighting control that controls whether the light emitting element is turned on by a lighting control signal supplied from the lighting control line corresponding to the pixel circuit. The lighting control line corresponding to each pixel circuit is connected to the lighting shift register corresponding to the pixel circuit, and corresponds to the lighting shift register and the lighting control line not corresponding to the pixel circuit. An image display device connected through the lighting control switch.

  ADVANTAGE OF THE INVENTION According to this invention, it can suppress that flicker is recognized with the naked eye, suppressing consumption of resources, such as power consumption of an image display apparatus.

It is a figure which shows an example of the circuit structure of the organic electroluminescence display which concerns on embodiment of this invention. It is a circuit diagram which shows an example of a structure of each pixel circuit. It is a wave form diagram which shows an example of the time change of the electric potential of RGB switching control line regarding a pixel circuit, a lighting control line, a precharge control line, a reset control line, node NA, and node NB. It is a figure which shows the time transition of the writing period of each pixel row, and the non-writing period. It is a figure which shows the relationship between the ratio of a lighting period, and a brightness | luminance. It is a block diagram which shows an example of a structure of a display control part. It is a figure which shows an example of a structure of a still image determination part. It is a figure which shows an example of the processing flow of the light emission mode selection part. It is a figure which shows the waveform applied to each lighting control line in a still image mode for every duty ratio. It is a figure which shows the waveform applied to each lighting control line in a moving image priority mode for every duty ratio. It is a figure which shows the waveform applied to each lighting control line in a balance normal mode for every duty ratio. It is a figure which shows the waveform applied to each lighting control line in a balance flicker suppression mode for every duty ratio. It is a figure which shows the waveform applied to each lighting control line in a flicker suppression mode for every duty ratio. It is a block diagram which shows the structure of a vertical scanning circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Of the constituent elements that appear, those having the same function are given the same reference numerals, and the description thereof is omitted. Hereinafter, a case where the present invention is applied to an organic EL display device which is a kind of image display device using a light emitting element will be described.

  The organic EL display device physically includes an array substrate, a flexible printed circuit board, and a driver integrated circuit enclosed in a package. A display area DA for displaying an image is arranged on the array substrate. FIG. 1 is a diagram showing an example of a circuit configuration of an organic EL display device according to an embodiment of the present invention. The circuit shown in FIG. 1 is mainly provided on the array substrate and the driver integrated circuit. A display area DA is provided on the array substrate of the organic EL display device, and pixels are arranged in a matrix in the display area DA. Three pixel circuits PCR, PCG, and PCB are arranged side by side in the horizontal direction in the drawing in each region to be a pixel. The pixel circuit PCR displays red, the pixel circuit PCG displays green, and the pixel circuit PCB displays blue. Hereinafter, when the colors emitted from the pixel circuits PCR, PCB, and PCG are not distinguished, they are called pixel circuits PC. Note that M columns × N rows of pixels PX are arranged in the display area DA. In the display area DA, pixel circuits PC of (3 × M) columns × N rows are arranged, and in this embodiment, the pixel circuits PC arranged in the same column display the same color. A group of pixel circuits PC in the same row is hereinafter referred to as a pixel row PXL.

  In the display area DA, corresponding to each column of the pixel circuits PC, data lines DATR, DATG, and DATB (hereinafter referred to as data lines DAT when these data lines are not distinguished) and a power supply line PWR that supplies a power supply potential Voled. Extends in the vertical direction in the figure, and the reset control line RES, the lighting control line ILM, the precharge control line PRE, and the light emission control signal line REF extend in the horizontal direction in the figure corresponding to each row of the pixel circuit PC. ing. Further, an area on the array substrate and below the display area DA in the figure is an RGB selector switch DSR, DSG, DSB provided corresponding to the data lines DATR, DATG, DATB, and an integrated data line DATI. And a data line driving circuit XDV, a vertical scanning circuit YDVL is provided in the area on the array substrate and on the left side of the display area DA in the figure, and a vertical scanning circuit YDVR is provided on the right side in the figure. It has been. The data line driving circuit XDV, the vertical scanning circuit YDVL, and the vertical scanning circuit YDVR are each connected to the display control unit CTL via a wiring group. Note that a part of the data line driving circuit XDV, the vertical scanning circuit YDVL, and the vertical scanning circuit YDVR is also provided in the driver integrated circuit.

  Pixel circuits PC connected to the same data line DAT display the same color. In the following, the data line DATR corresponding to the column of the pixel circuit PCR constituting the m-th pixel column corresponds to DATRm, the data line DATG corresponding to the column of the pixel circuit PCG corresponds to DATGm, and the column of the pixel circuit PCB. The data line DATB to be written is denoted as DATBm. A certain data line DAT supplies a data signal to a plurality of pixel circuits PC in the corresponding column. The number of reset control lines RES, lighting control lines ILM, precharge control lines PRE, and light emission control signal lines REF is the same number (N) as the number of pixel rows PXL. The reset control line RES corresponding to the nth pixel row PXL is referred to as RESn, the lighting control line ILM as ILMn, the precharge control line PRE as PREn, and the light emission control signal line REF as REFn. One end of the reset control line RES, lighting control line ILM, precharge control line PRE, and light emission control signal line REF is connected to the vertical scanning circuit YDVL, and the other end is connected to the vertical scanning circuit YDVR.

  The RGB selector switches DSR, DSG, and DSB are n-channel thin film transistors, and m are provided corresponding to the pixel columns. An RGB switching control line CLA is connected to the gate electrode of the RGB switching switch DSR, an RGB switching control line CLB is connected to the gate electrode of the RGB switching switch DSG, and an RGB switching control line CLC is connected to the gate electrode of the RGB switching switch DSB. Is connected.

  The source electrode of the RGB selector switch DSR is connected to the lower end of the data line DATRm corresponding to the pixel circuit PCR among the data lines DAT corresponding to the m-th column of pixels. Similarly, the source electrode of the RGB selector switch DSG is connected to the lower end of the data line DATGm, and the source electrode of the RGB selector switch DSB is connected to the lower end of the data line DATBm. The drain electrodes of the RGB selector switches DSR, DSG, and DSB are connected to the integrated data line DATI corresponding to the mth column of the M integrated data lines DATI corresponding to the pixel columns. Note that the polarity of the source electrode and the drain electrode of the thin film transistor is not fixed due to the structure. The direction of the current flowing through the thin film transistor and whether the thin film transistor is an n-channel type or a p-channel type are determined. Therefore, in the thin film transistor, the connection destination of the source electrode and the connection destination of the drain electrode may be reversed.

  FIG. 2 is a circuit diagram showing an example of the configuration of each pixel circuit PC according to the first embodiment. Each pixel circuit PC includes a light emitting element IL, a drive transistor TRD, a storage capacitor CP, an auxiliary capacitor CA, a lighting control switch SWI, a reset switch SWR, a selection switch SWS, a light emission signal control switch SWF, Charge switch SWP. A reference potential is supplied to one end of the light emitting element IL by a reference potential supply wiring (not shown). The drive transistor TRD is a p-channel thin film transistor, and controls the light emission amount of the light emitting element IL in accordance with the potential difference between the potential applied to the gate electrode and the potential applied to the source electrode. The other end of the light emitting element IL is connected to the drain electrode of the driving transistor via the lighting control switch SWI. One end of the storage capacitor CP is connected to the gate electrode of the drive transistor TRD. The other end of the storage capacitor CP is connected to one end of the selection switch SWS, and the other end of the selection switch SWS is connected to the data line DAT. The other end of the storage capacitor CP is also connected to one end of the light emission signal control switch SWF. The other end of the light emission signal control switch SWF is connected to the light emission control signal line REF. Here, a node to which the gate electrode of the drive transistor TRD is connected is called a node NA, and a node to which the other end of the storage capacitor CP is connected is called a node NB. Note that the light emitting element IL included in the pixel circuit PCR emits red light, the light emitting element IL included in the pixel circuit PCG emits green light, and the light emitting element IL included in the pixel circuit PCB emits blue light.

  One end of the auxiliary capacitor CA is connected to the node NB, and the other end is connected to the source electrode of the drive transistor TRD. The auxiliary capacitor CA suppresses the rise of the floating node NA and the node NB due to coupling with the precharge control line PRE in a precharge operation described later, and assists a series of precharge operations. The gate electrode and drain electrode of the drive transistor TRD are connected via a reset switch SWR. One end of the storage capacitor CP is connected to one end of the precharge switch SWP, and the other end of the storage capacitor CP is connected to the other end of the precharge switch. The lighting control switch SWI, the reset switch SWR, the selection switch SWS, the light emission signal control switch SWF, and the precharge switch SWP are n-channel thin film transistors. The gate electrodes of the selection switch SWS and the reset switch SWR are on the reset control line RES, the gate electrodes of the lighting control switch SWI and the light emission signal control switch SWF are on the lighting control line ILM, and the gate electrode of the precharge switch SWP is the precharge control line PRE. It is connected to the.

  The reference potential is a reference potential in relation to the power supply potential Voled supplied from the power supply line PWR, the data line DAT, the potential supplied to the gate electrode of the drive transistor TRD used for the switch such as the lighting control switch SWI, and the like. It is. The reference potential is not necessarily supplied from the grounded electrode.

  Next, a method for driving the organic EL display device according to this embodiment will be described. FIG. 3 is a waveform diagram showing an example of temporal changes in potentials of the RGB switching control lines CLA, CLB, CLC, lighting control line ILM, precharge control line PRE, reset control line RES, node NA, and node NB. In the figure, only signals for one pixel circuit PC are shown. The potentials of the node NA and the node NB are shown for the case where black is displayed in the previous frame (hereinafter referred to as the previous frame) and black is displayed in the present frame (BLACK).

  An operation for light emission with respect to a certain pixel circuit PC is performed in the order of a precharge operation, a data storage operation, and a light emission control operation. The precharge operation is an operation for lowering the gate potential of the drive transistor TRD, and a period during which this operation is performed is referred to as a precharge period PPR. The data storage operation is an operation for storing a potential difference corresponding to the gradation to be displayed in the storage capacitor CP, and a period during which this operation is performed is referred to as a data storage period PDW. Here, the precharge period PPR and the data storage period PDW are continuous, and the combined period is called a writing period PDL, and its length is one horizontal period (1H). The light emission control operation is an operation for controlling light emission of the light emitting element IL (lighting of the pixel circuit PC) included in the pixel circuit PC for which the precharge operation and the data storage operation have been completed. Call it. The non-writing period PND includes one or a plurality of lighting periods PIL in which the light emitting element IL emits light and a non-lighting period PNI in which light emission of the light emitting element IL is suppressed.

  The pixel circuits PC are arranged in a matrix, and the next row is sequentially scanned every horizontal period. In the example of this figure, when the pixel circuit PC in the nth row is in the writing period PDL, the pixel circuits PC other than the nth row are in the non-writing period PND. In the next horizontal period 1H, the pixel circuit PC in the (n + 1) th row becomes the writing period PDL, and the pixel circuits PC other than the (n + 1) th line become the non-writing period PND. Note that after scanning up to the last row in the display area DA, scanning is sequentially performed from the first row in order to display the next frame through a vertical blanking period. FIG. 4 is a diagram showing a time transition between the writing period PDL and the non-writing period PND of each pixel row PXL. In this embodiment, when the pixel row PXL is different, the times of the writing period PDL and the non-writing period PND are also different. The writing period PDL and the non-writing period PND are periods that are relatively determined in relation to scanning. For each pixel row PXL, the pixel circuit PC is lit at a fixed cycle from the timing when the pixel row is scanned to the timing when the pixel row is scanned next, and this cycle is referred to as a lighting cycle. This period is the same as the length of the vertical scanning period.

  Hereinafter, a driving method will be described. In the lighting period PIL included in the non-writing period PND before the precharge period PPR, the light emitting element IL emits light at the gradation displayed in the previous frame. At this timing, the node NA has a potential corresponding to the gradation of light emission. This potential increases as the gradation to be displayed changes from light (white) to dark (black). At the beginning of the precharge period PPR, the auxiliary capacitor CA stores the potential difference between the power supply line PWR and the light emission control signal line REF applied in the lighting period PIL of the previous frame, and the precharge switch SWP is turned on. At this time, the rise in the potential of the node NA and the node NB is suppressed. Thereby, an increase in the on-resistance of the precharge switch SWP is suppressed. At the beginning of the precharge period PPR, the potential of the lighting control line ILM is at a low level, and the lighting control switch SWI is off. Thereby, the light emitting element IL does not emit light. Immediately thereafter, the potential of the precharge control line PRE becomes high level, and the precharge switch SWP is turned on. At this time, the potential of the reset control line RES is at a low level, and the selection switch SWS and the reset switch SWR are in an off state. When the precharge switch SWP is turned on, both ends of the storage capacitor CP are connected to have the same potential. Due to the potential difference stored in the auxiliary capacitor CA, the potential of the node NA becomes close to the latter (Vref) of the potential Va of the node NA and the potential Vb of the node NB at the start of the precharge period PPR. Here, the reset switch SWR is turned off, and the current path from the power supply line PWR to the light emission control signal line REF is blocked.

  In the example of FIG. 3, the data line driving circuit XDV sequentially supplies data signals to the data lines DATR, DATG, and DATB during the precharge period PPR. At the beginning of the precharge period PPR, the RGB switching control line CLA becomes high level, the RGB switching switch DSR is turned on, and the data line driving circuit XDV displays the display gradation on the data line DATR connected thereto via the integrated data line DATI. The gradation signal shown is written. Next, the RGB switching control line CLB becomes high level instead of the RGB switching control line CLA, and the data line driving circuit XDV writes the gradation signal to the data line DATG via the integrated data line DATI. Similarly, the RGB switching control line CLC becomes high level instead of the RGB switching control line CLB, and the data line driving circuit XDV writes the gradation signal to the data line DATB via the integrated data line DATI. After the data line is written, the RGB selector switch DSB is turned off. Parasitic capacitance is generated between the data lines DATR, DATG, and DATB and wirings crossing them such as the reset control line RES. Therefore, the potential of the gradation signal supplied from the data line driving circuit XDV is stored in each data line DAT by the parasitic capacitance.

  At the end of the precharge period PPR, the potential of the precharge control line PRE becomes low level, and the precharge switch SWP is turned off. At the beginning of the data storage period PDW, the potential of the reset control line RES becomes a high level, and the selection switch SWS and the reset switch SWR are turned on. Thus, the potential of the gradation signal stored in the data line DAT is supplied to one end of the storage capacitor CP on the node NB side, and the node NA to which the other end of the storage capacitor CP is connected is connected to the drain electrode of the drive transistor TRD. Connected.

  Since the potential Va is low enough to turn on the driving transistor TRD at the beginning of the data storage period PDW, the driving transistor TRD is connected between the gate and the source in both the previous frame black and the previous frame white. A current is passed so that the potential difference becomes a threshold voltage. However, when the gradation to be displayed is black, the potential is lowered due to the coupling, and the potential Va is lowered instantaneously. After that, Va approaches Voled− | Vth |. Here, the value of the threshold voltage is Vth. The storage capacitor CP stores a potential difference between the potential Va of the node NA and the potential Vdata_b (black gradation potential) of the data signal at the end of the data storage period PDW.

  Then, the non-writing period PND is entered, and during the lighting period PIL, the potential of the lighting control line ILM becomes high level, the lighting control switch SWI and the light emission signal control switch SWF are turned on, and the light emission potential is applied to the node NB. A reference potential Vref is supplied. Since the amount of current flowing through the drive transistor TRD is determined by a value obtained by subtracting the threshold voltage from the potential difference between the gate and the source, the amount of current can be controlled regardless of variations in the threshold voltage when the drive transistor TRD is manufactured. As a result, the light emitting element IL emits light with a luminance corresponding to the potential of the data signal.

  In the non-lighting period PNI, the potential of the lighting control line ILM becomes low level, and the lighting control switch SWI and the light emission signal control switch SWF are turned off. Accordingly, the reference potential Vref is not supplied to the node NB, and the current through the driving transistor TRD does not flow through the light emitting element IL, so that the pixel circuit PC is not lit. Note that the wirings for controlling the lighting control switch SWI and the light emission signal control switch SWF may be separately provided and the switches may be controlled independently. In that case, the lighting of the pixel circuit PC is suppressed only by turning off one of the switches.

  FIG. 5 is a diagram illustrating the relationship between the ratio of the lighting period PIL and the luminance. The horizontal axis of the graph of this figure shows the gradation of the gradation signal, and the vertical axis shows the luminance. The line Cs1 in this drawing shows the case where the ratio (duty ratio DR) of the lighting period PIL in the non-writing period PND is 50%, and the line Cs2 shows the case where the duty ratio DR is 100%. As can be seen from the graph, the light emission luminance is also controlled by the duty ratio DR. As a result, the dynamic range of the DA converter that generates the gradation signal is further utilized.

  Hereinafter, the display control unit CTL that determines the arrangement of the duty ratio DR and the lighting period PIL in the non-writing period PND will be described. FIG. 6 is a block diagram showing the configuration of the display control unit CTL. The display control unit CTL controls the entire organic EL display device, and includes a lighting period condition setting unit CIC, a vertical scanning control signal generation unit CPT, a signal changeover switch SW, and an image signal processing unit PIM. Among these, the lighting period condition setting unit CIC and the vertical scanning control signal generation unit CPT constitute a control line driving condition setting unit, and the image signal processing unit PIM constitutes an image signal line control unit for controlling the data line driving circuit XDV. . The control line drive condition setting unit has an image data control signal at a predetermined timing according to an image data signal or an image luminance signal, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a data synchronization clock input from the outside. The control line drive signal is output to the vertical scanning circuits YDVL and YDVR. The image signal line control unit outputs a signal indicating the voltage of the gradation signal and a sampling signal of the image data to the data line driving circuit XDV.

  The image data signal IMG input from the outside is input to the image signal processing unit PIM. The image signal processing unit PIM generates a signal indicating the voltage of the gradation signal supplied to each pixel circuit PC from the image data signal. The image signal processing unit PIM includes a digital γ conversion unit, a color management function unit, and a digital inverse γ conversion unit. The digital γ conversion unit performs square digital γ conversion on the 8-bit RGB image data signal IMG input to the image signal processing unit, and outputs a RGB 16-bit luminance signal. The color management function unit performs hue conversion on the luminance signal obtained by the square digital γ conversion. By performing hue conversion, the color reproduction range can be adjusted to standard values such as the sRGB color space and the AdobeRGB color space. Next, the digital inverse γ conversion function unit converts the luminance-converted luminance signal into 8-bit data indicating the voltage of the gradation signal, and outputs the data to the data line driving circuit XDV.

  The data line driving circuit XDV latches input data for one pixel row PXL, and then inputs the signal to a DA converter provided for each column of the pixel circuit PC to input the potential of the gradation signal for one row. And the gradation signal is supplied to the pixel circuit PC of the scanned pixel row PXL.

  The signal selector switch SW switches the signal input source so that one of the image data signal and the luminance signal generated by the image signal processing unit PIM is input to the lighting period condition setting unit CIC. Switching may be performed according to user settings or the like, or may be determined in advance. The external light measurement unit SLM connected to the lighting period condition setting unit CIC measures the brightness around the organic EL display device.

  The lighting period condition setting unit CIC includes a frame average calculation unit CFA, a user setting unit USR, a maximum luminance calculation unit CMB, a still image determination unit DSI, a light emission mode selection unit SIM, and a lighting period control unit CIL. Including. The user setting unit USR holds setting information set by a user who operates the organic EL display device.

  The frame average calculation unit CFA calculates an average of gradations or an average of luminance corresponding to all pixels constituting a certain frame in accordance with an input image data signal or luminance signal. Which is calculated is determined by the signal selector switch. In the following, the average of gradation is referred to as an average image level (APL) and the average of luminance is referred to as an average luminance level (ALL). When calculating the APL, the frame average calculation unit CFA calculates a sum of values obtained by multiplying the RGB gradations of the image data by the adjustment coefficient for each RGB. APL may be obtained by calculating the sum of values obtained by multiplying image data of a plurality of frames by an adjustment coefficient for each RGB and dividing the result by the number of frames. Further, the frame average calculation unit CFA calculates the sum of one frame of the luminance signal calculated by the image signal processing unit PIM when calculating ALL. This may also be obtained from the sum of multiple frames.

  The maximum luminance calculation unit CMB sets the maximum luminance level in the frame screen to be displayed. Specifically, the maximum luminance level is the duty ratio DR. The operation of the maximum luminance calculation unit CMB is the same as determining the length of time for lighting each pixel circuit PC within the vertical scanning period non-writing period, and the maximum luminance calculation unit CMB may be called a lighting time determination unit. . The duty ratio DR is set according to the ambient brightness measured by the external light measurement unit SLM so that the duty ratio DR increases as the measured brightness increases. Further, it may be set according to APL or ALL calculated by the frame average calculation unit CFA, or may be set according to both ambient brightness and APL or ALL. Furthermore, the duty ratio may be corrected according to user setting information about the screen brightness held by the user setting unit USR, the continuous use time of the organic EL display device, and the like.

  The still image determination unit DSI is a circuit that determines whether the frame screen is a moving image or a still image based on input image data or the like. FIG. 7 is a diagram illustrating an example of the configuration of the still image determination unit DSI. The still image determination unit DSI includes a frame memory FRM, a motion amount calculation unit CMT, and a still image determination processing unit DSM. The frame memory FRM is a memory that stores image data of one frame. The motion amount calculation unit CMT calculates a motion amount based on the image data of a plurality of frames stored in the frame memory. The motion amount calculation unit CMT detects the motion amount using, for example, a comb filter. The motion amount calculation unit CMT calculates a motion amount based on the image data signal of the previous frame read from the frame memory FRM and the image data signal of the current frame. The motion amount calculation unit CMT may take a difference in gradation indicated by the image data signal using the image signal of the current frame and the image signal of the previous frame, and the amount of the difference may be used as the motion amount. In the present embodiment, the motion amount calculation unit CMT only needs to detect the motion amount, and does not have to detect the motion direction. The still image determination processing unit DSM determines whether the supplied image data is a still image or a moving image based on the calculated amount of motion. In principle, an image with a motion amount of zero is determined as a still image, but an image with a motion amount smaller than a predetermined determination threshold may be determined as a still image. This determination threshold value is given as a design value that takes into account experience and the like. The determination result is output to the light emission mode selection unit SIM as the determination result of the still image determination unit DSI.

The light emission mode selection unit SIM is a circuit that selects a light emission mode based on the calculated APL or ALL, the determination result of the still image determination unit DSI, and the like. There are four light emission modes to be selected: a still image mode, a moving image emphasis mode, a balance mode, and a flicker suppression mode.
In principle, the still image mode is a light emission mode in which the number of lighting periods is set to a predetermined number of 2 or more and the lighting periods are evenly arranged in the non-writing period PND. When the duty ratio DR is 100%, there is no lighting period interval, so there is one lighting period. The video emphasis mode is a light emission mode in which the number of lighting periods in which the pixel circuit PC is continuously lit in the non-writing period PND (vertical scanning period) is 1, and the non-lighting period PNI in the non-writing period PND is also one. It is. In the video emphasis mode, the occurrence of motion blur is suppressed compared to other modes. The moving image blur is a phenomenon in which the viewer recognizes two images of successive frames by overlapping the retina, and as a result, the outline of the image feels blurred. The balance emphasis mode is a light emission mode in which moving image blurring is more likely to occur than the moving image emphasis mode, but flickering is further suppressed. The flicker priority mode is a light emission mode in which the occurrence of flicker is further suppressed while the moving image blur is more likely to occur than the balance priority mode. Details of these light emission modes will be described later.

  FIG. 8 is a diagram illustrating an example of a processing flow of the light emission mode selection unit SIM. First, when the image displayed from the determination result of the still image determination unit DSI is a still image (Y in step S101), the light emission mode selection unit SIM sets the light emission mode to the still image mode (step S102). If the image is a moving image (N in step S101), it is determined whether APL or ALL is smaller than the first threshold (step S103). If APL or ALL is smaller than the first threshold value (Y in step S103), the light emission mode is set to the moving image priority mode (step S104). If APL or ALL is greater than or equal to the first threshold value (N in step S103), it is determined whether APL or ALL is smaller than the second threshold value (step S105). If APL or ALL is smaller than the second threshold (Y in step S105), the light emission mode is set to the balance mode (step S106). If APL or ALL is equal to or greater than the second threshold (N in step S105), the flicker suppression mode is set. (Step S107). Note that there are two types of light emission modes in the balance emphasis mode, and the selected light emission mode changes depending on whether the setting of the user setting unit USR is the normal setting or the flicker suppression setting. Hereinafter, the balance mode and normal setting are described as a balance normal mode, and the balance mode and flicker suppression setting are described as a balance flicker suppression mode. The light emission mode desired by the user may be held in the user setting unit USR, and the light emission mode may be selected regardless of the values of APL and ALL.

  The lighting period control unit CIL controls the number of lighting periods, the arrangement of the lighting periods, and the length of each lighting period according to the selected light emission mode and the determined duty ratio DR. Based on the control of the lighting period control unit CIL, the vertical scanning control signal generation unit CPT outputs the lighting period control signal to the vertical scanning circuits YDVL and YDVR, and the vertical scanning circuits YDVL and YDVR respond to the lighting period control signal. Control the potential of the ILM. Therefore, the lighting period control unit CIL controls lighting of each pixel circuit PC. The vertical scanning control signal generation unit CPT applies a lighting period control signal for controlling a light emission control signal applied to the lighting control line ILM to the vertical scanning circuits YDVL and YDVR according to the horizontal synchronization timing and the vertical synchronization timing, and a precharge control line PRE. A signal for controlling a signal to be supplied and a signal for controlling a signal to be supplied to the reset control line RES are output.

  FIG. 9 is a diagram showing waveforms applied to the respective lighting control lines ILM for each duty ratio DR in the still image mode. In the still image mode, the lighting period control unit CIL divides the lighting period PIL into four within the lighting period. The lighting period control unit CIL performs control so that each lighting period PIL satisfies the following conditions. The first condition is that the length of each lighting period PIL in each lighting cycle is the same, and the second condition is that the interval between the lighting periods PIL (the length of the non-lighting period PNI) is also the same. . The third condition is that the first lighting period PIL starts at the start timing of the non-writing period PND, and the last lighting period PIL ends at the end timing of the non-writing period PND.

  FIG. 10 is a diagram showing waveforms applied to the respective lighting control lines ILM for each duty ratio DR in the moving image priority mode. In the moving image priority mode, the lighting period control unit CIL does not divide the lighting period PIL within the lighting cycle. That is, the continuous lighting period PIL is one per lighting cycle. The lighting period control unit CIL controls the start of the lighting period PIL to be the start of the non-writing period PND regardless of the duty ratio DR. As a result, a period in which no light is emitted occurs after the lighting period PIL, thereby reducing motion blur between frames.

  FIG. 11 is a diagram showing waveforms applied to the respective lighting control lines ILM for each duty ratio DR in the balanced normal mode. In the balance normal mode, when the duty ratio DR is equal to or greater than a predetermined threshold, the lighting period control unit CIL performs one lighting that is continuous for the length of time indicated by the duty ratio DR (lighting time length) in the lighting cycle. Each pixel circuit PC is lit in the period PIL, and when the duty ratio DR is shorter than the threshold value, each pixel circuit PC is lit in a plurality of lighting periods PIL in which the total is the lighting time length in the lighting cycle. In the example of FIG. 11, the number of lighting periods PIL is four. Here, the lighting time length is a length of time obtained by multiplying the duty ratio DR by the non-writing period PND. If the threshold value is adjusted according to the non-writing period PND, the comparison between the duty ratio DR and the threshold value is the same as the comparison between the lighting time length and the threshold value. In terms of processing, the duty ratio DR may be compared with a threshold value, or the lighting time length may be compared with a threshold value. The threshold of the duty ratio DR is 60% in the present embodiment, but may be experimentally determined between 40% and 80%, for example, so as not to feel flickering with the naked eye of the person viewing the screen. In this way, when the duty ratio DR is larger than the limit for recognizing flickering with the naked eye, division of the lighting period PIL can be suppressed, so that power consumption can be suppressed and the burden on the device can be reduced.

  The lighting period control unit CIL performs control so that each lighting period PIL further satisfies the following conditions. First, when a plurality of lighting periods PIL are used, a period from the start of the first lighting period PIL to the end of the last lighting period PIL in the lighting cycle (duty ratio threshold value × non-writing period). PND) is a condition for the lighting arrangement period PIA obtained by PND). As a result, when the lighting periods PIL are plural, the pixel circuit PC does not emit light during the non-lighting period PNI of the non-writing period PND other than the lighting layout period PIA. Video blur is reduced. The second is a condition for matching the start of the lighting arrangement period PIA, that is, the start timing of the first lighting period PIL with the start of the non-writing period PND. The third condition is that the length of each lighting period PIL in each lighting cycle is the same, and the fourth condition is that the interval between the lighting periods PIL is also the same.

  FIG. 12 is a diagram showing waveforms applied to each lighting control line ILM for each duty ratio DR in the balance flicker suppression mode. In the balance flicker suppression mode, similarly to the balance normal mode, when the duty ratio DR is equal to or greater than a predetermined threshold value, the lighting period control unit CIL includes each lighting period PIL that continues for the lighting time length in the lighting cycle. When the pixel circuit PC is turned on and the duty ratio DR is shorter than the threshold value, each pixel circuit PC is turned on during a plurality of lighting periods PIL in which the total is the lighting period length in the lighting cycle. The lighting period control unit CIL controls each lighting period PIL so as to satisfy some conditions. The difference from the balanced normal mode is that the pixel circuit PC is divided into two groups, and the non-writing period PND is divided for each group. The lighting pattern which is the arrangement of the lighting period PIL is different. The number of types of lighting patterns (types of groups of pixel circuits PC) may be three or more.

  More specifically, the pixel circuits PC are divided into a group of pixel circuits PC in odd rows and a group of pixel circuits PC in even rows. Then, the lighting period control unit CIL lights at least one of the pixel circuits PC adjacent to each pixel circuit PC with a different lighting pattern. This makes it difficult for the viewer to recognize the flicker due to the difference in the light emission timing of the adjacent pixels PX. Further, in the present embodiment, the types of lighting patterns are as follows: the start timing of the lighting arrangement period PIA is the start timing of the non-writing period PND, and the end timing of the lighting arrangement period PIA is the end timing of the non-writing period PND. There are two types of things. Needless to say, the arrangement of the lighting periods PIL within the non-writing period PND is also the arrangement of the lighting periods PIL within the lighting cycle.

  FIG. 13 is a diagram showing waveforms applied to the lighting control lines ILM for each duty ratio DR in the flicker suppression mode. In the flicker suppression mode, the lighting period control unit CIL divides the lighting period PIL into four within the lighting period. The lighting period control unit CIL controls each lighting period PIL so as to satisfy the following conditions. The first is a condition that the length of each lighting period PIL in each lighting cycle is the same, and the second is the interval between the lighting periods PIL (the length of the non-lighting period PNI) (non-writing period). PND) − (lighting time length) ÷ (number of lighting periods PIL). Further, similarly to the balance flicker suppression mode, the pixel circuits PC are divided into a plurality of groups (two in this embodiment), and the lighting patterns that are the arrangement of the lighting periods PIL within the non-writing period PND are made different for each group. ing. Specifically, the start timing of the first lighting period PIL in the non-writing period PND is shifted. Since the divided lighting periods PIL are arranged in a more dispersed form, the flicker is suppressed compared to the balance flicker suppression mode.

  In addition, the number (dispersion number) of the lighting periods PIL in the case of dividing into the plurality of lighting periods PIL within the lighting cycle in each light emission mode described above may not be four. However, when the number of dispersion is 2, when displaying an image in which a line on the screen moves in a direction crossing the direction in which the line extends, a phenomenon that the line appears to split into two tends to occur. Therefore, the number of dispersions is desirably 3 or more. Further, since an increase in the number of dispersions causes an increase in power consumption of the driver IC due to the on / off operation, the number of dispersions is preferably 4 or less.

  FIG. 14 is a block diagram showing a configuration of the vertical scanning circuit YDVL. The configuration of the vertical scanning circuits YDVL and YDVR that realize the control of the lighting period PIL will be described with reference to FIG.

  Vertical scanning circuits YDVL and YDVR include write shift register SR1, lighting shift register SR2, and logic circuit LC. Further, the same number of lighting control connection switches SWH as the lighting control lines ILM are provided corresponding to the lighting control lines. The write shift register SR1 is connected to the logic circuit LC via the number of write signal lines R for the number of pixel rows PXL, and the lighting shift register SR2 is connected to the logic circuit LC via the number of lighting signal lines Q for the number of pixel rows PXL. Connected to. A reset control line RES and a precharge control line PRE corresponding to each pixel row PXL are connected to the logic circuit LC. Further, the logic circuit LC included in the vertical scanning circuit YDVL is connected to the lighting control line ILM corresponding to the even-numbered pixel row PXL, and the lighting control line ILM and lighting control connection switch SWH corresponding to the odd-numbered pixel row PXL. Connected through. Although not shown, the logic circuit LC included in the vertical scanning circuit YDVR is connected to the lighting control line ILM corresponding to the odd-numbered pixel row PXL, and is connected to the lighting control line ILM corresponding to the even-numbered pixel row PXL. Connection is made via a switch SWH. A plurality of light emission control signal lines REF are connected, and a reference potential Vref is supplied to them.

  A clock, a vertical scanning signal, and the like are supplied from the display control unit CTL to the write shift register SR1. The write shift register SR1 outputs, to the nth write signal line Rn, a signal indicating that the nth (n is an integer not smaller than 1 and not larger than N) pixel row PXL that has been sequentially scanned is a writing target. A signal indicating the lighting timing of the first pixel row PXL is supplied to the lighting shift register SR2, and is output to the first lighting signal line Q1. Here, the length of the lighting period PIL increases or decreases by the unit of the horizontal period. Then, a lighting control signal is sent to the nth lighting signal line Qn using the lighting shift register SR2 with a delay of (n-1) horizontal periods.

  The logic circuit LC supplies a signal obtained by processing signals supplied from the write shift register SR1 and the lighting shift register SR2 to the reset control line RES, the precharge control line PRE, and the lighting control line ILM. More specifically, the reset control line RES corresponding to the kth pixel row PXL (k is an integer from 1 to N) is supplied with a signal indicating the reset timing in the cycle of the signal of the write signal line Rk and the horizontal period. Supply logical product. A logical product of the signal of the write signal line Rk and a signal indicating the precharge timing is supplied in the period of the horizontal period to the precharge control line PRE corresponding to the kth pixel row PXL. Further, the signal of the lighting signal line Qk is supplied toward the lighting control line ILM corresponding to the kth pixel row PXL. As a result, it is possible to control the lighting period PIL so that the lighting periods PIL of the other pixel rows PXL also maintain the relative relationship with the writing period PDL, that is, have the same lighting pattern.

  One end of the lighting control line ILM corresponding to each pixel circuit PC is connected to the lighting shift register SR2 corresponding to the pixel circuit PC, and the other end of the lighting control line SRM corresponding to the pixel circuit PC is the lighting control line. The lighting control connection switch SWH corresponding to the ILM is connected. In the flicker priority mode and the balance flicker suppression mode, the lighting control connection switch SWH is turned off, and if the signal indicating the lighting timing of the first pixel row PXL is made different between the vertical scanning circuit YDVL and the vertical scanning circuit YDVR, they are connected. Two types of lighting patterns are realized by the lighting shift register. In the moving image priority mode or the like, the lighting control connection switch SWH is turned on, and the lighting period is more accurately controlled by the control from the lighting shift registers SR2 on both sides. In this way, it is possible to control lighting according to the characteristics of the light emission mode.

  Note that the scope of the present invention is not limited to the above-described embodiment. It goes without saying that various modifications are possible within the scope of the technical idea of the present invention. For example, the lighting period PIL is not necessarily controlled by the lighting control line ILM, but may be performed by changing the potential of a signal applied to the light emission control signal line REF.

CTL display control unit, DA display area, XDV data line drive circuit, YDVL, YDVR vertical scanning circuit, PC, PCR, PCG, PCB pixel circuit, PX pixel, PXL pixel row, CLA, CLB, CLC RGB switching control line, DAT , DATR, DATG, DATB data line, DATI integrated data line, DSR, DSG, DSB RGB changeover switch, ILM lighting control line, PRE precharge control line, REF light emission control signal line, RES reset control line, PWR power supply line, CP Storage capacity, CA auxiliary capacity, IL light emitting element, NA, NB node, SWF light emission signal control switch, SWI lighting control switch, SWP precharge switch, SWR reset switch, SWS selection switch, TRD drive transistor, DR duty ratio, PDL Inclusion period, PP R Precharge period, PDW data storage period, PND non-writing period, PIA lighting arrangement period, PIL lighting period, PNI non-lighting period, Cs1 Duty ratio 100%, Cs2 Duty ratio 50%, CFA frame average calculation Unit, CIC lighting period condition setting unit, CIL lighting period control unit, CMB maximum luminance calculation unit, CPT vertical scanning control signal generation unit, DSI still image determination unit, IMG image data signal, PIM image signal processing unit, SIM light emission mode selection Unit, SLM external light measurement unit, SW signal changeover switch, USR user setting unit, FRM frame memory, CMT motion amount calculation unit, DSM still image determination processing unit, SR1 write shift register, SR2 lighting shift register, R write signal Line, Q lighting signal line, LC logic circuit, SWH lighting control connection switch.

Claims (8)

A plurality of pixel circuits each including a light emitting element and lit using the light emitting element;
A lighting period controller that controls each of the pixel circuits to light up at a predetermined cycle;
A lighting time determination unit that determines a length of time for lighting each pixel circuit within the predetermined period,
The lighting period control unit causes the pixel circuits to light during one lighting period that is continuous for the length of time in the predetermined period when the length of time is equal to or longer than a predetermined length, When each of the pixel circuits is shorter than the predetermined length, each pixel circuit is lit during a plurality of lighting periods in which the sum of the predetermined periods is the length of the time,
An image display device characterized by that. When the length of time is shorter than the predetermined length, the lighting period control unit has a period from the start of the first lighting period to the end of the last lighting period in the predetermined period. Turn on the pixel circuit so that it is within the length,
The image display apparatus according to claim 1. Each of the pixel circuits corresponds to any one of a plurality of lighting patterns that are arrangements of lighting periods in the predetermined cycle, and the arrangements are different from each other.
The lighting period control unit controls each pixel circuit to light up according to the corresponding lighting pattern,
The image display device according to claim 1, wherein the image display device is an image display device. The plurality of pixel circuits are arranged in a first direction,
The corresponding lighting pattern is different between each of the pixel circuits and one of the pixel circuits adjacent to the pixel circuit.
The image display device according to claim 3. The corresponding lighting pattern is different between the even-numbered pixel circuit and the odd-numbered pixel circuit,
The image display device according to claim 4. The number of the lighting patterns is 2.
The image display device according to claim 3, wherein the image display device is an image display device. A plurality of lighting shift registers, each of which is provided corresponding to the lighting pattern, and controls lighting of the pixel circuit corresponding to the lighting pattern based on the control of the lighting period control unit;
The image display device according to claim 6. A plurality of lighting control lines provided corresponding to each of the plurality of pixel circuits;
A plurality of lighting control connection switches respectively corresponding to any of the plurality of lighting control lines,
Each pixel circuit includes a driving transistor that controls the light emission amount of the light emitting element, and a lighting control switch that controls whether or not the light emitting element is turned on by a lighting control signal supplied from the lighting control line corresponding to the pixel circuit. In addition,
The lighting control line corresponding to each pixel circuit is connected to the lighting shift register corresponding to the pixel circuit, and the lighting shift register not corresponding to the pixel circuit and the lighting control switch corresponding to the lighting control line are connected. Connected through
The image display device according to claim 7.

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