JP2012049660A - Phase-locked loop circuit - Google Patents

Abstract

Provided is a digital PLL capable of simplifying a circuit configuration and saving an area while satisfying necessary characteristics.
A TDC 101 for detecting a phase difference between a reference clock signal FR and a divided clock signal FD, an FF 103 for outputting an advance / delay of FD and FR, a phase error calculator 102, and a digital filter for smoothing a phase error (PERR). 104, a DCO 105 that outputs an output clock signal FO, an N divider 106 that outputs an FD obtained by dividing the FO, and a register 107 that samples a counter value in the N divider 106 in response to FR. The phase difference detection measurement range is within one cycle of FO, the phase difference between FR and FD is output as a decimal number converted to one cycle of FO, and the phase error calculator 102 determines that the phase difference between FD and FR is FO Is equal to or greater than an integral multiple of the period, and from the output of the register 107 and the sign information sign, and within one FO period, the output of the TDC and the sign information si To calculate output PERR from n.
[Selection] Figure 1

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit, and more particularly to a circuit configuration suitable for application to a digital PLL.

  The digital PLL is a phase-locked loop obtained by digitizing each block of the analog PLL and digitizing the processing. Digitization solves the problems in the analog PLL and makes it possible to realize the following advantages.

(A) To solve the problem of potential fluctuation due to the leak current and the problem of the area of the filter in the loop filter, which has been a problem in the analog PLL.

(B) Since RTL (Register Transfer Level) design is realized by digitization, redesign when changing the parameters of the PLL is facilitated.

(C) Since digital code processing is performed, the characteristic fluctuation of the circuit due to PVT (Process / Voltage / Temperature) fluctuation is small.

  In order to realize the above advantages, there is a complete digital PLL (All Digital PLL, abbreviated as “ADPLL”, also referred to as “all digital PLL”) in which each block of the analog PLL is replaced with digital processing. In ADPLL, for example, a method of comparing the phase difference between two inputs and digitizing the phase difference (this method will be referred to as a “relative comparison method” in this specification) is used. However, this method has problems in terms of accuracy, circuit area, and power.

  As a method for solving these problems, in recent years, an ADPLL employing a phase domain method has been developed. This method contributes to improving the characteristics in the case of an application that performs accuracy and phase modulation, but has disadvantages in terms of circuit area and processing speed. Hereinafter, the analog PLL and ADPLL will be outlined.

  FIG. 5 is a diagram illustrating the configuration of the analog PLL. In the PFD + CP block 11, the PFD (Phase Frequency Detector) compares the phase and frequency of the reference clock signal FREF and the divided clock signal FCKV, and CP (Charge Pump) is a voltage corresponding to the comparison result in the PFD. And a control voltage obtained by smoothing the voltage by a low-pass filter (LF) (also referred to as a “loop filter”) 12 is applied to a voltage controlled oscillator (VCO) 13, and the VCO 13 has a frequency corresponding to the control voltage. Oscillation clock FVCO is output, and the divided clock signal FCKV obtained by dividing the FVCO by N by the frequency divider (÷ N) 14 is fed back to the PFD.

  FIG. 6 is a diagram showing an example of a typical configuration of a complete digital PLL (ADPLL) obtained by digitizing each block of FIG. In FIG. 6, P2D (phase to digital converter) 21, digital filter (loop filter) (Digital LF) 22, DCO (digitally controlled oscillator) 23, and frequency divider 24 are PFD + CP11, LF12 of analog PLL in FIG. Each corresponds to the VCO 13 and the frequency divider 14.

  FIG. 7 is a diagram illustrating an example of the configuration of the P2D circuit of FIG. In the analog PLL of FIG. 5, UP / DN that is a PFD (phase frequency comparator) output is input to a CP (charge pump), converted into a voltage corresponding to the phase difference, and input to a loop filter (analog filter) 12. However, in ADPLL, the phase comparison result UP / DN of the PFD 201 is input to the NOR circuit 202, and the output of the NOR circuit 202 is input to a TDC (Time to Digital Converter) 203. The NOR circuit 202 outputs High when both UP and DN are Low, and outputs Low when one of UP and DN is High. The TDC 203 digitally encodes the phase difference and inputs it to a digital filter (Digital LF) 22. Although not particularly limited, for example, the PFD 201 outputs a high pulse having a pulse width from the rising edge of FDIV to the rising edge of FREF as UP, and a high pulse having a pulse width from the rising edge of FREF to the rising edge of FDIV. A circuit for outputting as a DN is provided, and one of UP and DN is set to a high pulse and the other is set to low for one period of FDIV.

  The PFD 201 only detects the phase difference between FREF and FDIV with the pulse width of UP or DN, that is, a relative value. Code information sign (1 bit) is obtained. Although not particularly limited, the flip-flop 204 inputs FREF to the data terminal D, inputs FDIV to the clock terminal, and samples FREF by the rising edge of FDIV. When FREF is High (1) at the rising transition of FDIV, the output Q is High (1), and when FREF is Low (0) at the rising transition of FDIV, the output Q is Low (0). The (L + 1) -bit signal obtained by adding the sign bit (1 bit) to the absolute value (L-bit signal) of the phase difference output from the TDC 203 is input to the digital filter (Digital LF) 22.

  In FIG. 7, the TDC 203 measures the pulse width of the Low pulse output from the NOR circuit 202 as the phase difference between FREF and FCKV. For example, when an UP high pulse is output from the PFD 201, a low pulse (the pulse width is equal to the pulse width of the UP high pulse and corresponds to the phase difference between FREF and FCKV) is output from the NOR circuit 202. The Low pulse from the NOR circuit 202 is input to the B terminal of the TDC 203, for example, and the inverted signal (High pulse) of the Low pulse is input to the A terminal of the TDC 203. The TDC 203 detects the phase difference between the rising edge of the High pulse (inverted signal at the B terminal) input to the A terminal and the rising edge of the Low pulse at the B terminal. The phase difference between the rising edge of the High pulse (inverted signal at the B terminal) input to the A terminal of the TDC 203 and the rising edge of the Low pulse at the B terminal of the TDC 203 is equal to the pulse width of the UP High pulse. And the absolute value of the phase difference of FCKV are detected.

  As a basic configuration of TDC, for example, the description in FIG. FIG. 8 shows an example of a typical basic configuration of TDC. In FIG. 8, the TDC measures the phase difference between the rising edges of the signals input to the terminals A and B, respectively. The signal input to the terminal A is delayed by a delay circuit array including a plurality of unit delay circuits (buffers) 211. The signal of each stage of the delay circuit array is input to the data terminal of the FF 212 provided corresponding to each stage, and the signal input to the terminal B is input to the clock terminals of the plurality of FFs 212 in common. In each FF 212, the signal at the data terminal is sampled at the rising edge of the signal input in common to the clock terminal. An AND circuit 213 is provided for inputting a signal obtained by inverting the output of each FF 212 and the output of the adjacent (following) FF 212 by an inverter 214. The AND circuit 213 outputs “1” when the output of the FF 212 is “1”, the output of the adjacent (following) FF 212 is “0”, and therefore the output of the inverter 214 is “1”, otherwise “0”. Functions as a detection circuit that outputs. The outputs of the plurality of AND circuits 213 are converted into parallel bits and decoded by a binary decoder 215. The output OUT of the binarization decoder 215 outputs the number of stages of the buffer 211 corresponding to the phase difference of the rising edges of the signals input to the terminals A and B as digital data.

  As an example of the operation in FIG. 8, for example, when a signal input to the terminal B rises after a delay time such as a phase separation of one stage of the buffer from the rising edge of the signal input to the terminal A, The signal (High level) input to the terminal A has already propagated for one stage of the buffer at the time of the rise of the signal commonly input to the clock terminals of, and the output of the first stage buffer 211 is “1”. However, the outputs of the buffers 211 in the second and subsequent stages are all “0”. Therefore, the output of the AND circuit 213 receiving the output of the first stage FF 212 and the output of the second stage FF 212 is “1”, the outputs of all the remaining AND circuits 213 are “0”, and the terminal A It can be seen that the phase difference of the B signal corresponds to the delay of one stage of the buffer. 8 detects the phase difference between two signals when the rising edge of the signal input to the terminal B is delayed in time from the rising edge of the signal input to the terminal A. .

  6 and FIG. 7, the width of the output UP / DN of the PFD 201 that receives the reference clock signal FREF and the signal FCKV obtained by dividing the output clock FVCO of the VCO by N (phase difference between FREF and FCKV). Is measured by the TDC 203 and digitally encoded (L-bit signal). In this case, the width of UP or DN may be expanded to about the cycle of the reference clock signal FREF. Accordingly, the phase error detection range (the number of buffer stages, the number of FF stages, the number of AND circuits, and the bus width) of the TDC 203 needs to be expanded. When the phase error detection range is expanded while maintaining accuracy, a TDC capable of long-time measurement is required, a large amount of delay elements and FFs are required, the circuit area is increased, and the power consumption is also increased.

  Apart from the configurations of FIGS. 6 and 7, a configuration as shown in FIG. 9 is also proposed (cited from FIG. 4 of Patent Document 1). In the circuit of FIG. 7, all the phase differences between FREF and FCKV are measured by the TDC 203, whereas the configuration of FIG. 9 realizes the same function by using the counter 404 and the delay line 401. It is.

  Referring to FIG. 9, the PFD + TDC includes a delay sequence (Delay-Line) 401, a control logic 402, a sampler 403, a counter 404, an adder 405, and an offset control 406. The frequency divider (DIV) includes a prescaler 407, a program counter 408, and a swallow counter (pulse swallow counter) 409. A wide range of phase difference between VREF and VDIV is measured with a relatively coarse accuracy by a counter 404 that receives the output of the divider DIV (VPRE in FIG. 9) as an input to the output VDCO of the DCO. A fine phase difference (that is, between VREF and VPRE) is measured with high accuracy by the delay train 401. The output VPRE of the DIV prescaler 407 is used as the clock of the counter 404.

  When the ADPLL is locked, the VPRE output is also locked. Therefore, using this as a clock, the relationship between the phase difference counted by the counter 404 and time is uniquely determined. The sampler 403 samples and synchronizes VREF with VPRE and uses it as a start signal for the counter 404, and VDIV serves as an end signal for the counter 404. Thereby, the phase difference between VREF and VDIV is measured with the accuracy of VPRE. The phase difference between VREF and VPRE is measured by the delay train 401. The control logic 402 combines the phase differences measured by the counter 404 and the delay train 401. The offset circuit (adder 405, offset control 406) adjusts the phase relationship between VREF and VDIV when the ADPLL is locked.

  According to the configuration of FIG. 9, it is not necessary to perform long-time measurement, and it is possible to prevent the TDC from becoming large-scale.

  In addition, according to the configuration of FIG. 9, the operation can always be interpolated within the VPRE 1 clock with the TDC measurement accuracy, so that the accuracy can be maintained.

  In FIG. 1 of Patent Document 2, a TDC, a DCO, a flip-flop that samples a reference clock at the output of the DCO, two accumulators, a DCO cycle normalization circuit, a phase error detector, a digital A configuration having a filter and a DCO gain normalization circuit is disclosed.

JP 2009-268047 A JP 2002-76886 A

  The analysis of related technology is given below.

  In the configuration of FIG. 6, in order to widen the phase detection width while maintaining the detection accuracy, a TDC corresponding to a long time (a large number of flip-flops + delay circuits) is required, and the circuit area and power consumption are reduced. This is a problem.

  Considering application to ADPLL as a digital circuit control clock generator placed inside an LSI, rather than a special environment (RF application) where phase modulation is required, phase detection accuracy (fine phase difference by TDC) It is not necessary to support a wide phase detection range while keeping (detection). In other words, a fine phase difference result is required only when the phases of FREF and FDIV in the locked state are close to each other, and a fine phase difference is rarely required where the phase difference is far away. .

  If the resolution of TDC is required only when the phase difference is small, the superiority can be improved even with the configuration of FIG. For example, by increasing the unit delay time (delay time per buffer stage) of the TDC unit delay elements (buffers) at locations where the phase difference is separated, there is an effect of reducing the total number of delay elements of the TDC.

  For example, as shown in FIG. 10, the unit delay time of a unit delay element (r buffer positioned on the rear stage side) corresponding to a position where the phase difference between A and B is large is 2α. Here, α is the delay time of the unit delay element corresponding to the case where the phase difference between A and B is small. That is, α is the delay time of the unit delay element arranged closer to the input terminals A and B of the TDC.

  However, it cannot be said that the configuration of FIG. 10 greatly contributes to the area reduction of the TDC.

  As a method for expanding the phase detection range while maintaining the detection accuracy of the phase difference, there is a configuration shown in FIG. However, the configuration of FIG. 9 requires a separate counter for measuring the phase error and its control block, which complicates the circuit configuration. Further, when the phase difference between VREF and VDIV is close, it is necessary to control the start (Stop) and stop (End) of the count operation of the counter 404 at high speed. For this reason, the device of a circuit is needed separately.

  Accordingly, an object of the present invention is to provide a digital PLL that can simplify the circuit configuration and reduce the area while satisfying necessary characteristics such as accuracy and processing speed.

  The present invention for solving the above-described problems is generally configured as follows.

According to the present invention, a time digital converter that receives a reference clock signal and a divided clock signal and detects a phase difference between the reference clock signal and the divided clock signal;
A phase error calculator;
A digital filter for smoothing the phase error output from the phase error calculator;
A digitally controlled oscillator that varies an oscillation frequency by an output signal from the digital filter and outputs an output clock signal of the frequency;
An N divider for outputting the divided clock signal obtained by dividing the output clock signal from the digitally controlled oscillator by a predetermined positive integer N;
A register that captures a counter value in the N divider in response to the reference clock signal;
With
The phase difference measurement range of the time digital converter is within one clock cycle of the output clock signal;
When the phase difference between the frequency-divided clock signal and the reference clock signal is an absolute value and the output clock signal is one clock cycle or more, the output of the time digital converter is 0, and the phase error calculator Using the counter value captured in the register, the phase error between the divided clock signal and the reference clock signal is calculated,
When the phase difference between the divided clock signal and the reference clock signal is an absolute value and less than one clock cycle of the output clock signal, the counter value captured in the register is set to 0, and the phase error calculator A digital phase-locked loop circuit is provided for computing the phase error using the output of the time digital converter.

In the present invention, the result obtained by sampling the other signal with one of the divided clock signal and the reference clock signal is used as code information representing the advance / lag of the divided clock signal and the reference clock signal. It has a flip-flop to output,
When the phase difference between the frequency-divided clock signal and the reference clock signal is less than one clock cycle of the output clock signal, the time digital converter converts a decimal value converted into a ratio to one clock cycle of the output clock signal. Output,
If the phase difference between the frequency-divided clock signal and the reference clock signal is one clock cycle or more of the output clock signal, the phase error calculator calculates a code based on the counter value sampled by the register and the code information. Output integer phase error with
If the phase difference is less than one clock cycle of the output clock signal, a phase error of a signed decimal value is output based on the decimal value output from the time digital converter and the sign information.

  According to the present invention, the circuit configuration is simplified and the area can be saved while satisfying necessary characteristics such as accuracy and processing speed.

It is a figure which shows the structure of one Embodiment of this invention. It is a timing diagram explaining operation | movement of one Embodiment of this invention. It is a timing diagram explaining operation | movement of one Embodiment of this invention. It is a figure explaining one Embodiment of this invention. It is a figure which shows the structural example of an analog PLL. It is a figure which shows the structural example of ADPLL. It is a figure which shows the structural example of P2D of FIG. It is a figure which shows the basic composition of TDC. It is a figure which shows the structure of patent document 1. FIG. It is a figure which shows an example of a structure of TDC.

  An embodiment of the present invention will be described. FIG. 1 is a diagram showing a configuration of an ADPLL circuit according to an embodiment of the present invention. Referring to FIG. 1, the ADPLL circuit of the present embodiment detects the phase difference between the reference clock signal FREF and the divided clock signal FD within the phase difference measurement range within one clock cycle (one cycle) of the output clock signal FO. TDC 101, flip-flop 103 that detects the advance and delay of the phase of FR and FD and outputs code information (sign), phase error calculator 102, and digital filter 104 that receives and smooths the output of phase error calculator 102 A digitally controlled oscillator (DCO) 105 that receives a signal from the digital filter 104 and variably controls the oscillation frequency, an N divider 106 that divides the output clock signal FO of the DCO 105 by N, and an N divider 106 A register that captures an internal variable (counter value) with a reference clock signal FR It is provided with a 07, a. The frequency-divided clock signal FD output from the frequency divider 106 is input to the TDC 101 and controlled so that the phase difference from the reference clock signal FR becomes 0, and a stable output clock signal FO is obtained when locked. .

  The FF 103 inputs the reference clock signal FR to the data terminal, inputs the divided clock signal FD to the clock terminal, captures the reference clock signal FR at the rising edge of the divided clock signal FD, and outputs the capture result Output from the terminal Q as code information (sign). When the reference clock signal FR has already risen to High (1) at the rise of the divided clock signal FD, the FF 103 outputs High (1) from its output terminal Q (the phase of FD is higher than that of FR). Running late). When the reference clock signal FR does not rise to High at the time of rising of the divided clock signal FD and is Low (0), the FF 103 outputs Low (0) from its output terminal Q (FD is FR) Phase is more advanced). When the duty of the reference clock signal FR is 50%, for example, when the phase difference between FD and FR is more than ± 180 degrees, the FF 103 cannot correctly detect the advance / delay of the FD and FR. For example, when the duty of the divided clock signal FD and the reference clock signal FR is smaller than 50%, the detectable range of the phase difference between FD and FR by the FF 103 is narrowed. Note that the frequency-divided clock signal FD may be input to the data terminal of the FF 103 and the reference clock signal FR may be input to the clock terminal. In this case, however, the duty of the FD is also set to 50%, for example.

  The phase error calculator (phase difference detector) 102 inputs the output (decimal number: absolute value) of the TDC 101, the sign information (sign) output from the FF 103, and the counter value (integer: absolute value) from the register 107. The phase error φE between the reference clock signal FR and the divided clock signal FD is calculated and output to the digital filter 104.

  The ADPLL circuit of this embodiment is suitable for use as a clock generator mounted on an LSI, for example, and supplies an output clock signal to a digital block mounted on the same LSI chip as the ADPLL circuit.

  In the present embodiment, an application is assumed in which a fine phase difference result is required only when the phases of the reference clock signal FR and the divided clock signal FD are close to each other (and therefore almost in a locked state). However, by making the configuration of FIG. 9 described above a simplified circuit configuration, an ADPLL having no disadvantages in terms of circuit area, processing speed, and the like is realized.

  In this embodiment, a method of relatively comparing the phase difference between two inputs and digitizing the phase difference (referred to as a “relative comparison method”) is employed, and functions only as a frequency divider circuit in related technologies. The feedback frequency dividing circuit (1 / N) that has been used is used as the phase error measuring circuit for the integer part.

  According to the present embodiment, the PFD circuit that generates the phase comparison result UP / DN is not necessary as compared with the relative comparison method of the related art, and the phase difference between the reference clock signal FR and the divided clock signal FD is detected. The TDC only needs to be able to detect only the decimal part (time length of one clock cycle or less of the output clock FO), and no additional counter (404 in FIG. 9) is required.

  With this configuration, according to the present embodiment, complicated processing such as the two accumulators (102 and 118 of Patent Document 2) and the DCO cycle normalization process (NORM) in the configuration of FIG. Only a counter that counts the multiplication value is required, and this counter is shared with the counter of the N frequency divider 106 of FIG. 1, so that it is compared with the configuration of FIG. In particular, the circuit configuration has been simplified. That is, in the present embodiment, the phase error detection of the integer part, which is a problem in relative comparison, is obtained from the internal variable (counter value) of the N frequency divider 106.

  In this embodiment, registers (flip-flops corresponding to the number of bits of the counter value of the N divider 106) 107 are added to the relative comparison ADPLL shown in FIG. 6, and the PFD 201 in FIG. 7 is removed. Has been. Note that FR and FD in FIG. 1 correspond to the reference clock signal FREF and the divided clock signal FCKV in FIG. 6.

  As the PLL, the first necessary information is how much the phase difference is between the edges (for example, the rising edge) of the reference clock signal FR and the divided clock signal FD. In related technologies such as FIG. 6, FIG. 7, FIG. 9, and FIG. 10, a TDC or a counter is used to detect this phase error.

  The inventors of the present application pay attention to the fact that the counter value having the phase information of the divided clock signal FD already exists in the N divider 106, and in the reference clock signal FR that is the other signal to be compared, It has been found that a phase difference similar to that in the related art can be obtained by capturing a counter value that is an internal variable of the N divider 106 (a variable value inside the circuit that is not output to the outside). That is, the phase difference information can be obtained by performing the following operations and processes.

  Normally, the N divider 106 is set to a multiplication value (= divided value) N, and when the output clock FO from the DCO 105 is counted up by the multiplication value, the count value = (multiplication value-1). Next, the rising edge (leading edge) of the clock pulse (High pulse) of the divided clock signal FD is generated and output in synchronization with the rising edge of the output clock signal FO.

  When the multiplication value N is 8 (the frequency of the output clock signal FO of the DCO 105 is 8 times the frequency of the divided clock signal FD), the counter operation in the N divider 106 will be described with reference to the timing charts of FIGS. I will explain. Although not particularly limited, the output clock signal FO and the reference clock signal FR of the DCO 105 have a duty of 50% and the duty of the divided clock signal FD is 12.5%, but are not limited to these values. The duty of the divided clock signal FD may be 50%.

  In the frequency dividing circuit 106, the multiplication value = 8 is set, and the count up from 0 in response to the rising edge of the output clock signal FO from the DCO 105. When the count value = (multiplication value-1) = 7, In response to the rising edge of the next output clock signal FO, the count value returns to 0, and the counting operation is performed cyclically between 0 and 7 in ascending order. Note that the N frequency divider 106 may be a down counter that counts down from (N−1) to 0.

  In FIG. 2, the numbers 0, 1, 2,..., 0, 1... Below each High pulse of the output clock signal FO are counter values of the N divider 106. As shown in FIG. 2, the counter value in the N divider 106 that counts the output clock signal FO is N−1 = 7, and the counter value is “7” in response to the rising edge of the next output clock signal FO. When the signal changes from “0” to “0”, the rising edge of the clock pulse of the divided clock signal FD (the leading edge of the pulse (leading edge)) is generated. In the counter inside the N frequency divider 106, the count value = 0 is the phase data of the divided clock signal FD. Although not particularly limited, the duty of the divided clock signal FD obtained by dividing the output clock signal FO by 8 is 12.5%. In this case, when the counter value in the N divider 106 that counts the output clock signal FO becomes “1”, the falling edge of the high pulse of the divided clock signal FD (the trailing edge of the pulse (trailing edge) )) Is generated. In the N divider 106, the output is set to High (1) in response to the change of the counter value from “7” to “0”, and in response to the change of the counter value from “0” to “7”. By providing an SR flip-flop or the like whose output is reset to Low (0), the divided clock signal FD in FIG. 2 is generated. When the duty of the frequency-divided clock signal FD is 50%, the SR flip-flop sets the output to High (1) in response to the change of the counter value from “7” to “0”, and the counter value The output is reset to Low (0) in response to the change from “3” to “4”.

  3, numbers 0, 1, 2,..., 0, 1,... Below the rising edge of the output clock signal FO are counter values of the N divider 106. As shown in FIG. 3, by capturing the counter value of the N divider 106 with the reference clock signal FR, an integer part of the phase difference between the reference clock signal FR and the divided clock signal FD (equal to the number of FO clocks) Phase error data) can be obtained.

  In FIG. 3, when the rising edge of the reference clock signal FR is between the counter values “1” and “2” as indicated by the arrow 1, the divided clock signal FD is greater than the reference clock signal FR. The phase is advanced by one clock cycle + α of the output clock signal FO (where α is a fractional part: less than one clock cycle of FO). At this time, since the reference clock signal FR is Low at the rising edge of the divided clock signal FD at the counter value 0, the code information (sign) output from the FF 103 is Low (0). When the divided clock signal FD is an integer multiple of the clock cycle of the output clock signal FO + α phase with respect to the reference clock signal FR, the phase error calculator 102 has an integer part of the counter value captured by the register 107; A phase error is calculated based on the sign information (sign).

  In FIG. 3, if the rising edge of the reference clock signal FR is between the counter values “5” and “6” as indicated by the arrow 2, the divided clock signal FD is higher than the reference clock signal FR. As for the output clock FO, the phase is delayed by 2 clock cycles + α (where α is a fractional part). When the divided clock signal FD rises at the counter value 0, the reference clock signal FR has already risen to High (FR is High between the counter values “5” and “6” corresponding to the arrow 2). The sign information (sign) output from the FF 103 is set to High (0), rising and falling to Low between the counter values “1” and “2”. When the phase of the divided clock signal FD is delayed from the reference clock signal FR by an integer multiple of the clock cycle of the output clock signal FO + α (decimal number), the phase error calculator 102 calculates the counter value captured by the register 107. A phase error is calculated based on the integer part and the sign information (sign). In FIG. 3, the counter value of the N frequency divider 106 captured by the register 107 is “5” and the code information (sign) output from the FF 103 is 1 by the rising edge (arrow 2) of the reference clock signal FR. Based on this, it is calculated as follows (detailed later with reference to FIG. 4).

  Phase error = 5 + (-(8-1)) = 5-7 = -2

  In the present embodiment, if the phase difference between the reference clock signal FR and the divided clock signal FD is within one clock cycle (decimal) of the output clock signal FO, the phase difference is detected by the TDC 101. The TDC 101 has a length corresponding to one clock cycle of the output clock FO as the number of stages of the terminal delay circuit (for example, the number of stages of the buffer 211 in FIG. 8) for detecting the phase difference between the rising edges of the signals at the terminals A and B. That's fine.

  When the phase difference between the reference clock signal FR and the divided clock signal FD is one clock cycle or more of the output clock signal FO (when the phase difference is 1 or more), the measurement range is over, and the TDC 101 can measure the phase difference. 0 is output. For example, in the TDC of FIG. 8, the signal input to the terminal B is equal to the sum of the delay times of all the stages of the TDC buffer 211 from the rising edge of the signal input to the terminal A (equal to the time of one clock cycle of the FO). ), The signal input from the terminal A has been propagated through all the buffers 212 at the time of the rising of the signal commonly input from the terminal B to the clock terminals of the FFs 212. The outputs of the buffer 211 are all “1”. Therefore, all the FFs 212 sample “1” in response to the rising edge of the signal at the terminal B. The outputs of the AND circuits 213 that receive the inversion of the output of the preceding FF 212 and the output of the succeeding FF 212 are all “0”, and a digital value 0 is output to OUT.

  On the other hand, when the phase difference between the reference clock signal FR and the divided clock signal FD is within one clock cycle of the output clock signal FO, the number of buffers 211 (unit delay circuits) corresponding to the phase difference is the total number of buffers 211. The divided decimal number (absolute value) is output as the phase difference. When the total number of buffers 211 in the TDC of FIG. 8 is M, the delay time of the buffer 211 is td, and one period of the output clock signal FO of the DCO 105 is TO (variable by the control signal), the relationship of M × td≈TO holds. . When the phase difference between the reference clock signal FR and the divided clock signal FD corresponds to n stages of the buffer 211, the TDC outputs n / M. The TDC 101 outputs the absolute value of the phase difference with respect to the positive / negative phase difference between FR and FD (within one clock cycle of FO).

  In the configuration of FIG. 8, when the rising timing of the signal input to the terminal A precedes the rising timing of the signal input to the terminal B, that is, the signal at the terminal A is When the phase is ahead of the signal at the terminal B, the phase difference between the rising edges of the signals input to the terminals A and B can be detected, but the rising timing of the signal input to the terminal A is When the signal input to B is delayed in time from the rising timing of the signal, that is, when the signal at terminal A is delayed in phase from the signal at terminal B, the signal input to terminals A and B The phase difference of the rising edge cannot be detected. 1 detects a phase difference when the rising edge of the reference clock signal FR input to the terminal A is behind the rising edge of the divided clock signal FD input to the terminal B. In the TDC 101, in addition to the configuration of FIG. 8, a plurality of buffers for delaying a signal input to the terminal B, and outputs of the plurality of buffers are used as rising edges of the signals input to the terminal A. A plurality of flip-flops (FF) that are sampled in common, and a plurality of AND circuits for detecting a mismatch between the outputs of both adjacent FFs for each of the plurality of FFs (each AND circuit is an inverter that outputs the output of the FF and the output of the adjacent FF) And a signal obtained by parallelizing a plurality of AND circuits by a binary decoder 215. To over de. With this configuration, when the phase difference between the rising edge of the reference clock signal FR and the rising edge of the divided clock signal FD input to the terminals A and B of the TDC 101 is lags behind the FR, and FD For each of the cases where the phase difference is more advanced than FR, the phase difference can be output as an absolute value.

  If only the counter value of the N divider 106 is captured in the register 107, a certain integer value is captured. Therefore, the captured counter value and the delayed / advanced sign signal (1, 0) output from the FF 103 are captured. 4 is processed by the phase error calculator 102 as shown in FIG.

  In the counter value, the sign value, and the phase error to be processed in FIG. 4, the horizontal axis represents the phase difference (+, −), and the vertical axis represents the counter value, the sign value, and the phase error (integer part), respectively.

  When the reference clock signal FR is High (1) and Low (0) at the rising time of the divided clock signal FD, the FF 103 corresponds to the phase difference − and + of FD and FR, sign = High (1), Low (0) is output.

  In the phase error computing unit 102, as shown in FIG. 4, with respect to Low (= 0) and High (= 1) of the code information (sign) output from the FF 103, a sign value 0,-(N-1) Is assigned.

  In the phase error calculator 102, the value of the sign information (sign) output from the FF 103 is set to 0 according to the sign of the phase difference between the FD and FR, based on the counter value of the N frequency divider 106 captured by the register 107. 1), add the sign value 0,-(N-1).

  As a result of the calculation of the counter value + sign value, as shown in FIG. 4, the “phase error to be processed” by the phase error calculator 102 is 0 from (N−1) when the phase difference between FD and FR is negative. If the phase difference between FD and FR is non-negative (positive or 0), the value is an integer from 0 to + (N-1).

  In the phase error calculator 102, Low (= 0) of the sign information (sign) output from the FF 103, High for the fractional part of the phase difference between the divided clock signal FD and the reference clock signal FR detected by the TDC 101, Depending on (= 1), positive and negative signs are added and output as a phase error. When a fractional part other than 0 is output from the TDC 101, the counter value of the N divider 106 captured by the register 107 is “0” or “7”, that is, the rising edge of the reference clock signal FR is This corresponds to the case where the position is within one clock cycle before and after the position of the 3 arrow (counter value 0). For example, when the counter value of the N divider 106 captured by the reference clock signal FR is “7”, the divided clock signal FD is delayed in phase from the reference clock signal FR, and the code information ( sign) is High, and the phase error calculator 102 calculates the counter value + sign value (= − (8-1)) as described with reference to FIG. Therefore, the integer part of the processed phase error is 7 + (− 7) = 0.

  When the counter value of the N divider 106 captured by the reference clock signal FR is “0”, the divided clock signal FD is in phase with the phase of the reference clock signal FR or coincides with the code output from the FF 103. The information (sign) is Low. In this case, as described with reference to FIG. 4, the phase error calculator 102 calculates the counter value + sign value (= 0), and the integer part of the phase error to be processed is 0 + 0 = 0. Then, the phase error calculator 102 calculates the code based on the decimal part (absolute value) of the phase difference between the divided clock signal FD and the reference clock signal FR detected by the TDC 101 and the code information (sign) output from the FF 103. The fractional number is output to the digital filter 104 as a phase error.

In the phase error calculator 102,
The counter value (integer part (absolute value)) of the N frequency divider 106 sampled by the register 107 using the reference clock signal FR is CNT [k],
The sign information sign sampled by the frequency-divided clock signal FD in the FF 103 is set to sign [k] (= 1 or 0),
The output from the TDC 101 (assuming that the decimal number (absolute value) is ε [k], the output phase error data φE [k] is given by the following equations (1) and (2), where k is the sampling clock (FR Or FD) represents the sampling number.

When the sign information sign [k] is 0,
φE [k] = CNT value [k] + ε [k] (1)
However,
When 0 <ε [k] <1, the CNT value [k] is 0,
When ε [k] = 0, the CNT value [k] is a non-negative integer (positive integer or 0).

When the sign information sign [k] is 1,
φE [k] = CNT value [k] − (N−1) −ε [k] (2)
However,
When 0 <ε [k] <1, the CNT value [k] − (N−1) is 0,
When ε [k] = 0, the CNT value [k] − (N−1) is a negative integer or 0.

  In this embodiment, the phase error characteristic is the characteristic of the PFD of the analog PLL itself, so that there is no problem in using the counter value of the N frequency divider even in consideration of the operation principle.

  In the present embodiment, the PFD required for P2D in FIG. 6 is not necessary, and the TDC only needs to be able to detect a phase difference in the vicinity where the phases of the reference clock signal FR and the divided clock signal FD coincide with each other. The circuit configuration is not large. In addition, in this embodiment, the counter is not required as an additional block by using the counter value that is an internal variable of the N frequency divider.

  Further, in the present embodiment, since the operation of only picking up the value from the counter that is always operating is performed by using the counter of the N divider, there is a problem in the P2D with the counter shown in FIG. Problems such as high-speed control of the counter START / END can be solved. For this reason, according to the present embodiment, it is possible to improve accuracy (accuracy) and increase the processing speed. As described above, ADPLL characteristics and performance equivalent to those of related technologies can be obtained while contributing to area reduction with a simpler circuit configuration.

  The disclosures of Patent Documents 1 and 2 are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

11 PFD + CP
12 LF (loop filter)
13 VCO
14 N divider 21 P2D
22 Digital filter (loop filter)
23 DCO
24 N frequency divider 101 TDC
102 Phase error calculator 103 FF
104 Digital filter 105 DCO
106 N divider 107 register (flip-flop)
201 PFD
202 NOR
203 TDC
204 FF
211 Buffer (Unit delay circuit)
212 FF
213 AND
213 Inverter 215 Binary decoder 401 Delay Line
402 Control Logic
403 Sampler
405 Adder 404 Counter
406 Offset Control
407 Prescaler
408 Program Counter
409 Swallow Counter

Claims (5)

A time digital converter for inputting a reference clock signal and a divided clock signal and detecting a phase difference between the reference clock signal and the divided clock signal;
A phase error calculator;
A digital filter for smoothing the phase error output from the phase error calculator;
A digitally controlled oscillator that varies an oscillation frequency by an output signal from the digital filter and outputs an output clock signal of the frequency;
An N divider for outputting the divided clock signal obtained by dividing the output clock signal from the digitally controlled oscillator by a predetermined positive integer N;
A register that captures a counter value in the N divider in response to the reference clock signal;
With
The phase difference measurement range of the time digital converter is within one clock cycle of the output clock signal;
When the phase difference between the frequency-divided clock signal and the reference clock signal is an absolute value and the output clock signal is one clock cycle or more, the output of the time digital converter is 0, and the phase error calculator Using the counter value captured in the register, the phase error between the divided clock signal and the reference clock signal is calculated,
When the phase difference between the divided clock signal and the reference clock signal is an absolute value and less than one clock cycle of the output clock signal, the counter value captured in the register is set to 0, and the phase error calculator A digital phase-locked loop circuit that calculates the phase error using the output of the time digital converter. A flip-flop that outputs a result obtained by sampling the other signal with one of the divided clock signal and the reference clock signal as sign information indicating the advance / lag of the divided clock signal and the reference clock signal; Prepared,
When the phase difference between the frequency-divided clock signal and the reference clock signal is less than one clock cycle of the output clock signal, the time digital converter converts a decimal value converted into a ratio to one clock cycle of the output clock signal. Output,
If the phase difference between the frequency-divided clock signal and the reference clock signal is one clock cycle or more of the output clock signal, the phase error calculator calculates a code based on the counter value sampled by the register and the code information. Output integer phase error with
2. If the phase difference is less than one clock cycle of the output clock signal, a phase error of a signed decimal value is output based on the decimal value output from the time digital converter and the sign information. The digital phase-locked loop circuit described. The counter value in the N divider circulates the values from 0 to N-1 one by one in ascending or descending order in response to the input of the output clock signal,
The phase error calculator, when the phase difference between the divided clock signal and the reference clock signal is one clock cycle or more of the output clock signal and is a positive value, the counter value is regarded as a phase error;
When the phase difference between the divided clock signal and the reference clock signal is one clock cycle or more of the output clock signal and is a negative value, a value obtained by subtracting (N−1) from the counter value is a phase error. The digital phase-locked loop circuit according to claim 1 or 2. The N divider generates a leading edge of a clock pulse of the divided clock signal every time the counter value takes 0,
When the counter value captured in response to the reference clock signal is an integer value between 1 and N-1, the phase difference between the divided clock signal and the reference clock signal is one clock cycle or more of the output clock signal. From the phase error calculator, a phase error of a signed integer value is generated from the counter value and the sign information,
When the counter value captured in response to the reference clock signal is 0, the phase error calculator determines that the phase difference between the divided clock signal and the reference clock signal is less than one clock cycle of the output clock signal, The digital phase-locked loop circuit according to claim 3, wherein a phase error of a signed decimal value is output from the decimal value output from the time digital converter and the sign information.   A semiconductor device comprising the digital phase-locked loop circuit according to claim 1.

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