JP2012042498A - Method for forming mask pattern and method for forming lithography target pattern - Google Patents

Abstract

A mask pattern capable of forming a desired pattern on a substrate is created accurately and easily in a short time.
According to one embodiment of the present invention, the light intensity calculation step includes: a light intensity that the cell gives to a peripheral region when lithography processing is performed on a cell configured with a cell pattern on a mask; The correspondence with the distance from the outer periphery of the cell is calculated using the lithography target of the cell. A lithography target having the same correspondence as the approximate value of the correspondence is calculated as an approximate pattern. In the OPC step, an OPC process is performed on a pattern in which the approximate pattern is arranged in a peripheral region of each cell. The mask pattern creation step creates a mask pattern for each cell by extracting the cells after the OPC from the pattern subjected to the OPC process.
[Selection] Figure 1

Description

  Embodiments described herein relate generally to a mask pattern creation method and a lithography target pattern creation method.

  As the pattern constituting the semiconductor integrated circuit device is miniaturized, it has become difficult to faithfully form the pattern in each process. As a result, there has been a problem that the final finished dimension does not follow the design pattern. For example, in a lithography process or an etching process, other patterns arranged around the pattern to be formed greatly affect the dimensional accuracy of the pattern to be formed.

  Optical proximity effect correction (OPC: Optical Proximity Correction) has been developed to avoid such an influence. In this OPC, an auxiliary pattern is added to the mask pattern in advance or the width of the pattern is changed so that the shape of the integrated circuit pattern after processing becomes a design pattern (desired value).

JP 2005-84101 A

  However, the conventional technique has a problem that it takes a long time for the OPC process and it is difficult to accurately create a mask pattern capable of forming a desired pattern on the substrate.

  An object of one embodiment of the present invention is to provide a mask pattern creation method and a lithography target pattern creation method capable of accurately and easily creating a mask pattern capable of forming a desired pattern on a substrate in a short time. .

  According to one embodiment of the present invention, a mask pattern creation method includes a light intensity calculation step, an approximate value calculation step, an approximate pattern calculation step, an OPC step, and a mask pattern creation step. In the light intensity calculation step, the correspondence between the light intensity that the cell gives to the peripheral region when the lithography process is performed on the cell configured with the cell pattern on the mask and the distance from the outer periphery of the cell, Calculation is performed using the lithography target of the cell. In the approximate value calculating step, an approximate value of the correspondence relationship is calculated using the correspondence relationship. In the approximate pattern calculating step, a lithography target having the same correspondence as the approximate value is calculated as an approximate pattern. In the OPC step, an OPC process is performed on a pattern in which the approximate pattern is arranged in a peripheral region of each cell. The mask pattern creation step creates a mask pattern for each cell by extracting the cells after the OPC from the pattern subjected to the OPC process.

FIG. 1 is a block diagram showing a configuration of a mask pattern creating apparatus according to the first embodiment. FIG. 2 is a flowchart showing a mask pattern creation processing procedure according to the first embodiment. FIG. 3 is a diagram for explaining a light intensity curve calculation method. FIG. 4 is a diagram showing an approximate curve for the light intensity curve. FIG. 5 is a diagram showing a light intensity curve of a universal pattern. FIG. 6 is a diagram illustrating an example of a universal pattern. FIG. 7 is a block diagram showing a configuration of a mask pattern creating apparatus according to the second embodiment. FIG. 8 is a flowchart showing a mask pattern creation processing procedure according to the second embodiment. FIG. 9 is a diagram illustrating an example of a wall pattern. FIG. 10 is a block diagram showing a configuration of a mask pattern creation system according to the third embodiment. FIG. 11 is a flowchart showing a storage processing procedure according to the third embodiment of post-OPC pattern data. FIG. 12 is a block diagram showing a configuration of a mask pattern creating apparatus according to the fourth embodiment. FIG. 13 is a flowchart showing a mask pattern creation processing procedure according to the fourth embodiment. FIG. 14 is a diagram for explaining the re-OPC process. FIG. 15 is a flowchart showing a mask pattern creation processing procedure when a re-OPC process is performed on a part of mask patterns. FIG. 16 is a flowchart showing the processing procedure of the re-OPC process performed on some mask patterns. FIG. 17 is a diagram for explaining a re-OPC process performed on a part of mask patterns. FIG. 18 is a diagram showing a configuration of post-OPC pattern data stored in the cell DB. FIG. 19 is a block diagram showing a configuration of a mask pattern creating apparatus according to the fifth embodiment. FIG. 20 is a flowchart showing a storage processing procedure according to the fifth embodiment of post-OPC pattern data. FIG. 21 is a diagram illustrating a hardware configuration of the mask pattern creating apparatus.

  Hereinafter, a mask pattern creation method and a lithography target pattern creation method according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a mask pattern creating apparatus according to the first embodiment. The mask pattern creating apparatus 1 is an apparatus such as a computer that performs OPC processing for each cell as a circuit unit for circuit patterns (data) constituting a semiconductor integrated circuit device (semiconductor device). The cell is a circuit pattern that achieves a predetermined function such as an AND circuit, a NAND circuit, or a flip-flop circuit. Below, the case where the semiconductor device is comprised by cell AI is demonstrated.

  In the present embodiment, after the lithography targets of the cells A to I are created, the mask pattern creation device 1 calculates the average value of the light intensity that each cell A to I gives to the peripheral region for each cell. Then, the mask pattern creating apparatus 1 calculates a pattern (universal pattern Up described later) that gives the same light intensity as the calculated average value of the light intensity. In other words, a pattern that gives the same optical proximity effect as the average value of the optical proximity effects from the cells A to I is calculated as the universal pattern Up. Further, the mask pattern creating apparatus 1 performs the OPC process for each cell in a state where the universal pattern Up is arranged around each cell. Thereafter, the mask pattern creating apparatus 1 creates a mask pattern for each cell by removing the universal pattern Up from the periphery of each cell A to I. Further, the mask pattern creating apparatus 1 creates a mask pattern of the semiconductor device by arranging each cell A to I (post-OPC pattern described later) after the OPC process in the mask pattern arrangement region.

  The mask pattern creation device 1 includes an input unit 11, a light intensity calculation unit 12, an approximate curve calculation unit 13, a universal pattern creation unit 14, a universal pattern placement unit 15, an OPC processing unit 16, a post-OPC pattern placement unit 17, and an output unit 18. It is configured with.

  The input unit 11 includes design cell data (design cell data DA to DI described later) of each cell A to I constituting the semiconductor device, information indicating an arrangement position of each cell A to I (hereinafter referred to as cell arrangement information), A lithography model M1 described later is input. The design cell data DA to DI are lithography target data of the cells A to I, and are data created based on the design layout data of the cells A to I.

  The lithography model M1 is a lithography simulation model having information on lithography conditions such as exposure conditions. The lithography model M1 of the present embodiment is for calculating the light intensity that each cell A to I gives to the periphery of each cell A to I when the lithography process is performed using each cell A to I on the mask. It contains information.

  The input unit 11 sends the design cell data DA to DI and the lithography model M1 to the light intensity calculation unit 12, and sends the design cell data DA to DI to the universal pattern placement unit 15. Further, the input unit 11 sends the lithography model M1 to the universal pattern creation unit 14 and sends cell placement information to the post-OPC pattern placement unit 17.

  The light intensity calculation unit 12 applies the lithography model M1 to each of the design cell data DA to DI, and when the lithography process is performed on each of the cells A to I, the light intensity that the cells A to I give to the periphery is the cell A to Calculate for each I. The light intensity calculation unit 12 calculates the light intensity corresponding to the distance from the cell frame that is the outer peripheral part of each of the cells A to I. For example, the light intensity calculation unit 12 calculates a light intensity curve indicating the correspondence between the distance from the cell frame and the light intensity for each of the cells A to I. The light intensity calculation unit 12 sends the calculated light intensity curve to the approximate curve calculation unit 13.

  The approximate curve calculation unit 13 calculates an approximate curve of the light intensity curves of the cells A to I. The approximate curve calculation unit 13 may calculate the approximate curve using any approximation method. For example, the approximate curve calculation unit 13 may use an average curve of each light intensity curve as an approximate curve, or may calculate an approximate curve by applying a least square method to each light intensity curve. The approximate curve calculation unit 13 sends the calculated approximate curve to the universal pattern creation unit 14.

  The universal pattern creation unit 14 uses the lithography model M1 to calculate a universal pattern Up in which the light intensity applied to the periphery when the lithography process is performed is the same as the approximate curve. The universal pattern creation unit 14 sends the calculated universal pattern Up to the universal pattern placement unit 15 and the post-OPC pattern placement unit 17.

  The universal pattern placement unit 15 places the universal pattern Up around each of the cells A to I using the design cell data DA to DI (cell pattern) and the universal pattern Up. The universal pattern placement unit 15 sends the design cell data DA to DI on which the universal pattern Up is placed to the OPC processing unit 16.

  The OPC processor 16 calculates post-OPC pattern data for each cell by performing OPC processing for each of the cells A to I with respect to the design cell data DA to DI in which the universal pattern Up is arranged. The OPC processing unit 16 sends post-OPC pattern data of the cells A to I to the post-OPC pattern placement unit 17.

  The post-OPC pattern placement unit 17 removes the universal pattern Up from the post-OPC pattern of each cell A to I based on the post-OPC pattern data and the universal pattern Up of each cell A to I. The post-OPC pattern placement unit 17 places the mask pattern of each of the cells A to I (post-OPC pattern data D1a to D1i) after removing the universal pattern Up in the mask pattern placement region, thereby arranging the mask pattern of the semiconductor device. create. The post-OPC pattern arrangement unit 17 arranges the mask patterns of the cells A to I in the mask pattern arrangement area based on the cell arrangement information. The post-OPC pattern placement unit 17 sends the mask pattern of the semiconductor device to the output unit 18. The output unit 18 outputs the mask pattern of the semiconductor device to an external device or the like.

  Next, a mask pattern creation processing procedure will be described. FIG. 2 is a flowchart showing a mask pattern creation processing procedure according to the first embodiment. Design cell data DA to DI, cell arrangement information, and lithography model M1 are input to mask pattern creating apparatus 1.

  The input unit 11 sends the design cell data DA to DI and the lithography model M1 to the light intensity calculation unit 12, and sends the design cell data DA to DI to the universal pattern placement unit 15. Further, the input unit 11 sends the lithography model M1 to the universal pattern creation unit 14 and sends cell placement information to the post-OPC pattern placement unit 17.

  The light intensity calculation unit 12 applies the lithography model M1 to each design cell data DA to DI, and calculates a light intensity curve indicating the correspondence between the distance from the cell frame and the light intensity for each of the cells A to I.

  Here, a method for calculating the light intensity curve will be described. FIG. 3 is a diagram for explaining a light intensity curve calculation method. Since the light intensity curve calculation method is the same for cells A to I, the light intensity curve calculation method for cell A will be described here.

  The light intensity calculation unit 12 sets a plurality of measurement points P around (outside the cell) the area (cell area Ca) where the cell A is formed. The measurement points P are positions where the light intensity is calculated, and are arranged at regular intervals, for example. Each measurement point P has various distances from the cell frame of the cell A, and various light intensities are calculated by being influenced by the cell A for each measurement point P. The light intensity calculation unit 12 calculates the light intensity curve of the cell A based on the light intensity at each measurement point P. The light intensity calculation unit 12 calculates the light intensity curve of the cell A using, for example, a predetermined approximation method.

  Similarly, the light intensity calculation unit 12 calculates the light intensity curves of the cells B to I (step S10). Then, the light intensity calculation unit 12 sends the calculated light intensity curve to the approximate curve calculation unit 13. The approximate curve calculation unit 13 calculates an approximate curve of the total light intensity curve (the light intensity curves of the cells A to I) (step S20).

  FIG. 4 is a diagram showing an approximate curve for the light intensity curve. In FIG. 4, the light intensity curves of the cells A and B are shown, and the light intensity curves of the cells C to I are omitted. For example, the light intensity curve Ia of the cell A is a curve indicating the correspondence between the distance from the cell frame of the cell A and the light intensity around the cell A (outside the cell frame). The light intensity curve Ib of the cell B is a curve showing the correspondence between the distance from the cell frame of the cell B and the light intensity around the cell B (outside the cell frame). The approximate curve Ix is a curve showing the correspondence between the distance from each cell frame of the cells A to I and the light intensity around the cells A to I (outside the cell frame).

  Although the case where the approximate curve Ix is calculated for all the light intensity curves of the cells A to I has been described here, the approximate curve Ix may be calculated for all the measurement points P of the cells A to I. In this case, without calculating the light intensity curves of the cells A to I, the light intensity at all the measurement points P set in the cells A to I is calculated, and the distance and the light intensity from the cell frame at each measurement point P. Is calculated. Based on this correspondence, an approximate curve Ix is calculated. The approximate curve calculation unit 13 sends the calculated approximate curve to the universal pattern creation unit 14.

  The universal pattern creation unit 14 creates, using the lithography model M1, a universal pattern Up in which the light intensity given to the periphery when the lithography process is performed is the same as the approximate curve Ix (step S30). The universal pattern creation unit 14 creates a universal pattern Up for each of the cells A to I based on the approximate curve Ix.

  FIG. 5 is a diagram showing a light intensity curve of the universal pattern, and FIG. 6 is a diagram showing an example of the universal pattern. As shown in FIG. 5, the light intensity curve Iu of the universal pattern Up is the same curve as the approximate curve Ix.

  The universal pattern Up is a pattern arranged around the area (cell area) where the cells A to I are arranged, and the size and shape of the universal pattern Up are different if the size and shape of the cell area are different. In FIG. 6, the universal pattern Up arrange | positioned around the cell A (cell area | region Ca) is shown. For example, the universal pattern Up has the same shape on the right side and the left side of the cell A in the X direction, and has the same shape on the upper side and the lower side of the cell A in the Y direction. The universal pattern creation unit 14 sends the universal pattern Up calculated for each of the cells A to I to the universal pattern placement unit 15 and the post-OPC pattern placement unit 17.

  The universal pattern placement unit 15 uses the design cell data DA to DI and the universal pattern Up for each of the cells A to I to place the universal pattern Up around each cell A to I (outside each cell) (step S40). . The universal pattern placement unit 15 sends the design cell data DA to DI on which the universal pattern Up is placed to the OPC processing unit 16.

  The OPC processing unit 16 performs OPC processing for each of the cells A to I with respect to the design cell data DA to DI in which the universal pattern Up is arranged (step S50). The OPC processing unit 16 sends the data after the OPC process to the post-OPC pattern placement unit 17 as post-OPC pattern data.

  The post-OPC pattern placement unit 17 removes the universal pattern Up from the post-OPC pattern of each cell A to I based on the post-OPC pattern data for each cell A to I and the universal pattern Up for each cell A to I. The post-OPC pattern placement unit 17 places the mask pattern of each of the cells A to I (post-OPC pattern data D1a to D1i) after removing the universal pattern Up in the mask pattern placement region, thereby arranging the mask pattern of the semiconductor device. create.

  The post-OPC pattern placement unit 17 sends post-OPC pattern data D1a to D1i to the output unit 18 as a mask pattern of the semiconductor device. The output unit 18 outputs post-OPC pattern data D1a to D1i to an external device or the like. The output unit 18 may output post-OPC pattern data D1a to D1i for each of the cells A to I, or may output post-OPC pattern data D1a to D1i as a whole for the semiconductor device.

  Thereafter, a mask is manufactured using post-OPC pattern data D1a to D1i which are mask pattern data of the semiconductor device. The mask is prepared for each exposure process (each layer) of the wafer process. The exposure apparatus performs an exposure process on the wafer using a mask for each layer. Thereafter, wafer development processing, etching processing, and the like are performed. Specifically, the mask material is processed from the resist pattern formed by transfer in the lithography process, and the processed film is patterned by using the patterned mask material to etch the processed film. . As a result, a desired on-wafer pattern (resist pattern or post-etching pattern) is formed as the on-substrate pattern. When manufacturing a semiconductor device, the above-described mask pattern creation process, mask creation process, exposure process using the mask, development process, etching process, and the like are repeated for each layer.

  As described above, according to the first embodiment, the universal pattern Up is created based on the approximate curve Ix calculated from the total light intensity curve and arranged around each of the cells A to I. ˜I is provided with substantially the same optical proximity effect from the universal pattern Up. For this reason, it is possible to perform an appropriate OPC process for each of the cells A to I. Therefore, a mask pattern capable of forming a desired on-wafer pattern (on-substrate pattern such as a resist pattern) can be easily created accurately and in a short time. In addition, it is possible to reduce the mask pattern manufacturing TAT and cost.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, each cell A to I is surrounded by a wall pattern. And universal pattern Up is arrange | positioned with respect to each cell AI with which a wall pattern is arrange | positioned, and an OPC process is performed.

  FIG. 7 is a block diagram showing a configuration of a mask pattern creating apparatus according to the second embodiment. Among the constituent elements in FIG. 7, constituent elements that achieve the same functions as those of the mask pattern creating apparatus 1 of the first embodiment shown in FIG. 1 are given the same numbers, and redundant descriptions are omitted.

  The mask pattern creation device 2 includes an input unit 11, a light intensity calculation unit 12, an approximate curve calculation unit 13, a universal pattern creation unit 14, a universal pattern placement unit 15, an OPC processing unit 16, a post-OPC pattern placement unit 17, and an output unit 18. In addition, a wall pattern placement portion 21 is provided. The input unit 11 sends the design cell data DA to DI to the wall pattern arrangement unit 21.

  The wall pattern placement unit 21 places a wall-like pattern (hereinafter referred to as a wall pattern Wp) so as to surround each cell A to I (cell boundary) based on the design cell data DA to DI. The wall pattern placement unit 21 sends the design cell data DA to DI after the wall pattern Wp is placed to the light intensity calculation unit 12.

  The light intensity calculation unit 12 applies the lithography model M1 to the design cell data DA to DI after the wall pattern Wp is arranged, and displays the light intensity curve indicating the correspondence between the distance from the cell frame and the light intensity. Calculated for each of A to I.

  Next, a mask pattern creation processing procedure will be described. FIG. 8 is a flowchart showing a mask pattern creation processing procedure according to the second embodiment. Design cell data DA to DI, cell arrangement information, and lithography model M1 are input to mask pattern creating apparatus 2.

  The input unit 11 sends the design cell data DA to DI to the wall pattern arrangement unit 21. Further, the input unit 11 sends the design cell data DA to DI and the lithography model M1 to the light intensity calculation unit 12, and sends the design cell data DA to DI to the universal pattern placement unit 15. Further, the input unit 11 sends the lithography model M1 to the universal pattern creation unit 14 and sends cell placement information to the post-OPC pattern placement unit 17.

  The wall pattern placement unit 21 places the wall pattern Wp around the cell pattern so as to surround each cell A to I (cell boundary) based on the design cell data DA to DI (step S110). FIG. 9 is a diagram illustrating an example of a wall pattern. FIG. 9 shows a wall pattern Wp arranged around the cell A. As shown in the figure, the wall pattern Wp is a ring-shaped pattern surrounding the cell area Ca of the cell A. The wall pattern Wp arranged around each of the cells B to I has the same configuration as the wall pattern Wp arranged around each cell A. The wall pattern arrangement unit 21 sends the design cell data DA to DI in which the wall pattern Wp is arranged to the light intensity calculation unit 12.

  Thereafter, the mask pattern creating apparatus 2 creates post-OPC pattern data D2a to D2i for each of the cells A to I by the same process as the mask pattern creating apparatus 1. That is, the light intensity calculation unit 12 applies the lithography model M1 to the design cell data DA to DI, and calculates a light intensity curve indicating the correspondence between the distance from the cell frame and the light intensity for each of the cells A to I. .

  Then, the approximate curve calculation unit 13 calculates an approximate curve Ix of the total light intensity curve (the light intensity curves of the cells A to I). Furthermore, the universal pattern creation unit 14 creates a universal pattern Up based on the approximate curve Ix.

  Thereafter, the universal pattern placement unit 15 places the universal pattern Up around each of the cells A to I where the wall pattern Wp is placed (step S120). Then, the OPC processing unit 16 performs an OPC process on the design cell data DA to DI on which the universal pattern Up is arranged for each design cell data DA to DI (step S130).

  Then, the post-OPC pattern placement unit 17 creates a mask pattern (post-OPC pattern data D2a to D2i) for each cell by deleting the universal pattern Up from the pattern after the OPC process for each cell. Further, the post-OPC pattern placement unit 17 creates the mask pattern of the semiconductor device by placing the mask pattern for each cell in the mask pattern placement region.

  The post-OPC pattern placement unit 17 sends post-OPC pattern data D2a to D2i to the output unit 18 as a mask pattern of the semiconductor device. The output unit 18 outputs post-OPC pattern data D2a to D2i to an external device or the like.

  As described above, according to the second embodiment, since the periphery of the cells A to I is surrounded by the wall pattern Wp, the optical proximity effect from the pattern constituting the cells A to I to the outside of the cells A to I can be reduced. Can be reduced. For this reason, the universal pattern Up with a small influence of the optical proximity effect on the cells A to I can be created.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIGS. In the third embodiment, among the created post-OPC pattern data, post-OPC pattern data that has passed the verification is stored in a database (cell DB 25 described later).

  FIG. 10 is a block diagram showing a configuration of a mask pattern creation system according to the third embodiment. The mask pattern creation system includes a mask pattern creation device 1, a mask pattern verification device 24, and a cell DB 25.

  The mask pattern creation device 1 is connected to a mask pattern verification device 24, and the mask pattern verification device 24 is connected to a cell DB 25. The cell DB 25 is connected to the mask pattern creation apparatus 1.

  The mask pattern creation device 1 of the present embodiment sends the created post-OPC pattern data D1a to D1i to the mask pattern verification device 24. The mask pattern verification device 24 is a device that verifies whether or not the post-OPC pattern data D1a to D1i is an appropriate mask pattern by lithography simulation. The mask pattern verification device 24 stores the post-OPC pattern data that has passed the verification in the cell DB 25. The cell DB 25 is a database that stores post-OPC pattern data that has passed the verification.

  Next, a procedure for storing post-OPC pattern data will be described. FIG. 11 is a flowchart showing a storage processing procedure according to the third embodiment of post-OPC pattern data. Note that description of processing similar to the creation processing of post-OPC pattern data described in the first embodiment is omitted.

  The mask pattern creating apparatus 1 creates post-OPC pattern data D1a to D1i for each of the cells A to I using the design cell data DA to DI, the cell arrangement information, and the lithography model M1.

  Specifically, the light intensity calculation unit 12 calculates a light intensity curve for each of the cells A to I, and the approximate curve calculation unit 13 calculates an approximate curve Ix of the total light intensity curve. Furthermore, the universal pattern creation unit 14 creates a universal pattern Up based on the approximate curve Ix, and the universal pattern placement unit 15 places the universal pattern Up around each of the cells A to I (step S210). Then, the OPC processing unit 16 performs OPC processing for each of the cells A to I with respect to the design cell data DA to DI in which the universal pattern Up is arranged (step S220). Thereafter, by deleting the universal pattern Up for each of the cells A to I, mask patterns (post-OPC pattern data D1a to D1i) of the cells A to I are obtained.

  Thereafter, the post-OPC pattern placement unit 17 creates the mask pattern of the semiconductor device by placing the mask patterns of the cells A to I in the mask pattern placement region. The post-OPC pattern placement unit 17 sends post-OPC pattern data D1a to D1i to the output unit 18 as a mask pattern of the semiconductor device. The output unit 18 sends post-OPC pattern data D1a to D1i to the mask pattern verification device 24.

  The mask pattern verification device 24 verifies whether or not the post-OPC pattern data D1a to D1i is an appropriate mask pattern by lithography simulation (step S230). The mask pattern verification device 24 may verify the post-OPC pattern data D1a to D1i for each of the cells A to I, or may verify the post-OPC pattern data D1a to D1i for the entire mask pattern. .

  If there is no error in the verification process (No at Step S240), the mask pattern verification device 24 determines that the verification is successful, and stores the post-OPC pattern data D1a to D1i that have passed the verification in the cell DB 25 (Step S250). .

  On the other hand, if there is an error in the verification process (step S240, Yes), the mask pattern verification device 24 determines that the verification has failed. In this case, the design modification of the design cell data DA to DI or the processing condition of the OPC process is changed (OPC modification) (step S260). Thereafter, the processes in steps S210 to S260 are repeated until no error is found in the verification process.

  The design modification of the design cell data in step S260 is performed on the design cell data determined to have a verification error. When OPC correction is performed, the corrected OPC may be applied to all the design cell data DA to DI, or the corrected OPC is applied to the design cell data determined to have a verification error. You may apply.

  Further, when the processes in steps S210 to S260 are repeated, the universal pattern Up may be recalculated and arranged around the cells A to I, or the calculated universal pattern Up may be arranged around the cells A to I. You may arrange.

  When creating a mask pattern for another semiconductor device, the mask pattern verification device 24 extracts post-OPC pattern data D1a to D1i from the cell DB 25 as necessary, and uses the extracted post-OPC pattern data D1a to D1i. To create a mask pattern.

  In the present embodiment, the case where the mask pattern creation system includes the mask pattern creation device 1 has been described. However, the mask pattern creation system includes the mask pattern creation device 2, the mask pattern verification device 24, the cell DB 25, You may comprise.

  As described above, according to the third embodiment, since the post-OPC pattern data D1a to D1i that have passed the verification are stored in the cell DB 25, a mask pattern is created for another semiconductor device thereafter. In doing so, post-OPC pattern data D1a to D1i can be extracted from the cell DB 25 as necessary. Therefore, a mask pattern can be created using the extracted post-OPC pattern data D1a to D1i, and the mask pattern creation time can be shortened.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIGS. In the fourth embodiment, the OPC process is executed again on the created post-OPC pattern data.

  FIG. 12 is a block diagram showing a configuration of a mask pattern creating apparatus according to the fourth embodiment. Of the constituent elements in FIG. 12, constituent elements that achieve the same functions as those of the mask pattern creating apparatus 1 of the first embodiment shown in FIG. 1 are given the same numbers, and redundant descriptions are omitted.

  The mask pattern creating apparatus 3 is connected to the cell DB 25 of the mask pattern creating system described in the third embodiment. The mask pattern creation device 3 includes an input unit 11, a post-OPC pattern placement unit 31, an OPC processing unit 32, and an output unit 18. The input unit 11 sends post-OPC pattern data D1a to D1i to the post-OPC pattern placement unit 31.

  The post-OPC pattern placement unit 31 has the same function as the post-OPC pattern placement unit 17 of the mask pattern creation apparatus 1. The post-OPC pattern placement unit 31 according to the present embodiment generates post-OPC patterns (OPCed cells A to I described later) corresponding to post-OPC pattern data D1a to D1i input from the input unit 11 based on the cell placement information. Arranged in the mask pattern arrangement area. The post-OPC pattern placement unit 31 sends post-OPC pattern data D1a to D1i in which post-OPC patterns are placed to the OPC processing unit 32.

  The OPC processing unit 32 has the same function as the OPC processing unit 16 of the mask pattern creating apparatus 1. The OPC processing unit 32 performs OPC processing on the pattern area where the post-OPC pattern is arranged. In other words, the OPC processing unit 32 creates a mask pattern of the semiconductor device by performing re-OPC processing (reexamination of correction values) on a pattern region in which a plurality of post-OPC patterns are arranged. The OPC processing unit 32 sends the mask patterns of the cells A to I to the output unit 18 as post-OPC pattern data D5a to D5i.

  FIG. 13 is a flowchart showing a mask pattern creation processing procedure according to the fourth embodiment. Note that description of processing similar to the creation processing of post-OPC pattern data described in the first embodiment is omitted.

  The post-OPC pattern data D1a to D1i and the cell arrangement information are input to the mask pattern creation device 3 from the cell DB 25 or the like. The mask pattern creation device 3 creates mask patterns (post-OPC pattern data D5a to D5i) for the cells A to I using post-OPC pattern data D1a to D1i and cell arrangement information.

  Specifically, the post-OPC pattern placement unit 31 masks the post-OPC patterns (OPCed cells A to I) corresponding to the post-OPC pattern data D1a to D1i input from the input unit 11 based on the cell placement information. It arrange | positions to a pattern arrangement | positioning area | region (step S310). The post-OPC pattern placement unit 31 sends the pattern data in which the post-OPC pattern is placed to the OPC processing unit 32.

  The OPC processing unit 32 creates a mask pattern of the semiconductor device by performing the re-OPC process on the pattern area where the post-OPC pattern is arranged (step S320). In other words, the OPC processing unit 32 executes the OPC process using the post-OPC pattern as an initial value. The OPC processing unit 32 sends the mask patterns of the cells A to I to the output unit 18 as post-OPC pattern data D5a to D5i. The output unit 18 sends post-OPC pattern data D5a to D5i to the cell DB 25 or the like.

  FIG. 14 is a diagram for explaining the re-OPC process. FIG. 14 shows a top view of the pattern. Here, a case where a mask pattern is created using the lithography target pattern 40 will be described.

  A lithography target pattern 40 is prepared (a). The lithography target pattern 40 is converted into the mask pattern 43 by using, for example, the OPC process described in the first or second embodiment (b). The mask pattern 43 has, for example, 80 to 90 points out of 100 as the pass / fail judgment value of the mask pattern.

  The OPC processing unit 32 performs lithography simulation using the mask pattern 43 as an initial value. Thereby, a pattern (on-wafer pattern 44) when a pattern corresponding to the mask pattern 43 is formed on the wafer is derived (c).

  Thereafter, the OPC processing unit 32 compares the on-wafer pattern 44 with the lithography target pattern 40. When the shape difference between the on-wafer pattern 44 and the lithography target pattern 40 is larger than a predetermined value, it is determined that the mask pattern 43 does not have a desired pass / fail determination value.

  When the mask pattern 46 does not have a desired pass / fail judgment value, the OPC processing unit 32 performs a re-OPC process on the lithography target pattern 40. Specifically, the OPC processing unit 32 divides the pattern edge (contour line) of the lithography target pattern 40 by jogs 41 having a predetermined interval. Further, the OPC processing unit 32 sets a simulation position 42 for each pattern edge sandwiched between jogs 41. Then, the OPC processing unit 32 calculates to which position each simulation position 42 should be moved when a pattern corresponding to the lithography target pattern 40 is formed on the wafer. By connecting the moved positions of the simulation positions 42, a mask pattern 46 corresponding to the lithography target pattern 40 is derived (d). In other words, the mask pattern 43 is converted into the mask pattern 46.

  Thereafter, the OPC processing unit 32 performs lithography simulation on the mask pattern 46. Thereby, a pattern (on-wafer pattern 47) when a pattern corresponding to the mask pattern 46 is formed on the wafer is derived (e).

  Then, the OPC processing unit 32 compares the on-wafer pattern 47 with the lithography target pattern 40. If the shape difference between the on-wafer pattern 47 and the lithography target pattern 40 is smaller than a predetermined value, it is determined that the mask pattern 43 has a desired pass / fail determination value. Accordingly, the OPC processing unit 32 determines the mask pattern 46 as a mask pattern corresponding to the lithography target pattern 40 (f).

  On the other hand, when the shape difference between the on-wafer pattern 47 and the lithography target pattern 40 is larger than a predetermined value, it is determined that the mask pattern 43 does not have a desired pass / fail judgment value. In this case, the OPC processing unit 32 creates a mask pattern having a desired pass / fail judgment value by repeating the processes (d) and (e) described above.

  Note that the re-OPC process on the mask pattern is not limited to the case of performing the process on all the mask patterns, and may be performed on a part of the mask patterns. FIG. 15 is a flowchart showing a mask pattern creation processing procedure when a re-OPC process is performed on a part of mask patterns. Note that the description of the same processing as the post-OPC pattern data creation processing described in FIG. 2 and FIG. 13 is omitted.

  The post-OPC pattern placement unit 31 of the mask pattern creation device 3 performs post-OPC patterns (OPCed cells A to I) corresponding to the post-OPC pattern data D1a to D1i input from the input unit 11, based on the cell placement information. It arrange | positions in a mask pattern arrangement | positioning area | region (step S410). The post-OPC pattern placement unit 31 sends the pattern data in which the OPCed cells A to I are placed to the OPC processing unit 32.

  Based on the tolerance information D6, the OPC processor 32 extracts a hot spot or a severe tolerance point from the pattern area in which the OPCed cells A to I are arranged. The tolerance information D6 is information indicating the position of a hot spot or a severe tolerance location. The hot spot here is a pattern position where the possibility that the pattern on the wafer becomes a defective pattern is higher than a predetermined value. Further, a severe tolerance point is a pattern position (narrow tolerance pattern position) in which the shape spec and dimension spec of the pattern on the wafer are higher than a predetermined value.

  The OPC processing unit 32 performs a re-OPC process on the extracted hot spot or severely tolerated location, thereby creating a mask pattern of the semiconductor device (step S420). The OPC processing unit 32 sends the mask patterns of the cells A to I to the output unit 18 as post-OPC pattern data D7a to D7i. The output unit 18 sends post-OPC pattern data D7a to D7i to the cell DB 25 or the like.

  Here, the process of step S420 will be described in detail. FIG. 16 is a flowchart showing the processing procedure of the re-OPC process performed on some mask patterns. FIG. 17 is a diagram for explaining a re-OPC process performed on some mask patterns. Note that FIG. 17 shows a top view of the mask pattern and the like.

  As shown in FIG. 17A, the OPC processing unit 32 extracts a hot spot or a severe tolerance point from a pattern area where a plurality of post-OPC patterns are arranged (step S510). Specifically, the OPC processing unit 32 performs a lithography simulation on a pattern region in which a plurality of post-OPC patterns D1a to D1i are arranged, thereby calculating the on-wafer pattern 50. Then, the OPC processing unit 32 extracts hot spots or severe tolerance points from the pattern 50 on the wafer. Further, the OPC processing unit 32 extracts positions on the lithography target (OPC review positions H1 and H2) corresponding to hot spots or severe tolerance points.

  Thereafter, as shown in FIG. 17B, the OPC processing unit 32 sets the re-OPC examination area 30 for the peripheral areas of the OPC review positions H1 and H2 and the PC review positions H1 and H2 ( Step S520). The re-OPC examination area 30 is an area on the lithography target where the re-OPC process is performed. The re-OPC review area 30 is, for example, a rectangular area having a predetermined distance in the X direction and a predetermined distance in the Y direction with the OPC review positions H1 and H2 as the center.

  Then, as shown in FIG. 17C, the OPC processing unit 32 extracts all the re-OPC processing segments 51 in the re-OPC examination area 30 (step S530). The segment 51 is a pattern edge (pattern edge portion sandwiched between the jog 41 and the jog 41) of the lithography target pattern 40 whose mask pattern is changed by the re-OPC process.

  The OPC processing unit 32 executes the re-OPC process on all the extracted segments 51 (Step S540), thereby moving the segments 51. As a result, the OPC processing unit 32 creates a mask pattern that has been subjected to the re-OPC process.

  As described above, according to the fourth embodiment, since the re-OPC process is executed using the post-OPC pattern data D1a to D1i, a mask pattern capable of forming a desired on-wafer pattern can be easily and accurately formed in a short time. Can be created.

  Further, since the re-OPC process is performed on the OPC review positions H1 and H2 such as a hot spot, it is possible to easily and accurately create a mask pattern capable of forming a desired on-wafer pattern. Become.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described with reference to FIGS. In the fifth embodiment, the post-OPC pattern data D1a to D1i are stored in the cell DB 25 while associating the design cell data DA to DI of the cells A to I with the post-OPC pattern data D1a to D1i.

  FIG. 18 is a diagram showing a configuration of post-OPC pattern data stored in the cell DB. In the cell DB 25, the design cell data DA to DI of the cells A to I created by the mask pattern creation devices 1 and 2 are stored. Thereafter, when the post-OPC pattern data D1a to D1i of the cells A to I are created by the mask pattern creation device 3 or the like, the post-OPC pattern data D1a to D1i are stored in the cell DB 25.

  At this time, the design cell data and the post-OPC pattern data are associated with each cell and stored in the cell DB 25. For example, by replacing the post-OPC pattern data D1a of the OPCed cell A with the design cell data DA of the cell corresponding to the OPCed cell A, the post-OPC pattern data is stored in the cell DB 25. When the post-OPC pattern data D1a to D1i are stored in the cell DB 25, the cell information 27 includes the names of the cells A to I, the design cell data DA to DI, and the post-OPC pattern data D1a to D1i. Correspondence relationship information indicating the association of, is stored.

  For example, when the cell B is configured by the cell B0 and the cell B1, the OPCed cell B is configured by the OPCed cell B0 and the OPCed cell B1. Also in this case, the cell information 27 indicates that the post-OPC pattern data 63 and 63 of the cells B0 and B1 are associated with the post-OPC pattern data 73 and 74 of the OPCed cells B0 and B1, respectively. Stores related information. In the present embodiment, the post-OPC pattern data D1a to D1i of the cells A to I are extracted from the cell DB 25 based on the cell information 27.

  FIG. 19 is a block diagram showing a configuration of a mask pattern creating apparatus according to the fifth embodiment. Among the constituent elements of FIG. 19, the constituent elements that achieve the same functions as the mask pattern creating apparatus 1 of the first embodiment shown in FIG. 1 and the mask pattern creating apparatus 3 of the fourth embodiment shown in FIG. Are given the same numbers, and redundant explanations are omitted.

  In addition to the components of the mask pattern creation device 1, the mask pattern creation device 4 includes a search unit 45, a post-OPC pattern placement unit 31, and an OPC processing unit 32. Based on the cell information 27, the search unit 45 searches and extracts the post-OPC pattern data D1a to D1i of the design cell data DA to DI input from the input unit 11 from the cell DB 25. When the post-OPC pattern data can be searched, the search unit 45 extracts the post-OPC pattern data that can be searched from the cell DB 25 and sends it to the post-OPC pattern placement unit 31. In addition, when the post-OPC pattern data cannot be searched, the search unit 45 sends the design cell data that could not be searched to the light intensity calculation unit 12.

  FIG. 20 is a flowchart showing a storage processing procedure according to the fifth embodiment of post-OPC pattern data. Note that description of processing similar to the post-OPC pattern data creation processing described in the first to fourth embodiments is omitted. Here, a case will be described in which a mask pattern of cell A that has already been created and a mask pattern of cell J for which pattern data after OPC has not been created are retrieved as post-OPC pattern data.

  When the design cell data DA and DJ of the cells A and J are created, the created design cell data DA and DJ are stored in the design cell data DB 81. When the design cell data DA and DJ in the design cell data DB 81 are input to the input unit 11 of the mask pattern creation device 4, the design cell data DA and DJ are sent to the search unit 45.

  The search unit 45 acquires the cell information 27 from the cell DB 25 (step S610). Then, the search unit 45 searches whether the post-OPC patterns of the cells A and J are stored in the cell DB 25. At this time, the search unit 45 searches the design cell data DA to DJ of the cells A and J from the design cell data DA to DJ stored in the cell information 27. Further, the search unit 45 determines whether or not post-OPC pattern data corresponding to the design cell data DA and DJ is stored in the cell DB 25 based on the cell information 27. As a result, a match search is performed to determine whether or not the post-OPC pattern that matches the design cell data DA and DJ of the cells A and J is stored in the cell DB 25 (step S620).

  Specifically, the search unit 45 stores the design cell data of the lithography target having the same pattern shape as the pattern shape or pattern dimension based on the pattern shape or pattern dimension of the lithography target corresponding to the design cell data DA and DJ. It is searched whether or not the cell information 27 exists. The search unit 45 searches based on the cell names (information for identifying the cells) of the cells A and J to determine whether or not the design cell data DA and DJ having the same cell name exists in the cell information 27. May be.

  When the design cell data DA and DJ matching the search target design cell data DA and DJ are registered in the cell information 27, the search unit 45 displays the post-OPC pattern of the design cell data DA and DJ in the cell information 27. Search whether it is registered. If the post-OPC pattern can be matched in the cell DB 25 (Yes in step S630), the search unit 45 extracts post-OPC pattern pattern data corresponding to the design cell data to be searched from the cell DB 25.

  For example, since the post-OPC pattern data DA corresponding to the design cell data DA is registered in the cell information 27, the search unit 45 performs the post-OPC pattern data corresponding to the design cell data DA based on the cell information 27. D1a is extracted from the cell DB 25.

  In addition, since post-OPC pattern data matching the design cell data DJ is not registered in the cell information 27, the search unit 45 determines that post-OPC pattern data corresponding to the design cell data DJ cannot be extracted from the cell DB 25. To do.

  The search unit 45 sends the post-OPC pattern data D1a of the extracted cell A to the post-OPC pattern placement unit 31. The post-OPC pattern placement unit 31 places the post-OPC pattern (OPCed cell) corresponding to the post-OPC pattern data D1a in the mask pattern placement area. The post-OPC pattern placement unit 31 sends post-OPC pattern data in which the OPCed cell A is placed to the OPC processing unit 32.

  The OPC processing unit 32 arranges post-OPC patterns (OPCed cells) of the cells constituting the semiconductor device in the mask pattern areas where the mask patterns are formed (step S640). Then, the OPC processing unit 32 performs a re-OPC process within the mask pattern region to create a mask pattern for the semiconductor device (step S650). The OPC processing unit 32 sends the created mask pattern (post-OPC pattern data) to the output unit 18. The output unit 18 sends the post-OPC pattern data to the cell DB 25 or the like.

  On the other hand, if the post-OPC pattern that matches the design cell data DA and DJ to be searched is not registered in the cell information 27 (No in step S630), the search unit 45 uses the design cell data that could not be searched for the light intensity. This is sent to the calculation unit 12.

  For example, since the post-OPC pattern that matches the design cell data DJ is not registered in the cell information 27, the search unit 45 sends the design cell data DJ of the cell J to the light intensity calculation unit 12.

  The light intensity calculation unit 12, the approximate curve calculation unit 13, the universal pattern creation unit 14, the universal pattern arrangement unit 15, the OPC processing unit 16, the post-OPC pattern arrangement unit 17, and the output unit 18 have been described in the first embodiment. OPC processing for the design cell data DJ and registration processing for post-OPC pattern data in the cell DB 25 are performed by the same method as the mask pattern creation method (step S660). Thereafter, in the cell information 27, information indicating a correspondence relationship between the name of the cell J, the design cell data DJ, and the post-OPC pattern data of the cell J is registered according to an instruction from the search unit 45. The cell information 27 may be stored in a management device that manages the cell DB 25 or the mask pattern creation device 4.

  Next, the hardware configuration of the mask pattern creating apparatuses 1 to 4 will be described. Since the mask pattern creating apparatuses 1 to 4 have the same hardware configuration, the hardware configuration of the mask pattern creating apparatus 1 will be described here.

  FIG. 21 is a diagram illustrating a hardware configuration of the mask pattern creating apparatus. The mask pattern creating apparatus 1 includes a CPU (Central Processing Unit) 91, a ROM (Read Only Memory) 92, a RAM (Random Access Memory) 93, a display unit 94, and an input unit 95. In the mask pattern creating apparatus 1, these CPU 91, ROM 92, RAM 93, display unit 94, and input unit 95 are connected via a bus line.

  The CPU 91 creates a mask pattern using a mask pattern creation program 97 that is a computer program. The display unit 94 is a display device such as a liquid crystal monitor, and displays design cell data, universal pattern Up, wall pattern Wp, post-OPC pattern data, cell name, and the like based on instructions from the CPU 91. The input unit 95 includes a mouse and a keyboard, and inputs instruction information (such as parameters necessary for creating a mask pattern) externally input from the user. The instruction information input to the input unit 95 is sent to the CPU 91.

  The mask pattern creation program 97 is stored in the ROM 92 and is loaded into the RAM 93 via the bus line. FIG. 21 shows a state in which the mask pattern creation program 97 is loaded into the RAM 93.

  The CPU 91 executes a mask pattern creation program 97 loaded in the RAM 93. Specifically, in the mask pattern creation device 1, the CPU 91 reads the mask pattern creation program 97 from the ROM 92 and expands it in the program storage area in the RAM 93 in accordance with an instruction input from the input unit 95 by the user, and performs various processes. Execute. The CPU 91 temporarily stores various data generated during the various processes in a data storage area formed in the RAM 93.

  The mask pattern creation program 97 executed by the mask pattern creation device 1 includes a light intensity calculation unit 12, an approximate curve calculation unit 13, a universal pattern creation unit 14, a universal pattern placement unit 15, an OPC processing unit 16, and a post-OPC pattern placement unit. The module configuration includes 17, which are loaded onto the main storage device and are generated on the main storage device.

  As described above, according to the fifth embodiment, when the created post-OPC pattern data is stored in the cell DB 25, the post-OPC pattern data is extracted from the cell DB 25, and the re-OPC process is performed. Since it is executed, a mask pattern capable of forming a desired on-wafer pattern can be easily and accurately created in a short time.

  As described above, according to the first to fifth embodiments, it is possible to easily and accurately create a mask pattern capable of forming a desired on-wafer pattern in a short time.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1-4 ... Mask pattern production apparatus, 12 ... Light intensity calculation part, 13 ... Approximate curve calculation part, 14 ... Universal pattern production part, 15 ... Universal pattern arrangement | positioning part, 16, 32 ... OPC process part, 17, 31 ... OPC Post pattern placement unit, 21 ... Wall pattern placement unit, 25 ... Cell DB, 45 ... Search unit, D1a-D1i, D2a-D2i, D5a-D5i, D7a-D7i ... Pattern data after OPC, DA to DI ... Design cell data , Ia, Ib: light intensity curve, Ix: approximate curve, P measurement point, Up: universal pattern, Wp: wall pattern.

Claims (9)

When a lithography process is performed on a cell configured with a cell pattern on a mask, the correspondence between the light intensity given to the peripheral region by the cell and the distance from the outer periphery of the cell is determined using the lithography target of the cell. A light intensity calculating step to calculate using,
An approximate value calculating step of calculating an approximate value of the correspondence using the correspondence;
An approximate pattern calculating step for calculating a lithography target having the same correspondence as the approximate value as an approximate pattern;
An OPC step for performing an OPC process on a pattern in which the approximate pattern is arranged in a peripheral region of each cell;
A mask pattern creating step for creating a mask pattern for each cell by extracting the cells after the OPC from the pattern subjected to the OPC process;
A mask pattern creating method comprising: A wall pattern arranging step of arranging a wall pattern surrounding the cell in a peripheral region of each cell;
2. The correspondence relationship is calculated in the light intensity calculation step using a lithography target of the cell and a lithography target of the wall pattern for a cell in which the wall pattern is arranged. The mask pattern creation method as described in 2. When a lithography process is performed using the mask pattern, the mask pattern is formed based on whether the pattern on the substrate formed on the substrate has a pattern shape and a pattern dimension according to the design layout of the cell. A mask pattern determination step for performing pass / fail determination of
A first data storage step of storing the mask pattern determined to be acceptable in a data storage device for each of the cells when the mask pattern is determined to be acceptable;
The mask pattern creating method according to claim 1, wherein: A mask pattern placement step of placing the mask pattern for each cell stored in the data storage device in the placement area of the mask pattern;
A re-OPC step of performing the OPC process again with the mask pattern as an initial value;
The mask pattern creating method according to claim 3, further comprising: Among the mask patterns arranged in the arrangement area of the mask pattern, a hot spot having a possibility that the pattern on the substrate becomes a defective pattern when a lithography process is performed using the mask pattern, or higher than a predetermined value, or An extraction step for extracting a narrow tolerance pattern position in which a dimension tolerance of the pattern on the substrate is narrower than a predetermined value;
5. The mask pattern creating method according to claim 4, wherein in the re-OPC step, the OPC process is performed again on the hot spot or the narrow tolerance pattern position. A second data storing step of storing the lithography target for each cell in the data storage device for each cell before storing the mask pattern in the data storage device;
In the first data storage step, by replacing the mask pattern of each cell with a lithography target corresponding to each cell, the mask pattern is stored in the data storage device for each cell, and for each cell. 6. The mask pattern creating method according to claim 3, wherein information indicating a correspondence relationship between the lithography target and the mask pattern is stored as replacement information. A search step for searching and extracting the mask pattern to be arranged in the arrangement area from the data storage device based on the information on the cell and the replacement information;
The said mask pattern arrangement | positioning step arrange | positions the extracted mask pattern in the said arrangement | positioning area | region, when the mask pattern arrange | positioned in the said arrangement | positioning area | region can be extracted from the said data storage apparatus. Mask pattern creation method. A search step for searching and extracting the mask pattern to be arranged in the arrangement area from the data storage device based on the information on the cell and the replacement information;
7. The mask according to claim 6, wherein in the mask pattern creation step, a mask pattern that could not be extracted is created when the mask pattern to be placed in the placement area cannot be extracted from the data storage device. Pattern creation method. When a lithography process is performed on a cell configured with a cell pattern on a mask, the correspondence between the light intensity given to the peripheral region by the cell and the distance from the outer periphery of the cell is determined using the lithography target of the cell. A light intensity calculating step for calculating
An approximate value calculating step of calculating an approximate value of the correspondence using the correspondence;
An approximate pattern calculating step for calculating a lithography target having the same correspondence as the approximate value as an approximate pattern;
A lithography target pattern creation method comprising:

Images