JP2011530228A - Method and apparatus for a receiver having dual mode automatic gain control (AGC) - Google Patents

Abstract

In a method and apparatus for toggling between a first mode and a second mode of a receiver based on an input signal level, comparing the gain state of the receiver to at least one gain state threshold And determining the presence of the jammer and switching the current mode of the receiver to a new mode based on the presence of the jammer and a comparison of the gain state. In one aspect, the apparatus is coupled to a jammer detector that provides two LNAs operating in different modes, a jammer detector that provides a jammer interrupt bit to indicate the presence of the jammer, And an automatic gain control (AGC) circuit that receives the interrupt bit, which selects between the two LNAs based on the jammer interrupt bit and the gain state comparison.
[Selection] Figure 12

Description

Claiming priority under 35 USC § 119

  This patent application is directed to provisional application 61 / 085,321 filed July 31, 2008 and entitled “Method and Apparatus for Receiver with Dual Mode Automatic Gain Control (AGC)”. Priority is claimed and assigned to the assignee of the present application, hereby expressly incorporated by reference.

Field

  The present disclosure generally relates to an apparatus and method for a communication receiver. More particularly, this disclosure relates to a dual mode AGC receiver with automatic gain control.

background

  In conventional communication receivers, there are two competing requirements: high sensitivity and high linearity. High sensitivity refers to a low noise figure receiver characteristic with high gain so that the receiver is sensitive to weak signals. A low noise figure LNA provides better sensitivity to the receiver and good SNR for weak signals. However, as the intermodulation level increases, a low noise figure LNA with high gain fails to provide adequate SNR when strong interference (ie jammer) is present. The increase in the intermodulation level is due to a low third order intercept point (IP3) and a low 1 dB compression point (P1 dB) for the sensitive receiver. Another effect is the low second order intercept point (IP2) that appears in ZIF (zero IF) and VLF (very low IF) receivers, along with superheterodyne receivers, to affect IF noise. An example of the cause of such a phenomenon may be a mixer.

  High linearity refers to receiver characteristics with a high third-order intercept point (IP3) and a high 1 dB compression point (P1 dB). High linearity receivers have improved noise immunity to strong signals and to strong interference (ie jammers). That is, a high linearity receiver has less distortion (eg, intermodulation product level, gain compression, phase nonlinearity, AM-PM conversion, etc.) when a strong signal or strong interference is present than a high sensitivity receiver. Have. However, a high linearity receiver (ie, its LNA) has a higher noise figure and lower gain, and is therefore optimal when there are only weak jammers or when no jammers appear at all. Sensitivity and SNR cannot be provided.

  There is a system design tradeoff between optimizing the receiver design for weak signals versus optimizing for strong signals. Thus, a high sensitivity receiver is optimal for weak signals and a high linearity receiver is optimal for strong signals.

  However, in many cases, there are combinations of weak desired signals and strong undesired jammers that are present in the receiver input. In one example, a weak desired signal and a strong undesired jammer are received simultaneously. In this case, the sensitive receiver may have degraded signal-to-noise ratio (SNR) performance due to gain compression and intermodulation distortion due to the presence of strong jammers in the receiver input. On the other hand, highly linear receivers may also degrade SNR performance due to higher noise figure resulting in higher noise levels and reduced sensitivity to weak desired signals. Thus, any one of the receiver designs (high sensitivity or high linearity) must make a compromise, or choice, to balance noise figure, IP3, and P1 dB performance.

Overview

  A method and apparatus is disclosed for providing a dual mode AGC receiver design that can toggle between a high sensitivity low noise amplifier (LNA) and a high linearity LNA depending on the input RF signal environment. In one aspect, the dual mode AGC receiver includes jammer detection.

  It is understood that other aspects will become readily apparent to those skilled in the art from the following detailed description, wherein it is shown and described various aspects by way of illustration. The drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.

FIG. 1A illustrates an exemplary schematic of an ultra-wideband dual mode AGC receiver system for multiple radio system management. FIG. 1B shows the carrier-to-noise (C / N) without any jammer compared to the carrier-to-noise plus third-order intermodulation level (C / (N + IM)) characteristic with jammer for a conventional receiver. The characteristics are illustrated. FIG. 2 illustrates an example for optimizing SNR (eg, C / N) by combining high linearity characteristics and high sensitivity characteristics in a receiver. FIG. 3 illustrates an example of a dual mode AGC receiver front end. FIG. 4 illustrates an example state transition diagram for dual mode in terms of switching points (SP) and gain states. FIG. 5A illustrates an example of the resulting dual mode AGC receiver gain state as a function of input RF level for both high sensitivity mode (mode 1) and high linearity mode (mode 2). FIG. 5B illustrates an example of a resulting dual mode AGC receiver noise figure condition as a function of input RF level for both high sensitivity mode (mode 1) and high linearity mode (mode 2). FIG. 6 illustrates an example of operation modes and state diagrams. FIG. 7 illustrates examples of voltage requirements at the ADC input for different gain states of a receiver having an AGC that may or may not be dual mode. FIG. 8 illustrates an example of a carrier to noise ratio (C / N) with increased intermodulation product levels for different gain states. FIG. 9 illustrates an example of a dual mode AGC receiver. FIG. 9A shows another example of a dual mode AGC receiver. FIG. 9B shows another example of a dual mode AGC receiver. FIG. 9C shows another example of a dual mode AGC receiver. FIG. 10A illustrates an example block diagram of a jammer detector (JD) coupled to an automatic gain control (AGC) circuit. FIG. 10B illustrates an example of an ultra-wideband dual AGC receiver block diagram. FIG. 11 illustrates an exemplary ratio between RF noise to ADC noise at a mixer / low pass filter (LPF) versus frequency analog output. FIG. 12 illustrates an exemplary flow diagram for toggling between dual modes based on the input signal environment. FIG. 13 illustrates an example of a device 1300 that is suitable for toggling between dual modes based on an input signal environment.

Detailed Description of the Invention

  The detailed description set forth below in connection with the appended drawings is intended as a description of various aspects of the disclosure and is not intended to represent the only aspects in which the disclosure may be practiced. Each aspect described in this disclosure is provided merely as an example or illustration of the present disclosure, and should not necessarily be construed as preferred or advantageous over other aspects. Absent. The detailed description includes specific details for the purpose of providing a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the present disclosure. Acronyms and other descriptive terminology are used for convenience and clarity and are not intended to limit the scope of the present disclosure.

  For purposes of simplicity, the methodology is shown and described as a series of operations, but some operations are in a different order and different from those shown and described in accordance with one or more aspects. It should be appreciated and appreciated that the methodology is not limited by the order of operations, as they may occur simultaneously with / or other operations. For example, those skilled in the art will understand and appreciate that a methodology can alternatively be represented as a series of interrelated states or events, such as a state diagram. Moreover, not all illustrated acts may be required to implement a methodology in accordance with one or more aspects.

  FIG. 1A illustrates an exemplary schematic of an ultra-wideband dual mode AGC receiver system for multiple radio system management. The system includes, for example, a hardware jammer detector for detecting near and far jammers, a coexistence management subsystem, and a dual mode AGC receiver. The dual mode AGC receiver consists of a first mode for providing high sensitivity and a second mode for providing high linearity. For the low jammer case, the receiver operates in the first mode, providing high sensitivity but low linearity. In the case of a high jammer above the threshold, the AGC receiver switches to the second mode to provide high linearity but provide moderate sensitivity.

  FIG. 1B illustrates a carrier-to-noise (C / N) characteristic without any jammer as compared to a jammed carrier-to-noise plus intermodulation level (C / (N + IM)) characteristic for a conventional receiver. To do. This conventional receiver design is based on a compromise between having high linearity characteristics and having high sensitivity characteristics. Ideally, the conventional receiver of FIG. 1B should operate to receive a weak signal with minimal degradation when jammers are present. One technique for optimizing the performance of a conventional receiver is to make the two ends of the curve less than some value, eg, 3 dB as shown in FIG. 1B. However, this optimization process is to balance between the noise figure (NF) and the input third-order intercept point (IIP3), which defines the intermodulation product and P1 dB, which is also As an example, it also affects the IP3 level or higher order IP. This optimization process results in a highly linear receiver. The disadvantages of using a high linearity receiver are the degraded NF (ie, higher noise figure value) and degraded LNA gain in favor of a higher input third-order intercept point (IIP3). It is. Also, sensitivity is sacrificed due to the reduced SNR by trying to “balance” the conventional receiver.

  Using a high sensitivity receiver (ie, high sensitivity LNA) in a dynamic wide range with only weak jammers or no jammers at all compared to using a high linearity receiver , Resulting in improved sensitivity. However, in the presence of strong jammers, SNR (eg, C / N) is degraded by gain compression and intermodulation distortion.

  FIG. 2 illustrates an example for optimizing SNR (eg, C / N) in a jammer environment by combining high linearity and high sensitivity characteristics in a single dual mode AGC receiver. By combining two characteristics of high linearity and high sensitivity for different input signal environments in a single dual mode AGC receiver, as shown in FIG. 2, the SNR (eg, C / N) Optimization is achieved. For example, when there is only a weak jammer or no jammer at all, even if the input desired signal level is high, the dual mode AGC receiver operates with its high sensitivity LNA characteristics. On the other hand, when there is a strong jammer, the dual mode AGC receiver operates with its high linearity LNA characteristics to optimize the SNR (eg, C / N replaced by C / (N + I)).

  FIG. 3 illustrates an example of a dual mode AGC receiver front end. In one example, an automatic gain control (AGC) signal from an AGC circuit (not shown) is applied during the dual mode AGC receiver front end shown in FIG. The AGC circuit increases the dynamic range of the dual mode AGC receiver and limits the receiver output power to a level that does not exceed the maximum allowed at the analog to digital converter (ADC) input. The AGC operates as a power or voltage limiter at the dual mode AGC receiver output, which limits the desired signal level at the ADC input. In one aspect, margins for component tolerance and for unwanted signal power leakage are included in the AGC circuit. In a jammer-free environment, the AGC circuit is optimized so that the receiver meets linearity and sensitivity requirements.

  In one example, a jammer detector is included in a dual mode AGC receiver to identify undesired signals and trigger a switch between dual mode, ie, high linearity mode and high sensitivity mode. . For example, dual modes are: (1) high sensitivity mode for low power signals with or without weak jammers, and (2) high linearity (shown in dashed line) with moderate sensitivity for strong jammers. Sex mode. FIG. 3 shows some exemplary gain state values for dual mode. For example, the high sensitivity mode includes a 20 dB gain state G0 having a noise figure of 1.4 dB. The high linearity mode has five gain states, for example, 14.5 dB G1 (with a 1.7 dB noise figure), 9.5 dB G2, 3 dB G3, and -8.5 dB G4, -22 dB G5. In one aspect, a dual mode AGC receiver (ie, dual mode LNA) is implemented as a parallel path. In another aspect, a dual mode AGC receiver (ie, dual mode LNA) is implemented as a single path.

  In one example, two AGC tables are included in a processor in a dual mode AGC receiver. One AGC table is used for the high sensitivity mode where a low noise figure LNA is used. The second AGC table is used for the high linearity mode where a high IP3 LNA is used. Two AGC tables allow maximizing the use of high sensitivity LNAs, improving system sensitivity over a wider signal range, and jammer detection when detected jammers exceed a predefined threshold Switch to high linearity LNA based on instrument response. In one aspect, the values in the AGC table are based on one or more of the following: That is, gain compression point; mixer protection; ADC protection against saturation; intermodulation product level for each CNR degradation. Another example may be some tables for mode 1 with optimized switching points and set vs. operating frequency, and tables for mode 2 with optimized switching points and set vs. operating frequency. . Another example is an adaptive switch point table that is based on, for example, frequency, modulation scheme, or a combination of all parameters.

  FIG. 4 illustrates an example state transition diagram for dual mode with respect to switching points (SP) and gain states. The switching point is represented as SPxy having an x value representing the mode and a y value representing the switching point. In FIG. 4, each mode (mode 1 and mode 2) has 6 switching points. The gain states are represented as G0 to G6 for mode 1 and G1 to G6 for mode 2. In mode 2, G0 is bypassed. The upper line segment shows the state transition for the high sensitivity mode (mode 1), and the lower line segment shows the state transition for the high linearity mode (mode 2). As shown in FIG. 4, a different gain state is selected at each switching point.

  FIG. 5A illustrates an example of a dual mode AGC receiver gain state that results as a function of input RF level for both high sensitivity mode (mode 1) and high linearity mode (mode 2). As shown in FIG. 5A, in mode 1, the dual mode AGC receiver starts at the highest gain state G0 for the low input power level (Pin) and the corresponding switching as the input power level (Pin) increases. At points (SP11, SP12, SP13...), Transition is made to continuous gain states (G1, G2, G3,...). As shown in FIG. 5A, in mode 2, the dual mode AGC receiver starts in a gain state G1 for a low input power level (Pin), and as the input power level (Pin) increases, the corresponding switching point ( In SP22, SP23,..., Transition to continuous gain states (G2, G3,...). The switching point SP21 for mode 2 is set to a very low input power level, eg 200 dBm, and bypasses the gain state G0 in mode 2.

FIG. 5B illustrates an example of a resulting dual mode AGC receiver noise figure condition as a function of input RF level for both high sensitivity mode (mode 1) and high linearity mode (mode 2). As shown in FIG. 5B, in mode 1, the dual mode AGC receiver starts at the highest gain state G0 and the lowest noise figure NF _{G0 for} the low input power level (Pin), and the input power level (Pin) As it increases, at corresponding switching points (SP11, SP12, SP13...), Successive gain states (G1, G2, G3) having corresponding noise figures (NF _G1 , NF _G2 , NF _G3 ,...). ,... As shown in FIG. 5B, in mode 2, the dual mode AGC receiver starts at the highest gain state G0 and lowest noise figure NF _{G1 for} the low input power level (Pin), and the input power level (Pin) As it increases, at the corresponding switching point (SP22, SP23...), It goes to a continuous gain state (G2, G3,...) Having a corresponding noise figure (NF _G2 , NF _G3 ,...). Transition. The switching point SP21 for mode 2 is set to a very low input power level, eg 200 dBm, and bypasses the gain state G0 in mode 2.

  Based on the state of the jammer detector, the AGC switching points may advance or retract relative to each other as shown in FIG. As shown in FIG. 5A, the AGC switch point affects the LNA gain state and noise figure versus RF input power. In the high gain state, AGC switching points may or may not be merged. The merge characteristic relies on output voltage level versus input power, where the output voltage level is limited to not exceed the ADC full scale criteria to prevent ADC saturation. In one aspect, the value of the switching point is modified to switch earlier when a jammer is present. In one aspect, the value of the switching point between gain states (other than the G0 state) is adaptable based on the jammer level.

  In one aspect, the switching point (SP) defined above is updated when switching between modes. In addition, the switching logic includes hysteresis to prevent toggling between modes. In another example, each jammer detector (JD) has its own switch point register for storing its threshold value. In another aspect, JD may optionally be ignored for higher gain states, eg, gain states above G3. In another example, the AGC SPs are merged to be identical in the high gain state.

  In another aspect, the AGC switch point table may be adaptable based on the received jammer level. The AGC switching point table is based on several parameters such as receiver compression point, ADC saturation point, IMR3 level, and operating frequency, which degrades the transmission / noise ratio and reduces the operating frequency. Affects the gain response with the above parameters. In a jammer free environment, the AGC switching point is optimized so that the receiver meets linearity and sensitivity requirements. In one example, the AGC switch point may be modified for earlier transitions based on the presence of jammers. The correction may be adaptable based on the received jammer power level.

  FIG. 6 illustrates an example of operation modes and state diagrams. FIG. 6 shows transitions between various operating states, including mode 1 for high sensitivity receiver states and mode 2 for high linearity receiver states, as well as debug mode and fixed mode.

  FIG. 7 illustrates an example of voltage requirements at the ADC input for different gain states for a receiver with an AGC that may or may not be dual mode. FIG. 7 is a graph of the output voltage (ie, input voltage to the ADC) from the RF section of the dual mode AGC receiver shown in FIG. 9 as a function of input RF power for the mixer shown in FIG. As the input RF power increases, the AGC circuit shown in FIG. 10A allows the output voltage from the RF section (ie, the input voltage to the ADC) to be kept below the ADC level maximum limit (GS1, GS2, GS3, GS4..., G1, G2, G3, G4. The ADC level maximum limit is a margin with respect to the ADC full-scale maximum voltage as shown in FIG. The margin prevents ADC saturation from interfering with signal leakage and signal peak-to-average ratio (PAR) and allows for AGC accuracy tolerances.

  FIG. 8 illustrates an example of the carrier to noise ratio (C / N) with increased intermodulation product levels for different gain states versus input RF power levels for the mixer shown in FIG. As shown in FIG. 8, the carrier-to-noise ratio (C / N) is degraded due to the increased intermodulation product level as the input level increases. In one example, such an increase occurs due to the presence of a strong jammer. Hysteresis between increasing power and decreasing power is introduced into the AGC circuit to prevent toggling at the switching point. In the high sensitivity mode (mode 1), the RF chain has higher gain and lower noise figure, which increases dual mode AGC receiver sensitivity. On the other hand, in the high linearity mode (mode 2), the dual mode AGC receiver operates with lower gain and higher noise figure. In one example, the normal gain (G0) state in the high linearity mode is bypassed by setting the first switching point (SP21) in mode 2 to -200 dBm (as shown in FIG. 4), Protect dual mode AGC receiver from C / N degradation due to the presence of strong jammers.

  A dual mode AGC receiver toggles between the two modes. In one aspect, the two modes include a high sensitivity mode (mode 1) and a high linearity mode (mode 2), and a dual mode AGC receiver depends on the input signal environment and these two modes Toggle between modes. If the dual mode AGC receiver is in a high sensitivity mode, this may require immediate protection when a strong jammer appears. In one example, such protection is achieved using a rapid attack automatic gain control (AGC) circuit or algorithm or both. Rapid attack refers to the characteristics of an automatic gain control (AGC) circuit or algorithm or both, which is a rapid gain decrease after the appearance of a strong input signal level (eg, jammer). Next, when the strong jammer disappears, the dual mode AGC receiver may require a slow release of the AGC circuit to avoid rapid toggling between the two modes. Slow release refers to a characteristic of an automatic gain control (AGC) circuit or algorithm or both, which is a slow gain increase after the disappearance of a strong input signal level (eg, strong jammer). Rapid Attack Low Release or Slow Attenuation JD is a term borrowed from AGC, which describes rapid gain decrement and slow convergence to final gain value when receiving strong signals. . In the present invention, there are two systems. AGC and jammer detector. The jammer detector operates in a rapid attack low release mode for the following reasons. The first priority is to protect the receiver and maintain quality of service. Thus, the jammer detector operates in a rapid attack mode, converting the receiver to a protected mode. This mode is defined as “Mode 2”, which is a high linearity medium sensitivity. Second, it is assumed that the receiving environment changes slowly (jammers do not appear quickly and do not disappear quickly). Therefore, there is a slow release process to avoid toggling between the two modes and thereby reduce receiver performance. In addition, the slow release process protects the system from fading and prevents signal distortion. The jammer detector signaling in the attack notifies the BB (eg, AGC circuit and / or algorithm) to switch from the mode 1 AGC table to the mode 2 AGC table. Note that the AGC table is a table of other settings such as gain state switching point versus input power and current settings. The mode 1 switching point table is used for the high sensitivity low linearity mode. This therefore includes the G0 gain state. The mode 2 AGC table is used for high linearity medium sensitivity. This therefore deliberately bypasses the G0 gain state by having its switching point set to, for example, -200 dBm. As a result, Mode 2 is a conventional receiver mode that starts in the G1 gain state and the design is a trade-off between sensitivity and linearity. As a result of the jammer detector interrupt, the gain of the system is reduced. The system maintains a low gain and a mode 2 switching point AGC table for a predefined release time. The AGC manages the gain of the receiver with the lower gain mode 2 table and switches back to mode 1 only after the release time does not show any jammers during that release period. Thus, slow release refers to the operation of AGC and JD, which means a slow gain increase after the jammer disappears.

  In conventional receiver designs, the AGC circuit is triggered by a single jammer detector (JD) that is designed for narrowband operation over a single radio frequency (RF) band. However, in many wireless scenarios, there are several interfering transmitters operating in different frequency bands, transmit power levels, and modulation schemes. A single jammer detector is not optimal for detecting various jammers over a very wide band. Nevertheless, there is a need to protect the receiver from all jammers present in the broadband environment.

  In conventional receiver designs, there is a single AGC switching point table, and the design is a compromise between linearity and sensitivity. Thus, the conventional design is similar to the mode 2 design, which is a protected mode. There is no sensitivity improvement in cases where the jammer is below a certain predetermined threshold. Conventional receivers protect against jammers at the expense of sensitivity by increasing the current in the LNA and mixer. Furthermore, conventional receivers do not have a rapid attack low release JD process to operate in burst mode. The present invention includes two types of jammer detectors. The receiver includes a narrowband jammer detector, which is in the vicinity of a band such as an alternative jammer appearing up to N + 4 (ie, the 4th adjacent band) as an example. Monitor jammers. Before the baseband filter senses jammers, the narrowband JD is either in the analog baseband of the receiver, or at the IF frequency in the superheterodyne receiver, or in some other low frequency reception block in the receiver. Realized. In addition, the receiver has a wideband jammer detector that protects the receiver from in-band distant jammers.

  FIG. 9 illustrates an example of a dual mode AGC receiver 900. In one example, a dual mode AGC receiver with automatic gain control (AGC) has two modes for AGC with two switch point tables for gain states. Furthermore, the dual mode AGC receiver has two LNA paths, one for high sensitivity low current (mode 1) and one for high linearity medium sensitivity (mode 2). .

  For a dual mode AGC receiver, mode 1 has high sensitivity and low linearity characteristics. Mode 2 has characteristics of high linearity and medium sensitivity. Mode 1 uses an LNA having a low noise figure, high gain, and low current consumption. Mode 1 is used when there is a low level jammer or no jammer at the receiver input. Mode 2 uses an LNA with lower gain, higher IP3, and higher current consumption. Mode 2 is used when there is a strong jammer at the dual mode AGC receiver input. The transition between the two modes is achieved by an automatic gain control (AGC) circuit triggered by a jammer detector (JD), not shown in FIG. In the case where a strong jammer is detected, the AGC is switched from the mode 1 switching point table (high sensitivity, low NF) to the mode 2 switching point table (high linearity, medium sensitivity).

  In one example, the input RF signal is captured by a receiver antenna (not shown) that is coupled to a dual mode AGC receiver to provide low noise amplification, mode 1 output mode signal, and mode 2 output RF signal. Sent to both mode 1 LNA and mode 2 LNA inputs (910, 920, respectively) for each generation. As shown in FIG. 9, the mode 1 LNA has an input 910 and the mode 2 LNA has an input 920. The AGC circuit provides a mechanism (not shown) that selects between a mode 1 output RF signal and a mode 2 output RF signal to produce a selected output RF signal. Those skilled in the art will appreciate that modes can be selected using various mechanisms known in the art without affecting the spirit and scope of the present disclosure.

  The selected output RF signal is sent to a mixer / low pass filter (LPF) 930 for frequency downconversion and generation of an input baseband signal. The input baseband signal is sent to an analog to digital converter (ADC) 940 for conversion to the input digital signal. The input digital signal is then sent to a digital variable gain amplifier (DVGA) 950, for example, for gain adjustment and generation of the output digital signal. The output digital signal, by way of example, captures digital symbols and forwards them to a sample server (SS) module 960 that transfers them for further demodulation processes, and energy estimation of the output digital signal (eg, receiver output energy) To an energy estimator (EE) for

  In one aspect, the dual mode AGC receiver toggles between the first mode and the second mode based on the input RF signal level. As shown in FIG. 9, the dual mode AGC receiver indicates the presence of a first LNA operating in a first mode, a second LNA operating in a second mode, and a jammer. A jammer detector for providing a jammer interrupt bit for and an automatic gain control (AGC) circuit and / or algorithm coupled to the jammer detector for receiving the jammer interrupt bit. Here, the AGC circuit selects between the first LNA and the second LNA based on the jammer interrupt bit and the gain state comparison. The dual mode AGC receiver further includes a mixer coupled to one of the two LNAs to downconvert the input RF signal to a downconverted signal. The dual mode AGC receiver includes a low pass filter (LPF) coupled to the mixer for filtering the downconverted signal to generate a filtered downconverted signal. The filtered downconverted signal is input to an analog to digital converter (ADC) for digitizing the filtered downconverted signal to produce a digitized signal. The digitized signal is then input to a digital variable gain amplifier (DVGA), which scales the digitized signal. An energy estimator coupled to the DVGA receives the scaled digitized signal and uses it to estimate the receiver output energy. The receiver output energy is then input to the jammer detector and used in setting the jammer detector threshold. The value of the jammer interrupt bit that indicates the presence of the jammer is based on a comparison of the RF input signal level against the jammer detector threshold. In one aspect, a dual mode AGC receiver comprises a processor for obtaining normalized receiver input energy at the input to one of the two LNAs based on the receiver input energy at baseband. To do. As shown in FIG. 9, the receiver input energy in baseband can be tapped at some of the ADC or DVGA outputs or at the input to the ADC. The processor sets a new gain for the dual mode AGC receiver to reflect the new mode and normalized receiver input energy, where the processor instructs the jammer detector to detect the jammer detector. Update the threshold. In one example, the processor is part of an AGC circuit.

  9A, 9B and 9C show three examples of dual mode AGC receivers. FIG. 9A shows one example of a dual mode AGC receiver with two LNA paths, each path using a full gain chain. Mode 2 LNA includes six gain states, G1 through G6, all six of which are operating at high current. Mode 1 LNA includes seven gain states G0 to G6, all of which are operating at low current. FIG. 9B shows a second example of a dual mode AGC receiver having a single LNA path including gain states G0 to G6. In the example of FIG. 9B, the gain state G0 is part of the gain chain, but when the dual mode AGC receiver is operating in mode 2, G0 is skipped. FIG. 9C shows a third example of a dual mode AGC receiver with two LNA paths, each using a full gain chain and a dedicated mixer / low pass filter. Mode 2 LNA includes six gain states G1 through G6, all six gain states and the mixer / low pass filter are operating at high current. Mode 1 LNA includes seven gain states G0 to G6, all seven gain states and the mixer / low pass filter are operating at low current. One skilled in the art will understand that in one aspect, high current and low current are meant to imply relative values to each other.

FIG. 10A illustrates an example block diagram of a jammer detector (JD) 1010 coupled to an automatic gain control (AGC) circuit 1020. A jammer detector (JD) 1010 and an automatic gain control (AGC) circuit 1020 are coupled to the dual mode AGC receiver 900 shown in FIG. In one aspect, jammer detector (JD) 1010 and automatic gain control (AGC) circuit 1020 are part of dual mode AGC receiver 900. The jammer detector input signal, including both the jammer and the desired signal, is sent to a jammer detector (JD) 1010 for strong jammer detection. In one example, the jammer detector input signal is the output of an energy estimator (EE) (shown in FIG. 9). When the level of the jammer detector input signal exceeds a predetermined jammer detector threshold TH _j , a jammer detector interrupt bit is set by the jammer detector (JD) 1010 and is sent to the AGC circuit 1020. Sent. In one example, a jammer detector interrupt bit = 1 means that a jammer level above TH _j has been detected, and a jammer detector interrupt bit = 0 detects any jammer above TH _j Means not. In one example, the jammer detector threshold TH _j is applied to a comparator within the jammer detector. In one aspect, the jammer detector 1010 is a combination of a plurality of jammer detectors, each set with a predetermined jammer detector threshold TH _j . In one aspect, the jammer detector 1010 is based on several complementary jammer detectors, both hardware and software based. Jammer detector 1010 includes a narrowband jammer detector (NB JD) for detecting in-band jammers and a wideband jammer detector (WB JD) for detecting out-of-band jammers and distant jammers. Incorporates a narrowband jammer detector (SW JD) to detect operational jammers. Each of NB JD, WB JD, and SW JD has its own optimized jammer detector threshold (TH _j ). Those skilled in the art within the spirit and scope of the present disclosure may have the jammer detector 1010 be a plurality of jammer detectors, each set with a predetermined jammer detector threshold TH _j . .

  The AGC circuit 1020 receives the current LNA gain state, current DVGA gain state, and current EE value, along with the jammer detector interrupt bit or interrupt status bit, as inputs to the AGC circuit and / or algorithm. accept. The output of the AGC circuit is an updated LNA gain state and an updated DVGA gain state based on various AGC inputs. The AGC circuit selects between one of the two LNAs based on the jammer detector interrupt bit and a gain state comparison of the current LNA gain state against a series of gain state thresholds. In one example, the output of the AGC circuit or algorithm or both is directed to one of the two LNAs (shown in FIG. 9) and DVGA 950. The AGC circuit or algorithm or both 1020 incorporates two AGC tables that govern the selection of gain states during the high sensitivity mode (mode 1) and during the high linearity mode (mode 2). In one example, if a dual mode AGC receiver is set to mode 1 (high sensitivity mode) and the jammer detector interrupt bit is asserted HIGH (ie, bit = 1), a strong jammer To indicate presence, the AGC circuit 1020 responds by setting the updated LNA gain state and the updated DVGA gain state to their appropriate values in mode 2 (high linearity mode). In one aspect, two AGC tables are combined as one AGC table. In another example, the dual mode AGC receiver is set to mode 2 (high linearity mode) and the jammer detector interrupt bit remains LOW (ie, bit = 0) for a predetermined time period. In order to indicate that there is no strong jammer for a predetermined period of time, the AGC circuit will update the updated LNA gain state and the updated DVGA gain state to their appropriate Set to value.

  FIG. 10B illustrates an example of an ultra-wideband dual AGC receiver block diagram. The jammer detector 1010 of FIG. 10A is shown in more detail in FIG. 10B as consisting of three separate detectors: a narrowband jammer detector, a broadband jammer detector, and a software-based jammer detector. . Interrupts from these three detectors are sent to the JD readout block, which sends a composite interrupt signal to the AGC algorithm block for gain state control as described above. In addition, the serial bus interface (SBI) control unit provides several control signals (counter, interrupt mask, threshold setting, and interrupt clear to the jammer detector based on the status of the JD and AGC algorithms. )I will provide a.

  In one aspect, a mode 2 (high linearity mode) LNA has multiple gain states. In one example, a mode 2 LNA has three gain states, G1, G2, and G3 in order of decreasing gain and increasing noise figure. Furthermore, mode 2 may have other higher gain states G4, G5, and G6. In one aspect, in an AGC circuit, the mode 2 LNA gain state relies on exceeding the AGC switch point. In one example, a mode 1 LNA has multiple gain states. Those skilled in the art will appreciate that the amount of gain state for Mode 1 and / or Mode 2 can be chosen depending on the particular application and design parameters without affecting the spirit and scope of the present disclosure. right.

  Each of the two AGC tables includes a set of AGC switching points (SP) corresponding to each of the two modes of the dual mode AGC receiver. In one example, for mode 1, the AGC switching point (SP) for the transition from gain state G0 to G1 is approximately −80 dBm. The gain state G0 corresponds to a low noise figure, high gain LNA path in mode 1. In one example, for mode 2, an AGC for transition from gain state G0 to G1 such that gain state G0 is efficiently skipped and gain state G1 is active at lower input signal level states. The switching point (SP) is very low, for example, set to about -200 dBm. In one aspect, the AGC switching point (SP) setting is updated when switching between the two modes. Hysteresis is added to prevent toggling between the two modes.

A dual mode AGC receiver improves receiver sensitivity in the presence of jammers compared to conventional single mode receivers. In addition, dual mode AGC receivers provide buffering for analog to digital converter (ADC) noise so that the overall system noise figure is minimized. For example, in a digital receiver, the analog signal of the receiver is sampled by an analog to digital converter (ADC). The ADC generates ADC noise, denoted as N _ADC . The design of the digital receiver is governed by the desired carrier to noise ratio (C / N). LNA design parameters are chosen to optimize C / N. The effect of the LNA noise figure on the overall RF noise figure is shown by equation (1).

Equation (1) shows that an LNA with a low noise figure F ₁ and a high gain G ₁ compensates for the noise figure of the remaining RF chain, resulting in a lower F _eq . By extension, the LNA also compensates for ADC noise. RF section at the ADC input has a noise figure F _T and the gain G _T. The ADC may be modeled as a cascade block with a noise figure F _ADC . Therefore, the ADC noise at that input port is given by equation (2). ADC noise includes quantization noise, thermal noise, and other noise components.

The total RF noise referenced at the ADC input is given by equation (3).

The cascade noise figure is given by equation (4).

Equation (4) shows that G _T is given by a larger nominal (G 0) gain state compared to the G 1 gain state, and by a reduced total RF noise figure F _T when in the nominal (G 0) gain state. When increasing, it shows that the cascade noise figure is improved.

Equation (5) defines the noise ratio (NR).

Here, N _ADC in Equation (5) is a ADC noise density given by equation (2), k is the Boltzmann constant, T is the ambient temperature of the Kelvin temperature, the G _T, Is the total RF gain, F _T is the total RF noise figure, and F _ADC is the ADC noise figure.

Equation (5) shows that a low noise figure LNA with high gain results in higher RF noise N _RF than ADC noise N _ADC . This relationship shows that the ADC noise contribution to the overall system noise figure is negligible.

Equation (6) defines the takeover gain (TOG).

As shown in equation (6), a higher takeover gain (TOG) implies that the ADC noise contribution is lower. Moreover, NR improves and the cascade noise figure F _{T — RX} approaches F _T. FIG. 11 is a spectrum graph of noise versus frequency (measured in dBm). FIG. 11 illustrates an exemplary ratio between RF noise (N _RX ) and ADC noise (N _ADC ) at the mixer / low pass filter (LPF) 930 vs. frequency analog output (shown in FIG. 9).

This represents the ratio between RF noise (N _RX ) to ADC noise (N _ADC ) in logarithmic units.

The dual mode AGC receiver utilizes a nominal (G0) gain state with an improved noise figure and higher gain, and a cascaded noise figure F relative to the cascaded noise figure under the G1 gain state. _{Improve T_Rx} . Under G0 gain state, G _T is different from the G1 gain state, since higher, it is possible performance improvement. Therefore, the cascade noise figure F _{T_Rx} is further improved to approach F _T as shown in Equation (4), and the takeover gain is improved.

Equation (7) shows the cascade noise figure (NF) ratio between the G1 gain state and the G0 gain state. Equation (8) shows the TOG ratio between the G1 gain state and the G0 gain state.

  The AGC circuit interaction with the jammer detector (JD) is illustrated in FIG. 10A, where the gain state and noise figure state for the operating mode are provided in FIGS. 4-6. Inputs to the processor algorithm are LNA-mixer gain state, DVGA (digital variable gain amplifier) state, jammer detector interrupt status, and EE (energy estimation) value. Based on these inputs and energy estimates, a new AGC state, a new LNA state, and a new DVGA state are calculated. In one aspect, a processor 905 (not shown) in the dual mode AGC receiver performs the calculations. In one example, processor 905 is part of AGC circuit 1020.

  FIG. 12 illustrates an exemplary flow diagram for toggling between dual modes (such as high sensitivity mode and high linearity mode) based on the input signal environment (ie, input signal level). . At block 1210, the receiver input energy of the dual mode AGC receiver is estimated. In one aspect, the receiver input energy is measured at baseband, for example, at the input to the ADC, at the output of the ADC, or at the output of the DVGA. The receiver input energy includes jammer energy, desired signal level, and noise level. At block 1220, normalized at the receiver front end by dividing the receiver input energy at baseband by the aggregate gain (ie, at the dual mode AGC receiver for one of the LNAs shown in FIG. 9). Get the receiver input energy. In one aspect, the processor 905 obtains normalized receiver input energy. The aggregated gain is one of the gains of DVGA 950 (shown in FIG. 9), ADC 940, mixer / LPF 930, and one of the two LNAs depending on the mode of the dual mode AGC receiver. Including one or more. At block 1230, the current mode of the dual mode AGC receiver is determined. If the dual mode AGC receiver is in mode 1 (high sensitivity mode), proceed to block 1240. At block 1240, for example, a mode 1 AGC SP table (having switching points S11 to S16) is used. If the dual mode AGC receiver is in mode 2 (high linearity mode), proceed to block 1250. At block 1250, for example, a mode 2 AGC SP table (having switching points S21 to S26) is used. Following block 1240, in block 1241, whether the gain state (GS) is greater than or equal to G0 and whether the gain state (GS) is less than or equal to G1 (ie, G0 ≦ GS ≦ G1) is determined. In one example, determine whether the mode 1 comparator threshold is for G0 or G1. If the gain state (GS) is greater than or equal to G0 and the gain state (GS) is less than or equal to G1, proceed to block 1243. If the gain state (GS) is not greater than or equal to G0 and less than or equal to G1, proceed to block 1242. At block 1242, it is determined whether the gain state (GS) is greater than G2. In one example, determine whether the mode 1 comparator threshold is for G2. If the gain state (GS) is greater than G2, proceed to block 1280. If the gain state (GS) is not greater than G2, proceed to block 1243. At block 1243, the value of the jammer detector interrupt bit is determined. The value of the jammer detector interrupt bit is based on the input signal level and the jammer detector threshold THj. The value of the jammer detector interrupt bit is used to determine whether to switch the current mode to a new mode. If the jammer detector interrupt bit is 1, proceed to block 1245 to switch the dual mode AGC receiver to mode 2 (high linearity mode) and mode 2 AGC (with switch points S21 to S26). Use SP table. If the jammer detector interrupt bit is 0, proceed to block 1280. In one example, the state of the jammer detector is based on the input to the jammer detector and the status of the jammer detector interrupt bit.

  Following block 1250, at block 1251, whether the gain state (GS) is greater than or equal to G1, whether it is less than G2, or equal to G2 (ie, G1 ≦ GS ≦ G2). ). In one example, it is determined whether the mode 2 comparator threshold is for G1 or G2. If the gain state (GS) is greater than or equal to G1 and less than or equal to G2, proceed to block 1253. If the gain state (GS) is not greater than or equal to G1, or less than or equal to G2, proceed to block 1252. At block 1252, it is determined whether the gain state (GS) is greater than G3. In one example, determine whether the mode 1 comparator threshold is for G3. If the gain state (GS) is greater than G3, proceed to block 1280. If the gain state (GS) is not greater than G3, proceed to block 1253. At block 1253, the value of the jammer detector interrupt status bit is determined. The value of the jammer detector interrupt status bit is based on the input signal level and the jammer detector threshold THj. The value of the jammer detector interrupt status bit is used to determine whether to switch the current mode to a new mode. If the jammer detector interrupt status bit is 0, proceed to block 1255 to switch the dual mode AGC receiver to mode 1 (high sensitivity mode) and mode 1 AGC (with switch points S11 to S16). Use SP table. If the jammer detector interrupt status bit is 1, proceed to block 1280.

  Following block 1245 or block 1255, proceed to block 1260. At block 1260, the jammer detector threshold is updated. In one aspect, a jammer detector threshold in a jammer counter (not shown) is updated. In another aspect, the jammer detector threshold in the jammer comparator (not shown) is updated. Following block 1260, proceed to block 1270. At block 1270, a new gain state is set to reflect the switched mode of the dual mode AGC receiver (ie, the new mode) and to reflect the normalized receiver input energy. At block 1270, the jammer detector threshold in the jammer comparator is updated based on the new gain state. At block 1280, a new gain state is set to reflect the current mode of the dual mode AGC receiver and to reflect the normalized receiver input energy. At block 1280, the jammer detector threshold in the jammer comparator is updated based on the new gain state. In one aspect, the new gain state may be equal to the gain state (GS). In one example, the new gain state in block 1270 or block 1280 includes LNA gain and / or post LNA gain. In one aspect, following either block 1270 or block 1280, return to block 1210. Those skilled in the art will appreciate that the algorithm illustrated in FIG. 12, or portions thereof, can be repeated without affecting the spirit or scope of the present disclosure. In one aspect, some of the algorithms illustrated in FIG. 12 may be executed by a processor 905 (not shown) in the dual mode AGC receiver 900. In another aspect, the processor 905 is part of the AGC circuit 1020.

  Various exemplary components, logic blocks, modules, circuits, and / or algorithm steps described in connection with the examples disclosed herein may be electronic hardware, firmware, computer software, or a combination thereof. Those skilled in the art will further appreciate that it may be implemented. To clearly illustrate this interchangeability of hardware, firmware, and software, various exemplary components, blocks, modules, circuits, and / or algorithm steps have been generally described above with respect to their functionality. Whether such functionality is implemented as hardware, firmware, or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in a manner that varies for each particular application, but such implementation decisions may depart from the scope or spirit of this disclosure. Should not be interpreted as

  For example, for hardware implementation, a processor may include one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), fields May be implemented in a programmable gate array (FPGA), processor, controller, microcontroller, microprocessor, other electronic unit designed to perform the functions described herein, or a combination thereof. Good. In software, implementation may be by modules (eg, procedures, functions, etc.) that perform the functions described herein. The software code may be stored in the memory unit and executed by the processor unit. In addition, the various exemplary flow diagrams, logic blocks, modules, and / or algorithm steps described herein may be used as computer readable instructions carried on any computer readable medium known in the art. It may be coded.

  FIG. 13 illustrates an example of a device 1300 that is suitable for toggling between dual modes (such as a high sensitivity mode and a high linearity mode) based on the input signal environment. In one aspect, the device 1300 is as described herein in blocks 1310, 1320, 1330, 1340, 1341, 1342, 1343, 1345, 1350, 1351, 1352, 1353, 1355, 1360, 1370, and 1380. One or more modules that are configured to provide different aspects for toggling between dual modes (such as high sensitivity mode and high linearity mode) based on different input signal environments Implemented by at least one processor. For example, each module includes hardware, firmware, software, or some combination thereof. In one aspect, device 1300 is also implemented with at least one memory in communication with at least one processor.

  The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various improvements to these aspects will be readily apparent to those skilled in the art. The general principles defined herein may be applied to other aspects without departing from the spirit or scope of the present disclosure.

Claims (22)

In a receiver having a first mode and a second mode,
The receiver is toggled between the first mode and the second mode based on an input RF signal level;
The receiver
A first LNA operating in the first mode;
A second LNA operating in the second mode;
A jammer detector that provides a jammer interrupt bit to indicate the presence of the jammer;
An automatic gain control (AGC) circuit coupled to the jammer detector and receiving the jammer interrupt bit;
The AGC circuit is a receiver that selects between the first LNA and the second LNA based on the jammer interrupt bit and a gain state comparison. A mixer coupled to one of the first LNA and the second LNA and downconverting the input RF signal to a downconverted signal;
The receiver of claim 1, further comprising a low pass filter (LPF) coupled to the mixer and filtering the downconverted signal to generate a filtered downconverted signal.   An analog-to-digital converter (coupled to the LPF, digitizing the filtered downconverted signal to generate a digitized signal and inputting the digitized signal into a digital variable gain amplifier (DVGA)). 3. The receiver of claim 2, further comprising an ADC), wherein the DVGA scales the digitized signal.   An energy estimator coupled to the DVGA and for estimating receiver output energy based on the scaled digitized signal, the receiver output energy being input to the jammer detector; 4. A receiver as claimed in claim 3, used in setting a jammer detector threshold.   The receiver of claim 4, wherein the value of the jammer interrupt bit is based on a comparison of the level of the RF input signal to the jammer detector threshold.   The processor further comprises: obtaining a normalized receiver input energy at an input to one of the first LNA and the second LNA based on the receiver input energy in baseband. The receiver according to 1.   The receiver of claim 6, wherein the processor sets a new gain for the receiver to reflect a new mode and the normalized receiver input energy.   The receiver of claim 7, wherein the processor instructs the jammer detector to update the jammer detector threshold. In a receiver having a first mode and a second mode,
The receiver is toggled between the first mode and the second mode based on an input signal level;
The receiver
A first LNA operating in the first mode;
A second LNA operating in the second mode;
A jammer detector that provides a jammer interrupt bit to indicate the presence of the jammer;
Means for receiving said jammer interrupt bit and means for selecting between said first LNA and said second LNA based on said jammer interrupt bit and a gain state comparison;   The receiver of claim 9, wherein a new gain of the receiver is set to reflect the selection between the first LNA and the second LNA. In a method for toggling between a first mode and a second mode of a receiver based on an input RF signal level,
Comparing the gain state of the receiver to at least one gain state threshold;
Determining the presence of jammers,
Switching the current mode of the receiver to a new mode based on the presence of the jammer and the comparison of the gain state.   12. The method of claim 11, further comprising determining a current mode of the receiver, wherein the current mode is either a high linearity mode or a high sensitivity mode.   The method of claim 12, further comprising estimating receiver output energy.   The method of claim 13, further comprising obtaining a normalized receiver input energy based on the receiver output energy.   The method of claim 14, further comprising setting a new gain for the receiver to reflect the new mode and the normalized receiver input energy.   The method of claim 15, further comprising updating the jammer detector threshold.   The method of claim 11, further comprising estimating receiver output energy.   The method of claim 17, further comprising obtaining normalized receiver input energy based on the receiver output energy.   The method of claim 18, further comprising making a determination not to switch from the current mode to the new mode.   The method of claim 19, further comprising setting a new gain for the receiver to reflect the current mode and the normalized receiver input energy. In a computer readable medium storing a computer program,
The execution of the computer program is as follows:
Comparing the gain state of the receiver to one or more gain state thresholds;
Let the value of the jammer detector interrupt bit be determined,
Based on the value of the jammer detector interrupt bit and the comparison of the gain state, for determining whether to switch the current mode to a new mode,
The computer-readable medium, wherein the jammer detector interrupt bit is based on the input signal level and a jammer detector threshold.   The computer readable medium of claim 21, wherein execution of the computer program is for determining a current mode of the receiver, wherein the current mode is either a high linearity mode or a high sensitivity mode. Possible medium.

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