JP2011238881A - Composite semiconductor element, method for manufacturing the same, magnetic sensor, and image formation device - Google Patents

Abstract

[PROBLEMS] To create a Hall element or the like using a compound semiconductor wafer material, there are many wasted parts, resulting in an increase in cost.
A composite semiconductor element includes a substrate (11), a flattening layer (14) which is provided on the substrate (11) and is mainly made of an organic material, and a compound semiconductor element which forms, for example, a Hall element. A semiconductor thin film (12) bonded on the insulating layer (14). A metal wiring film (23) for electrical connection with the compound semiconductor thin film (12) is further provided, and a compound semiconductor layer having a higher impurity concentration is provided between the compound semiconductor thin film (12) and the metal wiring film (23). (17) may be interposed.
[Selection] Figure 1

Description

  The present invention relates to a composite semiconductor element, a manufacturing method thereof, a magnetic sensor, and an image forming apparatus. In particular, the present invention relates to a composite semiconductor device in which a compound semiconductor device and a silicon substrate are combined, and a method for manufacturing the same. For example, a composite in which a Hall device having a GaAs or the like as an active layer and a silicon wafer are combined. The present invention relates to a magnetic sensor in which a semiconductor element, a silicon IC, and a Hall element are combined and integrated. The present invention further relates to an image forming apparatus using a magnetic sensor.

Compound semiconductors such as GaAs, InAs, and InSb having high electron mobility are suitable as materials for high-sensitivity Hall elements and magnetic sensors.
Further, there is known a magnetic sensor in which these elements and a signal processing unit using a silicon integrated circuit are integrated (Patent Document 1). In these sensors, a chip made of a GaAs substrate and a chip made of a silicon substrate are accommodated in one package. It has been realized as a configuration of a multi-chip module or a hybrid IC.

JP 2003-243646 A

  The Hall element is manufactured using an expensive compound semiconductor wafer material, but the ratio of the area occupied by the Hall element part in a chip formed by dividing the wafer into a small piece is small, and the terminal pad part or There is a problem that the area of the wiring portion occupies most of the chip, which is uneconomical.

  In addition, a magnetic sensor using a Hall element is realized as a multi-chip module or hybrid IC configuration in which a Hall element chip using a GaAs substrate and a signal processing unit chip using a silicon substrate are housed in one package. It was. A magnetic sensor IC using a Hall element chip and a signal processing unit chip has a need to mount the chip on a lead frame and connect the electrode pads between the chips with wires, which increases the package size. There was a problem.

  Furthermore, the Hall element made of the compound semiconductor inevitably has temperature dependency, and there is a problem that an error occurs in the magnetic field measurement result due to temperature change.

The composite semiconductor element of the present invention is
A substrate,
A planarization layer comprising an organic material as a main material provided on the substrate;
A semiconductor thin film including a compound semiconductor element and bonded on the planarizing layer is provided.

The magnetic sensor of the present invention is
A semiconductor substrate including an integrated circuit;
A planarization layer mainly composed of an organic material provided on the upper layer of the substrate;
It has a compound semiconductor thin film bonded on the planarizing layer.

  According to the present invention, it is possible to reduce a compound semiconductor that is wasted in producing a composite semiconductor element. In addition, a magnetic sensor with low temperature dependence can be obtained.

(A) And (b) is the top view and sectional drawing which show the composite semiconductor element which concerns on Embodiment 1 of this invention. FIG. 3 is a diagram illustrating one stage of a method for manufacturing the composite semiconductor element according to the first embodiment. FIG. 3 is a diagram illustrating one stage of a method for manufacturing the composite semiconductor element according to the first embodiment. (A) And (b) is a figure which shows operation | movement of the Hall element based on Embodiment 1. FIG. FIG. 10 is a diagram showing one stage in a modified example of the method for manufacturing the composite semiconductor element according to the first embodiment. FIG. 6 is a circuit diagram showing the magnetic sensor according to the second embodiment of the present invention. FIG. 7 is a circuit diagram illustrating a configuration example of a reference voltage circuit in FIG. 6. FIG. 7 is a circuit diagram illustrating a configuration example of a control voltage generation circuit of FIG. 6. (A)-(d) is a figure which shows roughly the structure of the composite chip which mounts the Hall element based on Embodiment 2 of this invention, and a magnetic sensor using this composite chip, FIG.9 (a) 9B is a top view of the magnetic sensor chip, FIG. 9B is a cross-sectional view corresponding to the AA ′ portion of FIG. 9A, and FIG. 9C is a package product in which the magnetic sensor chip is assembled in a resin mold package. FIG. 9D is a similar side perspective view. It is a top view which shows the magnetic sensor produced by resin-sealing the chip | tip using the structure which concerns on Embodiment 2, and the conventional magnetic sensor for a comparison. It is a graph which shows the temperature coefficient of the reference voltage output from the reference voltage circuit of FIG. 10 is a graph showing a comparison between a temperature characteristic of the Hall voltage of the Hall element shown in FIG. 9 and an output temperature characteristic of the magnetic sensor circuit having the configuration of FIG. 6. 5 is a schematic cross-sectional view showing an image forming apparatus equipped with a magnetic sensor according to Embodiment 2. FIG. FIG. 14 is a cross-sectional view schematically illustrating a configuration of a toner cartridge of the printer described with reference to FIG. 13.

  In the following description, a signal and a terminal for inputting / outputting the signal may be indicated by the same symbol.

Embodiment 1 FIG.
(Configuration of Embodiment 1)
FIGS. 1A and 1B are diagrams schematically showing a configuration of a composite semiconductor element chip 10 in which a Hall element according to Embodiment 1 of the present invention is formed, and FIG. FIG. 1 and FIG. 1B are cross-sectional views corresponding to the AA ′ portion of FIG.

In FIG. 1A, a composite semiconductor element 10 has a chip 11 made of a silicon wafer substrate. A large number of the chips 11 are formed on a silicon wafer (not shown) and obtained by dividing into pieces using a known dicing technique.
The Hall element 12 shown hatched in a substantially ten-bundle shape is composed of a GaAs semiconductor layer. As will be described later, the epitaxial layer is peeled off from the base material of the GaAs wafer and pasted on the silicon wafer, and then required. The portion is formed by etching. At the time of this pasting, it is bonded and bonded (bonded) without using an adhesive.

  The composite semiconductor element chip 10 further includes an electrode pad 15 formed on the chip 11, a thin film wiring (metal wiring) 16 connecting the pad 15 and the Hall element 12, and a contact formed on the upper surface of the Hall element portion 12. Part 17.

In addition, the area | region enclosed with the broken line 13 is a sticking area | region of a GaAs epitaxial film, and the area | region where a GaAs epitaxial film is stuck is shown with the broken line 13. FIG. The epitaxial film is obtained by separating and peeling the above-described epitaxial layer on the GaAs wafer substrate into a film.
In the illustrated example, the epitaxial film has a rectangular shape, more specifically a square shape, and the length of one piece is shown as L2.

The flattened region surrounded by the alternate long and short dash line 14 reduces the surface roughness of the chip 11 (corresponding to the height difference between the valleys and peaks of the surface irregularities) before attaching the epitaxial film, For example, polyimide having excellent heat resistance and elasticity that can withstand high-temperature treatment can be used.
The surface roughness of the polyimide layer after planarization is preferably 5 nm or less.

The silicon substrate 11 on which the planarized region 14 is formed using photosensitive polyimide is subjected to plasma treatment in a reduced pressure environment using a plasma cleaning apparatus in order to activate the surface state of the polyimide layer.
Next, after the above-described epitaxial film 13 is loaded on the upper surface of the flattened region 14, the polyimide layer is slightly elastically deformed by pressurizing the epitaxial film 13 so that the surface roughness is eliminated. Adhering to each other, the epitaxial film and the polyimide layer are firmly bonded by intermolecular force.
At this time, the adhesive force can be further increased by heating the silicon substrate during the pressurization described above.

  Next, by using a well-known photolithography method, except the necessary portion of the epitaxial film region 13 is removed by etching, a substantially cross-shaped Hall element portion indicated by reference numeral 12 can be formed. In addition, although the Hall element part 12 shall be formed in a substantially cross-shaped shape as an example, this invention is not limited to this.

In FIG. 1A, the length of one side of the GaAs region 13 from which the Hall element portion 12 is formed is L2, and the side of a chip made of a silicon substrate is shown as a length L1. Of course, L2 <L1, and the area of the GaAs region 13 occupying the chip 11 is very small.
As will be described later, a large number of GaAs regions 13 are formed in the upper layer of the GaAs wafer on which the GaAs regions 13 are formed with minute gaps. The GaAs regions 13 are peeled off from the GaAs wafer and loaded on the chip 11. Thus, the GaAs epitaxial layer can be disposed without waste, and the GaAs wafer can be utilized without waste.

FIG.1 (b) is sectional drawing corresponding to the AA 'part of Fig.1 (a).
As shown in FIG. 1B, a passivation is formed on a silicon wafer base 11 so as to cover a metal layer 15 that forms electrode pads and an upper layer of the wafer base 11 including the peripheral edge of the pad 15. The protective film 21, the planarizing layer 14 made of polyimide, and the GaAs layer 12 described above are provided. The GaAs layer 12 is formed by etching so that a necessary portion remains after the epitaxial film 13 is laminated.
The protective film 21 has, for example, a single layer or multilayer structure including at least one of a silicon oxide film and a silicon nitride film.
The contact layer 22 is formed on the upper layer of the GaAs layer 12 and is made of a GaAs layer containing a higher concentration of impurities than the GaAs layer 12. The contact layer 22 corresponds to the contact portion 17 in FIG.

The metal wiring layer 23 is composed of a thin film wiring for connecting the Hall element 12 and the electrode pad 15 and corresponds to the wiring layer 16 in FIG.
In this manner, the contact region 17 can be formed by overlapping the metal wiring layer 23 at a predetermined position on the contact layer 22.

The metal wiring layer 23 is preferably a material that can be connected to the GaAs layer forming the contact layer 22 in an ohmic manner, and a material such as Au—Ge or Au—Ge—Ni can be used.
Further, as shown in FIG. 1B, by disposing the metal wiring layer 23 over the upper layer of the pad 15, the surface corrosion prevention of the pad 15 during dicing and the connection strength with the gold wire during wire bonding. It is more preferable because an effect such as an increase in the thickness can be obtained.

(Epitaxial film manufacturing method)
An epitaxial film manufacturing process necessary for forming the GaAs layer 13 shown in FIG. 1 will be described.
2 and 3 are cross-sectional views schematically illustrating the epitaxial film manufacturing process.

  The epitaxial layer 122 (described as an epitaxial layer 122 before being peeled and described as an epitaxial film 122 after being peeled off) is manufactured by metal organic chemical vapor deposition (MO-CVD) or metal organic chemical vapor deposition (MO-CVD). It can be performed using molecular beam epitaxy (MBE: Molecular Beam Epitaxy) or the like.

FIG. 2 is a diagram showing a stage in the process of manufacturing the epitaxial film described above.
As shown in FIG. 2, a buffer layer, an etching stop layer 101, and a release layer 102 are sequentially formed on the upper surface of a compound semiconductor wafer, for example, a GaAs wafer 100.
Note that InGaP can be used as the etching stop layer 101, and AlAs can be used as the release layer 102. The substrate 121 including the GaAs substrate after the epitaxial film is peeled from the release layer 102, as will be described later, is manufactured. This can be reused to form a new epitaxial layer.

  Next, a GaAs layer 103 containing a donor impurity, an etching stop layer 104, and a GaAs layer 105 containing a relatively high concentration of donor impurities are sequentially formed on the AlAs separation layer (sacrificial layer) 102.

As will be described later, the AlAs release layer 102 can be selectively removed by using a known photolithography method and wet etching method.
By appropriately selecting the composition of the chemical used for the wet etching, the etching rate for the AlAs release layer 102 can be remarkably increased as compared with the etching rate for the GaAs layer 103 and the etching stop layer 101. Can be selectively etched.
Thereby, the epitaxial film 122 can be peeled from the epitaxial film manufacturing substrate 121.

  FIG. 3 shows one stage of the process of peeling the epitaxial film 122 from the epitaxial film manufacturing substrate 121 during the above-described epitaxial film manufacturing process.

  As shown in FIG. 3, when the epitaxial layer 122 is peeled off, the groove 112 is formed in advance, and the epitaxial layer 122 is divided into small regions by the groove. Each of the small areas divided by the grooves is a part constituting one Hall element.

The groove 112 can be formed using a photolithography process and a wet etching process in which a region other than the predetermined region of the groove is masked with a resist or the like.
Note that FIG. 3 shows a state in which a part of the AlAs release layer 102 remains (the state in the middle of etching), but the AlAs release layer is finally held with the epitaxial film 122 held by means not shown. 102 is completely removed.

  When the epitaxial film 122 is peeled off, a support for supporting and protecting the epitaxial film can be provided on the epitaxial film 122. For example, when a support is provided on the epitaxial film 122, the surface of the epitaxial film support is adsorbed by, for example, vacuum adsorption or a photocurable adhesive sheet (adhesive sheet having a function of losing adhesiveness by light irradiation). , Can move to a predetermined position.

  The epitaxial film (indicated by reference numeral 13 in FIG. 1) formed in the shape of a substantially rectangular film using the groove portion 112 and the release layer 102 in this manner is brought into close contact with the upper portion of the planarizing layer 14 made of polyimide. The film 13 and the polyimide layer 14 are firmly bonded by the intermolecular force acting between the surfaces.

  Next, the contact layer 105 other than the contact region 17 in FIG. 1 is removed by etching by a photolithographic method, the etching stop layer 104 is also removed by using the InGaP etchant, and the Hall element in FIG. 1 is further obtained by photolithography. The Hall element portion 12 is formed by removing the GaAs layer 103 in a region other than the portion 12.

In this way, a part of the GaAs layer 105 in FIG. 3 becomes the contact part 17 in FIG. 1A, and a part of the GaAs layer 103 in FIG. 3 becomes the Hall element part 12 in FIG.
By providing the contact portion 22 between the metal wiring layer 23 and the hall element portion 12 in FIG. 1B as described above, alloying of the interface portion between the contact layer 22 and the metal wiring layer 23 is promoted, and the contact resistance thereof is increased. Can be minimized.

(Hall element operation)
FIG. 4 shows a simplified view of the main part of the Hall element 12 having the structure shown in FIGS. 1A and 1B. FIG. 4A is an enlarged plan view, and FIG. It is sectional drawing which follows the AA 'line of 4 (a).

As is well known from the theory of electronic properties,
The Hall element section 12 includes terminals HT1 to HT4, and applies a current Id from the terminal HT1 to the terminal HT2 as indicated by an arrow in a state where a magnetic field is applied in a direction perpendicular to the paper surface of FIG. When flowing, a Hall voltage Vh represented by the following equation is generated between the terminals HT3 and HT4.
Vh = Rh × Id × B / d (1)
Where Rh is the Hall coefficient,
B is a magnetic flux density, and indicates a magnetic field in a direction penetrating the Hall element 12 perpendicular to the paper surface.
Moreover, d shows the thickness of the semiconductor layer which comprises a Hall element, as FIG.4 (b) shows.

The Hall coefficient Rh is given by the following equation.
Rh = 1 / (N × q) (2)
Where q is the charge of the electron,
N is the carrier density.
On the other hand, when ρ is resistivity and μ is mobility,
Rh = ρ × μ (3)
It can be expressed as.

  As apparent from the equation (1), the magnetic flux density B can be detected by measuring the Hall voltage Vh, and as shown in the equation (3), the mobility μ varies due to a temperature change or the like. Even in this case, the variation of the Hall voltage can be compensated by changing the current Id so as to cancel the temperature coefficient of mobility.

In FIG. 4B, the passivation protection film 21 formed on the upper layer of the chip 11 made of a silicon base material, the planarization layer 14 made of polyimide or the like formed thereon, and the donor impurity formed thereon. A GaAs semiconductor layer 12 containing is shown.
As shown in the equation (1), the Hall voltage Vh is inversely proportional to the thickness d of the semiconductor layer. Therefore, in order to increase the Hall voltage Vh with respect to the magnetic flux density B, that is, to increase the detection sensitivity of magnetic flux, It can be seen that the thickness d should be reduced, and from equation (2) it can be seen that the carrier density should be lowered in order to increase the Hall coefficient.

On the other hand, increasing the carrier concentration lowers the sensitivity of the Hall element and is not suitable for high-precision magnetic field measurement, but has the advantage of reducing the temperature change rate of the Hall voltage. is necessary.
Therefore, the impurity concentration of the semiconductor layer (103 in FIG. 2) is preferably 10 ^{−17 to} 5 × 10 ⁻¹⁷ cm ⁻³ , particularly preferably 2 to 3 × 10 ⁻¹⁷ cm ⁻³ .

  Also, since the semiconductor layer has a low electron density, if it is made too thin, it will be depleted and no electrical conduction will occur. In order to avoid this, the thickness d of the semiconductor layer is preferably 0.1 μm or more.

(Modification)
FIG. 5 shows a modification of the manufacturing method described with reference to FIG. The same reference numerals as those in FIG. 2 denote the same layers.

  FIG. 5 is a diagram showing a stage in the process of manufacturing the epitaxial film in this modification. The epitaxial layer 122 (described as an epitaxial layer 122 before being peeled off and described as an epitaxial film 122 after being peeled off) is manufactured by metal organic chemical vapor deposition (MO-CVD) or metal organic chemical vapor deposition (MO-CVD). Molecular beam epitaxy (MBE: Molecular Beam Epitaxy) or the like can be used.

As shown in FIG. 5, a buffer layer, an etching stop layer 101, and a release layer 102 are sequentially formed on the upper surface of the GaAs wafer 100.
Note that InGaP can be used as the etching stop layer 101, and AlAs can be used as the release layer 102. The substrate 121 including the GaAs substrate after the epitaxial film is peeled from the release layer 102, as will be described later, is manufactured. This can be reused to form a new epitaxial layer.

  Next, on the AlAs release layer (sacrificial layer) 102, the GaAs layer 103, the buffer layer 131, the compound semiconductor layer 132 containing donor impurities, the etching stop layer 133, and a relatively high concentration (higher concentration than the GaAs layer 103). A GaAs layer 134 containing a donor impurity is sequentially formed.

  The compound semiconductor layer 132 shown in FIG. 5 is made of a material having a higher carrier mobility than GaAs such as InAs, InSb, InGaAsSb, etc., so that the Hall coefficient can be further increased, and a more sensitive magnetic sensor can be obtained. Can be realized.

  The compound semiconductor epitaxial layer 122 shown in FIG. 5 is formed by selectively removing the aforementioned AlAs release layer 102 using a known photolithography method and a wet etching method, as shown in FIG. Can be peeled off.

By appropriately selecting the composition of the chemical used for the wet etching, the etching rate for the AlAs release layer 102 can be remarkably increased as compared with the etching rate for the GaAs layer 103 and the etching stop layer 101. Can be selectively etched.
Thereby, the epitaxial film 122 can be peeled from the epitaxial film manufacturing substrate 121.
For this purpose, the groove 112 is preferably formed in advance when the epitaxial layer 122 is peeled in the same manner as shown in FIG.

(Effect of Embodiment 1)
Hall elements are manufactured using expensive compound semiconductor wafers,
The ratio of the area occupied by the Hall element part in the chip produced by dividing the wafer into pieces is small, and the area of the terminal pad part and the wiring part occupies most of the chip, which is uneconomical. was there.

On the other hand, in the configuration of the first embodiment (FIG. 1), the epitaxial layer formed on the compound semiconductor wafer is separated in a piecewise manner and bonded to a necessary portion on the silicon wafer as a base material. Since the configuration is adopted, the compound semiconductor is not wasted.
Furthermore, the compound semiconductor wafer substrate after peeling off the above-described epitaxial layer can be reused for the formation of the epitaxial layer.
In this way, it is possible to realize a Hall element having excellent economic efficiency by eliminating waste of material resources.

Embodiment 2. FIG.
(Configuration of Embodiment 2)
FIG. 6 is a circuit diagram showing a part of the magnetic sensor according to the second embodiment of the present invention using functional blocks. The reference voltage circuit 201 includes an output terminal VREF, and generates a reference voltage Vref from the terminal. Although the reference voltage Vref has a positive temperature coefficient with respect to the temperature, the temperature coefficient can be not only a positive value but also a negative value as described later, and the temperature coefficient is substantially zero. You can also. The internal configuration of the reference voltage circuit 201 will be described later.

The control voltage generation circuit (ADJ block) 202 includes a reference voltage input terminal VREF, correction signal input terminals SA3 to SA0, and a control voltage output terminal V. The internal configuration of the control voltage generation circuit 202 will be described later.
The illustrated magnetic sensor further includes a PMOS transistor 203, a Hall element portion 12 made of a GaAs semiconductor similar to that described in connection with the first embodiment, and an amplifier circuit 204. The amplifier circuit 204 includes an operational amplifier 215 and resistors 211 to 214. Resistance values of the resistors 211 to 214 are shown as RA1 to RA4 in the drawing.

  The output terminal VREF of the reference voltage circuit 201 is connected to the input terminal VREF of the control voltage circuit 202. Logic input terminals SA3 to SA0 of the control voltage circuit 202 are connected to a polysilicon fuse and a terminal pad (not shown). The purpose of adopting the above configuration is to correct manufacturing variations, and the outline thereof is as follows.

  First, electrical measurement is performed in the probing test after the manufacture of the magnetic sensor circuit shown in FIG. 6 is completed, and the degree of characteristic variation due to the semiconductor manufacturing process is grasped. Next, the logic levels of the logic input terminals SA3 to SA0 are determined so that the drive current of the Hall element becomes a predetermined value.

  Further, the polysilicon fuse is selectively blown by the test device so as to fix the logic levels of the logic input terminals SA3 to SA0. Although the above-described correction processing is intended to adjust the drive current of the Hall element, a similar configuration can be applied to the reference voltage circuit 201 and the amplifier circuit 204, and compensation of temperature characteristics and output characteristics of the magnetic sensor can be improved. Compensation can also be performed.

  Returning to the description of the other parts of FIG. 6, the source terminal of the PMOS transistor 203 is connected to the power supply VDD, the gate terminal is connected to the output terminal V of the control voltage circuit 202, and the drain terminal is connected to the terminal HT1 of the Hall element 12. Is done. A drain current of the PMOS transistor 203, that is, a current for driving the terminal HT1 of the Hall element 12 is indicated by a symbol Id.

  The Hall element terminal HT2 is connected to the ground, the Hall element terminal HT4 is connected to the input terminal 204A of the amplifier circuit 204, and the Hall element terminal HT3 is connected to the input terminal 204B of the amplifier circuit 204. The output terminal 204C of the amplifier circuit 204 is connected to the terminal Vo.

In the amplifier circuit 204 illustrated in FIG. 6, the terminal 204 </ b> A is connected to one end of the resistor 211, and the other end of the resistor 211 is connected to one end of the resistor 212 and the inverting input terminal of the operational amplifier 215.
The terminal 204B is connected to one end of the resistor 213, and the other end of the resistor 213 is connected to one end of the resistor 214 and the non-inverting input terminal of the operational amplifier 215. The other end of the resistor 214 is connected to the ground. The other end of the resistor 212 is connected to the output terminal of the operational amplifier 215, and is also connected to the output terminal 204C of the amplifier circuit 204. The output terminal of the operational amplifier 215 is connected to the output terminal Vo of the magnetic sensor.

Now, the potential of the input terminal 204A is Va, and the potential of the input terminal 204B is Vb. At this time, the output voltage Vo of the amplifier circuit 204 is Vo = [(RA1 + RA2) / (RA3 + RA4)] × (RA4 / RA1) × Vb− (RA2 / RA1) × Va.
Can be obtained as

Here, for simplification, RA1 = RA3, RA2 = RA4,
The Hall voltage Vh generated between the terminals HT3 and HT4 of the Hall element 12 is expressed as Vh = Vb−Va
If you sort it out,
Vo = (RA2 / RA1) × Vh
It becomes.

  Thus, by appropriately setting the ratio of the resistors RA1 and RA2, the Hall voltage Vh generated in the Hall element can be amplified to obtain the output voltage Vo having a desired voltage level.

  Note that the amplification circuit 204 in FIG. 6 has been described as an example in which amplification is performed using one operational amplifier in order to simplify the description. However, the amplification circuit 204 includes two or three operational amplifiers instead of the amplification circuit 204. An instrumentation amplifier (instrumentation amplifier) can also be used.

(Reference voltage circuit)
FIG. 7 shows the configuration of the reference voltage circuit (VREF) 201 in the second embodiment.
The illustrated reference voltage circuit 201 includes PMOS transistors 221 and 222, NPN bipolar transistors 223 and 224, and resistors 225 and 226.
The source terminals of the PMOS transistor transistors 221 and 222 are connected to the power supply VDD, and their gate terminals are connected to each other.
Further, the gate terminal and the drain terminal of the PMOS transistor 222 are connected.

  The drain terminal of the PMOS transistor 221 is connected to the base terminal of the bipolar transistor 223 via the resistor 226, and the base terminal and collector terminal of the NPN transistor 223 are connected via the resistor 225.

  The drain terminal of the PMOS transistor 222 is connected to the collector terminal of the NPN transistor 224, and the base terminal of the NPN transistor 224 is connected to the collector terminal of the NPN transistor 223.

  The emitter terminals of the NPN transistors 223 and 224 are connected to the ground. Further, the drain terminal of the PMOS transistor 221 is connected to the output terminal VREF, and generates the reference voltage Vref.

  Here, the emitter area of the NPN transistor 224 is set to N times the emitter area of the NPN transistor 223 (N> 1).

  In FIG. 7, the drain currents of the PMOS transistors 221 and 222 are denoted by reference numerals I1 and I2, respectively, the resistance value of the resistor 225 is RB1, the resistance value of the resistor 226 is RB2, and the connection point between the resistor 226 and the resistor 225 is denoted by reference numeral 223B. The collector portion of the NPN transistor is denoted by reference numeral 223C, and the base-emitter voltage of the NPN transistor 223 is denoted as Vbe1, and the base-emitter voltage of the NPN transistor 224 is denoted as Vbe2.

(Configuration of control voltage generation circuit (ADJ circuit))
FIG. 8 shows an example of the internal configuration of the control voltage generation circuit (ADJ circuit) 202 of FIG.
The control voltage generation circuit 202 shown in FIG.
An operational amplifier 231, a PMOS transistor 232, an analog multiplexer circuit 233, and a resistor string RCH are included.
The source of the PMOS transistor 232 is connected to the power supply VDD, the gate terminal is connected to the output terminal of the operational amplifier 231 and the terminal V, and the control voltage Vcontrol is output from the terminal V.

  The PMOS transistor 232 has the same gate length as the PMOS transistor 203 of FIG. Further, the drain current of the PMOS transistor 232 is indicated by a symbol Iref in the drawing.

  The inverting input terminal of the operational amplifier 231 is connected to the VREF terminal, the reference voltage Vref is applied, the non-inverting input terminal is connected to the output terminal Y of the multiplex 233 described later, and the output terminal of the operational amplifier 231 is connected to the PMOS transistor 232. The gate terminal is connected to the terminal V, and is connected to the gate terminal of the PMOS transistor 203 in FIG. The resistor string RCH is formed by connecting 16 resistors R00 to R15 in series.

  The multiplexer circuit 233 includes 16 input terminals P0 to P15 to which analog voltages are input, an output terminal Y to output analog voltages, and four input terminals SB3 to SB0 to which logic signals are input. One of the input terminals P <b> 0 to P <b> 15 is selected by a combination of 16 signal logics set by the logic signal, and the potential applied to the terminal is output from the output terminal Y. In other words, any one of the input terminals P0 to P15 is selected according to the logic signal level of the input terminals SB3 to SB0, and a current path is formed between the input terminals P0 to P15.

A feedback control circuit is configured by a circuit including the operational amplifier 231, the resistor string RCH, and the PMOS transistor 232, and the potential of the non-inverting input terminal of the operational amplifier 231 is controlled to be substantially equal to Vref.
For this reason, the drain current Iref of the PMOS transistor 232 of FIG. 8 is the combined resistance value of the portion selected by the multiplexer 233 (the combined resistance value from the portion selected by the multiplexer 223 to the ground) of the resistors R00 to R15. And the reference voltage Vref input to the operational amplifier 231.

More specifically, for example, when the logical values of the input terminals SB3 to SB0 are “1111” and the correction state is commanded to be maximum, the input terminal P15 and the output terminal Y of the multiplexer 233 are The conduction state is set, and the potential of the input terminal P15 is controlled to be substantially equal to the reference voltage Vref. As a result, the drain current Iref of the PMOS transistor 232 is
Iref = Vref / R00
It becomes.

Further, when the logical values of the input terminals SB3 to SB0 are “0111” and the center of the correction state is commanded, the input terminal P7 and the output terminal Y of the multiplexer 233 are brought into conduction, and the input terminal P7. Is controlled to be substantially equal to the reference voltage Vref. As a result, the drain current Iref of the PMOS transistor 232 is
Iref = Vref / (R00 + R01 +... + R07 + R08)
It becomes.

Furthermore, when the logical values of the input terminals SB3 to SB0 are “0000” and the minimum correction state is instructed, the input terminal P0 and the output terminal Y of the multiplexer 233 are brought into conduction, and the input terminal Control is performed such that the potential of P0 is substantially equal to the reference voltage Vref. As a result, the drain current Iref of the PMOS transistor 232 is
Iref = Vref / (R00 + R01 +... + R14 + R15)
It becomes.

  As described above, the PMOS transistor 203 and the PMOS transistor 232 in FIG. 6 are configured to have the same gate length and are controlled so as to operate in the saturation region. Thus, a drain current Id proportional to the reference current Iref is generated in the PMOS transistor 203.

  As a result, the drain current Iref of the PMOS transistor 232 can be adjusted to 16 stages according to the logical value state applied to the input terminals SB3 to SB0 of the multiplexer 233, and the drain current of the PMOS transistor 203 of FIG. can do.

(Magnetic sensor)
FIGS. 9A to 9D schematically show a configuration of a composite chip 241 on which the Hall element according to the second embodiment is mounted and a magnetic sensor using the composite chip.
9A is a top view of the magnetic sensor chip, FIG. 9B is a cross-sectional view corresponding to the AA ′ portion of FIG. 9A, and FIG. 9C is a resin mold package for the magnetic sensor chip. FIG. 9D is a similar side perspective view of the package product assembled in FIG.

In FIG. 9 (a), a number of chips made of a silicon wafer substrate (the outline of which is indicated by reference numeral 241) are formed on a silicon wafer (not shown) and separated into pieces using a known dicing technique. It is.
The Hall element portion 12 made of a substantially cross-shaped GaAs semiconductor layer indicated by hatching is formed using the method described with reference to FIGS. 1A and 1B, FIG. 2 and FIG. After the epitaxial layer is peeled off from the GaAs wafer base material and pasted on the silicon wafer, the required portion is formed by etching.

  A pad electrode 15 is formed on the chip 241. In addition to the output terminal Vo shown in FIG. 6, three pad electrodes 15 are shown as a power supply VDD terminal and a ground terminal.

Note that 242A surrounded by a broken line indicates an arrangement region of a control circuit portion formed using a silicon semiconductor including the reference voltage circuit 201, the control voltage generation circuit 202, the PMOS transistor 203, the amplifier circuit 204, and the like in FIG. In consideration of mechanical damage given to the lower layer of the pad electrode at the time of wire bonding, the control circuit unit is disposed in a region (242A) avoiding the pad unit 15.
Further, in order to effectively use the area of the chip 241, the Hall element unit 12 can be arranged on the upper part of the control circuit arrangement region 242A.

  FIG. 9B is a cross-sectional view corresponding to the AA ′ portion of the top view of the magnetic sensor chip described with reference to FIG. 9A, and includes the silicon substrate 11, the pad electrode 15, and the circuit arrangement. A control circuit part 242C, a passivation protection film 21, a thin film wiring (metal wiring) 23, a planarization layer 14 and a Hall element part 12 arranged in the region 242 are shown.

The control circuit unit 242C includes circuit members such as the reference voltage circuit 201, the control voltage generation circuit 202, the PMOS transistor 203, and the amplification circuit 204 shown in FIG.
Although the thin film wiring (metal wiring) 23 is also arranged in the upper layer of the pad electrode 15 in FIG. 9, the contact portion (not shown) of the Hall element 12 and the predetermined terminal of the control circuit portion arranged in the circuit arrangement region 242 Is connected.

  The planarization layer 14 reduces the surface roughness of the chip 11 (corresponding to the height difference between the valleys and peaks of the surface irregularities) before attaching the epitaxial film, thereby improving the adhesion with the epitaxial film. Therefore, it is possible to use polyimide that is provided with high heat resistance and elasticity that can withstand high temperature processing. The surface roughness after planarization is preferably 5 nm or less.

The silicon wafer on which the planarization layer 14 is formed using photosensitive polyimide is subjected to plasma treatment in a reduced pressure environment using a plasma cleaning apparatus in order to activate the surface state of the polyimide layer.
Next, after the above-described epitaxial film is loaded on the upper surface of the flattening layer 14, the polyimide layer is slightly elastically deformed by pressing with the epitaxial film interposed therebetween, and the surface roughness is eliminated, thereby being adhered. Thus, the epitaxial film and the polyimide layer are firmly bonded by intermolecular force. In addition, the adhesive force can be further increased by heating the silicon base material during the pressurization described above.

  Next, a substantially cross-shaped Hall element portion 12 can be formed by etching and removing a portion other than the necessary portion of the epitaxial film region using a known photolithography method. In addition, although the Hall element part 12 shall be formed in the substantially cross shape as an example, this invention is not limited to this.

  As is apparent with reference to FIGS. 9A and 9B, the area of the GaAs region 12 occupying the chip 11 (outline 241) is very small, and the epitaxial film area required to form it is also minimal. It is. A large number of the epitaxial films are formed on the upper layer of the GaAs wafer with minute gaps, and the epitaxial film is peeled off from the GaAs wafer and loaded on the chip 11 to waste the GaAs epitaxial layer 122 shown in FIG. The GaAs wafer can be used without waste.

A composite chip (FIG. 6) using the configuration of the second embodiment is formed by combining the silicon chip 241 and the Hall element 12 described above.
FIG. 9C is a top perspective view of a magnetic sensor formed by resin-sealing the composite chip.
The illustrated magnetic sensor includes lead frame terminal portions 251, 252, and 253 of the magnetic sensor formed by resin sealing, an island portion 254 of a lead frame on which the composite chip 241 is mounted, and a pad portion 15 of the composite chip. And a bonding wire 256 for connecting the lead frame terminal portion and an epoxy mold portion 255 for resin sealing.

  FIG. 9D corresponds to FIG. 9C and is a side perspective view of a magnetic sensor formed by resin-sealing the composite chip.

(Comparison with conventional configuration)
10A and 10B are diagrams showing a magnetic sensor produced by resin-sealing a chip using the configuration of the second embodiment, and a conventional magnetic sensor for comparison.

FIG. 10A is a top perspective view of the magnetic sensor according to the second embodiment, and corresponds to FIG. 9C. On the other hand, FIG. 10B is a top perspective view of a similar magnetic sensor in the conventional configuration.
In the magnetic sensor shown in FIG. 10B, a Hall element chip 301 using a GaAs substrate is composed of a Hall element portion, an electrode pad, and the like that are hatched. The control circuit chip 302 is formed on the upper layer using a silicon substrate. The Hall element chip 301 and the control circuit chip 302 are mounted on the island portion 254 of the lead frame, and the pad electrode and the lead frame terminal of the control circuit chip 302 are connected by the bonding wire 256 and at the same time. The control circuit chip 302 is also connected to predetermined terminal pad portions by bonding wires.

  10A and 10B, the control circuit chip 302 having the conventional configuration includes not only the output terminal Vo, the power supply VDD terminal, and the ground terminal shown in FIG. It is necessary to dispose four pad electrodes for connection to the chip, and the chip size is larger than that of FIG. In addition, in the conventional configuration, since a plurality of chips are mounted on the island of the lead frame, the area required for the configuration is large, and the resin-sealed package outer shape 255 is also enlarged. End up. On the other hand, by adopting the configuration of the second embodiment, it is possible to downsize the package shape sealed with resin.

(Operation of the reference voltage circuit 201)
Let us calculate the output voltage Vref generated at the output terminal VREF in the reference voltage circuit 201 described with reference to FIGS. For this purpose, first, the current I1 is obtained. As is well known from the theory of electronic properties, the following relationship holds between the emitter current Ie of the bipolar transistor and the base-emitter voltage Vbe.
Ie≈Is × exp (qVbe / (kT))
Here, Is is a saturation current, which is a constant determined in proportion to the element area of the bipolar transistor.
exp () is an exponential function,
q is the charge of the electron, q = 1.6 × 10 ⁻¹⁹ [C],
k is Boltzmann's constant, k = 1.38 × 10 ⁻²³ [J / K],
T is an absolute temperature and is about 298 [K] at a room temperature of 25 [° C.].

The above equation is transformed to obtain the following equation.
Vbe = (kT / q) × ln (Ie / Is)
Note that ln () is a natural logarithmic function.
Here, for the NPN transistors 223 and 224,
The emitter-to-emitter voltage is Vbe1, Vbe2,
The emitter current is Ie1, Ie2,
The saturation current is Is1, Is2
Will be written.

At this time, the following equation holds for the bipolar transistors 223 and 224.
Vbe1 = (kT / q) × ln (Ie1 / Is1)
Vbe2 = (kT / q) × ln (Ie2 / Is2)
Referring to FIG. 7, the potential at one end of the resistor RB1 is Vbe1, and the potential at the other end is Vbe2.
Therefore, the potential difference ΔVbe generated across the resistor RB1 is ΔVbe = Vbe1−Vbe2
It is. Substituting the above two formulas into the previous formula,
ΔVbe = (kT / q) × [ln (Ie1 / Isl) −ln (Ie2 / Is2)]
= (KT / q) × ln [(Is2 / Isl) × (Ie1 / Ie2)]
Is obtained.
As described above, the emitter area ratio of the bipolar transistors 223 and 224 is set to 1: N and (N> 1), and the saturation current is proportional to the element area of the transistor.
Is2 = Is1 × N
It becomes.

Further, as described above, the PMOS transistors 221 and 222 have a current mirror relationship, and I1 = I2. In this way, Ie1 and Ie2 are substantially equal,
ΔVbe = (kT / q) × ln (N)
The relationship is obtained.

Since the current I1 shown in FIG. 7 is substantially equal to the current flowing through the resistor RB1,
I1 = ΔVbe / RB1
= (1 / RB1) × (kT / q × ln (N)
It is.
Since the current I1 flows through the resistor RB2, the potential Vref at the VREF output terminal is Vref = I1 × RB2 + Vbe1.
= (RB2 / RB1) × (kT / q) × ln (N) + Vbe1 (4)
It is obtained.

The first term of the equation (4) shows a positive temperature coefficient with respect to the absolute temperature, whereas the temperature coefficient of the base-emitter voltage of the bipolar transistor, which is the second term, is about −2 mV / ° C., which is negative. With dependencies.
As a result, the temperature dependence of the Vref potential can be set to a positive value, a negative value, or substantially zero by appropriately setting the ratio of the resistors RB2 and RB1 in the above equation.

(Temperature coefficient of reference voltage Vref)
FIG. 11 is a graph showing the temperature coefficient of the reference voltage Vref output from the reference voltage circuit 201. The horizontal axis shows the set value of the voltage Vref, and the vertical axis shows the temperature coefficient of the voltage Vref.

A point SD shown on the graph is when the resistance value RB2 (resistance value of the resistor 226 in FIG. 7) is substantially zero, and the voltage Vref at this time corresponds to the base-emitter voltage Vbe1 of the NPN transistor 223. As described above, the temperature dependency is about 12 mV / ° C., and when the base-emitter voltage is 0.6 V, the temperature coefficient Tc is
Tc = -2 × 10 ⁻³ /0.6=−0.33 [% / ° C.]
It is.

  On the other hand, the point SE in the graph corresponds to the case where the voltage Vref is about 1.25 V, and this voltage is called a bandgap reference voltage, and it is well known that its temperature coefficient is substantially zero. .

Further, when the resistance value RB2 is selected to be large and the voltage Vref is set to be high, the first term becomes larger than the second term and becomes dominant in the above equation (4) of the voltage Vref. At this time, the temperature coefficient Tc of the first term is (1 / T), and when the room temperature T = 300 [K], Tc = + 0.33 [% / ° C.]
It becomes.

  In the graph of FIG. 11, a portion having a temperature coefficient of zero is indicated by a broken line, and an asymptotic line (+ 0.33% / ° C. line) of the graph when the voltage Vref is set high is indicated by a one-dot chain line.

  As apparent from FIG. 11, by using the reference voltage circuit having the configuration of FIG. 7, the temperature coefficient can be set to a desired value from -033% / ° C. to + 0.33% / ° C. it can. As a result, the value of the voltage Vref also increases or decreases, and the resistance value of R00 to R15 shown in FIG. 8 is adjusted accordingly to keep the value of the reference current Iref in FIG. 8 at a predetermined value. Can do.

(Temperature dependence of Hall element)
FIG. 12 is a graph showing a comparison between the temperature characteristic (curve CF) of the Hall voltage Vh of the Hall element 12 shown in FIG. 9 and the temperature characteristic (curve CG) of the output of the magnetic sensor circuit having the configuration of FIG. For easy comparison, the value at room temperature is 100%, and the change with respect to temperature is displayed as a percentage.

  The Hall element in the configuration of FIG. 9 uses an epitaxial film of a GaAs semiconductor, and the Hall voltage Vh changes by + 4% at a temperature of −50 ° C. and −6% at + 150 ° C. as indicated by the curve CF.

In the temperature range (−50 ° C. to 150 ° C.), the fluctuation range of the Hall voltage is 10%.
−10% / (150 − (− 50)) = − 0.05 [% / ° C.]
This is due to the fact that the carrier mobility of the GaAs semiconductor layer varies with temperature.
From this, the Hall coefficient Rh has the temperature dependency described above.

  On the other hand, the curve CG shows the temperature characteristic of the output voltage Vo in the magnetic sensor having the configuration of FIG. In FIG. 6, the temperature coefficient of the output voltage Vref of the reference voltage circuit 201 shown in FIG. 6 is +0.05 [% / ° C.] so as to correct the temperature characteristic −0.05 [% / ° C.] of the curve CF. Is set.

  As a result, the reference current Iref in FIG. 8 increases at a rate of +0.05 [% / ° C.] with respect to the temperature, and the drive current Id of the Hall element given the relationship between the current Iref and the current mirror also changes to the temperature. On the other hand, it increases at a rate of +0.05 [% / ° C.].

As described above, the Hall voltage Vh obtained from the Hall element 12 is given by the following equation.
Vh = Rh × Id × B / d
From the above equation, the Hall element drive current Id has the positive temperature coefficient, so that the negative temperature dependence of the Hall coefficient Rh can be compensated, and a substantially constant sensor output voltage can be obtained with respect to the temperature change. .

  By doing so, it can be seen that the curve CG of FIG. 12 has a characteristic that is substantially constant with respect to a temperature change, and its temperature dependency is remarkably improved.

  As described above, the reference voltage generation circuit 201 generates an output voltage having a polarity opposite to that of the temperature coefficient of the Hall voltage generated from the Hall element 12 formed of the compound semiconductor thin film and having substantially the same absolute value. It operates as a temperature compensation circuit that compensates for the temperature dependence of the Hall element. The control voltage generation circuit 202 and the PMOS transistor 203 controlled by the reference voltage output from the reference voltage circuit 201 are controlled by the output of the reference voltage generation circuit 201 to generate a drive current corresponding to the temperature, and are composed of a compound semiconductor thin film. The hall element 12 is driven.

(Effect of Embodiment 2)
A conventional magnetic sensor using a Hall element includes a multi-chip module in which a Hall element chip in which a compound semiconductor is formed on a GaAs substrate and a signal processing unit chip using a silicon substrate are housed in one package. It was realized as a hybrid IC configuration. Since the magnetic sensor IC using the Hall element chip and the signal processing unit chip described above needs to mount the chip on a lead frame and connect the electrode pads between the chips with wires, the package size is increased. There was a problem of ending up.
On the other hand, in the configuration of the second embodiment (FIG. 9), the epitaxial layer formed on the compound semiconductor wafer is sectioned and bonded to the main part on the silicon wafer as a base material. Since the configuration is adopted, the compound semiconductor is not wasted.

In addition, on the silicon wafer, there is provided a drive circuit for driving the Hall element at a constant current and compensating for the temperature dependence of the Hall element, and the temperature dependence of the magnetic sensor comprising the Hall element. The effect that it can suppress is acquired.
Thus, by eliminating the waste of material resources, it is possible to realize a magnetic sensor that is excellent in economy and excellent in temperature characteristics.

(Usage form)
The Hall elements and magnetic sensors described in connection with Embodiments 1 and 2 above can be used for detecting the rotational speed of brushless motors and various sensors in electrophotographic printers. Hereinafter, a tandem color printer will be taken as an example, and the operation will be described with reference to FIGS.

(Tandem color printer)
FIG. 13 is a schematic cross-sectional view illustrating an image forming apparatus equipped with the magnetic sensor according to the second embodiment. The magnetic sensor according to the second embodiment is included in a toner cartridge constituting the developing device of the image forming apparatus. An example of application when used as a toner remaining amount sensor will be described.

  In FIG. 13, an image forming apparatus 600 includes four process units 601 to 604 that respectively form black (K), yellow (Y), magenta (M), and cyan (C) images. Are arranged in order from the upstream side of the conveyance path 620 of the recording medium 605. Since the internal configurations of the process units 601 to 604 are common, the internal configuration will be described below using the magenta process unit 603 as an example.

  In the process unit 603, a photosensitive drum 603a as an image carrier is rotatably arranged in the direction of an arrow. Around the photosensitive drum 603a, a charging device 603b and an exposure device 603c are sequentially arranged from the upstream side in the rotation direction. A developing device 603d and a cleaning device 603e are provided.

The charging device 603b supplies a charge to the surface of the photosensitive drum 603a to charge it.
The exposure device 603c selectively irradiates light on the surface of the charged photosensitive drum 603a to form an electrostatic latent image. For example, an LED head is used as the exposure apparatus 603c.

The developing device 603d generates a visible image by attaching magenta (predetermined color) toner to the surface of the photosensitive drum 603a on which the electrostatic latent image is formed. The developing device 603d includes a toner cartridge described later. .
The cleaning device 603e removes the toner remaining when the visible image of the toner on the photosensitive drum 603a is transferred.
The drums or rollers used in these devices rotate by receiving power from a drive source (not shown) via gears.

  In addition, the image forming apparatus 600 has a paper cassette 606 for storing a recording medium 605 such as paper stacked in a lower portion thereof, and a recording medium 605 is separated and transported one by one above the paper cassette 606. A hopping roller 607 is provided. Further, by sandwiching the recording medium 605 together with the pinch rollers 608 and 609 on the downstream side of the hopping roller 607 in the conveying direction of the recording medium 605, the conveying roller 610 for conveying the recording medium and the recording medium 605 are skewed. A registration roller 611 that is corrected and conveyed to the process unit 601 is disposed. The hopping roller 607, the transport roller 610, and the registration roller 611 are rotated by power transmitted from a driving source (not shown) via a gear or the like.

  Transfer rollers 612 made of semiconductive rubber or the like are disposed at positions facing the respective photosensitive drums of the process units 601 to 604. These transfer rollers 612 have a potential difference between the surface potentials of the photosensitive drums 601 a to 604 a and the surface potentials of the respective transfer rollers 612 at the time of transferring the visible image by the toner attached on the photosensitive drum 603 a to the recording medium 605. A potential is applied for the purpose.

  The fixing device 613 includes a heating roller and a backup roller, and fixes the toner transferred on the recording medium 605 by pressurizing and heating. The downstream discharge rollers 614 and 615 sandwich the recording medium 605 discharged from the fixing device 613 together with the pinch rollers 616 and 617 of the discharge unit and convey them to the recording medium stacker unit 618. The fixing device 613, the discharge roller 614, and the like are rotated by transmission of power from a drive source (not shown) via gears.

Next, the operation of the image recording apparatus having the above configuration will be described.
First, the recording medium 605 stored in a stacked state in the paper cassette 606 is separated and transported one by one from the top by the hopping roller 607. Subsequently, the recording medium 605 is sandwiched between the conveyance roller 610, the registration roller 611, and the pinch rollers 608 and 609 and is conveyed between the photosensitive drum 601 a of the process unit 601 and the transfer roller 612. Thereafter, the recording medium 605 is sandwiched between the photosensitive drum 601a and the transfer roller 612, and a toner image is transferred to the recording surface thereof and is simultaneously conveyed by the rotation of the photosensitive drum 601a.

  Similarly, the recording medium 605 sequentially passes through the process units 602 to 604, and the electrostatic latent images formed by the exposure devices 601c to 604c in the passing process are developed for the respective colors developed by the developing devices 601d to 604d. The toner images are sequentially transferred onto the recording surface and superimposed.

  Then, after the toner images of the respective colors are superimposed on the recording surface, the recording medium 605 on which the toner image is fixed by the fixing device 613 is sandwiched between the discharge rollers 614 and 615 and the pinch rollers 616 and 617, and the image is transferred. The recording medium is ejected to a recording medium stacker 618 outside the recording apparatus 600. Through the above process, a color image is formed on the recording medium 605.

(Toner cartridge)
FIG. 14 is a cross-sectional view schematically showing a configuration of a toner cartridge constituting the developing device (for example, 603d) of the image forming apparatus described with reference to FIG.
The illustrated toner cartridge has a rod 701 provided in the toner cartridge main body 700.
One end (lower end) of the rod 701 is rotatably connected to an agitation shaft 705 forming a crank portion.
The other end (upper end) of the rod 701 is slidably connected to a guide portion 702 provided on the upper portion of the toner cartridge case 700.
A magnet 703 is attached to the other end portion (upper end) of the rod 701 so as to exert a magnetic force on the magnetic sensor 710 via a film 704 provided on the upper wall of the guide portion 702.
The magnetic sensor 710 having the structure of the second embodiment can be used.

  The toner cartridge main body 700 is further provided with a swinging portion 707 and a knob portion 708. The knob portion 708 moves a fixing claw (not shown in FIG. 14) that fixes the toner cartridge and the photosensitive drum unit (not shown).

The toner cartridge body 700 contains toner 706,
The rotation speed of the stirring shaft 705 in the arrow direction varies depending on the remaining amount of the toner 706.
That is, when the toner 706 is full, the resistance to the rotation of the stirring shaft 705 is large, and the rotation of the stirring shaft is slowed. On the other hand, when the toner 706 is consumed and the remaining amount decreases, the volume of the upper gap is increased. In addition, the resistance to rotation of the agitation shaft 705 is reduced, resulting in faster rotation.

  The rotation of the stirring shaft 705 is transmitted as the vertical movement of the magnet 703 via the rod 701 and appears as a duty ratio of a magnetic force change waveform to the magnetic sensor 710. As a result, the remaining amount of toner in the toner cartridge can be detected by detecting the duty ratio of the waveform obtained from the magnetic sensor.

In addition to the above, by using the magnetic sensor described in connection with the second embodiment, it is possible to provide a high-quality image forming apparatus (printer, copier, etc.) that can accurately detect the remaining amount of toner.
The same effect can be obtained not only in the above-described full-color image forming apparatus but also in a monochrome or multi-color image forming apparatus.

  The case where the Hall element having the configuration described with respect to Embodiments 1 and 2 is used in an image forming apparatus such as a printer has been described above. However, the present invention is not limited to this, and the magnetized rotor portion of the brushless motor is Rotation speed detection, current sensor that detects the current value by detecting the magnetic field generated around the current when the current flows through the electric wire, mounted on the mobile phone with GPS (Global Positioning System) function, It can be used for a wide range of applications such as a geomagnetic sensor that measures the direction and intensity of geomagnetism.

  DESCRIPTION OF SYMBOLS 11 Substrate, 12 Semiconductor thin film, 14 Planarization layer, 17 Contact layer, 23 Metal wiring film, 201 Reference voltage circuit, 202 Control voltage generation circuit, 203 PMOS transistor, 204 Amplifier circuit, 700 Toner cartridge, 710 Magnetic sensor

Claims (13)

A substrate,
A planarization layer comprising an organic material as a main material provided on the substrate;
A composite semiconductor element comprising a semiconductor thin film including a compound semiconductor element and bonded onto the planarizing layer. The composite semiconductor element according to claim 1, wherein the semiconductor thin film is a compound semiconductor containing any one of GaAs, InAsInSb, and InGaAsSb. The compound semiconductor thin film according to claim 2, wherein the compound semiconductor thin film has an impurity concentration of 10 ^{−17 to} 5 × 10 ⁻¹⁷ cm ⁻³ . A metal wiring film for electrical connection with the compound semiconductor thin film is further provided, and a compound semiconductor layer having a higher impurity concentration than the compound semiconductor element thin film is interposed between the compound semiconductor thin film and the metal wiring film. The composite semiconductor device according to claim 3. Forming a planarization layer on a silicon wafer substrate;
On the upper surface of the compound semiconductor wafer,
Forming a release layer; and
On the release layer,
Depositing an epitaxial layer including a first compound semiconductor layer;
Forming a groove in the epitaxial layer and dividing it into a plurality of small regions;
Etching the release layer to release the divided epitaxial layer from the substrate to obtain an epitaxial film;
Adhering an epitaxial film onto the planarizing layer on the silicon wafer.   6. The method of manufacturing a composite semiconductor element according to claim 5, further comprising a step of dicing the silicon wafer to which the epitaxial film is closely attached by dicing. The epitaxial layer further includes a second compound semiconductor layer having a higher impurity concentration than the first compound semiconductor layer;
7. The method of manufacturing a composite semiconductor element according to claim 6, wherein a contact layer is formed on the second compound semiconductor layer by photolithography and etching. A semiconductor substrate including an integrated circuit;
A planarization layer mainly composed of an organic material provided on the upper layer of the substrate;
A magnetic sensor comprising a compound semiconductor thin film bonded on the planarizing layer. The said board | substrate is a semiconductor substrate containing an integrated circuit, Comprising: The surface layer is provided with the protective film of the single layer or multilayer structure containing at least one of a silicon oxide film and a silicon nitride film. The magnetic sensor according to 8.   The magnetic sensor according to claim 8, wherein the semiconductor thin film is provided on a region where the integrated circuit is formed. A semiconductor substrate including the integrated circuit includes a voltage generation circuit that generates an output voltage corresponding to temperature, and a current driving circuit.
The magnetic sensor according to claim 8, wherein the current driving circuit is controlled by an output of the voltage generating circuit to generate a driving current corresponding to a temperature, and the compound semiconductor thin film is driven by the current. The compound semiconductor thin film generates a Hall voltage,
The voltage generation circuit generates an output voltage having a polarity opposite to the temperature coefficient of the Hall voltage and approximately equal in absolute value so as to compensate for the temperature dependence of the Hall voltage generated from the compound semiconductor thin film. The magnetic sensor according to claim 11.   An image forming apparatus using the magnetic sensor according to claim 8 as a toner remaining amount sensor in a toner cartridge.

Images