JP2011238681A - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device having a structure capable of suppressing the operation of a parasitic bipolar transistor and improving the withstand capability irrespective of carrier lifetime control.
In a region where a diode structure is formed, not only a p ⁺ type impurity region 2 but also an n ⁺ type impurity region 3 is partially formed on the back surface side of an n ⁻ type drift layer 1. As a result, the width of the p ⁺ -type impurity region 2 is narrowed, and as a result, the distance from the boundary between the p ⁺ -type impurity region 2 and the n ⁺ -type impurity region 3 is shortened. Therefore, the bias voltage is reduced by reducing the internal resistance of the n ⁻ -type drift layer 1, and the operation of the parasitic bipolar transistor can be suppressed. Therefore, irrespective of the carrier lifetime control, the operation of the parasitic bipolar transistor can be suppressed and the withstand capability can be improved.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device provided with a diode structure.

  Conventionally, in an inverter circuit for performing DC-AC conversion, an insulated gate bipolar transistor (hereinafter referred to as IGBT) and a free wheel diode (hereinafter referred to as FWD) functioning as a switching element are integrated in the same chip. Used semiconductor devices are used. DC-AC exchange is performed by turning on and off the IGBT, and when the IGBT is turned off, a current flowing through a load (for example, a motor) is returned through the FWD.

FIG. 4 is a cross-sectional view of this conventional semiconductor device. As shown in this figure, in the conventional semiconductor device, a p-type base region J2, an n ⁺ -type impurity region J3 serving as an emitter region, and a trench gate structure J4 are formed on the surface of an n-type drift layer J1, and an n-type An IGBT is formed by forming a p ⁺ -type impurity region J5 serving as a collector region on the back side of the drift layer J1. Further, by forming the p-type deep well layer J6 so as to surround the outer periphery of the region where the IGBT is formed, by providing the FWD composed of the p-type deep well layer J6 and the n-type drift layer J1, the IGBT and FWD are provided. The cell area is configured.

In this semiconductor device, the entire surface of the back surface of the n-type drift layer J1 is not the p ⁺ -type impurity region J5, but an n ⁺ -type impurity region J7 that partially serves as a cathode region is formed, thereby forming the n-type drift layer The collector of IGBT and the cathode of FWD are configured on the back surface of J1.

In such a semiconductor device, if the back surface of the portion disposed below the p-type deep well layer J6 in the n-type drift layer J1 is the entire n ⁺ -type impurity region J7, the forward bias is applied during recovery, that is, When a diode is operated by injecting holes from the hanging p-type deep well layer J6, excessive injection of holes from the p-type deep well layer J6 may result in a decrease in withstand capability, leading to destruction. For this reason, as shown in FIG. 4, the back surface of the portion of the n-type drift layer J1 disposed below the p-type deep well layer J6 is a p ⁺ -type impurity region J5, whereby the p-type deep well layer J6 The hole injection from the surface is suppressed, and the resistance is improved.

JP 2007-227806 A

In the semiconductor device having the above structure, at the time of recovery, holes are basically extracted upward and electrons are extracted downward, but carriers (holes) accumulated in the n-type drift layer J1 are extracted from the p-type deep well layer J6. The n ⁺ type impurity region J7 may escape through the n type drift layer J1. In this case, a bias is applied between the PN junction formed by the p ⁺ -type impurity region J5 and the n-type drift layer J1, the parasitic bipolar transistor operates, and holes are reinjected. Bipolar transistor operation has a negative temperature characteristic with respect to temperature, and has a negative resistance when an avalanche breakdown occurs, so that there is a problem that the element is easily destroyed.

On the other hand, there is a technique for controlling the lifetime of carriers by performing electron beam irradiation and the like so that the parasitic bipolar transistor does not operate due to carriers accumulated in the n-type drift layer J1. However, since the electron beam irradiation for lifetime control is simultaneously performed not only in the region where the FWD is formed but also in the cell region where the IGBT is formed, the on-voltage of the IGBT is increased. In order to suppress the increase in the on-voltage, problems such as an increase in the impurity concentration (boron concentration) of the p ⁺ -type impurity region J5 also occur.

In the above description, the IGBT is taken as an example of the switching element. However, in the case where a simple diode is provided with a diode structure, a p ⁺ type impurity region J5 is provided to suppress hole injection at the outer periphery during FWD operation. In addition, the above problem can also occur when a rapid current change during recovery is suppressed. Even in a MOSFET or an npn bipolar transistor, a diode may be formed in the same chip and a p ⁺ -type impurity region J5 may be disposed, which may cause the same problem with respect to FWD characteristics.

  In view of the above-described points, an object of the present invention is to provide a semiconductor device having a structure capable of suppressing the operation of a parasitic bipolar transistor and improving the withstand capability regardless of carrier lifetime control.

  In order to achieve the above object, the invention according to claim 1 includes a first conductivity type drift layer (1) and a second conductivity type deep well layer (13) formed in a surface layer portion of the drift layer. A second conductivity type impurity region (2) is formed in a region where the diode structure is formed on the back surface side of the drift layer (1), and the second conductivity type impurity region (2) is formed. (2) includes a first conductivity type impurity region (3) depleted by a depletion layer extending from the second conductivity type impurity region (2).

  As described above, in the region where the diode structure is formed, the first conductivity type impurity region (3) is partially formed in addition to the second conductivity type impurity region (2) on the back side of the drift layer (1). It is. For this reason, the width of the second conductivity type impurity region (2) is reduced, and as a result, the second conductivity type impurity region (2) is farthest from the boundary with the first conductivity type impurity region (3). The distance becomes shorter. Therefore, the bias voltage is reduced by reducing the internal resistance of the drift layer (1), and the operation of the parasitic bipolar transistor can be suppressed. As a result, it is possible to suppress the operation of the parasitic bipolar transistor and improve the withstand capability regardless of the lifetime control of the carrier.

  For example, as described in claim 2, the diode structure is provided in a diode forming region surrounding a region where the semiconductor element (100) is formed in the cell region.

  In this case, as described in claim 3, the first conductivity type impurity region (3) can be constituted by an annular structure surrounding the region in which the semiconductor element (100) is formed in the cell region. Furthermore, as described in claim 4, the first conductivity type impurity region (3) may be constituted by a plurality of annular structures. Furthermore, as described in claim 5, a structure in which a plurality of first conductivity type impurities (3) are interspersed in a dot shape may be employed.

  Further, as described in claim 6, the diode structure may be provided below the gate runner (20) connected to the gate electrode (8).

  As such a semiconductor device, as described in claim 7, there is a semiconductor device provided with an IGBT (100) as a semiconductor element and a free wheel diode (200) as a diode structure. Further, as described in claim 8, a MOSFET may be provided as a semiconductor element, and a free wheel diode (200) may be provided as a diode structure.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a top surface layout diagram of the semiconductor device shown in FIG. 1. It is a top surface layout diagram of a semiconductor device concerning a 2nd embodiment of the present invention. It is sectional drawing of the conventional semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view of the semiconductor device according to this embodiment, and FIG. 2 is a top layout view of the semiconductor device shown in FIG. FIG. 1 corresponds to the AA cross-sectional view of FIG. Hereinafter, the semiconductor device of this embodiment will be described with reference to these drawings.

As shown in FIG. 1, the semiconductor device according to the present embodiment includes, for example, an IGBT 100 or a semiconductor substrate constituting an n ⁻ type drift layer 1 having an impurity concentration of 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ^−3. It is comprised by providing FWD200. As shown in FIGS. 1 and 2, the IGBT forming region provided with the IGBT 100 and the diode forming region provided with the FWD 200 are defined as cell regions, and the outer peripheral region is provided in the outer peripheral portion of the cell region. As shown in FIG. 2, a cell region is formed by arranging a diode forming region so that a central portion of a chip constituting the semiconductor device is an IGBT forming region and surrounds the periphery thereof. An outer peripheral region is arranged so as to surround the outer periphery.

In the IGBT formation region and the diode formation region in the cell region, the surface layer portion of the n ⁻ type drift layer 1 on the back surface side of the n ⁻ type drift layer 1 has ap ⁺ type impurity region 2 corresponding to the collector region and the cathode region. A corresponding n ⁺ -type impurity region 3 is formed. The p ⁺ -type impurity region 2 is formed by implanting a p-type impurity such as boron, and has an impurity concentration of 1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ⁻³ , for example. The n ⁺ -type impurity region 3 is formed by implanting an n-type impurity such as phosphorus, and has an impurity concentration of 1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ⁻³ , for example. Although the back surface side of the n ⁻ type drift layer 1 is basically a p ⁺ type impurity region 2, the n ⁺ type impurity region 3 is partially formed. The detailed structures of the p ⁺ -type impurity region 2 and the n ⁺ -type impurity region 3 will be described later.

In the IGBT formation region in the cell region, a p-type base region 4 having a predetermined thickness is formed in the surface layer portion of the n ⁻ -type drift layer 1. A plurality of trenches 6 are formed so as to penetrate the p-type base region 4 and reach the n ⁻ -type drift layer 1, and the p-type base region 4 is separated into a plurality of trenches 6. Specifically, a plurality of trenches 6 are formed at a predetermined pitch (interval), and a stripe structure in which each trench 6 extends in parallel in the depth direction (perpendicular to the paper surface) in FIG. 1 or extends in parallel. After being installed, it is drawn around at the tip thereof to form an annular structure. In the case of an annular structure, for example, a plurality of annular structures formed by each trench 6 constitute a multiple ring structure.

The p-type base region 4 is divided into a plurality of parts by the adjacent trenches 6, but at least a part of the p-type base region 4 becomes a channel p layer 4 a constituting the channel region, and the emitter region is formed in the surface layer portion of the channel p layer 4 a An n ⁺ type impurity region 5 corresponding to is formed. In the present embodiment, the case where each divided p-type base region 4 becomes the channel p layer 4a is illustrated, but a part of them is a float layer in which the n ⁺ -type impurity region 5 is not formed. Also good.

The n ⁺ -type impurity region 5 has a higher impurity concentration than the n ⁻ -type drift layer 1, terminates in the p-type base region 4, and is disposed so as to be in contact with the side surface of the trench 6. More specifically, the structure extends in the shape of a rod along the longitudinal direction of the trench 6 and terminates inside the tip of the trench 6.

  Each trench 6 includes a gate insulating film 7 formed so as to cover the inner wall surface of each trench 6 and a gate electrode 8 made of doped Poly-Si or the like formed on the surface of the gate insulating film 7. Embedded. The gate electrodes 8 are electrically connected to each other in a cross section different from that shown in FIG. 1, and a gate voltage having the same potential is applied thereto.

Further, the n ⁺ -type impurity region 5 and the channel p layer 4a are electrically connected to the upper electrode 10 corresponding to the emitter electrode through a contact hole 9a formed in the interlayer insulating film 9, and the upper electrode 10 and the channel p layer 4a are not shown. A protective film 11 is formed so as to protect the wiring and the like. The lower electrode 12 is formed on the back surface side of the p ⁺ -type impurity region 2 to constitute the IGBT 100.

On the other hand, also in the diode formation region in the cell region, the p-type base region 4 having a predetermined thickness is formed in the surface layer portion of the n ⁻ -type drift layer 1, similarly to the IGBT formation region. Further, a p-type deep well layer 13 having a junction depth deeper than that of the p-type base region 4 is formed so as to surround the p-type base region 4. The p-type deep well layer 13 is configured with a higher impurity concentration than the p-type base region 4, for example, with an impurity concentration of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ .

Therefore, the p-type base region 4 and the p-type deep well layer 13 provided in the diode formation region are used as an anode, and the n ^- type drift layer 1 and the n ⁺ -type impurity region 3 are used as a cathode to have a diode structure. The FWD 200 is configured. The FWD 200 has a structure in which the upper electrode 10 is electrically connected as an anode electrode to the p-type deep well layer 13 and the lower electrode 12 is electrically connected as a cathode electrode to the n ⁺ -type impurity region 3. Has been.

  Therefore, the IGBT 100 and the FWD 200 have a structure in which the emitter and the anode are electrically connected, and the collector and the cathode are electrically connected, so that they are connected in parallel to each other in the same chip.

In the outer peripheral region, although not shown, a p-type diffusion layer deeper than the p-type base region 4 is formed in the surface layer portion of the n ⁻ -type drift layer 1 so as to surround the outer periphery of the cell region. An outer peripheral withstand voltage structure is configured such that a p-type guard ring layer is formed as a multiple ring structure so as to surround the outer periphery of the type diffusion layer. With this outer peripheral withstand voltage structure, the electric field can be spread without unevenness, thereby improving the withstand voltage of the semiconductor device.

Next, the detailed structure of the above-described p ⁺ -type impurity region 2 and n ⁺ -type impurity region 3 will be described.

In FIG. 2, the region indicated by the solid line hatching is a region where the n ⁺ -type impurity region 3 is formed, and the other region is a region where the p ⁺ -type impurity region 2 is formed. A region indicated by broken line hatching in FIG. 2 is a region where the p-type deep well layer 13 is formed.

As shown in FIG. 2, the back surface side of the n ⁻ type drift layer 1 is basically a p ⁺ type impurity region 2, but the n ⁺ type impurity region 3 is partially formed. ing. In the present embodiment, the n ⁺ -type impurity region 3 includes a plurality of strip-shaped strips arranged in the cell region, and surrounds the cell region below the portion corresponding to the p-type deep well layer 13. Thus, a plurality of rings are arranged in a ring shape. Of these n ⁺ -type impurity regions 3, at least the width of the annularly arranged regions 3a to 3c is completely depleted by the depletion layer extending from the p ⁺ -type impurity region 2 arranged so as to sandwich both sides of the regions 3a to 3c. The dimension is depleted (pinch-off). This width is intended to be set from the n ⁺ -type impurity region 3 so that electrons are not injected, are determined based on the relationship between the impurity concentration of the p ⁺ -type impurity regions 2 and n ⁺ -type impurity region 3. Note that the strip-shaped portion of the n ⁺ -type impurity region 3 is drawn as five vertically divided into two in FIG. 2, but in reality, a large number of strips are formed. ing.

  As described above, the semiconductor device in which the IGBT 100 and the FWD 200 according to the present embodiment are integrated is configured. The semiconductor device configured as described above is provided in a switching circuit such as an inverter circuit for performing DC-AC conversion, for example, and the IGBT 100 is caused to function as a switching element. It is made to function as a flowing reflux element.

In such a semiconductor device, as described above, the p ⁺ -type impurity region 2 is basically formed on the back surface side of the n ⁻ -type drift layer 1 in the region where the diode structure provided on the outer periphery of the IGBT formation region is formed. In this structure, the n ⁺ -type impurity region 3 is partially formed. For this reason, the following effects can be acquired.

First, assuming that the entire back surface of the portion of the n ⁻ -type drift layer 1 disposed below the p-type deep well layer 13 is the n ⁺ -type impurity region 3, at the time of recovery, that is, a forward bias is applied. When holes are injected from the p-type deep well layer 13 to operate as a diode, the holes are excessively injected from the p-type deep well layer 13 and the withstand capability is reduced, leading to destruction. However, the p ⁺ -type impurity region 2 is basically formed in a portion of the n ⁻ -type drift layer 1 disposed below the p-type deep well layer 13. For this reason, it is possible to suppress an excessive injection of holes from the p ⁺ -type deep well layer 13, and it is possible to suppress a reduction in withstand capability.

Further, the n ⁺ -type impurity region 3 is partially formed on the back surface side of the n ⁻ -type drift layer 1 in the diode forming region and the outer peripheral region surrounding the outer periphery of the IGBT forming region. The width of the n ⁺ -type impurity region 3 is set to a size that is completely depleted by a depletion layer extending from the p ⁺ -type impurity region 2. This n ⁺ -type impurity region 3 makes it possible to reduce the bias voltage between the p ⁺ -type impurity region 2 and the n ⁻ -type drift layer 1 and suppress the operation of the parasitic bipolar transistor.

That is, at the time of recovery, holes are basically extracted upward and electrons are extracted downward, but carriers (holes) accumulated in the n ⁻ -type drift layer 1 are transferred from the p-type deep well layer 13 to the n ⁻ -type drift. The n ⁺ -type impurity region 3 may escape through the layer 1. At this time, a bias is applied between the PN junctions of the p ⁺ type impurity region 2 and the n ⁻ type drift layer 1. However, in the present embodiment, at least in the region where the diode structure is formed, the n ⁺ type impurity region 3 is formed on the back surface of the n ⁻ type drift layer 1 in addition to the p ⁺ type impurity region 2. The bias voltage applied between the PN junctions can be reduced.

Specifically, the parasitic bipolar transistor is configured by a PNP transistor including a p ⁺ type impurity region 2 and an n ⁻ type drift layer 1 and an n ⁺ type impurity region 3 and a p type deep well layer 13. Since the p ⁺ -type impurity region 2 and the n ⁺ -type impurity region 3 in this PNP transistor are electrically connected to the lower electrode 12 and have the same potential, the potential corresponding to the internal resistance of the n ⁻ -type drift layer 1 The drop equivalent is the bias voltage applied across the PN junction. This bias voltage decreases as the potential drop due to the internal resistance of the n ⁻ -type drift layer 1 decreases. The magnitude of the internal resistance of n ⁻ type drift layer 1 is determined by the distance from p ⁺ type impurity region 2 to the position farthest from the boundary with n ⁺ type impurity region 3 (however, the p ⁺ type impurity is not included). This is the distance from the region 2 to the n ⁺ -type impurity region 3 arranged at the shortest distance). In other words, since the bias voltage becomes the largest at a position farthest from the boundary with the n ⁺ -type impurity region 3 in the p ⁺ -type impurity region 2, the distance between the n ⁺ -type impurity regions 3 is shortened, If the distance from the boundary between the p ⁺ -type impurity region 2 and the n ⁺ -type impurity region 3 to the farthest location is shortened, the bias voltage is reduced and the operation of the parasitic bipolar transistor can be suppressed.

In the semiconductor device of this embodiment, the n ⁺ type impurity region 3 is partially formed on the back surface side of the n ⁻ type drift layer 1 in the region where the diode structure is formed. For this reason, the width of the p ⁺ -type impurity region 2 is reduced, and as a result, the distance from the boundary with the n ⁺ -type impurity region 3 in the p ⁺ -type impurity region 2 is shortened. Therefore, the bias voltage is reduced by reducing the internal resistance of the n ⁻ -type drift layer 1, and the operation of the parasitic bipolar transistor can be suppressed. As a result, it is possible to suppress the operation of the parasitic bipolar transistor and improve the withstand capability regardless of the lifetime control of the carrier.

Further, since the width of the n ⁺ -type impurity region 3 is set to a size that is completely depleted by a depletion layer extending from the p ⁺ -type impurity region 2 on both sides, it is possible to prevent electrons from being injected from the n ⁺ -type impurity region 3. For this reason, it is possible to suppress the carrier balance from being lost by injecting electrons from the n ⁺ -type impurity region 3.

In the p ⁺ -type impurity region 2, the region that operates as a parasitic bipolar transistor is a region where a diode structure is formed. Therefore, it is necessary to reduce the internal resistance of the n ⁻ type drift layer 1 and reduce the bias voltage by reducing the width of the p ⁺ type impurity region 2 located below the p type deep well layer 13. is there. This is because the bias voltage is such that the parasitic bipolar transistor does not operate at the place where the shortest distance to the boundary with the n ⁺ -type impurity region 3 of the p ⁺ -type impurity region 2 is longest on the layout shown in FIG. It only has to be suppressed.

Further, at the time of a large current, electrons move from the n ⁻ type drift layer 1 toward the n ⁺ type impurity region 3, whereby the electric field strength distribution is displaced. Specifically, in the normal, p-type deep well layer 13 and the n ^- becomes a field intensity distribution as the electric field intensity is highest at the boundary position between -type drift layer 1, when a large current, electrons n ^- type When the concentration is higher than the concentration of the drift layer 1, the position where the electric field strength becomes the highest is displaced toward the boundary position between the n ⁻ type drift layer 1 and the n ⁺ type impurity region 3. As a result, secondary breakdown occurs, and the withstand capability of the semiconductor device decreases. With respect to this, by providing the p ⁺ -type impurity region 2 as in the present embodiment, the PN junction is biased when the number of electrons exceeds the concentration of the n ⁻ -type drift layer 1, and the p ⁺ -type impurity region 2 is present. Since holes are injected from this and electrons are neutralized by this hole injection, this can be prevented. However, if the width (area) of the p ⁺ -type impurity region 2 is narrow, hole injection is insufficient and electron neutralization is insufficient, and conversely, if the width (area) of the p ⁺ -type impurity region 2 is wide, excessive holes are formed. To reduce the resistance. For this reason, it is preferable to set the width (area) of the p ⁺ -type impurity region 2 so that electron neutralization by hole injection can be performed satisfactorily.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, a part of the configuration of the semiconductor device is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only different parts will be described.

  FIG. 3 is a top surface layout diagram of the semiconductor device according to the present embodiment. As shown in this figure, in this embodiment, a gate runner 20 is provided for making each gate electrode 8 have the same potential without bias, and a p-type deep well layer 13 is also formed below the gate runner 20. Structure. The gate runner 20 is electrically connected to each gate electrode 8 of each cell. The gate electrode 8 is made of, for example, doped Poly-Si. Due to the internal resistance of the material constituting the gate electrode 8, the gate voltage is applied differently as the distance from the connection portion with the gate wiring (not shown) increases even in the same gate electrode 8. In order to suppress this difference as much as possible, for example, gate runners 20 are arranged in the vertical direction with respect to the gate electrodes 8 arranged in stripes, and the gate electrodes 8 are electrically connected to the gate runners 20 and gates are arranged. A gate voltage is applied through the runner 20. In such a structure, the p-type deep well layer 13 is formed below the gate runner 20.

Also with such a structure, the p-type deep well layer 13 formed below the gate runner 20 may operate as a parasitic bipolar transistor. For this reason, by providing the n ⁺ type impurity region 3 below the p-type deep well layer 13 below the gate runner 20, the same effect as in the first embodiment can be obtained.

(Other embodiments)
In the above embodiment, the n ⁺ -type impurity region 3 is formed in the p ⁺ -type impurity region 2 located below the p-type deep well layer 13 and the n ⁺ -type impurity region 3 has a ring structure. . However, the n ⁺ -type impurity region 3 provided in the p ⁺ -type impurity region 2 located below the p-type deep well layer 13 does not necessarily have to be annular. For example, the n ⁺ -type impurity regions 3 may be dotted in the form of dots. Further, a combination of an annular structure and a dot-like structure may be used.

In the above embodiment, a semiconductor device including an IGBT as a semiconductor element having a vertical MOS structure has been described as an example. However, the semiconductor device is not limited to the IGBT. For example, the present invention can be applied to a power MOSFET. When in the power MOSFET, since basically, so that the n ⁺ -type impurity regions 5 described above are n ⁺ -type source region, n ⁺ -type impurity region 3 functions as a n ⁺ -type drain region, p ⁺ -type impurity regions 2 does not need to be formed, but by forming the p ⁺ -type impurity region 2, it is possible to suppress the secondary breakdown at the time of the large current described above. In this case, the parasitic bipolar transistor is formed by forming a p ⁺ -type impurity region 2, the parasitic bipolar transistor is a problem due to the operation can occur, p ⁺ -type impurity regions 2 and n ⁺ -type drain region By configuring the n ⁺ -type impurity region 3 to be as in the above embodiments, the same effects as those in the above embodiments can be obtained.

Similarly, in the case where a parasitic diode is configured such as a bipolar transistor or a diode structure such as a simple diode, electron neutralization is achieved by injecting holes with the p ⁺ -type impurity region 2. The present invention can be applied to a simple structure. Also in this case, by configuring the p ⁺ -type impurity region 2 and the n ⁺ -type impurity region 3 as in the above embodiments, the same effects as those in the above embodiments can be obtained.

  In each of the above-described embodiments, an n-channel type IGBT in which the first conductivity type is n-type and the second conductivity type is p-type is basically described as an example. A channel type IGBT can also be applied. In this case, the components other than the IGBT also have a structure in which the conductivity type is inverted. The same can be said for the power MOSFET.

In the above embodiment, the structure in which the field stop (FS) layer is not formed is taken as an example. On the back surface of the n ⁻ type drift layer 1, the p ⁺ type impurity region 2 and the n ⁺ type impurity region 3 An FS layer composed of an n-type impurity layer may be formed so as to be positioned between the n ⁻ -type drift layer.

1 n ⁻ type drift layer 2 p ⁺ type impurity region 3 n ⁺ type impurity region 4 p type base region 4a channel p layer 5 n ⁺ type impurity region 6 trench 7 gate insulating film 8 gate electrode 9 interlayer insulating film 10 upper electrode 12 Lower electrode 13 p-type deep well layer 20 Gate runner 100 IGBT
200 FWD

Claims (8)

A semiconductor device having a diode structure constituted by a PN junction having a first conductivity type drift layer (1) and a second conductivity type deep well layer (13) formed in a surface layer portion of the drift layer,
A second conductivity type impurity region (2) is formed in a region where the diode structure is formed on the back surface side of the drift layer (1), and the second conductivity type impurity region (2) includes the second conductivity type impurity region (2). And a first conductivity type impurity region (3) depleted by a depletion layer extending from the two conductivity type impurity region (2).   A cell region having a semiconductor element (100) is provided, and the diode structure is provided in a diode formation region surrounding the region in which the semiconductor element (100) is formed in the cell region. The semiconductor device according to claim 1.   The semiconductor device according to claim 2, wherein the first conductivity type impurity region (3) has an annular structure surrounding a region in the cell region where the semiconductor element (100) is formed.   The semiconductor according to claim 2, wherein the first conductivity type impurity region (3) has a plurality of annular structures surrounding a region of the cell region where the semiconductor element (100) is formed. apparatus.   5. The semiconductor device according to claim 1, wherein a plurality of the first conductivity type impurities are scattered in a dot shape. 6.   A cell region having a MOS structure semiconductor element (100) having a gate electrode (8) is provided, and the diode structure is provided below a gate runner (20) connected to the gate electrode (8). The semiconductor device according to claim 1, wherein the semiconductor device is provided.   The insulated gate bipolar transistor (100) is provided as the semiconductor element, and a free wheel diode (200) is provided as the diode structure. The semiconductor device described.   7. The semiconductor device according to claim 1, wherein a MOSFET is provided as the semiconductor element, and a free wheel diode (200) is provided as the diode structure.

Images