JP2011232800A - Microcomputer and image display apparatus - Google Patents

Abstract

The burden of creating a user program is reduced by using hardware for control for LCD direct drive.
A timer pulse unit (103) capable of forming a clock signal, a DMA controller (110) capable of performing DMA transfer of display data to a liquid crystal display, a first clock signal used for the DMA transfer, and the liquid crystal A selector (105) capable of selectively transmitting a second clock signal used for display on the display to a clock input terminal of the liquid crystal display is provided. Further, a register (106) capable of setting the selection state of the selector and a control logic (107) for controlling the selection state of the selector in synchronization with the DMA transfer based on the setting information of the register are provided. . In the user program, it is only necessary to set the register regarding the control for the LCD direct drive, so the burden of creating the user program can be reduced.
[Selection] Figure 1

Description

  The present invention relates to a technique for transferring display data from a microcomputer to an LCD (Liquid Crystal Display) by DMA (Direct Memory Access) for display.

  Patent Document 1 describes a technique for reducing the number of input / output pins in an integrated circuit incorporating a control circuit related to the use of a data bus. According to this, the parallel / serial converter 10 converts the request signals DREQ0 to DREQ3 output from the DMA device 4 into a serialized request signal SREQ and inputs it to the LSI 16. In the LSI 16, the serial / parallel converter 14 generates request signals CREQ 0 to 3 corresponding to the respective DMA devices 4 from the serialized request signal SREQ and supplies them to the DMA controller 12. On the other hand, the acknowledge signals CACK0-3 output from the DMA controller 12 are converted into a 2-bit digital signal EACK by the encoding unit 24 and output from the LSI 16, and the decoding unit 26 receives an acknowledge signal DACK0 to each DMA device 4 from the digital signal. Generate ~ 3.

  Patent Document 2 describes a technique for improving a display data transfer method and providing a matrix type display control device that has low power consumption and is suitable for large-capacity display. According to this, the module controller 100 monitors the low-frequency oscillation circuit 110, the timing signal generation circuit 120 that generates the scan start signal YD and the like based on the low-frequency clock fL, the communication with the host MPU 10, and the system bus 14a. A standby circuit 130 for creating an intermittent operation start control signal ST for updating display data in the VRAM 12 is provided. The display data is read out from the high-frequency oscillation circuit 140 and the VRAM 12 that are phase-synchronized with the low-frequency clock fL and the VRAM 12 through the dedicated bus 14b by direct memory access, and the X drivers 250-1 to 250- are connected through the data bus 17. It has a DMA circuit 150 for transferring to N frame memories 252.

Japanese Patent Laid-Open No. 11-250002 JP-A-06-130910

  The inventor of the present application has studied a technique (hereinafter referred to as “LCD direct drive”) that performs DMA transfer of data from a microcomputer to an LCD without using an LCD controller. A microcomputer having an LCD direct drive function is equipped with a DMAC (hereinafter referred to as “EXDMAC”) that enables control / processing by the CPU simultaneously with image data transfer to the LCD, in addition to the DMAC for internal data transfer. By using this EXDMAC, the internal bus and the external bus can be operated independently, and the LCD can be controlled without using the LCD controller. Such a microcomputer having an LCD direct drive function controls data transfer to the LCD and display of the data on the LCD via a predetermined terminal.

  In the control for the LCD direct drive, it is necessary to switch on the microcomputer side between a clock signal when the display data is DMA-transferred to the LCD and a clock signal for displaying the transferred display data. Since the frequency of the clock signal supplied from the microcomputer to the LCD varies depending on the specifications of the LCD coupled to the microcomputer, the clock signal supplied to the LCD is switched by software (user program) executed by the microcomputer. Done. For this reason, in creating the user program, it is necessary to consider the control for the LCD direct drive, and it takes time and effort to create the user program. Such a problem cannot be solved by the techniques described in Patent Documents 1 and 2.

  An object of the present invention is to reduce the burden of creating a user program by using hardware for control for an LCD direct drive.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the microcomputer has a timer pulse unit capable of forming a clock signal, a DMA controller that is activated in response to an interrupt request from the timer pulse unit, and capable of DMA transfer of display data to the liquid crystal display, and the DMA transfer. A selector capable of selectively transmitting a first clock signal used for the display and a second clock signal used for display on the liquid crystal display to a clock input terminal of the liquid crystal display. The microcomputer includes a register capable of setting the selection state of the selector, and control logic for controlling the selection state of the selector in synchronization with the DMA transfer based on setting information of the register.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, by using hardware for the control for the LCD direct drive, it is possible to reduce the burden of creating a user program.

It is a block diagram which shows the structural example of the microcomputer concerning this invention. It is a block diagram of a configuration example of an image display device including the microcomputer. It is explanatory drawing of the example of a setting of the PFCR register contained in the said microcomputer. It is a block diagram of a configuration example of EXDMAC included in the microcomputer. It is a block diagram of a configuration example of a TPU included in the microcomputer. It is a flowchart which shows the example of a setting of the said TPU. It is explanatory drawing of the signal output example by the compare match in the said TPU. It is a timing diagram of the LCD display in the said image display apparatus.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A microcomputer (10) according to a typical embodiment of the present invention is activated and displayed in response to an interrupt request from the timer pulse unit (103) capable of forming a clock signal and the timer pulse unit. And a DMA controller (110) capable of DMA transferring data to the liquid crystal display. The microcomputer can selectively transmit a first clock signal used for the DMA transfer and a second clock signal used for display on the liquid crystal display to a clock input terminal of the liquid crystal display. ). Further, the microcomputer has a register (106) capable of setting the selection state of the selector, and a control logic for controlling the selection state of the selector in synchronization with the DMA transfer based on the setting information of the register. 107).

  According to the above configuration, the frequency of the clock signal supplied to the clock input terminal of the LCD can be made to correspond to the specification of the LCD by setting the register. Since it is only necessary to set the register regarding the control, the burden of creating the user program is reduced.

  [2] In the above [1], the control logic (107) is configured to switch the selection state of the selector (105) at the start of DMA transfer and at the end of DMA transfer based on the setting information of the register. Can do. Thereby, it is possible to appropriately switch between the first clock signal used for the DMA transfer and the second clock signal used for display on the liquid crystal display.

  [3] In the above [2], a logic inverting circuit (104) capable of inverting the logic of the signal output from the DMA controller (110) and then transmitting it to the selector can be provided. Thereby, the logic of the signal output from the DMA controller (110) can be made to correspond to the specification of the LCD.

  [4] In the above [3], the register (106) includes a bit for instructing the logical inversion of the signal output from the DMA controller, and the logical inversion circuit performs the logical inversion according to the logical state of the bit. The logic of the signal output from the DMA controller can be inverted. In this way, the logic of the signal output from the DMA controller (110) can be easily performed by setting the register (106).

  [5] An image display device (200) according to a typical embodiment of the present invention includes a liquid crystal display (11), a memory (12) capable of storing display data, and display data in the memory. And a microcomputer (10) having a function of performing DMA transfer and displaying on the liquid crystal display. At this time, the microcomputer (10) is activated in response to an interrupt request from the timer pulse unit (103) capable of forming a clock signal and the timer pulse unit, and the display data is DMA transferred to the liquid crystal display. Possible DMA controller (110). Further, the microcomputer has a selector capable of selectively transmitting a first clock signal used for the DMA transfer and a second clock signal used for display on the liquid crystal display to a clock input terminal of the liquid crystal display. (105) can be provided. Further, the microcomputer (10) controls the selection state of the selector in synchronization with the DMA transfer based on the register (106) capable of setting the selection state of the selector and the setting information of the register. Control logic (107).

  According to the above configuration, the frequency of the clock signal supplied to the clock input terminal of the LCD can be made to correspond to the specification of the LCD by setting the register. Since it is only necessary to set the register regarding the control, the burden of creating the user program is reduced.

  [6] In the above [5], the control logic (107) can be configured to switch the selection state of the selector at the start of DMA transfer and at the end of DMA transfer based on the setting information of the register. Thereby, it is possible to appropriately switch between the first clock signal used for the DMA transfer and the second clock signal used for display on the liquid crystal display.

  [7] In the above [6], a logic inverting circuit (104) capable of inverting the logic of the signal output from the DMA controller (110) and then transmitting it to the selector can be provided. Thereby, the logic of the signal output from the DMA controller (110) can be made to correspond to the specification of the LCD.

  [8] In the above [7], the register (106) includes a bit for instructing logical inversion of a signal output from the DMA controller, and the logical inversion circuit (104) Accordingly, the logic of the signal output from the DMA controller (110) can be inverted. In this way, the logic of the signal output from the DMA controller (110) can be easily performed by setting the register (106).

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 2 shows a configuration example of an image display device according to the present invention. The image display device 200 shown in FIG. 2 is not particularly limited, but can be mounted on various home appliances such as a printer and a refrigerator, and includes a microcomputer 10, an LCD (Liquid Crystal Display) 11, an SRAM (Static Random). Access Memory) 12, touch panel 13, and input circuit 14.

  The microcomputer 10 is not particularly limited, but is formed on a single semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique, and transfers display data in the SRAM 12 to the LCD 11 by DMA (Direct Memory Access). Display function (LCD direct drive function). The display data in the SRAM 12 is updated by the microcomputer 10. The microcomputer 10 includes an output terminal for display data D [15: 0], an output terminal for an address signal ADDRESS, an output terminal for a write enable signal WE, an output terminal for a chip select signal CS, an output terminal for an LCD direct drive signal LDD, It includes an output terminal for the enable signal ENABLE, an output terminal for the clock signal TIOCB3, an output terminal for the vertical synchronization signal Vsync, and input terminals for the analog signals AN0 to AN3. The display data D [15: 0] includes data groups D15-D11, D10-D5, D4-D0 corresponding to RGB. Data groups D15-D11, D10-D5, and D4-D0 correspond to display input data groups R5-R1, G5-G0, and B5-B1 in LCD 11. The pixel data of the LCD 11 is R (5 bits), G (6 bits), and B (5 bits), and corresponds to the display input data groups R5-R1, G5-G0, and B5-B1. The address signal ADDRESS is transmitted to the SRAM 12 when writing data to the SRAM 12 or reading data from the SRAM 12. The SRAM 12 is selected when the microcomputer 10 asserts the chip select signal CS. When the microcomputer 10 asserts the write enable signal WE, the writing of display data to the SRAM 12 is instructed. In a state where the write enable signal WE is negated by the microcomputer 10, data can be read from the SRAM 12. The LCD direct drive signal LDD is transmitted to the input terminal of the clock signal CLK in the LCD 11. The LCD direct drive signal LDD includes a clock signal used for the DMA transfer and a clock signal used for image display on the LCD 11. The clock signal used for the DMA transfer is set to a frequency suitable for the DMA transfer. The clock signal used for display on the LCD 11 is set to a frequency suitable for image display on the LCD 11. The enable signal ENABLE is transmitted to the input terminal of the enable signal ENABLE in the LCD 11. When the enable signal ENABLE is enabled by the microcomputer 10, display data can be transferred to the LCD 11 and displayed. The clock signal TIOCB3 is transmitted as the horizontal synchronization signal Hsync to the input terminal of the horizontal synchronization signal Hsync in the LCD 11, and the vertical synchronization signal Vsync is transmitted to the input terminal of the vertical synchronization signal Vsync in the LCD 11. The LCD 11 is supplied with a power supply voltage Vcc with respect to the ground GND.

  The touch panel 13 is not particularly limited, but is placed on the display screen of the LCD 11 so that information can be input to the microcomputer 12 by touching the operator's finger. Information input to the microcomputer 12 is performed in the form of analog signals AN0 to AN3. Input circuit 14 includes a circuit for applying a DC voltage for enabling input of analog signals AN0 to AN3 from touch panel 13, and a noise filter for preventing noise from being mixed into analog signals AN0 to AN3.

  FIG. 1 shows a configuration example of the microcomputer 10.

  The microcomputer 10 includes a DMAC 101, an interrupt controller 102, a TPU (timer pulse unit) 103, a logic inversion circuit 104, a selector 105, a PFCR register 106, a control logic 107, a switch 108, a bus controller 109, an EXDMAC 110, and a CPU (central processing unit). 111 and ADC (analog-digital converter) 112. The microcomputer 10 further includes a ROM (read only memory) 113 and a RAM (random access memory) 114. The DMAC 101, the CPU 111, the ADC 112, the ROM 113, and the RAM 114 are coupled to each other by a data bus (referred to as “internal data bus”) 115 provided in the microcomputer 10. The CPU 111 executes a user program. The ADC 112 converts the input analog signal into a digital signal. An analog signal from the touch panel 13 is converted into a digital signal by the ADC 112. The ROM 113 is provided for storing a user program executed by the CPU 111. Although not particularly limited, a flash memory can be applied to the ROM 113. The RAM 114 is used as a work area when the CPU 111 executes a user program.

  The TPU 103 has a plurality of timer channels each capable of forming a timer pulse under a predetermined condition. The TPU 103 generates an EXDMAC 110 activation interrupt request when a predetermined condition is satisfied. Further, clock signals TIOCB3, TIOCB4, TIOCB5 formed by specific channels, for example, channels 3, 4, 5 among the plurality of channels in the TPU 103 are output. The clock signal TIOCB3 is transmitted to the LCD 11 as the horizontal synchronization signal Vsync of the LCD 11. Clock signals TIOCB4 and TIOCB5 are transmitted to selector 105.

  The DMAC 101 controls DMA transfer performed via the internal data bus 115 in the microcomputer 10. The interrupt controller 102 adjusts interrupt requests from various devices according to a predetermined priority order, and notifies the CPU 111 of them. The EXDMAC 110 is a DMAC dedicated to data transfer performed using a bus (referred to as “external bus”) arranged outside the microcomputer 10, and is provided separately from the DMAC 101 coupled to the internal data bus 115. The EXDMAC 110 can perform transfer between an external device with EDACK (DMA transfer notification) and an external memory at high speed instead of the CPU 111. In this example, the LCD 11 is an example of an external device with EDACK (DMA transfer notification). In this example, the SRAM 12 is an example of the external memory. The EXDMAC 110 has a dual address mode and a single address mode as transfer modes. The EXDMAC 110 outputs a single address transfer acknowledge signal EDACK3 in the single address mode. The single address transfer acknowledge signal EDACK3 is a low-active signal when it is output from the EXDMAC 110, but can be changed to a high-active signal by inverting the logic of the signal in the logic inverting circuit 104 in the subsequent stage. it can. The logic inversion circuit 104 includes an inverter 104A that inverts and outputs the logic of the single address transfer acknowledge signal EDACK3 output from the EXDMAC 110, and a selector 104B for selecting an input / output signal of the inverter 104A. The single address transfer acknowledge signal EDACK3 output from the logic inversion circuit 104 becomes a low active signal when the input signal of the inverter 104A is selected by the selector 104B, and the output signal of the inverter 104A is selected by the selector 104B. In this case, it becomes a high active signal. The selection state of the selector 104B is determined by a control signal EDACKRS based on a predetermined bit setting in the PFCR register 106.

  Based on the output of the control logic 107, the selector 105 selects one signal from the clock signals TIOCB4 and TIOCB5 from the TPU 103 and the single address transfer acknowledge signal EDACK3 from the logic inversion circuit 104, and outputs it to the LCD direct drive. The signal LDD is transmitted to the input terminal of the clock signal CLK in the LCD 11. The selection state of the selector 105 is determined by a control signal from the control logic 107. The control logic 107 is an LCD formed based on a selection control signal EDACK_sel indicating the output start timing of the single address transfer acknowledge signal EDACK3 output from the EXDMAC 110, a signal ETEND indicating the end of EXDMA transfer, and a specific bit in the PFCR register 106. Based on the direct control signal LCDDIRECT [1: 0], the selection operation of the selector 105 is controlled.

  The bus controller 109 manages a bus (referred to as “external bus”) arranged outside the microcomputer 10. The bus controller 109 permits the EXDMAC 110 to use the external bus in response to a bus right request from the EXDMAC 110. The external bus includes a data bus for transmitting data D [15: 0], an address bus for transmitting address signal ADDRESS, and a control bus for transmitting chip select signal CS and write enable signal WE. . The external bus is coupled to the LCD 11 and the SRAM 12. The chip select signal CS is switched by the switch 108. In writing display data to the SRAM 12, the chip select signal CS output from the bus controller 109 is selected by the switch 108 and transmitted to the SRAM 12. In the LCD direct mode, since it is necessary to select the SRAM 12 in synchronization with the LCD direct drive signal LDD, the selection output of the selector 105 is selected by the switch 108 and is transmitted to the SAM 12 as the chip select signal CS. .

  The vertical synchronization signal Vsync and the enable signal ENABLE supplied to the LCD 11 are formed under the control of the CPU 111.

  FIG. 3 shows a configuration example of the PFCR register 106.

  The PFCR register 106 has an 8-bit configuration. Bit 5 of the PFCR register 106 is assigned to the logical setting of the EDACKRS signal. When bit 5 is a logical value “0”, the single address transfer acknowledge signal EDACK3 is low active, and when bit 5 is a logical value “1”, the single address transfer acknowledge signal EDACK3 is high active. The initial value of bit 5 of the PFCR register 106 is set to a logical value “0”.

  Bits 6 and 7 of the PFCR register 106 are assigned to the logical setting of the LCD direct control signal LCDDIRECT [1: 0]. When bits 6 and 7 of the PFCR register 106 are logical values “0” and “0”, switching by the selector 105 is not performed. When bits 6 and 7 of the PFCR register 106 are set to logical values “0” and “1”, the selection state by the selector 105 is switched from TIOCB 4 to EDACK 3 at the start of EXDMAC transfer under the control of the control logic 107, EXDMAC Returned from EDACK 3 to TIOCB 4 at the end of transfer. When bits 6 and 7 of the PFCR register 106 are set to logical values “1” and “0”, the selection state by the selector 105 is switched from TIOCB4 to TIOCB5 at the start of EXDMAC transfer under the control of the control logic 107, and EXDMAC When the transfer is completed, it is returned from TIOCB5 to TIOCB4. In this example, bits 0 to 4 of the PFCR register 106 are reserved bits.

  FIG. 4 shows a configuration example of the EXDMAC 110.

  The EXDMAC 110 includes a data buffer 1101, an address buffer 1102, an arithmetic unit 1103, a control logic 1105, and various registers EDSAR, EDDAR, EDTCR, and has a plurality of transfer channels. The address buffer 1102, the arithmetic unit 1103, and various registers EDSAR, EDDAR, and EDTCR are coupled to each other by a module data bus 1104. Data buffer 1101 and address buffer 1102 are coupled to bus controller 109. EDSAR is an XDMA source address register for designating a transfer source address, EDDAR is an EXDMA destination address register for designating a transfer destination address, and EDTCR is an EXDMA transfer count register for setting the number of transfers. The control logic 1105 includes registers EDMDR and EDACR. The EDMDR is an EXDMA mode control register that controls the operation of the EXDMAC 110. EDACR is an EXDMA address control register for designating increase / decrease of address register and repeat area function. A request signal EDREQ from an external device is transmitted to the control logic 1105. The control logic 1105 indicates the output start timing of the signal EDARK for confirming acceptance of the transfer request, the signal ETEND indicating the end of EXDMA transfer, the single address transfer acknowledge signal EDACK, and the single address transfer acknowledge signal EDACK3 output from the EXDMAC 110. A selection control signal EDACK_sel is output. The control logic 1105 outputs an interrupt request signal to the CPU 111 for each channel.

  FIG. 5 shows a configuration example of the TPU 103.

  The TPU 103 includes six-channel 16-bit timer units 50 to 55 corresponding to the channels 0 to 5, control logic 54 and 55, and a common circuit 56. The control logic 54 controls the operation of the 16-bit timer units 50 to 52, and the control logic 55 controls the operation of the 16-bit timer units 53 to 55. The 16-bit timer unit 50 includes a timer controller register TCR, a timer I / O control register TIORH, a timer interrupt enable register TIER, a timer mode register TMDR, a timer I / O control register TIORL, a timer status register TSR, a timer counter TCNT, a timer general Includes registers TGRA, TGRB, TGRC, TGRD. The 16-bit timer unit 51 includes a timer controller register TCR, a timer I / O control register TIOR, a timer interrupt enable register TIER, a timer mode register TMDR, a timer status register TSR, a timer counter TCNT, and timer general registers TGRA and TGRB. The 16-bit timer unit 53 has the same configuration as the 16-bit timer unit 50. The 16-bit timer units 52, 54 and 55 have the same configuration as the 16-bit timer unit 51. The common circuit 56 includes a control logic 561, a timer start register TSTR, a timer machine black register TSYR, and a bus interface 562. The 16-bit timer units 50 to 55 and the common circuit 56 are coupled to each other via a module data bus 57. The common circuit 56 receives internal clock signals φ / 1, φ / 4, φ / 16, φ / 64, φ / 256, φ / 1024, φ / 4096, and external clocks TCLKA, TCLKB, TCLKC, and TCLKD. The Bus interface 562 is coupled to internal data bus 115. The common circuit 56 outputs an A / D conversion start request signal and a PPG output trigger signal. Also, a plurality of input terminals for capturing signals for each channel and a plurality of output terminals for outputting interrupt request signals are provided. In this example, although not particularly limited, 16-bit timer units 53, 54, and 55 are used. The horizontal synchronization signal Hsync in the LCD 11 is formed by the output signal TIOCB3 of the 16-bit timer unit 53. The 16-bit timer units 54 and 55 are used for clock signal generation, and their output signals TIOCB4 and TIOCB5 are transmitted to the selector 105.

  FIG. 6 shows a setting example of the TPU 103.

  Various settings in the TPU 103 are executed by the CPU 111 based on the description of the user program.

  First, an interrupt request (TGIEB) permission is set in TIER (601). The initial logical value “0” output, logical value “1” output, or toggle output is selected by TIOR (602). During the period until the first compare match occurs, the set initial value is output to the TIOC terminal. Timing for generating a compare match in TGRB is set (603). Then, the CST bit of TSTR is set to a logical value “1”, and the count operation is started (604).

  FIG. 7 shows an example of signal output by the compare match in the TPU 103.

  When the timing for generating a compare match in TGRB is set (603) and the CST bit in TSTR is set to a logical value “1” and the count operation is started (604), the counter is cleared by the TGRB compare match. , TIOCB toggle output (clock signal output) is performed. In this way, TIOCB3, TIOCB4, and TIOCB5 (clock signal) are obtained by the 16-bit timer units 53, 54, and 55. The frequency of TIOCB3, TIOCB4, and TIOCB5 is determined by the setting value of the corresponding TGRB. That is, by setting TGRB according to the specifications of the LCD 11 to be connected, the frequencies of TIOCB3, TIOCB4, and TIOCB5 can be easily matched to the specifications of the LCD11.

  FIG. 8 shows the LCD display timing.

  The one-frame display operation in the LCD 11 is performed in synchronization with the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync. One frame data transfer period is provided between the back porch and the front porch. This one-frame data transfer is performed by EXDMA transfer from the SRAM 12 to the LCD 11. That is, the display data is taken into the LCD in the same bus cycle as the display data is output from the SRAM 12 to the external data bus D [15: 0]. One line data transfer is performed a plurality of times during one frame data transfer period. In the one-line data transfer period, as shown in an enlarged manner in FIG. 8, the clock signal transmitted to the clock signal CLK input terminal of the LCD 11 is switched (port switching in the microcomputer 10). This switching is performed as follows.

  Due to a TGRB compare match in the timer unit 53 (channel 3) in the TPU 103, a startup interrupt request for the EXDMAC 110 is generated. The EXDMAC 110 is activated by an interrupt process in the CPU 111 based on the activation interrupt request of the EXDMAC 110, and EXDMA transfer for one line of display data is started. The EXDMAC 110 is activated and the selection state of the selector 105 is switched by the control logic 107 in synchronization with the timing at which EDACK 3 is output from the EXDMAC 110.

  For example, when bits 6 and 7 of the PFCR register 106 are set to logical values “0” and “1”, the control logic 107 controls the selection state by the selector 105 at the start of EXDMAC transfer (timing 801). It is switched from TIOCB4 to EDACK3, and is returned from EDACK3 to TIOCB4 at the end of EXDMAC transfer (timing 802). In this case, EXDMA transfer for one line of display data is performed based on EDACK3. At this time, the logic of EDACK 3 is determined by the setting of bit 5 in the PFCR register 106.

  When bits 6 and 7 of the PFCR register 106 are set to logical values “1” and “0”, the selection state by the selector 105 is controlled by the control logic 107 when the EXDMAC transfer starts (timing 801). The TIOCB4 is switched to the TIOCB5 at the end, and is returned from the TIOCB5 to the TIOCB4 at the end of EXDMAC transfer (timing 802). In this case, EXDMA transfer for one line of display data is performed based on TIOCB5.

  Thus, by setting the PFCR register 106, the frequency of the clock signal supplied to the input terminal of the clock signal CLK of the LCD 11 can be made to correspond to the specifications of the LCD 11. Therefore, in the user program, for the LCD direct drive, Since it is only necessary to set the PFCR register 106 for control, the burden of creating a user program is reduced.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

10 Microcomputer 11 LCD
12 SRAM
13 Touch Panel 14 Input Circuit 101 DMAC
102 Interrupt controller 103 TPU
104 logic inversion circuit 104A inverter 104B selector 105 selector 106 PFCR register 107 control logic 108 switch 109 bus controller 110 EXDMAC
111 CPU
112 ADC
113 ROM
114 RAM
115 Internal data bus 200 Image display device

Claims (8)

A timer pulse unit capable of forming a clock signal;
A DMA controller that is activated in response to an interrupt request from the timer pulse unit and capable of DMA-transferring display data to the liquid crystal display;
A selector capable of selectively transmitting a first clock signal used for the DMA transfer and a second clock signal used for display on the liquid crystal display to a clock input terminal of the liquid crystal display;
A register capable of setting the selection state of the selector;
And a control logic for controlling a selection state of the selector in synchronization with the DMA transfer based on setting information of the register.   2. The microcomputer according to claim 1, wherein the control logic switches the selection state of the selector at the start of DMA transfer and at the end of DMA transfer based on the setting information of the register.   3. The microcomputer according to claim 2, further comprising a logic inverting circuit capable of inverting the logic of the signal output from the DMA controller and then transmitting the signal to the selector.   The register includes a bit for instructing the logic inversion of the signal output from the DMA controller, and the logic inversion circuit inverts the logic of the signal output from the DMA controller according to the logic state of the bit. The microcomputer according to claim 3. A liquid crystal display,
Memory that can store display data;
A microcomputer having a function of displaying the data for display in the memory by DMA transfer to the liquid crystal display;
The microcomputer is
A timer pulse unit capable of forming a clock signal;
A DMA controller that is activated in response to an interrupt request from the timer pulse unit and capable of DMA-transferring the display data to a liquid crystal display;
A selector capable of selectively transmitting a first clock signal used for the DMA transfer and a second clock signal used for display on the liquid crystal display to a clock input terminal of the liquid crystal display;
A register capable of setting the selection state of the selector;
And a control logic for controlling the selection state of the selector in synchronization with the DMA transfer based on setting information of the register.   6. The image display device according to claim 5, wherein the control logic switches the selection state of the selector at the start of DMA transfer and at the end of DMA transfer based on the setting information of the register.   The image display apparatus according to claim 6, further comprising a logic inversion circuit capable of inverting the logic of a signal output from the DMA controller and then transmitting the signal to the selector.   The register includes a bit for instructing the logic inversion of the signal output from the DMA controller, and the logic inversion circuit inverts the logic of the signal output from the DMA controller according to the logic state of the bit. The image display device according to claim 7.

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