JP2011229085A - Semiconductor integrated circuit - Google Patents

Abstract

A semiconductor integrated circuit capable of performing a high-speed test without increasing the circuit scale is provided.
A semiconductor integrated circuit according to the present invention includes a memory cell unit 22 configured by a plurality of memory cells, a control unit that controls writing and reading of data to and from the memory cell, and a control unit according to a clock CLK. And a pulse signal generation unit that generates a pulse signal input to. The pulse signal generation unit includes a one-shot pulse generation circuit 20. The one-shot pulse generation circuit 20 generates a one-shot pulse signal synchronized with the clock CLK as a pulse signal in the normal operation mode, and pulses a continuous one-shot pulse signal synchronized with the clock CLK and the pulse signal in the high-speed operation mode. Generate as a signal.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor integrated circuit capable of generating a high-speed clock.

  In recent years, the necessity of a memory test for detecting a failure of a memory such as SRAM (Static Random Access Memory) has increased. In particular, as a higher quality memory test, there is an increasing need for a memory test (hereinafter simply referred to as a high speed memory test) when the memory is operated at high speed. Further, in order to reduce costs, it is required to perform a memory test using a low speed tester without using a high speed tester.

  As a solution to such a requirement, Patent Document 1 discloses a semiconductor device (semiconductor integrated circuit) capable of performing a high-speed memory test and a test method therefor. In this semiconductor device, one of a row decoder for selecting a word line and a column selector for selecting a bit line pair is operated at a higher speed than the external input clock. A conventional semiconductor device performs a memory test by continuously accessing designated memory cells. Here, the conventional semiconductor device determines whether or not a data retention failure (failure) has occurred in the memory cell, using the number of patterns corresponding to the clock of the external input clock signal. At this time, the number of patterns corresponding to the clock of the external input clock signal is smaller than the number of test patterns actually subjected to the memory test. Thus, the conventional semiconductor device generates a high-speed clock inside the semiconductor device. Therefore, the conventional semiconductor device can perform a high-speed memory test using a low-speed tester. In addition, Patent Documents 2 to 4 disclose semiconductor integrated circuits capable of performing a high-speed memory test.

Japanese Patent Laid-Open No. 2004-22014 JP 2002-196046 A Japanese Patent No. 3061988 Japanese Patent No. 4115676

  Here, the semiconductor integrated circuit described in Patent Document 1 includes a multiplier circuit that outputs a high-speed clock to either the column selector or the row decoder. Also, in the semiconductor integrated circuits described in Patent Documents 2 to 4, as in the case of Patent Document 1, either a clock generation circuit having a VCO or a PLL (Phase Locked Loop) is used to generate a high-speed clock. Prepare.

  Therefore, the conventional semiconductor integrated circuit has a problem that the circuit scale increases. In addition, when a plurality of memories are mounted on one chip, a conventional semiconductor integrated circuit requires setting of a multiplier circuit for each memory. Therefore, there is a problem that the test cost increases as the memory test becomes more complicated.

  The semiconductor integrated circuit according to the present invention is inputted to the control unit in accordance with an external clock, a memory cell unit composed of a plurality of memory cells, a control unit for controlling writing and reading of data to and from the memory cell A pulse signal generation unit that generates a pulse signal, and the pulse signal generation unit includes a one-shot pulse generation circuit, and the one-shot pulse generation circuit is synchronized with the external clock in a normal operation mode. A shot pulse signal is generated as a pulse signal, and in the high-speed operation mode, a continuous one-shot pulse signal synchronized with the external clock and the pulse signal is generated as a pulse signal.

  With the circuit configuration as described above, a high-speed clock can be generated without increasing the circuit scale.

  The present invention can provide a semiconductor integrated circuit capable of generating a high-speed clock without increasing the circuit scale.

1 is a diagram showing a semiconductor integrated circuit and its peripheral circuits according to a first embodiment of the present invention. 4 is a timing chart showing operations of the semiconductor integrated circuit and its peripheral circuits according to the first embodiment of the present invention; 1 is a diagram showing a semiconductor integrated circuit according to a first exemplary embodiment of the present invention. 1 is a diagram showing a semiconductor integrated circuit according to a first exemplary embodiment of the present invention. 4 is a timing chart in the normal operation mode of the semiconductor integrated circuit according to the first exemplary embodiment of the present invention; 6 is a timing chart in the high-speed operation mode of the semiconductor integrated circuit according to the first exemplary embodiment of the present invention; FIG. 3 is a diagram illustrating a semiconductor integrated circuit and its peripheral circuits according to a second embodiment of the present invention. 7 is a timing chart showing operations of the semiconductor integrated circuit and its peripheral circuits according to the second embodiment of the present invention. 7 is a timing chart showing operations of the semiconductor integrated circuit and its peripheral circuits according to the second embodiment of the present invention. It is a semiconductor integrated circuit of a prior art.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. For clarity of explanation, duplicate explanation is omitted as necessary.

Embodiment 1
FIG. 1 shows a memory (semiconductor integrated circuit) 10 and its peripheral circuits according to the first embodiment of the present invention. The circuit shown in FIG. 1 includes a memory 10, a pattern generation circuit 11, a comparison circuit 12, and a delay control circuit 13.

  In the pattern generation circuit 11, the external clock EXCLK, the mode switching signal CKGEN, and the test switching signal BISTM are input. The external clock EXCLK is a clock signal supplied from the outside. The mode switching signal CKGEN is one of a mode for operating the memory 10 at a high speed (hereinafter simply referred to as a high speed operation mode) and a mode for normally operating the memory 10 (hereinafter simply referred to as a normal operation mode). It is a signal for switching to. The test switching BISTM is a signal for switching the test contents of the memory 10, for example. The mode switching signal CKGEN is also input to the memory 10 and the comparison circuit 12.

  The pattern generation circuit 11 outputs a START signal, a MODE signal, an ADDRESS signal, and a DATA signal to the memory 10. The START signal is used as a clock signal for the memory 10. The MODE signal is in any one of a mode in which data is read out in the memory 10 (hereinafter simply referred to as a read mode) and a mode in which data is written (hereinafter simply referred to as a write mode). It is a signal for switching. The ADDRESS signal is a signal for selecting a memory cell from which data is to be read or written from among a memory cell group (described later) included in the memory 10. The DATA signal is data for writing to the memory cell selected by the ADDRESS signal. The pattern generation circuit 11 further outputs expected value data to the comparison circuit 12.

  The memory 10 outputs the internal clock CLKS to the pattern generation circuit 11, the comparison circuit 12, and a subsequent external circuit (not shown) via the delay control circuit 13. The delay control circuit 13 adjusts the delay value added to the internal clock CLKS based on the control signal CCNT. The pattern generation circuit 11 and the comparison circuit 12 operate in synchronization with the delay-adjusted internal clock CLKS. Thereby, the memory 10, the pattern generation circuit 11, and the comparison circuit 12 can operate normally in synchronization with the internal clock CLKS that changes at the same timing.

  In the normal operation mode, the internal clock CLKS forms a pulse having the same cycle as that of the external clock EXCLK. On the other hand, in the high-speed operation mode, the internal clock CLKS forms a plurality of pulses within one cycle of the external clock EXCLK.

  Further, the memory 10 outputs read data to the comparison circuit 12 in the read mode. When performing the memory test, the comparison circuit 12 compares the read data from the memory 10 with the expected value data from the pattern generation circuit 11. The comparison circuit 12 determines that the operation is normal when the two data match, and outputs a determination result. On the other hand, when the two data do not match, the comparison circuit 12 determines that the operation is abnormal and outputs a determination result. In the normal operation, the comparison circuit 12 outputs, for example, read data from the memory 10 as it is.

  An example in which a high-speed memory test is performed on the memory 10 will be described with reference to the timing chart of FIG. In the present embodiment, the normal operation mode is indicated when the mode switching signal CKGEN is at a low level. On the other hand, when the mode switching signal CKGEN is at a high level, the high-speed operation mode is indicated. As shown in FIG. 2, the circuit shown in FIG. 1 is initially set in the normal operation mode. Thereafter, a data write or read operation is performed on the memory 10 in the high-speed operation mode. Thereafter, the data read from the memory 10 in the normal operation mode is compared with the expected value data.

  As shown in FIG. 2, the pattern generation circuit 11 generates a START signal synchronized with the external clock EXCLK when the mode switching signal CKGEN is at a low level. On the other hand, when the mode switching signal CKGEN is at the high level, the pattern generation circuit 11 raises the START signal once in synchronization with the external clock EXCLK, and then outputs the START signal until the mode switching signal CKGEN switches to the low level. Keep at a high level. During this period, the memory 10 generates an internal clock CLKS formed by a plurality of pulses.

  As described above, the memory 10 according to the present embodiment can operate at high speed by the clock generated inside the memory 10. Therefore, in the memory 10 according to the present embodiment, it is possible to perform a high-speed memory test using a low-speed tester.

  Next, details of the memory 10 according to the present embodiment will be described with reference to FIG. The memory 10 includes a pulse signal generation circuit 36, a memory cell unit 22, a row decoder 23, a column selector 24, an input / output circuit 25, a selector 26, an AND logic gate (hereinafter simply referred to as AND) 27, . The pulse signal generation circuit 36 includes a one-shot pulse generation circuit 20 and a timing adjustment circuit 21. The row decoder 23, the column selector 24, and the input / output circuit 25 constitute a control unit that controls writing and reading of data to and from the memory cell. The control unit and the memory cell unit 22 constitute an internal circuit. The pulse signal generation circuit 36, the selector 26, and the AND 27 constitute a pulse signal generation unit.

  First, the circuit configuration of the memory 10 will be described. The clock input terminal CLK is connected to one input terminal of the selector 26 and one input terminal of the AND 27. The other input terminal of the AND 27 is connected to the output terminal of the timing adjustment circuit 21. The output terminal of the AND 27 is connected to the other input terminal of the selector 26. The output terminal of the selector 26 is connected to the clock output terminal CLKS and one input terminal of the one-shot pulse generation circuit 20. The mode switching terminal CKGEN is connected to the switching control terminal of the selector 26.

  Note that a START signal from the pattern generation circuit 11 is supplied to the clock input terminal CLK. A mode switching signal CKGEN from the pattern generation circuit 11 is supplied to the mode switching terminal CKGEN. An ADDRESS signal from the pattern generation circuit 11 is supplied to the ADDRESS terminal. A MODE signal from the pattern generation circuit 11 is supplied to the MODE terminal. The clock output terminal CLKS is a terminal that outputs the internal clock CLKS, and is connected to the delay control circuit 13.

  The output terminal of the one-shot pulse generation circuit 20 is connected to clock input terminals of the timing adjustment circuit 21, the row decoder 23, the column selector 24, and the input / output circuit 25. The output terminal of the timing adjustment circuit 21 is connected to the other input terminal of the one-shot pulse generation circuit 20 in addition to the other input terminal of the AND 27.

  The memory cell unit 22 is configured by arranging a plurality of memory cells as memory elements in a matrix. Between the memory cell unit 22 and the row decoder 23, a plurality of word lines are wired in parallel in the row direction (the horizontal direction in FIG. 3). Between the memory cell unit 22 and the column selector 24, a plurality of bit line pairs are wired in parallel in the column direction (vertical direction in the drawing of FIG. 3). The column selector 24, the data output terminal Q, and the data input terminal DATA are connected to each other via the input / output circuit 25.

  Although not shown, the ADDRESS terminal is connected to the row decoder 23 and the column selector 24. The MODE terminal is connected to the input / output circuit 25, for example. The DATA signal from the pattern generation circuit 11 (FIG. 1) is supplied to the data input terminal DATA. The data output terminal Q is a terminal for outputting read data, and is connected to the comparison circuit 12 (FIG. 1).

  Next, the operation of the circuit shown in FIG. 3 will be described.

  Based on the mode switching signal CKGEN, the selector 26 is one of a START signal (a signal supplied to the CLK terminal) and a logical product of the START signal and the feedback signal (a signal obtained by delaying the pulse signal) FB. One is selected and output to the one-shot pulse generation circuit 20 and the clock output terminal CLKS. More specifically, the selector 26 outputs a START signal in the normal operation mode. The selector 26 outputs a logical product of the START signal and the feedback signal FB in the high-speed operation mode. In the following description, a signal output from the selector 26 is referred to as an internal clock CLKS.

  The one-shot pulse generation circuit 20 generates a one-shot pulse signal (pulse signal) ICLK synchronized with the internal clock CLKS. More specifically, the one-shot pulse generation circuit 20 generates a one-shot pulse signal ICLK synchronized with the START signal in the normal operation mode. In the high-speed operation mode, the one-shot pulse generation circuit 20 generates a continuous one-shot pulse signal ICLK synchronized with the START signal and the feedback signal FB. The one-shot pulse generation circuit 20 outputs the one-shot pulse signal ICLK to the timing adjustment circuit 21, the row decoder 23, the column selector 24, and the input / output circuit 25.

  The timing adjustment circuit 21 generates a feedback signal FB based on the one-shot pulse signal ICLK.

  An internal circuit including the control unit and the memory cell unit 22 operates in synchronization with the one-shot pulse signal ICLK. More specifically, the internal circuit operates in synchronization with the one-shot pulse signal ICLK having the same frequency as the START signal in the normal operation mode. In the high-speed operation mode, the internal circuit operates in synchronization with the one-shot pulse signal ICLK having a high-speed frequency.

  Note that the memory 10 is switched to one of the read mode and the write mode by the MODE signal. Further, in the memory 10, among the memory cells constituting the memory cell unit 22, a memory cell that is a target of data reading or writing is selected by the ADDRESS signal.

  More specifically, the row decoder 23 selects one of a plurality of word lines based on the ADDRESS signal. The column selector 24 selects one of the plurality of bit line pairs based on the ADDRESS signal. Thereby, a memory cell to be read or written of data is selected from the plurality of memory cells arranged in the memory cell unit 22.

  The memory cell unit 22 outputs data read from the selected memory cell toward the data output terminal Q via the column selector 24 and the input / output circuit 25 in the read mode. On the other hand, the memory cell unit 22 inputs write data from the data input terminal DATA to the selected memory cell via the input / output circuit 25 and the column selector 24 in the write mode.

  Thereby, in the read mode, data stored in the selected memory cell is read from the data output terminal Q. On the other hand, in the write mode, write data from the data input terminal DATA is written to the selected memory cell. The row decoder 23, the column selector 24, and the input / output circuit 25 operate in synchronization with the one-shot pulse signal ICLK.

  FIG. 4 is a diagram showing the circuit configuration of the memory 10 shown in FIG. 3 in more detail. The timing adjustment circuit 21 includes a pulse width adjustment circuit 30, an operation completion signal generation circuit 31, and a NAND logic gate (hereinafter simply referred to as NAND) 32. The one-shot pulse generation circuit 20 includes a latch circuit 33, an AND 34, and an inverter (hereinafter simply referred to as INV) 35. The latch circuit 33 is, for example, an RS latch circuit (set / reset flip-flop).

  The output terminal of the selector 26 is connected to the input terminal of the INV 35 and one input terminal of the AND 34 via one input terminal of the one-shot pulse generation circuit 20. The output terminal of the INV 35 is connected to the other input terminal of the AND 34. The output terminal of the AND 34 is connected to the S terminal (set terminal) of the latch circuit 33. The terminal Q (output terminal) of the latch circuit 33 is connected to each of the timing adjustment circuit 21, the row decoder 23, the column selector 24, and the input / output circuit 25 via the output terminal of the one-shot pulse generation circuit 20. Connected to the clock input terminal. The terminal Q of the latch circuit 33 is connected to the input terminal of the pulse width adjustment circuit 30 and the input terminal of the operation completion signal generation circuit 31 via the output terminal of the one-shot pulse generation circuit 20 and the input terminal of the timing adjustment circuit 21. And connected to. The output terminal of the pulse width adjustment circuit 30 is connected to one input terminal of the NAND 32. The output terminal of the operation completion signal generation circuit 31 is connected to the other input terminal of the NAND 32. The output terminal of the NAND 32 is connected to the other input terminal of the AND 27 via the output terminal of the timing adjustment circuit 21 and is further connected to the R of the latch circuit 33 via the other input terminal of the one-shot pulse generation circuit 20. Connected to the terminal (reset terminal).

  An inverted signal of the feedback signal FB is input to the R terminal of the latch circuit 33. A pulse signal synchronized with the rising edge of the internal clock CLKS is input to the S terminal (set terminal) of the latch circuit 33. The latch circuit 33 outputs a one-shot pulse signal ICLK from the Q terminal. The pulse width adjustment circuit 30 generates a pulse width adjustment signal based on the one-shot pulse signal ICLK. The operation completion signal generation circuit 31 generates an operation completion signal based on the one-shot pulse signal ICLK. The NAND 32 receives the pulse width adjustment signal and the operation completion signal and outputs a feedback signal FB. The other circuit configuration is the same as that of the circuit shown in FIG.

  Here, the elapsed time between the detection edge of the one-shot pulse signal ICLK and the detection edge of the pulse width adjustment signal generated based on the detection edge is necessary for the one-shot pulse signal ICLK to access the internal circuit. It corresponds to time (access time).

  That is, the pulse width adjustment circuit 30 detects the access time by providing a replica of the internal circuit, for example, and generates a pulse width adjustment signal. Alternatively, the pulse width adjustment circuit 30 receives the access time detected from the internal circuit and generates a pulse width adjustment signal. Alternatively, the pulse width adjustment circuit 30 generates a pulse width adjustment signal after elapse of a predetermined access time set in advance. The pulse width of the one-shot pulse signal ICLK is adjusted by this pulse width adjustment signal.

  In the high-speed operation mode, the time from the detection edge of the one-shot pulse signal ICLK to the detection edge of the next cycle corresponds to the time from the start of the operation of the internal circuit to the completion of the operation. In other words, in the high-speed operation mode, the elapsed time between the detection edge of the one-shot pulse signal ICLK and the detection edge of the operation completion signal generated based thereon is the time from the start of operation of the internal circuit to the completion of the operation. It corresponds to.

  The operation start of the internal circuit means, for example, the time when the one-shot pulse signal ICLK rises. The completion of the operation of the internal circuit means, for example, the time when data is read from the selected memory cell based on the one-shot pulse signal ICLK. In other words, it refers to the time when the writing and reading of data to and from the memory cell by the control unit operating based on the one-shot pulse signal ICLK is completed.

  That is, the operation completion signal generation circuit 31 detects an operation completion time of the internal circuit by providing a replica of the internal circuit, for example, and generates an operation completion signal. Alternatively, the operation completion signal generation circuit 31 receives the operation completion time detected from the internal circuit and generates an operation completion signal. Alternatively, the operation completion signal generation circuit 31 generates an operation completion signal after elapse of a predetermined time set in advance. This operation completion signal determines the frequency of the one-shot pulse signal ICLK in the high-speed operation mode. In the timing adjustment circuit 21, the NAND 32 generates a feedback signal FB based on the pulse width adjustment signal and the operation completion signal.

  In the normal operation mode, an inverted signal of the feedback signal FB is input to the R terminal of the latch circuit 33. The START signal is input to the S terminal of the latch circuit 33 as the internal clock CLKS. On the other hand, in the high-speed operation mode, an inverted signal of the feedback signal FB is input to the R terminal of the latch circuit 33. The logical product of the feedback signal FB and the START signal is input to the S terminal of the latch circuit 33 as the internal clock CLKS.

  The operations of the one-shot pulse generation circuit 20 and the timing adjustment circuit 21 will be described in more detail with reference to FIGS. FIG. 5 is a timing chart of the one-shot pulse generation circuit 20 and the timing adjustment circuit 21 in the normal operation mode. FIG. 6 is a timing chart when the one-shot pulse generation circuit 20 and the timing adjustment circuit 21 are in a high-speed operation mode.

  First, operations in the normal operation mode of the one-shot pulse generation circuit 20 and the timing adjustment circuit 21 will be described with reference to FIG. In the following description, the START signal (signal supplied to the CLK terminal) is referred to as a clock CLK. The case where the initial state of the one-shot pulse signal ICLK is at a low level and the initial state of the feedback signal FB is at a high level will be described as an example.

  The selector 26 selects the clock CLK and outputs it as the internal clock CLKS. Therefore, when the clock CLK rises, the internal clock CLKS also rises. The one-shot pulse generation circuit 20 raises the one-shot pulse signal ICLK in synchronization with the rise of the internal clock CLKS (time T0).

  The timing adjustment circuit 21 detects the rising edge of the one-shot pulse signal ICLK at time T0, and then lowers the feedback signal FB after a time corresponding to the access time of the internal circuit (time Ta). The one-shot pulse generation circuit 20 falls the one-shot pulse signal ICLK in synchronization with the fall of the feedback signal FB at time Ta (time Tb). Thereafter, the timing adjustment circuit 21 raises the feedback signal FB in response to the fall of the one-shot pulse signal ICLK at time Tb (time Tc). The timing adjustment circuit 21 raises the feedback signal FB at time Tc after the time corresponding to the completion of the operation from the start of the operation of the internal circuit after the one-shot pulse signal ICLK rises at the time T0. Yes.

  That is, from the time Tc to the next rising edge of the clock CLK (time T2), the feedback signal FB and the one-shot pulse signal ICLK both indicate an initial state. Thus, the one-shot pulse generation circuit 20 generates the one-shot pulse signal ICLK that is synchronized with the rising edge of the clock CLK. That is, the one-shot pulse generation circuit 20 generates a one-shot pulse signal ICLK having the same frequency as the clock CLK.

  Note that the period from time T0 to T1 is the time required from the start of the operation of the internal circuit to the completion of the operation. That is, the time from time T0 to T1 indicates the maximum operation cycle of the internal circuit. Therefore, the time required for the memory test can be shortened by adjusting the time per cycle of the one-shot pulse signal ICLK to the time T0 to T1. At the same time, a high-speed memory test can be performed as a higher quality memory test.

  Note that the conventional circuit shown in FIG. 10 also exhibits the same operation as that shown in FIG. The circuit illustrated in FIG. 10 does not include the selector 26 and the AND 27 as compared with the circuit illustrated in FIG. That is, in the circuit shown in FIG. 10, only the pulse signal synchronized with the rising edge of the clock CLK is input to the one-shot pulse generation circuit 20. The other circuit configuration is the same as that of the circuit shown in FIG.

  Next, the operation of the one-shot pulse generation circuit 20 and the timing adjustment circuit 21 in the high-speed operation mode will be described with reference to FIG. In the following description, the START signal (signal supplied to the CLK terminal) is referred to as a clock CLK. The case where the initial state of the one-shot pulse signal ICLK is at a low level and the initial state of the feedback signal FB is at a high level will be described as an example.

  The selector 26 selects the logical product of the clock CLK and the feedback signal FB and outputs it as the internal clock CLKS. Note that, in the high-speed mode, the clock CLK maintains a high level state after it rises once until the mode is switched. Therefore, the selector 26 outputs the internal clock CLKS having the detection edge (rising edge) as the rising edge of the clock CLK and the rising edge of the feedback signal FB (corresponding to the detection edge of the operation completion signal).

  The one-shot pulse generation circuit 20 raises the one-shot pulse signal ICLK in synchronization with the rise of the internal clock CLKS at time T0. The rise of the internal clock CLKS at time T0 is due to the rise of the clock CLK.

  The timing adjustment circuit 21 detects the rising edge of the one-shot pulse signal ICLK at time T0, and then lowers the feedback signal FB after a time corresponding to the access time of the internal circuit (time Ta). As a result, the internal clock CLKS falls (time Tb). Further, the one-shot pulse generation circuit 20 causes the one-shot pulse signal ICLK to fall in synchronization with the fall of the feedback signal FB at time Ta (time Tb). Thereafter, the timing adjustment circuit 21 raises the feedback signal FB in response to the fall of the one-shot pulse signal ICLK at time Tb (time Tc). The timing adjustment circuit 21 raises the feedback signal FB at time Tc after the time corresponding to the completion of the operation from the start of the operation of the internal circuit after the one-shot pulse signal ICLK rises at the time T0. Yes.

  In the high-speed operation mode, the clock CLK maintains a high level state as described above. Therefore, when the feedback signal FB rises at time Tc, the one-shot pulse generation circuit 20 raises the one-shot pulse signal ICLK in synchronization with it (time T1).

  The timing adjustment circuit 21 detects the rising edge of the one-shot pulse signal ICLK at time T1, and then lowers the feedback signal FB after a time corresponding to the access time of the internal circuit (time Td). As a result, the internal clock CLKS falls (time Te). Further, the one-shot pulse generation circuit 20 causes the one-shot pulse signal ICLK to fall in synchronization with the fall of the feedback signal FB at time Td (time Te). Thereafter, the timing adjustment circuit 21 raises the feedback signal FB in response to the fall of the one-shot pulse signal ICLK at time Te (time Tf). Note that the timing adjustment circuit 21 raises the feedback signal FB at time Tf after a lapse of time from the start of operation of the internal circuit to the completion of operation after the one-shot pulse signal ICLK rises at time T1. Yes. Such an operation is repeated while the clock CLK is at a high level.

  As described above, the one-shot pulse generation circuit 20 is synchronized with the rising edge of the clock CLK and the rising edge of the feedback signal FB (corresponding to the detection edge of the operation completion signal) in the high-speed operation mode. Is generated.

  Note that the period from time T0 to T1 is the time required from the start of the operation of the internal circuit to the completion of the operation. That is, the time from time T0 to T1 indicates the maximum operation cycle of the internal circuit. Here, the one-shot pulse generation circuit 20 generates the one-shot pulse signal ICLK synchronized with the operation completion signal from the timing adjustment circuit 21 as described above. Therefore, the one-shot pulse generation circuit 20 can generate the one-shot pulse signal ICLK having a cycle corresponding to the maximum operation cycle of the internal circuit.

  With such a circuit configuration, the semiconductor integrated circuit (memory 10) according to the present embodiment automatically generates the one-shot pulse signal ICLK having a cycle corresponding to the high-speed operation cycle of the internal circuit in the high-speed operation mode. can do. Thereby, the semiconductor integrated circuit according to the present embodiment selects a memory cell to be read or written of data for each detection edge (for example, rising edge) of the one-shot pulse signal ICLK, and selects the memory cell. Thus, data can be read or written. Therefore, the semiconductor integrated circuit according to the present embodiment can reduce the time required for the memory test. At the same time, the semiconductor integrated circuit according to the present embodiment can perform a high-speed memory test as a higher quality memory test.

  Note that the pulse signal generation circuit 36 as shown in FIG. 3 is generally provided in a semiconductor memory device. That is, the semiconductor integrated circuit according to the present embodiment can generate a high-speed one-shot pulse signal ICLK using a conventional circuit. Therefore, the semiconductor integrated circuit according to the present embodiment does not need to use a large-scale circuit such as a PLL, and can suppress an increase in circuit scale.

Embodiment 2
FIG. 7 shows a memory (semiconductor integrated circuit) 10 and its peripheral circuits according to the second embodiment of the present invention. The circuit shown in FIG. 7 includes a delay control circuit 14 instead of the delay control circuit 13 as compared with the circuit shown in FIG. In the circuit shown in FIG. 7, the pattern generation circuit 11 further outputs a NOP signal to the memory 10. The NOP signal is a signal for switching whether or not the memory 10 is set to the NOP mode. The delay control circuit 13 has a frequency dividing function in addition to a function of adding a delay value to the input signal and outputting the signal.

  In the NOP mode, the memory 10 does not read or write data, and the one-shot pulse generation circuit 20 only generates the one-shot pulse signal ICLK. At the same time, the memory 10 generates an internal clock CLKS having the same frequency as the one-shot pulse signal ICLK. The memory 10 outputs the internal clock CLKS to the pattern generation circuit 11 and the comparison circuit 12 via the delay control circuit 14.

  Accordingly, the circuit shown in FIG. 7 can confirm high-speed operation with respect to a peripheral circuit (not shown), the pattern generation circuit 11 and the comparison circuit 12 provided in the memory 10. That is, the memory 10 according to the present embodiment generates the one-shot pulse signal ICLK for confirming the high-speed operation for the peripheral circuit, the pattern generation circuit 11 and the comparison circuit 12 provided in the memory 10. be able to. As in the case of the first embodiment, the one-shot pulse generation circuit 20 according to the present embodiment generates a one-shot pulse signal ICLK corresponding to each of the normal operation mode and the high-speed operation mode in the NOP mode. Since other circuit configurations are the same as those in the first embodiment, description thereof is omitted.

  FIG. 8 is a timing chart showing the operation of the delay control circuit 14. In FIG. 8, the delay value control function of the delay control circuit 14 will be described. As described above, the delay control circuit 14 adds a delay value to the internal clock CLKS and outputs it to the pattern generation circuit 11 and the comparison circuit 12.

  If the delay control circuit 14 does not add a delay value to the internal clock CLKS, as shown in FIG. 8, the detected edge of the internal clock CLKS (S1) input to the pattern generation circuit 11 and the comparison circuit 12, and the memory 10 Is shifted from the detected edge of the internal clock CLKS (S0). On the other hand, when the delay control circuit 14 adds a delay value to the internal clock CLKS, as shown in FIG. 8, the detection edge of the internal clock CLKS (S2) input to the pattern generation circuit 11 and the comparison circuit 12, and the memory 10 And the detected edge of the internal clock CLKS (S0) coincide with each other. Thereby, the memory 10, the pattern generation circuit 11, and the comparison circuit 12 can operate normally in synchronization with the internal clock CLKS that changes at the same timing. The same applies to the delay control circuit 13 shown in FIG.

  FIG. 9 is a timing chart showing the operation of the delay control circuit 14 in FIG. In FIG. 9, the frequency dividing function of the delay control circuit 14 will be described. FIG. 9 illustrates a case where high-speed operation is confirmed for the peripheral circuit, the pattern generation circuit 11, and the comparison circuit 12 provided in the memory 10. Here, the operating frequency of the internal clock CLKS may be higher than the requested operating frequency. In this case, the delay control circuit 14 divides the internal clock CLKS up to the requested operating frequency.

  As shown in FIG. 9, the case where the operating frequency of the internal clock CLKS (S0) in the memory 10 is 200 MHz and the requested operating frequency of the internal clock CLKS (S1) is 50 MHz will be described. In this case, the delay control circuit 14 divides the internal clock CLKS (S0) in the memory 10 by four (S2).

  The operating frequency required for the internal clock CLKS input to the pattern generation circuit 11 and the comparison circuit 12 corresponds to, for example, the operating frequency at the time of at-speed. Thereby, the pattern generation circuit 11 can generate a test pattern that changes in accordance with the operating frequency at the time of at-speed.

  As described above, the semiconductor integrated circuit according to the above-described embodiment does not use a multiplier circuit such as a PLL, but uses a conventional circuit (pulse signal generation circuit 36) to perform a high-speed one-shot pulse signal ICLK. Can be generated. Therefore, the semiconductor integrated circuit according to the above embodiment can perform a high-speed memory test without increasing the circuit scale. Furthermore, since the semiconductor integrated circuit according to the above embodiment controls the frequency of the one-shot pulse signal ICLK based on the operating frequency of the internal circuit, the one-shot pulse signal ICLK is automatically set to the maximum operating frequency of the internal circuit. It is possible to adjust.

  Thus, the semiconductor integrated circuit according to the above embodiment can perform a high-quality memory test using a low-speed tester. That is, in the semiconductor integrated circuit according to the above embodiment, it is not necessary to prepare a high-speed tester device or a high-speed interface, so that the cost can be reduced.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. In the above embodiment, the case where the one-shot pulse generation circuit 20 is an RS latch circuit has been described as an example, but the present invention is not limited to this. Any circuit configuration capable of generating the one-shot pulse signal ICLK based on the internal clock CLKS can be changed as appropriate.

DESCRIPTION OF SYMBOLS 10 Memory 11 Pattern generation circuit 12 Comparison circuit 13 Delay control circuit 14 Delay control circuit 20 One shot pulse generation circuit 21 Timing adjustment circuit 22 Memory cell part 23 Row decoder 24 Column selector 25 Input / output circuit 26 Selector 27 AND
30 Pulse Width Adjustment Circuit 31 Operation Completion Signal Generation Circuit 32 NAND
33 Latch circuit 34 AND
35 Inverter (INV)
36 Pulse signal generation circuit CLK clock CLKS internal clock FB feedback signal ICLK one-shot pulse signal

Claims (5)

A memory cell unit composed of a plurality of memory cells;
A control unit for controlling writing and reading of data to and from the memory cell;
A pulse signal generation unit that generates a pulse signal input to the control unit according to an external clock,
The pulse signal generation unit has a one-shot pulse generation circuit,
The one-shot pulse generation circuit
A semiconductor that generates a one-shot pulse signal as a pulse signal based on the external clock in a normal operation mode, and generates a continuous one-shot pulse signal as a pulse signal based on the external clock and the pulse signal in a high-speed operation mode Integrated circuit. The one-shot pulse generation circuit
Has a set-reset flip-flop circuit,
In the normal operation mode, in the set reset flip-flop circuit, a signal corresponding to the external clock is input to the set input terminal, and a signal that gives a delay to the output signal of the set reset flip-flop circuit is input to the reset input terminal. To generate the one-shot pulse signal,
In the high-speed operation mode, a signal obtained by delaying the output signal of the set-reset flip-flop circuit is further input to the set input terminal of the set-reset flip-flop circuit, thereby generating the continuous one-shot pulse signal. The semiconductor integrated circuit according to claim 1. The pulse signal generator is
3. The semiconductor integrated circuit according to claim 1, further comprising a timing adjustment circuit that delays the pulse signal and outputs the delayed signal to the one-shot pulse generation circuit. The timing adjustment circuit includes:
The controller that has operated based on the pulse signal detects that data writing or reading to the memory cell has been completed, and sends a delay to the pulse signal to the one-shot pulse generation circuit. 4. The semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit outputs the signal. The pulse signal generator
A selector circuit that selects one of the external clock and a logical product of the external clock and the pulse signal based on a mode selection signal from the outside, and outputs the selected one to the one-shot pulse generation circuit The semiconductor integrated circuit according to claim 1, further comprising:

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