JP2011210053A - Method and device for designing semiconductor integrated circuit, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize power consumption in a clock signal part while minimizing a clock skew and a clock delay under manufacturing variations.SOLUTION: A device for designing a semiconductor integrated circuit includes: a mesh network delay calculation part 103 for calculating a delay of a mesh network; a mesh network driving structure delay calculation part 105 for calculating a delay of a mesh network driving structure; a clock element hierarchical cluster generation part 106 for hierarchically generating clusters of clock elements; a clock gating structure generation part 107; a local clock structure generation part 108; a local clock structure delay calculation part 109; a clock structure evaluation part 110 for calculating a clock skew by taking into consideration a maximum clock delay and delay variations, for an entire generated clock structure; and a clock structure selecting means 111 for selecting a clock structure from a set of local clock structure candidates on the basis of respective calculated local clock structure delays and respective calculated clock skews.

Description

  The present invention relates to a semiconductor integrated circuit design method, a design apparatus, and a computer program, and more particularly, a design method, a design apparatus, and a design apparatus for arranging and wiring a semiconductor integrated circuit including a clock distribution circuit having a clock gating structure and a mesh structure. It relates to a computer program.

  A synchronous semiconductor integrated circuit includes a logic element (hereinafter also referred to as a logic cell or a logic gate) for performing operations and control of operations and a sequential circuit element (hereinafter referred to as a clock element) for synchronizing operations of the logic element group. , Flip-flop, or FF). Each flip-flop is supplied with a clock signal that periodically oscillates from one clock supply source (hereinafter also referred to as a clock source), and the data held by the flip-flop according to the rising or falling edge of the clock signal. Is supplied to the logic element group. The logic element uses the supplied data as an input to perform operations and control operations, and stores the results in flip-flops. The above processing is repeated according to the rising or falling edge of the periodically changing clock signal.

  The ideal clock signal distribution circuit placement and wiring conditions for operating the above-described synchronous circuit at normal timing with reference to the clock signal are exactly the same at any flip-flop clock input terminal. It is to obtain a clock signal waveform. However, in reality, it is difficult to make the time for arrival of the clock signal exactly the same for each flip-flop due to the density of the distribution of the clock signal wiring and the connected clock elements.

  The difference in the arrival time of the clock signal in the flip-flop pair is called clock skew. If the clock skew is large, the circuit may not operate normally. Therefore, it is important to reduce the clock skew as much as possible in the placement and routing of the clock distribution circuit.

  As a circuit configuration for distributing the clock signal, there is a configuration in which a tree-like wiring path passing through a plurality of buffers is set from a clock source and the clock signal is distributed to each clock element in a tree shape. Here, by setting the tree shape so that the propagation path of the clock signal from the clock source to each clock element has the same length and the same number of buffer stages, the clock skew can be reduced. For example, Patent Document 1 discloses a technique for generating a tree structure as described above. An example of the arrangement and wiring of the clock distribution circuit according to this technique is shown in FIG. Here, a path 16-02 for distributing a clock signal from the clock source 16-01 to the clock element 16-03 via the relay buffer 16-04 is set.

  However, even with such a distribution circuit configuration, in actual design, it is inevitable that clock skew will occur due to the influence of deviation of each path shape, variation in manufacturing process, and the like. In particular, in recent years, with the miniaturization of semiconductor processes, the delay variation problem due to quality variations in manufacturing has become serious, and accordingly, minimization of clock skew has become more difficult.

  As a well-known example of a technique for extending the method of Patent Document 1 so that manufacturing variation tolerance becomes strong, there is Patent Document 2, but in a tree-like structure, it is unavoidable that a difference in delay variation at the signal branch destination occurs. Therefore, there is a limit to minimizing skew.

  Therefore, in order to cope with such a manufacturing variation problem, a technique for reducing the difference in clock signal arrival time from the clock source to each clock element by wiring-shorting the output of the terminal buffer of the clock distribution circuit having a tree structure. Has been proposed. According to this technique, by short-circuiting the output of the buffer, clock signals that have passed through different paths from the clock supply source are averaged, and clock skew due to manufacturing variations can be reduced. For example, Patent Document 4, Patent Document 4 discloses a technique for connecting a clock tree structure terminal buffer output terminal to a wiring having a mesh structure (also referred to as a lattice structure) and distributing a clock signal from a mesh-shaped wiring to a clock element. 5, proposed in Patent Document 6. FIG. 17 shows an example in which the terminal buffer (17-03) output of the clock distribution tree (17-01) is short-circuited by the mesh structure wiring (17-02 and 17-04).

  On the other hand, recent advances in semiconductor circuit scale and speed have led to an increase in power consumption at the clock signal section, and clock layout and wiring design that realizes low power consumption in addition to clock skew reduction Technology is also becoming important.

  As an effective method for reducing the power consumption of the clock signal unit, a gated clock circuit design method has been proposed and widely used (for example, Patent Document 7). This is a technique for reducing power consumption by stopping clock operation when the circuit does not operate. A control signal called a gating signal (or called an enable signal) from a logic circuit is a clock distribution circuit. Connect to the top to control the propagation of the clock signal.

  An example of clock gating is shown in FIG. Gating logic gate 18-04 that controls the distribution of the clock signal to the clock elements by taking the logical product of the gating signal (18-01, 18-02) and the clock signal from clock source 16-01 A set of clock elements 16-03, which is called a cell and to which a clock signal is distributed from a gating cell to which the same gating signal is connected, is called a gated circuit 18-03. An input terminal of the gating cell to which the gating signal is connected is referred to as an enable terminal.

  Furthermore, in recent years, in order to realize both low power consumption and low skew, techniques for combining clock gating and a mesh structure have been proposed in, for example, Patent Document 8 and Patent Document 9. Here, as shown in FIG. 19, a mesh structure 17-02 is applied to each partial circuit to which clock gating is applied. Looking at this in the layout structure, as shown in FIG. 20, the mesh structure 17-02 generated for each gated circuit is superimposed on the same layout region.

  However, in the conventional technology combining clock gating and mesh structure, as shown in FIGS. 19 and 20, since the mesh structure is applied to each partial circuit to which clock gating is applied, connection to different mesh structures is performed. There is a problem that the skew of the clock element pair cannot be made sufficiently small. That is, in a clock configuration including a gating structure, mesh-shaped wiring that short-circuits all buffer outputs connected to the clock element input terminal in the chip cannot be applied, and mesh-shaped wiring is set for each gated circuit. Therefore, although the clock skew in the same gated circuit can be reduced, the propagation path of the clock signal differs between different gated circuits, and the clock skew increases.

  In addition, usually, clock elements belonging to different gated circuits are often mixed and distributed on the chip. Therefore, setting the mesh structure in an overlapping manner consumes a lot of wiring resources, and wiring properties are reduced. There is a problem that it leads to deterioration and an increase in power consumption.

  In order to solve this problem, in Japanese Patent Application No. 2009-283886, as shown in FIG. 21, a gating cell is duplicated and gated circuits driven by different enable signals are connected to the same mesh structure 17-02 or lower. Proposing technology.

JP-A-5-054100 JP 2007-123336 A JP 2004-334468 A Japanese Patent Laid-Open No. 2003-092352 JP 2003-282712 A JP 2007-214334 A JP 2009-053830 A JP 2003-109382 A JP 2007-019414 A

  The combination technique of the mesh structure and the clock gating structure proposed in Japanese Patent Application No. 2009-283886 is applied to the clock element 16-03 from the clock source 16-01 via the gating cell 18-04. When applied to the distribution of clock signals, the clock structure (mesh structure 17-02, buffer tree 17-02 that drives the mesh structure, and local structure after the mesh is replicated as shown in FIG. A combination of gating cell sets 18-04 and enable signals).

  In this case, the delay time from the clock source to the clock element is the delay time D1 (04-01 in FIG. 4) of the buffer tree structure for driving the mesh net and the delay time D2 (04 in FIG. 4) for driving the mesh net itself. -02) and the delay time D3 (04-03 in FIG. 4) for driving the gated circuit. Here, since D3 has a different value for each clock element, the minimum delay time of this clock structure is D1 + D2 + min {D3}, and the maximum delay time is D1 + D2 + max {D3}. min {D3} indicates the minimum value of D3, and max {D3} indicates the maximum value of D3.

  The main skew of this clock structure occurs up to the mesh net (D1 + D2) due to the effect of the short-circuit wiring, and can be suppressed to almost zero, and therefore occurs in the delay time D3 for driving the gated circuit. Since the gated circuit part is not short-circuited, the effect of delay variation cannot be mitigated. If the delay variation coefficient is k, the skew of this clock structure is max {D3} * (1 + k) -min {D3} * (1-k) Here, k is given as a decimal number between 0 and 1.

  In addition to the clock structure delay and skew described above, the design places an upper limit on the delay time D4 of the enable signal for driving the gating cell (04-04 in FIG. 4). As the number of duplicated gating cells increases, the fanout number of the enable signal increases, and it may be difficult to satisfy the delay time constraint.

In the design of the clock structure, it is desired to find the best combination of the mesh net structure, the mesh net driving buffer tree structure, and the gated clock structure for any of the following problems.
1) Clock skew max {D3} * (1 + k)-min {D3} * under the upper limit constraints on enable signal delay time D4 and clock maximum delay D1 + D2 + max {D3} Minimize (1-k).
2) Maximum delay of clock D1 + D2 under the upper limit constraint on enable signal delay time D4 and clock skew max {D3} * (1 + k)-min {D3} * (1-k) + Minimize max {D3}.

  A design technique for efficiently solving this problem has not yet been proposed.

  The present invention has been made to solve the above-described problems, and comprehensively considers enable signal delay, clock delay, and clock skew in a semiconductor integrated circuit including a clock distribution circuit having a clock gating structure. Another object of the present invention is to provide a design method, a design apparatus, and a computer program for performing placement and routing.

The semiconductor integrated circuit design apparatus of the present invention comprises:
A memory device for storing chip information of a semiconductor integrated circuit including a clock gating structure, and selecting one lattice number from the mesh net lattice number candidates, taking into account the input terminal positions of all clock elements included in the chip information. A mesh net generating means for generating a mesh net of the selected number of lattices, a mesh net delay calculating means for calculating a delay of the mesh net generated by the mesh net generating means, and a buffer tree for driving the mesh net A mesh net driving structure generating means for generating a mesh net driving structure delay calculating means for calculating a delay of the mesh net driving structure generated by the mesh net driving structure generating means, and an arrangement of clock elements included in the chip information Consider different distributions and clock gating structures Clock element hierarchy cluster generating means for hierarchically generating a cluster of clock elements that do not include clock elements included in the head circuit and include a set of clock elements arranged in the vicinity, and the clock element hierarchy For each clock element hierarchy cluster generated by the cluster generation means, select a clock element hierarchy to be connected to the enable signal so as to satisfy the delay constraint of the enable signal, and the clock elements included below the selected cluster hierarchy belong. Duplicating a gating cell that distributes a clock signal to a gated circuit and inserting it as a gating cell that drives the hierarchical cluster; and a mesh net and each duplicated gating cell input terminal Connect the clock source from the gating cell. Local clock structure generating means for generating a connection structure up to and a local clock structure delay calculating means for calculating the delay from the input terminal of the mesh net to each clock element for each local clock structure generated by the local clock structure generating means And a clock structure evaluation means for calculating a clock skew considering the maximum clock delay and delay variation for the entire generated clock structure, and a set of local clock structure candidates performed for all mesh net lattice number candidates To clock structure selection means for selecting a clock structure based on each calculated local clock structure delay and each calculated clock skew.

A method for designing a semiconductor integrated circuit according to the present invention includes:
The chip information of the semiconductor integrated circuit including the clock gating structure is stored, one lattice number is selected from the mesh net lattice number candidates, and the input terminal positions of all the clock elements included in the chip information are considered, Generate a mesh net structure of the selected number of lattices, calculate the delay of the mesh net structure, generate a mesh net drive buffer tree structure that drives the mesh net structure, and calculate the delay of the mesh net drive buffer tree structure In consideration of the clock element arrangement distribution and the clock gating structure included in the chip information, the clock elements included in different gated circuits are not mixed, and a set of clock elements arranged in the vicinity is included. The cluster of clock elements is generated hierarchically, and each clock element hierarchical class On the other hand, a gating cell that selects a clock element hierarchy to be connected to the enable signal so as to satisfy the delay constraint of the enable signal and distributes the clock signal to the gated circuit to which the clock element included in the selected cluster hierarchy or lower belongs. Is duplicated and inserted as a gating cell for driving the hierarchical cluster, the mesh net and each duplicated gating cell input terminal are connected, and a connection structure from the gating cell to the clock element is generated, For each local clock structure generated by the local clock structure generating means, the delay from the input terminal of the mesh net to each clock element is calculated, and the clock skew considering the maximum clock delay and delay variation is calculated for the entire generated clock structure. Calculate all meshes Tsu generates a set of local clock structure candidate against preparative grating number candidates, from among them, selects a clock structure based was calculated to calculated each local clock structure delays were in each clock skew.

  The computer program of the present invention selects a lattice number from a mesh net lattice number candidate and a procedure for storing chip information of a semiconductor integrated circuit including a clock gating structure in a computer that functions as a semiconductor integrated circuit design device. Taking into account input terminal positions of all clock elements included in the chip information, generating a mesh net structure of the selected number of lattices, calculating a delay of the mesh net structure, and the mesh net Considering a procedure for generating a mesh net driving buffer tree structure for driving a structure, a procedure for calculating a delay of the mesh net driving buffer tree structure, and an arrangement distribution of clock elements and a clock gating structure included in the chip information Therefore, clock elements included in different gated circuits are mixed. And a hierarchical generation of a clock element cluster including a set of clock elements arranged in the vicinity so that the delay constraint of the enable signal is satisfied for each of the clock element hierarchical clusters Then, a clock element hierarchy to be connected to the enable signal is selected, a gating cell that distributes a clock signal to a gated circuit to which a clock element included in the selected cluster hierarchy or lower belongs is duplicated, and a gate that drives the hierarchical cluster is copied. A procedure for inserting as a gating cell, a procedure for connecting the mesh net and each duplicated gating cell input terminal, generating a connection structure from the gating cell to the clock element, and the local clock structure generating means Mesh net input terminal for each local clock structure The procedure for calculating the delay to each clock element, the procedure for calculating the clock skew considering the clock maximum delay and delay variation for the entire generated clock structure, and the local number for all mesh net lattice number candidates A set of clock structure candidates is generated, from which a procedure for selecting a clock structure based on each calculated local clock structure delay and each calculated clock skew is executed.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, etc. are also effective as an aspect of the present invention.

  The various components of the present invention do not necessarily have to be independent of each other. A plurality of components are formed as a single member, and a single component is formed of a plurality of members. It may be that a certain component is a part of another component, a part of a certain component overlaps with a part of another component, or the like.

  Moreover, although the several procedure is described in order in the method and computer program of this invention, the order of the description does not limit the order which performs a several procedure. For this reason, when implementing the method and computer program of this invention, the order of the several procedure can be changed in the range which does not interfere in content.

  Furthermore, the plurality of procedures of the method and the computer program of the present invention are not limited to being executed at different timings. For this reason, another procedure may occur during the execution of a certain procedure, or some or all of the execution timing of a certain procedure and the execution timing of another procedure may overlap.

  According to the present invention, a clock distribution circuit including a gating structure that is effective for reducing power consumption is divided into an entire clock structure without dividing a mesh structure that is effective for reducing skew including manufacturing variations. In consideration of the overall delay, skew, and enable signal delay, it is possible to generate the best clock structure in which all clock elements are connected to the same mesh structure or lower. As a result, the power consumption, the delay, and the delay skew of the clock distribution circuit can be reduced.

It is a functional block diagram which shows the structure of the design apparatus of the semiconductor integrated circuit which concerns on embodiment of this invention. It is a flowchart which shows an example of the process sequence of the design method of the semiconductor integrated circuit which concerns on embodiment of this invention. It is a figure which shows an example of the clock structure used as the input to the design apparatus and design method of this invention. It is a figure which shows an example of the clock structure produced | generated by the design apparatus and design method of this invention. It is an example of a mesh net structure. It is a figure which shows an example of the table | surface which hold | maintains the delay of mesh net itself about each combination of the number of mesh net drive buffers and mesh net capacity | capacitance used in order to calculate the delay of a mesh net structure. It is a figure which shows an example of the buffer tree structure used in order to drive a mesh net structure. It is a figure which shows an example of the clock element hierarchy clustering which considered the gating structure and clock element arrangement | positioning. It is the figure which showed an example of the clock element hierarchy clustering which considered the gating structure and clock element arrangement | positioning from a layout viewpoint. It is a figure which shows the example which connected the enable signal to the highest hierarchy cluster. It is the figure which showed the example which connected the enable signal to the highest hierarchy cluster from a layout viewpoint. It is a figure which shows the example which connected the enable signal to the 2nd hierarchy cluster from the bottom. It is the figure which showed the example which connected the enable signal to the 2nd hierarchy cluster from the bottom in terms of layout. It is a figure which shows the example of the gating clock structure after the mesh net structure obtained by connecting an enable signal to the 2nd hierarchy cluster from the bottom. It is the figure which showed the example of the gating clock structure after the mesh net structure obtained by connecting an enable signal to the 2nd hierarchy cluster from the bottom from a layout viewpoint. It is a figure which shows the clock distribution method of patent document description. It is a figure which shows mesh structure insertion of patent document description. It is a figure which shows the gating clock circuit structure of a patent document description. It is a figure which shows the circuit structure of the combination of the gating clock and mesh structure of patent document description. It is a figure which shows the layout of the combination of the gating clock and mesh structure of patent document description. It is a figure which shows the combination structure of gating clock and mesh structure of Japanese Patent Application No. 2009-283886. It is a figure which shows the example of 1 structure of a computer.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
(First embodiment)
FIG. 1 is a functional block diagram showing a configuration of a semiconductor integrated circuit design apparatus according to an embodiment of the present invention.

  The semiconductor integrated circuit design device 100 of this embodiment includes a chip information storage unit 90 that stores chip information of a semiconductor integrated circuit including a clock gating structure, a chip information reception unit 101, and a lattice number from a mesh net lattice number candidate. A mesh net generation unit 102 that generates a mesh net having the selected number of lattices in consideration of input terminal positions of all clock elements included in the chip information, and a mesh generated by the mesh net generation unit 102 Mesh net delay calculation unit 103 for calculating net delay, mesh net drive structure generation unit 104 for generating a buffer tree for driving the mesh net, and delay of mesh net drive structure generated by mesh net drive structure generation unit 104 And a mesh net driving structure delay calculating unit 105 for calculating.

  In addition, the semiconductor integrated circuit design device 100 of the present embodiment takes into account the clock element arrangement distribution and the clock gating structure included in the chip information, and the clock elements included in different gated circuits are not mixed, and A clock element hierarchy cluster generation unit 106 that hierarchically generates a cluster of clock elements that includes a set of clock elements arranged in the vicinity, and satisfies the delay constraint of the enable signal for each of the clock element hierarchy clusters. As described above, the clock element hierarchy to be connected to the enable signal is selected, the gating cell that distributes the clock signal to the gated circuit to which the clock element included in the selected cluster hierarchy or lower belongs is duplicated, and the hierarchical cluster is driven. A clock gating structure generation unit 107 to be inserted as a gating cell; Obtain.

  Furthermore, the semiconductor integrated circuit design device 100 of the present embodiment connects the mesh net and each duplicated gating cell input terminal, and generates a connection structure from the gating cell to the clock element. For each local clock structure generated by the local clock structure generation unit 108, the delay from the input terminal of the mesh net to each clock element is calculated, and the local clock structure delay calculation unit 109 and the generated clock structure The clock structure evaluation unit 110 that calculates the clock skew considering the maximum delay and delay variation, and each local clock structure delay calculated from the set of local clock structure candidates performed for all mesh net lattice number candidates And each calculated clock skew It includes a clock structure selection unit 111 for selecting a clock structure.

  The chip information storage unit 90 is connected to each unit from the mesh net generation unit 102 to the clock structure evaluation selection unit 111, and the generation data generated by each unit, the calculated calculation result, and the evaluated evaluation result are the chip information storage unit 90. Generation data generated by each generation unit is stored in the chip information storage unit 90, and data calculated by each calculation unit is received from the chip information storage unit 90. However, data calculated by the calculation unit may be received from the corresponding generation unit. Further, a part of the data may be received from the generation unit and other data may be received from the chip information storage unit 90. For example, the mesh net delay calculation unit 103 generates a mesh net by generating part of the data regardless of whether the mesh net generated by the mesh net generation unit 102 is received from the chip information storage unit 90 or the mesh net generation unit 102. Other data may be received from the chip information storage unit 90. Therefore, in FIG. 1, the mesh net generation unit 102 to the clock structure selection unit 111 are connected by an arrow in one direction. However, this does not necessarily mean that data is sent in the direction of the arrow. Data may be sent via the storage unit 90.

  Further, the data of the input terminal positions of all clock elements used in the mesh net generation unit 102 may be received directly from the chip information reception unit 101 without going through the chip information storage unit 90.

  The semiconductor integrated circuit design device 100 of this embodiment can be configured by hardware such as a dedicated IC, but can be configured by a general computer including a control device, a storage device, an input device, and a display device. it can. Each of these parts will be described with reference to FIG. Each unit is constructed and controlled on a storage device such as a ROM (Read Only Memory) and a RAM (Random Access Memory) by a control device that operates according to a computer program stored in the storage device. That is, each component of the semiconductor integrated circuit design device includes a CPU (Central Processing Unit) 1104 as a control device of an arbitrary computer, a memory 1103 as a storage device such as a ROM (Read Only Memory), a RAM (Random Access Memory), A program that realizes the components shown in the figure loaded in the memory, a storage unit 1105 such as a hard disk for storing the program, a display unit 1102 such as a liquid crystal display, an input / output unit 1101 such as a network connection interface, and the like. It is realized by an arbitrary combination of hardware and software centering on the bus 1106. It will be understood by those skilled in the art that there are various modifications to the implementation method and apparatus.

  Each drawing described below shows a functional unit block, not a hardware unit configuration. In the following drawings, the configuration of parts not related to the essence of the present embodiment is omitted and not shown.

  The chip information storage unit 90 stores information (chip data) on a gate level netlist including clock elements of a semiconductor integrated circuit chip to be designed. Here, the set of clock elements is divided into subsets that can control the propagation of the clock signal with the same gating logic from the logic structure of the circuit. The unit of each subset is also referred to as a gated circuit. In addition, arrangement coordinates are given to each clock element.

  The chip information receiving unit 101 receives chip data and stores it in the chip information storage unit 90. The chip information receiving unit 101 receives and receives data from various recording media or storage devices, or other devices via a network, for example, via an input / output interface (not shown) of the semiconductor integrated circuit design device 100. Alternatively, data input by a user may be accepted. The information in the chip information storage unit 90 does not necessarily have to be received and updated every time, and information already stored in the chip information storage unit 90 can be used.

  The mesh net generation unit 102 selects one lattice number from the mesh net lattice number candidates, and considers the input terminal positions of all clock elements stored in the chip information storage unit 90, and the selected mesh number. Generate a mesh net structure. Here, as the mesh wiring structure, it is conceivable to use a structure such as a grid-like wiring. As the mesh net lattice number candidates, for example, combinations of vertical and horizontal lattice numbers such as 2 × 2, 4 × 4, and 8 × 8 are given. The mesh net shape is generated by creating a vertical and horizontal grid that covers all clock elements, connecting the center of each grid to the center of the adjacent grid, and a mesh net drive buffer is placed at the center of each grid, and its output terminal Is connected to the mesh net.

  The mesh net delay calculation unit 103 calculates the delay of the mesh net generated by the mesh net generation unit 102.

  The mesh net drive structure generation unit 104 generates a buffer tree that drives the mesh net. Here, the buffer that directly drives the mesh net becomes the end buffer of the buffer tree, and the configuration and shape of the buffer tree that distributes the clock signal from the clock source to the end buffer set are determined. Here, the configuration and shape are determined so that the delay to each end buffer is the same, but for the generation of such a buffer tree, for example, a shape such as an H-tree type or a binary tree type should be used. Is possible.

  The mesh net drive structure delay calculation unit 105 calculates the delay from the clock source to the terminal buffer input terminal in the mesh net drive structure generated by the mesh net drive structure generation unit 104.

  The clock element hierarchy cluster generation unit 106 generates a cluster of clock elements in consideration of a set unit that can control the propagation of the clock signal with the same gating logic determined from the logic structure of the circuit and the arrangement distribution of the clock elements. . Specifically, a set of clock elements that can control the propagation of a clock signal with the same gating logic is divided, and a plurality of clock element clusters are generated so that clock elements with close arrangement coordinates are included in the same cluster. At this time, an upper limit is given to the number of clock elements included in one clock element cluster. By repeating this process, a hierarchical clustering structure is generated.

  The clock gating structure generation unit 107 selects the clock element hierarchy to be connected to the enable signal so that the delay constraint of the enable signal is satisfied for each clock element hierarchy cluster generated by the clock element hierarchy cluster generation unit 106. The gating cell that distributes the clock signal to the gated circuit to which the clock element included below the selected cluster hierarchy belongs is duplicated and inserted as a gating cell that drives the hierarchical cluster. In this process, for example, a method may be considered in which the hierarchy to be selected is started from the cluster of the lowest hierarchy and is raised to the upper hierarchy one by one until the delay constraint of the enable signal is satisfied.

  The local clock structure generation unit 108 connects the mesh net and each duplicated gating cell input terminal, and generates a connection structure from the gating cell to the clock element. Here, for example, for each gating cell, a buffer is arranged near a point on the mesh net structure closest to the input terminal of the gating cell, the buffer input terminal and the mesh net are connected, and the inserted buffer output terminal To the input terminal of the gating cell is generated, and each gating cell is connected to a clock element in a clock element cluster driven by the gating cell. The connection between the output terminal of the gating cell and the clock element can use an existing clock tree generation means, which is not related to the essence of the present embodiment, and therefore will not be described in detail.

  The local clock structure delay calculation unit 109 calculates the delay from the input terminal of the mesh net to each clock element for each local clock structure generated by the local clock structure generation means 108.

  The clock structure evaluation unit 110 calculates the clock skew considering the maximum clock delay and delay variation for the entire generated clock structure. If the delay time of the buffer tree structure that drives the mesh net is D1, the delay time that drives the mesh net itself is D2, and the delay time D3 that drives the gated circuit, D3 has a different value for each clock element. The minimum delay time of the structure is D1 + D2 + min {D3}, and the maximum delay time is D1 + D2 + max {D3}. min {D3} indicates the minimum value of D3, and max {D3} indicates the maximum value of D3. The main skew of this clock structure occurs in the delay time D3 for driving the gated circuit, because the mesh net can be suppressed to almost zero due to the effect of the short-circuit wiring. Since the gated circuit part is not short-circuited, the effect of delay variation cannot be mitigated. If the delay variation coefficient is k, the skew of this clock structure is max {D3} * (1 + k) -min {D3} * (1-k) Here, k is given as a decimal number between 0 and 1.

  The clock structure selection unit 111 generates a set of clock structure candidates by applying a series of clock structure generation units to all mesh net lattice number candidates, and selects a clock structure suitable for the purpose from the set. select.

  In the semiconductor integrated circuit design device 100 of the present embodiment, the CPU can realize each function of each unit by reading a program stored in the hard disk into the memory and executing it.

  The computer program of the present embodiment is a computer for realizing the semiconductor integrated circuit design apparatus 100. The computer program for realizing the semiconductor integrated circuit design apparatus 100 stores the chip information of the semiconductor integrated circuit including the clock gating structure, and sets the number of grids from one mesh net lattice number candidate. A step of generating a mesh net structure of the selected number of lattices in consideration of input terminal positions of all clock elements included in the chip information, a step of calculating a delay of the mesh net structure, A procedure for generating a mesh net driving buffer tree structure for driving the mesh net structure, a procedure for calculating a delay of the mesh net driving buffer tree structure, an arrangement distribution of clock elements included in the chip information, and a clock gating structure In consideration of clock elements included in different gated circuits A procedure for hierarchically generating a cluster of clock elements that includes a set of clock elements that are not mixed and arranged in the vicinity, and the delay constraint of the enable signal is satisfied for each of the clock element hierarchical clusters As described above, the clock element hierarchy to be connected to the enable signal is selected, the gating cell that distributes the clock signal to the gated circuit to which the clock element included in the selected cluster hierarchy or lower belongs is duplicated, and the hierarchical cluster is driven. A procedure for inserting as a gating cell, a procedure for connecting the mesh net and each duplicated gating cell input terminal to generate a connection structure from the gating cell to the clock element, and generation by the local clock structure generation means Mesh net input for each local clock structure The procedure for calculating the delay from the child to each clock element, the procedure for calculating the clock skew considering the clock maximum delay and delay variation for the entire generated clock structure, and all the mesh net lattice number candidates, It is described to generate a set of local clock structure candidates, from which a procedure for selecting a clock structure based on each calculated local clock structure delay and each calculated clock skew is executed. .

  The operation of the semiconductor integrated circuit design apparatus 100 of the present embodiment configured as described above will be described below. FIG. 2 is a flowchart showing an example of the processing procedure of the method for designing a semiconductor integrated circuit according to the embodiment of the present invention.

The method for designing the semiconductor integrated circuit of this embodiment is as follows:
Receive and store chip information of a semiconductor integrated circuit including a clock gating structure (step S101), select one of the mesh net lattice number candidates (step S102), and select all clock elements included in the chip information Generating a mesh net structure having the selected number of lattices in consideration of the input terminal position (step S103), calculating a delay of the mesh net structure (step S104), and driving the mesh net structure Generate a buffer tree structure (step S105), calculate the delay of the mesh net drive buffer tree structure (step S106), and take into account the clock element arrangement distribution and the clock gating structure included in the chip information The clock elements included in the gated circuit are not mixed, and the set of clock elements arranged in the vicinity is The clock element cluster is generated hierarchically (step S107), and for each clock element hierarchy cluster, first, the lowest hierarchy of the clock elements is selected as the connection target of the enable signal (step S108). ) When the enable signal is connected to the selected clock element hierarchy, it is checked whether the delay of the enable signal satisfies the delay constraint (step S109) .If the delay constraint of the enable signal is not satisfied, the clock to which the enable signal is to be connected is checked. The element level is increased by one level and selected again (step S110) .In step S109, it is repeated until whether the delay of the enable signal satisfies the delay constraint until the enable signal delay satisfies the delay constraint. As a result, the clock signal is sent to the gated circuit to which the clock elements included below the selected cluster hierarchy belong. Duplicating the distributed gating cell, inserting it as a gating cell for driving the hierarchical cluster (step S111), connecting the mesh net and each duplicated gating cell input terminal, and from the gating cell to the clock element (Step S112), for each local clock structure generated by the local clock structure generation means, calculate the delay from the input terminal of the mesh net to each clock element (step S113), the generated Calculate the clock skew considering the maximum clock delay and delay variation for the entire clock structure (step S114), and check whether the series of clock structure generation methods are applied to all mesh net lattice number candidates (Step S115), if there are still unapplied mesh net lattice numbers, Repeat steps S102 through S114, and select a clock structure from the set of finally obtained clock structure candidates based on each calculated local clock structure delay and each calculated clock skew. (Step S116).

  Hereinafter, this will be specifically described with reference to FIGS.

  First, the chip information receiving unit 101 receives input of information (chip data) related to a gate level netlist including clock elements of a semiconductor integrated circuit chip to be designed and stores it in the chip information storage unit 90 (step S101). . Here, the set of flip-flops is divided into subsets that can control the propagation of the clock signal with the same gating logic from the logic structure of the circuit. Each subset is also referred to as a gated circuit. The clock distribution circuit included in the input data has a clock gating structure as shown in FIG. That is, the clock signal is distributed from the clock source (16-01) to the clock element (16-03) via the gating cell (18-04), and the gating cell receives the clock signal and the gating signal (18-01). , 18-02) is used to control clock signal propagation. Here, clock elements below the same gating signal are collectively referred to as a single gated circuit. Further, it is assumed that arrangement coordinates are given to each clock element.

  Next, as shown in FIG. 5, the mesh net generation unit 102 selects one lattice number from the mesh net lattice number candidates (step S102), and all the clock elements stored in the chip information storage unit 90 are selected. Considering the input terminal position, a mesh net structure (17-02) having the selected number of lattices is generated (step S103). Here, as the mesh wiring structure, it is conceivable to use a structure such as a grid-like wiring. As the mesh net lattice number candidates, for example, combinations of vertical and horizontal lattice numbers such as 2 × 2, 4 × 4, and 8 × 8 are given. The mesh net shape is generated by creating a vertical and horizontal grid that covers all clock elements and connecting the center of each grid to the center of the adjacent grid, and a mesh net drive buffer (17-03) is placed at the center of each grid. The output terminal is connected to the mesh net. FIG. 5 shows an example of the number of 4 × 4 lattice points in (a) and the number of 2 × 2 lattice points in (b).

  Next, the mesh net delay calculation unit 103 receives the mesh net structure generated by the mesh net generation unit 102 from the chip information storage unit 90, and calculates the delay of the mesh net (step S104). A method for calculating the delay of a net having a plurality of drive buffers with high accuracy in a short time is not known, and circuit simulation such as spice is generally used. However, since the purpose here is to search for the best clock structure, it is not practical to perform circuit simulation for each structure. In order to solve this problem, here, for each combination of the number of mesh net drive buffers and the mesh net capacity, a delay calculated by circuit simulation is held in advance and used. FIG. 6 shows an example of a table that holds the delay (06-01) of the mesh net itself for each combination of the number of mesh net drive buffers and the mesh net capacity used to calculate the delay of the mesh net structure.

  The mesh net drive structure generation unit 104 generates a buffer tree for driving the mesh net (step S105). Here, the buffer that directly drives the mesh net becomes the end buffer of the buffer tree, and the buffer tree that distributes the clock signal (07-01) from the clock source (16-01) to these end buffer sets (17-03) Determine configuration and shape. Here, the configuration and shape (17-01) including the relay buffer (16-04) on the tree are determined so that the delay to each end buffer (the delay of the path of the clock signal 07-01) is the same. However, for generation of such a buffer tree, for example, a shape such as an H-tree type or a binary tree type can be used. FIG. 7 shows an example of a mesh net driving buffer tree structure. FIG. 7A shows the case where the number of lattices is 4 × 4, and FIG. 7B shows the case where the number of lattices is 2 × 2. Here, for the sake of simplicity, an H-tree structure is shown as an example of a completely symmetric clock distribution signal layout having 16 or 4 terminal buffers, but the present invention is not limited to this.

  Next, the mesh net drive structure delay calculation unit 105 performs a delay from the clock source to the terminal buffer input terminal (the path of the clock signal 07-01 in the mesh net drive buffer tree structure generated by the mesh net drive structure generation unit 104. (Delay) is calculated (step S106). FIG. 7 shows a path on the buffer tree to be subjected to delay calculation.

  Next, the clock element hierarchy cluster generation unit 106 can control the propagation of the clock signal with the same gating logic stored in the chip information storage unit 90 and determined from the logic structure of the circuit, and the distribution distribution of the clock elements In consideration of the above, a cluster of clock elements is generated (step S107). Specifically, a set of clock elements that can control the propagation of a clock signal with the same gating logic is divided, and a plurality of clock element clusters are generated so that clock elements with close arrangement coordinates are included in the same cluster. At this time, an upper limit is given to the number of clock elements included in one clock element cluster. By repeating this process, a hierarchical clustering structure is generated. FIG. 8 shows an example of hierarchical clustering of clock elements (16-03) connected to the mesh structure (17-02) or lower. First, at hierarchical level 1, eight clusters (08-01) having the number of clock elements of 2, 3, 3, 2, 2, 3, 3, 2 are created. Next, referring to the center of gravity of each cluster, level 2 clustering is performed, and four clusters (08-02) having the number of clock elements of 5, 5, 8, and 2 are created. Next, level 3 clustering is performed to create two clusters (08-03) with 10 and 10 clock elements, respectively. FIG. 9 is a diagram showing the hierarchical clustering of FIG. 8 from the viewpoint of layout. FIG. 9A shows a state in which level 1 clustering (08-01) has been completed for the clock element 16-03, and FIG. 9B shows levels 2 (08-02) and 3 clustering. Each state after (08-03) is shown.

  Next, the clock gating structure generation unit 107 applies the enable signal connection target clock element hierarchy to each clock element hierarchy cluster generated by the clock element hierarchy cluster generation unit 106 so as to satisfy the delay constraint of the enable signal. And the gating cell that distributes the clock signal to the gated circuit to which the clock element included in the selected cluster hierarchy or lower belongs is copied and inserted as a gating cell that drives the hierarchical cluster. More specifically, first, the lowest hierarchy cluster of the clock elements is selected as the connection target of the enable signal (step S108), and when the enable signal is connected to the selected clock element hierarchy, the delay of the enable signal is a delay constraint. If the delay constraint of the enable signal is not satisfied, the clock element layer to which the enable signal is to be connected is increased by one layer (step S110), and the enable signal is enabled again in step S109. Checking whether the delay of the signal satisfies the delay constraint is repeated until the delay of the enable signal satisfies the delay constraint. For example, the clock gating structure of FIG. 10 is generated with the lowest layer cluster of FIGS. 8 and 9 as the enable signal connection target (04-04 indicates the enable signal). On the other hand, it is confirmed whether or not the delay of the enable signal (04-04) shown in FIG. 10 satisfies the upper limit constraint. FIG. 11 is a diagram showing the structure of FIG. 10 from the viewpoint of layout, and 16-04 indicates a relay buffer on the enable signal distribution tree. When the enable signal delay (the delay from the source of the enable signal to the gating cell 18-04) in FIG. 10 is not less than the upper limit constraint, the gating structure in FIG. . As in the case of FIG. 10, it is checked whether the delay of the enable signal (04-04) connected to the root of each cluster is below the upper limit constraint. FIG. 13 is a diagram illustrating the gating structure of FIG. 12 from a layout viewpoint. Like FIG. 11, 16-04 indicates a relay buffer on the enable signal distribution tree. As a result, the gating cell that distributes the clock signal to the gated circuit to which the clock element included below the selected cluster hierarchy belongs is duplicated and inserted as a gating cell (18-04) that drives the hierarchical cluster ( Step S111).

  Next, the local clock structure generation unit 108 connects the mesh net and the duplicated gating cell input terminals, and generates a connection structure from the gating cell to the clock element (step S112). Here, for example, for each gating cell, a buffer is arranged near a point on the mesh net structure closest to the input terminal of the gating cell, the buffer input terminal and the mesh net are connected, and the inserted buffer output terminal To the input terminal of the gating cell is generated, and each gating cell is connected to a clock element in a clock element cluster driven by the gating cell. The connection between the output terminal of the gating cell and the clock element can use an existing clock tree generation means, which is not related to the essence of the present embodiment, and therefore will not be described in detail. FIG. 14 shows a gating clock structure generated from the enable signal connection hierarchy selected in FIG. 12 and FIG. FIG. 15 is a diagram showing the gating clock structure of FIG. 14 from the viewpoint of layout. A relay buffer 16-04 is inserted immediately after the mesh structure 17-04 to connect to the gating cell 18-04. The clock signal distribution to the clock element 16-03 is performed from the gating cell. The buffer drive capability of the relay buffer 16-04 and the gating cell 18-04 is such that the delay 04-03 to each clock element after the mesh structure 17-02 is the same for all clock elements and is as small as possible. Adjusted.

  Next, the local clock structure delay calculation unit 109 calculates the delay from the input terminal of the mesh net to each clock element for each local clock structure generated by the local clock structure generation means (step S113). Specifically, the delay 04-03 of each local structure shown in FIG. 14 is calculated.

  Next, the clock structure evaluation unit 110 calculates a clock skew considering the maximum clock delay and delay variation for the entire generated clock structure (step S114). If the delay time of the buffer tree structure that drives the mesh net is D1, the delay time that drives the mesh net itself is D2, and the delay time D3 that drives the gated circuit, D3 has a different value for each clock element. The minimum delay time of the structure is D1 + D2 + min {D3}, and the maximum delay time is D1 + D2 + max {D3}. The main skew of this clock structure occurs in the delay time D3 for driving the gated circuit, because the mesh net can be suppressed to almost zero due to the effect of the short-circuit wiring. Since the gated circuit part is not short-circuited, the effect of delay variation cannot be mitigated. If the delay variation coefficient is k, the skew of this clock structure is max {D3} * (1 + k) -min {D3} * (1-k) Here, k is given as a decimal number between 0 and 1.

  Next, the clock structure selection unit 111 confirms whether or not the series of clock structure generation method groups has been applied to all mesh net lattice number candidates (step S115), and the number of mesh net lattices that have not yet been applied. Is present again, the processing from step S102 to S114 is repeated again, and a clock structure suitable for the purpose is selected from the finally obtained set of clock structure candidates (step S116). Here, the clock structure selection means is that clock maximum delay D1 + D2 + max {D3} is within the upper limit constraint, clock skew max {D3} * (1 + k)-min {D3} * (1-k) Or clock skew max {D3} * (1 + k)-min {D3} * (1-k) is within upper bounds and clock maximum delay D1 + D2 + max {D3} Select the clock structure that is the smallest.

  In the flow described above, the processes from step S101 to step S116 are sequentially processed in series. However, when steps S101 to S106 are the first processing, steps S107 to S111 are the second processing, and steps S112 to S113 are the third processing, the first processing and the second processing are performed. May be processed in parallel, and the second process may be performed prior to the first process.

  As described above, according to the semiconductor integrated circuit design apparatus and design method of the present embodiment, the skew distribution including the manufacturing variation is reduced with respect to the clock distribution circuit including the gating structure effective for reducing the power consumption. The best clock structure that connects all clock elements to the same mesh structure or less, considering the delay and skew of the entire clock structure and the enable signal delay without dividing the mesh structure that is effective for reduction Can be generated. As a result, the power consumption, the delay, and the delay skew of the clock distribution circuit can be reduced.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

A part or all of the above embodiment can be described as in the following supplementary notes, but is not limited to the following configuration.
(Appendix 1)
A storage device for storing chip information of a semiconductor integrated circuit including a clock gating structure;
Selecting one lattice number from mesh net lattice number candidates, and considering the input terminal positions of all clock elements included in the chip information, mesh net generating means for generating a mesh net of the selected lattice number;
Mesh net delay calculating means for calculating a delay of the mesh net generated by the mesh net generating means;
Mesh net driving structure generating means for generating a buffer tree for driving the mesh net;
A mesh net driving structure delay calculating means for calculating a delay of the mesh net driving structure generated by the mesh net driving structure generating means;
In consideration of the clock element arrangement distribution and clock gating structure included in the chip information, the clock elements included in different gated circuits are not mixed, and a set of clock elements arranged in the vicinity is included. Clock element hierarchical cluster generating means for hierarchically generating a cluster of various clock elements;
For each clock element hierarchy cluster generated by the clock element hierarchy cluster generation means, a clock element hierarchy to be connected to the enable signal is selected so as to satisfy the delay constraint of the enable signal, and is included below the selected cluster hierarchy. A clock gating structure generating means for duplicating a gating cell that distributes a clock signal to a gated circuit to which the clock element belongs, and inserting it as a gating cell for driving the hierarchical cluster;
A local clock structure generating means for connecting the mesh net and each duplicated gating cell input terminal and generating a connection structure from the gating cell to the clock element;
For each local clock structure generated by the local clock structure generating means, calculating the delay from the input terminal of the mesh net to each clock element, local clock structure delay calculating means,
Clock structure evaluation means for calculating a clock skew considering the clock maximum delay and delay variation for the entire generated clock structure;
Clock structure selection means for selecting a clock structure based on each calculated local clock structure delay and each calculated clock skew from a set of local clock structure candidates performed for all mesh net lattice number candidates When,
A device for designing a semiconductor integrated circuit.
(Appendix 2)
In the semiconductor integrated circuit design device according to appendix 1,
The clock gating structure generating means includes
Means for selecting the lowest hierarchy cluster of clock elements as a connection target of the enable signal, means for checking whether the delay of the enable signal satisfies the delay constraint when the enable signal is connected to the selected clock element hierarchy, and enable If the signal delay constraint is not satisfied, the clock element layer to which the enable signal is to be connected is increased by one layer, the selection is performed again, and a check is performed again to check whether the delay of the enable signal satisfies the delay constraint. And a means for repeating until the delay of the enable signal satisfies the delay constraint.
(Appendix 3)
In the semiconductor integrated circuit design device according to appendix 1,
The mesh net delay calculating means includes a table holding delays calculated by circuit simulation in advance as a library for each combination of the number of mesh net driving buffers and mesh net capacity, and uses the library for delay calculation. A semiconductor integrated circuit design device.
(Appendix 4)
Storing chip information of a semiconductor integrated circuit including a clock gating structure;
One mesh number is selected from the mesh net lattice number candidates, and the mesh net structure of the selected lattice number is generated in consideration of the input terminal positions of all clock elements included in the chip information. Calculate the delay of
Generating a mesh net driving buffer tree structure for driving the mesh net structure, calculating a delay of the mesh net driving buffer tree structure;
In consideration of the clock element arrangement distribution and clock gating structure included in the chip information, the clock elements included in different gated circuits are not mixed, and a set of clock elements arranged in the vicinity is included. Hierarchical cluster of clock elements,
For each clock element hierarchy cluster, select a clock element hierarchy to be connected to the enable signal so as to satisfy the delay constraint of the enable signal, and the clock signal to the gated circuit to which the clock element included below the selected cluster hierarchy belongs Is copied as a gating cell for driving the hierarchical cluster,
The mesh net and the duplicated gating cell input terminals are connected to generate a connection structure from the gating cell to the clock element, and for each generated local clock structure, from the mesh net input terminal to each clock element. Calculate the delay,
For the entire generated clock structure, calculate the clock skew considering the clock maximum delay and delay variation,
A semiconductor that generates a set of local clock structure candidates for all mesh net lattice number candidates, and selects a clock structure based on the calculated local clock structure delays and calculated clock skews. Integrated circuit design method.
(Appendix 5)
In the method for designing a semiconductor integrated circuit according to appendix 4,
When generating the clock gating structure, first, select the lowest hierarchy cluster of clock elements as the connection target of the enable signal, and when the enable signal is connected to the selected clock element hierarchy, does the delay of the enable signal satisfy the delay constraint? If the delay constraint of the enable signal is not satisfied, the clock element layer to which the enable signal is to be connected is increased by one layer and selected again, and it is checked again whether the delay of the enable signal satisfies the delay constraint and these processes are performed. Is repeated until the delay of the enable signal satisfies the delay constraint.
(Appendix 6)
In the mesh net delay calculation of the semiconductor integrated circuit design method described in appendix 4, for each combination of the number of mesh net drive buffers and the mesh net capacity, a table holding the delay calculated by circuit simulation is prepared in advance as a library. A method for designing a semiconductor integrated circuit used for delay calculation.
(Appendix 7)
To a computer functioning as a semiconductor integrated circuit design device,
A procedure for storing chip information of a semiconductor integrated circuit including a clock gating structure;
Selecting one lattice number from mesh net lattice number candidates, taking into account the input terminal positions of all clock elements included in the chip information, and generating a mesh net structure of the selected lattice number;
Calculating a delay of the mesh net structure;
Generating a mesh net driving buffer tree structure for driving the mesh net structure;
Calculating a delay of the mesh net driven buffer tree structure;
In consideration of the clock element arrangement distribution and clock gating structure included in the chip information, the clock elements included in different gated circuits are not mixed, and a set of clock elements arranged in the vicinity is included. To generate a cluster of clock elements hierarchically,
For each clock element hierarchy cluster, select a clock element hierarchy to be connected to the enable signal so as to satisfy the delay constraint of the enable signal, and the clock signal to the gated circuit to which the clock element included below the selected cluster hierarchy belongs Duplicating the gating cell that distributes and inserting as a gating cell that drives the hierarchical cluster;
Connecting the mesh net and each duplicated gating cell input terminal, and generating a connection structure from the gating cell to the clock element;
For each local clock structure generated by the local clock structure generating means, a procedure for calculating a delay from the input terminal of the mesh net to each clock element;
Calculating the clock skew considering the clock maximum delay and delay variation for the entire generated clock structure;
A procedure for generating a set of local clock structure candidates for all mesh net lattice number candidates, and selecting a clock structure based on the calculated local clock structure delays and calculated clock skews When,
A computer program that executes
(Appendix 8)
In the computer program according to appendix 7,
The clock gating structure generation procedure includes:
A procedure for selecting the lowest hierarchy cluster of clock elements as the connection target of the enable signal;
A procedure for checking whether the delay of the enable signal satisfies the delay constraint when the enable signal is connected to the selected clock element hierarchy,
If the delay constraint for the enable signal is not satisfied, the clock element layer to be connected to the enable signal is increased by one layer and reselected, and the procedure for checking again whether the delay of the enable signal satisfies the delay constraint,
A computer program comprising: repeating these procedures until the delay of the enable signal satisfies a delay constraint.
(Appendix 9)
In the computer program according to appendix 7,
The mesh net delay calculation procedure includes a procedure in which a table holding delays calculated by circuit simulation is prepared in advance as a library for each combination of the number of mesh net drive buffers and mesh net capacity, and used for delay calculation. A computer program characterized by the above.

  The present invention is applied to a design method, a design apparatus, and a computer program for arranging and wiring a semiconductor integrated circuit including a clock distribution circuit having a clock gating structure and a mesh structure.

04-01 Delay time of mesh net drive buffer tree structure
04-02 Delay time of mesh net itself
04-03 Delay time of local clock structure
04-04 Delay time of enable signal
06-01 Delay time when driving the corresponding mesh net capacity with the corresponding number of drive buffers
07-01 Delay calculation target path of mesh net drive buffer tree structure
08-01 Clock element cluster level 1
08-02 Clock element cluster level 2
08-03 Clock element cluster level 3
16-01 Clock source
16-02 Wiring route
16-03 Clock element
16-04 Relay buffer
17-01 Global structure (H-tree)
17-02 Mesh structure
17-03 Global structure end buffer
17-04 Global Structure / Mesh Connection Wiring
18-01 Gating signal 1
18-02 Gating signal 2
18-03 gated circuit
18-04 Gating cell
90 Chip information storage
100 Semiconductor integrated circuit design equipment
101 Chip information reception
102 Mesh net generator
103 Mesh net delay calculator
104 Mesh net drive structure generator
105 Mesh net drive structure delay calculator
106 Clock element hierarchy cluster generator
107 Clock gating structure generator
108 Local clock structure generator
109 Local clock structure delay calculator
110 Clock structure evaluation section
111 Clock structure selector

Claims (9)

A storage device for storing chip information of a semiconductor integrated circuit including a clock gating structure;
Selecting one lattice number from mesh net lattice number candidates, and considering the input terminal positions of all clock elements included in the chip information, mesh net generating means for generating a mesh net of the selected lattice number;
Mesh net delay calculating means for calculating a delay of the mesh net generated by the mesh net generating means;
Mesh net driving structure generating means for generating a buffer tree for driving the mesh net;
A mesh net driving structure delay calculating means for calculating a delay of the mesh net driving structure generated by the mesh net driving structure generating means;
In consideration of the clock element arrangement distribution and clock gating structure included in the chip information, the clock elements included in different gated circuits are not mixed, and a set of clock elements arranged in the vicinity is included. Clock element hierarchical cluster generating means for hierarchically generating a cluster of various clock elements;
For each clock element hierarchy cluster generated by the clock element hierarchy cluster generation means, a clock element hierarchy to be connected to the enable signal is selected so as to satisfy the delay constraint of the enable signal, and is included below the selected cluster hierarchy. A clock gating structure generating means for duplicating a gating cell that distributes a clock signal to a gated circuit to which the clock element belongs, and inserting it as a gating cell for driving the hierarchical cluster;
A local clock structure generating means for connecting the mesh net and each duplicated gating cell input terminal and generating a connection structure from the gating cell to the clock element;
For each local clock structure generated by the local clock structure generating means, calculating the delay from the input terminal of the mesh net to each clock element, local clock structure delay calculating means,
Clock structure evaluation means for calculating a clock skew considering the clock maximum delay and delay variation for the entire generated clock structure;
Clock structure selection means for selecting a clock structure based on each calculated local clock structure delay and each calculated clock skew from a set of local clock structure candidates performed for all mesh net lattice number candidates When,
A device for designing a semiconductor integrated circuit. In the design apparatus of the semiconductor integrated circuit of Claim 1,
The clock gating structure generating means includes
Means for selecting the lowest hierarchy cluster of clock elements as a connection target of the enable signal, means for checking whether the delay of the enable signal satisfies the delay constraint when the enable signal is connected to the selected clock element hierarchy, and enable If the signal delay constraint is not satisfied, the clock element layer to which the enable signal is to be connected is increased by one layer, the selection is performed again, and a check is performed again to check whether the delay of the enable signal satisfies the delay constraint. And a means for repeating until the delay of the enable signal satisfies the delay constraint. In the design apparatus of the semiconductor integrated circuit of Claim 1,
The mesh net delay calculating means includes a table holding delays calculated by circuit simulation in advance as a library for each combination of the number of mesh net driving buffers and mesh net capacity, and uses the library for delay calculation. A semiconductor integrated circuit design device. Storing chip information of a semiconductor integrated circuit including a clock gating structure;
One mesh number is selected from the mesh net lattice number candidates, and the mesh net structure of the selected lattice number is generated in consideration of the input terminal positions of all clock elements included in the chip information. Calculate the delay of
Generating a mesh net driving buffer tree structure for driving the mesh net structure, calculating a delay of the mesh net driving buffer tree structure;
In consideration of the clock element arrangement distribution and clock gating structure included in the chip information, the clock elements included in different gated circuits are not mixed, and a set of clock elements arranged in the vicinity is included. Hierarchical cluster of clock elements,
For each clock element hierarchy cluster, select a clock element hierarchy to be connected to the enable signal so as to satisfy the delay constraint of the enable signal, and the clock signal to the gated circuit to which the clock element included below the selected cluster hierarchy belongs Is copied as a gating cell for driving the hierarchical cluster,
The mesh net and the duplicated gating cell input terminals are connected to generate a connection structure from the gating cell to the clock element, and for each generated local clock structure, from the mesh net input terminal to each clock element. Calculate the delay,
For the entire generated clock structure, calculate the clock skew considering the clock maximum delay and delay variation,
A semiconductor that generates a set of local clock structure candidates for all mesh net lattice number candidates, and selects a clock structure based on the calculated local clock structure delays and calculated clock skews. Integrated circuit design method. The method of designing a semiconductor integrated circuit according to claim 4,
When generating the clock gating structure, first, select the lowest hierarchy cluster of clock elements as the connection target of the enable signal, and when the enable signal is connected to the selected clock element hierarchy, does the delay of the enable signal satisfy the delay constraint? If the delay constraint of the enable signal is not satisfied, the clock element layer to which the enable signal is to be connected is increased by one layer and selected again, and it is checked again whether the delay of the enable signal satisfies the delay constraint and these processes are performed. Is repeated until the delay of the enable signal satisfies the delay constraint.   5. In the mesh net delay calculation of the semiconductor integrated circuit design method according to claim 4, for each combination of the number of mesh net drive buffers and the mesh net capacity, a table holding delays calculated by circuit simulation is prepared in advance as a library. A method for designing a semiconductor integrated circuit used for delay calculation. To a computer functioning as a semiconductor integrated circuit design device,
A procedure for storing chip information of a semiconductor integrated circuit including a clock gating structure;
Selecting one lattice number from mesh net lattice number candidates, taking into account the input terminal positions of all clock elements included in the chip information, and generating a mesh net structure of the selected lattice number;
Calculating a delay of the mesh net structure;
Generating a mesh net driving buffer tree structure for driving the mesh net structure;
Calculating a delay of the mesh net driven buffer tree structure;
In consideration of the clock element arrangement distribution and clock gating structure included in the chip information, the clock elements included in different gated circuits are not mixed, and a set of clock elements arranged in the vicinity is included. To generate a cluster of clock elements hierarchically,
For each clock element hierarchy cluster, select a clock element hierarchy to be connected to the enable signal so as to satisfy the delay constraint of the enable signal, and the clock signal to the gated circuit to which the clock element included below the selected cluster hierarchy belongs Duplicating the gating cell that distributes and inserting as a gating cell that drives the hierarchical cluster;
Connecting the mesh net and each duplicated gating cell input terminal, and generating a connection structure from the gating cell to the clock element;
For each local clock structure generated by the local clock structure generating means, a procedure for calculating a delay from the input terminal of the mesh net to each clock element;
Calculating the clock skew considering the clock maximum delay and delay variation for the entire generated clock structure;
A procedure for generating a set of local clock structure candidates for all mesh net lattice number candidates, and selecting a clock structure based on the calculated local clock structure delays and calculated clock skews When,
A computer program that executes The computer program according to claim 7, wherein
The clock gating structure generation procedure includes:
A procedure for selecting the lowest hierarchy cluster of clock elements as the connection target of the enable signal;
A procedure for checking whether the delay of the enable signal satisfies the delay constraint when the enable signal is connected to the selected clock element hierarchy,
If the delay constraint for the enable signal is not satisfied, the clock element layer to be connected to the enable signal is increased by one layer and reselected, and the procedure for checking again whether the delay of the enable signal satisfies the delay constraint,
A computer program comprising: repeating these procedures until the delay of the enable signal satisfies a delay constraint. The computer program according to claim 7, wherein
The mesh net delay calculation procedure includes a procedure in which a table holding delays calculated by circuit simulation is prepared in advance as a library for each combination of the number of mesh net drive buffers and mesh net capacity, and used for delay calculation. A computer program characterized by the above.

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