JP2011254024A - Semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

A semiconductor integrated circuit device having a structure in which a memory and a connection portion between the memory and a peripheral circuit portion can be stably formed and the memory can be stably operated.
A memory layer made of a resistance change material and having information recorded by a resistance value, and a memory formed in common with a plurality of memory cells and formed above a semiconductor substrate. A circuit element including a control circuit is formed on the semiconductor substrate 1, and is electrically connected to the circuit elements of the peripheral circuit unit 31 and the peripheral circuit unit 31, and is formed in the insulating layer 12 on the semiconductor substrate 1. Each of the layers 21 and 22 constituting the memory 20 including the plug layer 11 extends to the plug layer 11 and is electrically connected to the plug layer 11 so that the metal element diffuses. Thus, a semiconductor integrated circuit device having a resistance value lower than that of other portions is configured.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit device including a memory (memory device) including a resistance change type storage element and a control circuit such as a transistor, and a method for manufacturing the semiconductor integrated circuit device.

Conventionally, resistance variable nonvolatile memory elements have been proposed.
The variable resistance nonvolatile memory element uses a material whose resistance value varies (hereinafter referred to as a resistance variable material) to form a memory layer that stores information according to the resistance value.

  In a memory (storage device) composed of such storage elements, in order to reduce the size of the memory and increase the storage capacity, the size of the memory cells constituting the memory is reduced and more memory cells are integrated. It is requested to do.

Conventionally, it has been proposed to separate the resistance change material of the memory layer for each memory cell by etching or the like.
However, in this configuration, as the size of the memory cell becomes smaller, it becomes difficult to form each memory cell with high accuracy due to variations in etching and the like.

Therefore, instead of separating each memory cell, a configuration is proposed in which a memory layer is formed in common by a plurality of memory cells, and electrodes and the like electrically connected to the memory layer are separated for each memory cell. . For example, the memory layer is formed in common for memory cells in the same column or the same row, or formed in common for memory cells in a certain area or all memory cells.
Specifically, the lower electrode connected under the memory layer is formed separately for each memory cell.
Then, if a storage layer is formed on a via wiring connected to a memory cell selection transistor, a portion of each storage layer on each via wiring can be a memory cell.
With this configuration, since the connection between the selection transistor and the memory can be made only by via wiring, the area occupied by the memory is reduced in the semiconductor integrated circuit device including the memory and the peripheral circuit portion. be able to.

By the way, in order to record information on a specific memory cell among a large number of formed memory cells, a configuration for selecting the specific memory cell is required.
However, if a memory cell is selected using only the selection transistor, two types of vertical and horizontal wirings for selecting the memory cell are required between the storage element and the selection transistor. Since there are two types of wiring, the via wiring connecting the selection transistor and the memory layer needs to be formed at an interval, which hinders the reduction in the size of the memory cell.

  Therefore, if the upper electrode or the memory layer and the upper electrode are patterned for each column or row of the memory cell and also used as a wiring (bit line or the like), the wiring for selecting the memory cell is reduced to one type. Thus, it is possible to shorten the interval between the via wirings in a portion where there is no wiring.

On the other hand, in order to drive a memory having a large number of memory cells, it is necessary to electrically connect the peripheral circuit portion including the control circuit and the memory.
For example, the upper electrode formed on the memory layer and the peripheral circuit portion are electrically connected.
Then, a configuration has been proposed in which a via wiring is formed on the upper electrode, and the peripheral circuit portion and the memory are electrically connected via an upper wiring connected via the via wiring ( For example, see Patent Document 1).

However, in the case of manufacturing this configuration, after forming the resistance change material, the via wiring is formed above the resistance change material, and therefore the resistance change material may be damaged by the heat when forming the via wiring ( For example, see Patent Document 2).
Further, in order to reduce the size of the memory cell, patterning for processing into a planar pattern of wiring is also performed at a fine pitch. And it is necessary to form the via wiring formed on the upper electrode at a fine pitch.
However, since the via wiring is formed in the upper layer with respect to the memory layer formed on the transistor via the via wiring, the via wiring is formed at a considerably high position when viewed from the semiconductor substrate on which the transistor is formed. become. For this reason, it is difficult to accurately form a via wiring having a fine pattern, and the via wiring cannot be formed at the same fine pitch as that of the upper electrode, or a deviation occurs between the upper electrode and the via wiring. There is a concern to do.

On the other hand, in FIG. 8 of Patent Document 2, the upper electrode is formed so as to extend to the outside of the stacked film of the memory, and this extended portion is formed as a via connected to the transistor in the peripheral circuit portion. A configuration connected to wiring has been proposed.
In Patent Document 3, the upper electrode is formed so as to extend to the outside of the stacked film of the memory, and this extended portion is used as a part of the via wiring connected to the transistor in the peripheral circuit portion. Has been proposed.
With these configurations, the via wiring for connecting the peripheral circuit portion and the memory is formed before the storage layer and below the storage layer, so that damage to the storage layer is avoided, and the via wiring is formed. It can be formed with a fine pitch.

JP 2004-349504 A (FIG. 1) JP 2007-19305 A JP 2009-260060 A

However, in the configuration disclosed in FIG. 8 of Patent Document 2, the upper electrode is formed along the upper surface and the side wall surface of the patterned memory laminated film, and the upper electrode is formed on the lower via wiring than the memory laminated film. The electrodes are connected.
Therefore, the upper electrode is formed including a step due to the laminated film of the memory, and there is a concern that the film of the upper electrode may be cut off by this step.
In the configuration disclosed in Patent Document 3, the upper electrode is formed along the side wall surface and the bottom surface of the via hole.
Therefore, the upper electrode is formed including a step at the via hole portion, and when the via hole is reduced by reducing the size of the memory cell, the upper electrode film can be stably formed in the fine via hole. It becomes difficult.

On the other hand, for example, a configuration in which the memory layer and the upper electrode are extended and formed on the via wiring connected to the transistor in the peripheral circuit portion is conceivable.
In this case, a portion of the storage layer on the via wiring connected to the transistor in the peripheral circuit portion serves as a current path, and the upper electrode and the via wiring are electrically connected through this portion.
If comprised in this way, since a level | step difference will not arise in an upper electrode, the film | membrane of an upper electrode can be formed stably.

However, with this configuration, the resistance value of the memory layer in the portion serving as the current path changes depending on the voltage and current.
If the memory layer in this portion changes to a high resistance state, there arises a problem that it becomes impossible to exchange signals between the memory cell and the control circuit in the peripheral circuit section.

  In order to solve the above problems, in the present invention, even when the cell size is reduced, the memory and the connection portion between the memory and the peripheral circuit portion can be stably formed, and the memory can be operated stably. The present invention provides a semiconductor integrated circuit device having such a configuration. The present invention also provides a method for manufacturing this semiconductor integrated circuit device.

The semiconductor integrated circuit device of the present invention includes a memory and a control circuit that controls the memory.
The semiconductor substrate is made of a variable resistance material whose resistance value changes, and includes a storage layer in which information is recorded by the resistance value. The storage layer is shared by a plurality of memory cells. And a memory formed above the semiconductor substrate.
In addition, a peripheral circuit portion in which a circuit element including a control circuit is formed on a semiconductor substrate, and a plug layer electrically connected to the circuit element in the peripheral circuit portion and formed in an insulating layer on the semiconductor substrate; including.
Further, each layer constituting the memory including the storage layer is formed extending to the plug layer and is electrically connected to the plug layer, and the metal element is present at the connection portion near the plug layer. The structure is diffused and the resistance value is lower than other portions.

The method for manufacturing a semiconductor integrated circuit device according to the present invention is a method for manufacturing a semiconductor integrated circuit device including a memory and a control circuit.
Then, a step of forming a circuit element of the peripheral circuit portion including the control circuit on the semiconductor substrate, and a plug layer electrically connected to the circuit element in the insulating layer after forming the insulating layer so as to cover the circuit element Forming the step.
A step of forming each layer constituting the memory, including a storage layer made of a resistance change material whose resistance value changes and information is recorded by the resistance value, extending to the plug layer; Forming a layer containing a metal element thereabove.
Furthermore, the metal element of the layer containing the metal element is subjected to a patterning process and heat treatment so that the layer containing the metal element remains only in the connection portion that electrically connects the plug layer and each layer constituting the memory. And diffusing to each layer constituting the memory.

According to the configuration of the semiconductor integrated circuit device of the present invention described above, each layer constituting the memory including the storage layer is formed extending to the plug layer and electrically connected to the plug layer. Thereby, each layer (memory layer, upper electrode, etc.) constituting the memory has no step, and each layer constituting the memory can be electrically connected to the plug layer without causing a problem such as disconnection.
In each layer constituting the memory cell, the metal element is diffused in the connection portion near the plug layer, and the resistance value is lower than that of the other portions. As a result, the metal element diffuses in the connection portion of the memory layer, and the resistance value is lower than that of the other portions. Therefore, the memory layer of the connection portion changes to a high resistance state, and signals are transferred to and from the peripheral circuit portion. The signal can be exchanged stably without interfering with the signal.

According to the above-described method for manufacturing a semiconductor integrated circuit device of the present invention, each layer constituting the memory including the storage layer is formed so as to extend onto the plug layer. Thus, no step is formed in each layer (memory layer, upper electrode, etc.) constituting the memory, and each layer constituting the memory is electrically connected to the plug layer without causing a problem such as disconnection. be able to.
In addition, a layer containing a metal element is formed above the memory layer, and this layer is patterned so as to remain only in a connection portion that electrically connects the plug layer and each layer of the memory. Diffuse in each layer. As a result, the metal element diffuses in the connection portion of the memory layer and the resistance value becomes lower than that of the other portions, so that the memory layer of the connection portion changes to a high resistance state and prevents transmission and reception of signals with the peripheral circuit portion. It becomes the composition which does not have.

According to the above-described present invention, each layer constituting the memory can be electrically connected to the plug layer without causing a problem such as disconnection. Therefore, each layer constituting the memory, the memory, the peripheral circuit unit, Can be formed stably.
In addition, according to the present invention, since the memory layer of the connection portion is changed to a high resistance state and does not hinder the transmission / reception of signals to / from the peripheral circuit unit, stable signal transmission / reception between the memory and the peripheral circuit unit is achieved. Therefore, the memory can be operated stably.
Therefore, according to the present invention, even when the cell size is reduced, the semiconductor integrated circuit device can stably form the memory and the connection portion between the memory and the peripheral circuit portion and can stably operate the memory. Can be realized.

1 is a schematic configuration diagram (cross-sectional view) of a first embodiment of a semiconductor integrated circuit device of the present invention. FIG. 2 is a schematic enlarged perspective view in which a main part of the semiconductor integrated circuit device of FIG. 1 is extracted. FIGS. 3A and 3B are manufacturing process diagrams showing a manufacturing method of the semiconductor integrated circuit device shown in FIGS. 1 and 2; FIGS. C and D are manufacturing process diagrams showing a manufacturing method of the semiconductor integrated circuit device shown in FIGS. It is a schematic block diagram (schematic enlarged perspective view) of the second embodiment of the semiconductor integrated circuit device of the present invention. It is a schematic block diagram (sectional drawing) of 3rd Embodiment of the semiconductor integrated circuit device of this invention. It is a figure which shows the change of the conductance before and behind annealing at the time of using Ti. It is a figure which shows the change of the conductance before and behind annealing at the time of using W.

Hereinafter, the best mode for carrying out the invention (hereinafter referred to as an embodiment) will be described.
The description will be given in the following order.
1. First Embodiment 2. FIG. Second Embodiment 3. FIG. Third embodiment 4. Experimental example

<1. First Embodiment>
FIG. 1 shows a schematic configuration diagram (cross-sectional view) of a semiconductor integrated circuit device according to a first embodiment of the present invention.
An element isolation layer 2 made of an insulating layer such as an oxide is formed on a semiconductor substrate 1 such as a silicon substrate, and transistors Tr1 and Tr2 are formed on a portion of the semiconductor substrate 1 where the element isolation layer 2 is not formed. ing.
The right part in the figure is a memory cell portion 31, and the memory cell of the memory element 20 is formed above the transistor Tr 1 formed on the semiconductor substrate 1. A memory (storage device) is configured by the storage element 20 having a large number of memory cells.
The left part of the figure is a peripheral circuit part 32 including a control circuit for controlling the memory element 20, and a transistor Tr 2 is formed on the semiconductor substrate 1.
A semiconductor integrated circuit device is configured including the memory cell portion 31 and the peripheral circuit portion 32.

The transistor Tr1 of the memory cell unit 31 includes a source / drain region 3 in the semiconductor substrate 1, a gate insulating film 5 on the semiconductor substrate 1, a gate electrode 6 on the gate insulating film 5, and a side wall of the gate electrode 6. Wall 7.
The transistor Tr2 in the peripheral circuit section 32 includes a source / drain region 4 in the semiconductor substrate 1, a gate insulating film 8 on the semiconductor substrate 1, a gate electrode 9 on the gate insulating film 8, and a side wall of the gate electrode 9. Wall 10.
The gate insulating films 5 and 8 of the transistors Tr1 and Tr2 are formed of, for example, a silicon oxide film. The gate electrodes 6 and 9 are formed of polycrystalline silicon, a stacked layer of polycrystalline silicon and metal silicide, or the like. The sidewalls 7 and 10 are made of an insulating material such as silicon oxide.

An interlayer insulating layer 12 is formed so as to cover the semiconductor substrate 1 and the transistors Tr1 and Tr2.
Further, a plug layer 11 made of a conductor (metal, silicon, or the like) is formed on one of the source / drain regions 3 of the transistor Tr1 of the memory cell portion 31 and one of the source / drain regions of the transistor Tr2 of the peripheral circuit portion 32. It is connected. The plug layer 11 is formed in the via hole formed in the interlayer insulating layer 12.

A laminated film that is connected to the plug layer 11 and forms the memory element 20 is formed.
In the present embodiment, the memory element 20 is formed by a stacked film of a memory layer 21 capable of recording information by a change in resistance value and an ion source layer 22 that supplies a metal element serving as ions to the memory layer 21. It is configured.
The memory layer 21 and the ion source layer 22 of the stacked film of the memory element 20 are formed to extend in the left and right directions in the drawing.

  The resistance value of the memory layer 21 changes due to the entry and exit of metal element ions supplied from the ion source layer 22. When metal element ions are supplied and contained, the resistance value of the memory layer 21 is low, and when metal element ions are returned to the ion source layer 22, the resistance value of the memory layer 21 is high. These operations can be reversibly changed by passing a current through the memory element 20 and changing the direction of the current.

The material of the memory layer 21 is an oxide of one or more elements (metal elements) selected from Ta, Nb, Al, Hf, Zr, Ni, Co, and Ce, or a chalcogen compound containing Te as a main component, for example, AlTe. Etc. can be used.
As a material of the ion source layer 22, a material containing at least one element selected from Cu, Ag, Zn, Al, and Zr and at least one element selected from Te, S, and Se is used. Can do. For example, CuTe or the like can be used.

The resistance value of the memory layer 21 is sufficiently higher than the resistance value of the ion source layer 22. Therefore, it is difficult for current to flow in the film surface direction of the memory layer 21, and current flows between the plug layer 11 and the ion source layer 22. It can be a memory cell.
The memory element 20 shown in FIG. 1 has a configuration in which a memory layer 21 and an ion source layer 22 constituting the memory element 20 are continuously formed of the same layer by a plurality of memory cells.

Since the ion source layer 22 has a resistance value sufficiently lower than that of the memory layer 21, it is easy to flow a current in the film surface direction of the ion source layer 22, and the ion source layer 22 also serves as the upper electrode of the memory element. be able to.
Furthermore, the ion source layer 22 can also be used as a wiring such as a bit line.

The transistor Tr1 of the memory cell unit 31 is provided to select a memory cell of the memory element. When the transistor Tr1 is turned on, the memory cell connected to the transistor Tr1 is selected.
The source / drain regions common to the transistors Tr1 of the two memory cell units 31 shown in FIG. 1 are connected to a wiring such as a word line. In FIG. 1, the wiring such as the word lines is not shown.

Since the transistor Tr <b> 2 of the peripheral circuit unit 32 is electrically connected to the memory element 20, it operates as a control circuit that controls the operation of the memory element 20. For example, a current is applied to the memory cell of the memory element 20 or a voltage is applied.
When the transistor Tr2 is turned on, a current flows or a voltage is applied to the memory cell in the column connected to the transistor Tr2. In addition to the selection of the memory cell by the transistor Tr1 of the memory cell unit 31, it is possible to pass a current or apply a voltage to a specific memory cell among the memory cells arranged vertically and horizontally.

The peripheral circuit section 32 may include not only a MOS transistor such as the illustrated transistor Tr2 but also other transistors such as bipolar transistors and other circuit elements other than the transistors.
Further, the transistor Tr1 of the memory cell unit 31 and the transistor Tr2 of the peripheral circuit unit 32 do not necessarily have the same required characteristics. Therefore, even in the same MOS transistor, the gate length and the gate electrode material are different. There may be.
Further, FIG. 1 shows only the MOS transistor having the same conductivity type channel as the transistor Tr1 of the memory cell unit 31 as the transistor Tr2 of the peripheral circuit unit 32. In the actual peripheral circuit section 32, an NMOS transistor and a PMOS transistor are formed to constitute a CMOS circuit.

Further, in the present embodiment, in particular, in the laminated film constituting the memory element 20, the connection portion 25 with the plug layer 11 connected to the transistor Tr2 of the peripheral circuit portion 32 is the memory layer 23 in which the metal element is diffused. In addition, the ion source layer 24 is diffused with metal elements.
Examples of the metal element diffusing in these layers 23 and 24 include Ti and Zr, which are easily diffused by heat.
The memory layer 23 in which the metal element is diffused and the ion source layer 24 in which the metal element is diffused are formed of the same layer as the memory layer 21 and the ion source layer 22, respectively.

As described above, the connection portion 25 is the memory layer 23 in which the metal element is diffused and the ion source layer 24 in which the metal element is diffused. The resistance value is sufficiently low. As a result, the ion source layer 22 also serving as the upper electrode and the plug layer 11 connected to the transistor Tr2 of the peripheral circuit section 32 can be made conductive.
Further, the memory layer 23 in which the metal element is diffused has a sufficiently low resistance value due to the diffusion of the metal element, and the resistance value does not change greatly unlike the memory layer 21 of the memory cell portion 31, and the plug layer 11 can be stabilized.

Here, FIG. 2 shows a schematic enlarged perspective view in which the main part of the semiconductor integrated circuit device of FIG. 1 is extracted. FIG. 2 shows the plug layer 11 and the stacked films 21 and 22 that are formed on the plug layer 11 and constitute the memory element 20 in FIG.
The ion source layer 22 of the memory element 20 is also used as the upper electrode of the memory element 20 as shown in FIG.
Furthermore, the stacked films 21 and 22 of the memory element 20 are formed in a horizontally long planar pattern extending on the plug layer 11 connected to the transistor (Tr2 in FIG. 1) in the peripheral circuit portion including the control circuit.
The ion source layer 22 is also used as a wiring such as a bit line.
Further, as shown in FIG. 1, in the connection portion 25 on the plug layer 11 connected to the transistor Tr2 in the peripheral circuit portion, the memory layer 23 in which the metal element is diffused and the ion source layer 24 in which the metal element is diffused. Is formed.

The semiconductor integrated circuit device of the present embodiment can be manufactured, for example, as shown below.
First, as shown in FIG. 1, an element isolation layer 2, source / drain regions 3 and 4 of a transistor, gate electrodes 6 and 9, and the like are formed on a semiconductor substrate 1.
Further, an interlayer insulating layer 12 is formed over the entire surface so as to cover the gate electrodes 6 and 9 of the transistors Tr1 and Tr2.
Next, via holes are formed in the interlayer insulating layer 12 on the source / drain regions 3 and 4 of the transistors Tr1 and Tr2 by etching or the like.
Subsequently, a conductor layer to be a via wiring is formed by filling the inside of the via hole.
Thereafter, the conductor layer on the interlayer insulating layer 12 is removed, and the plug layer 11 made of the conductor layer is formed.

The manufacturing process will be described below with reference to a schematic enlarged perspective view similar to FIG.
As shown in FIG. 3A, a memory layer 21, an ion source layer 22, and a metal film 13 containing a metal that easily diffuses, such as Ti and Zr, are sequentially formed and stacked on the plug layer 11. As the metal film 13, a Ti film, a Zr film, or an alloy film containing Ti or Zr is formed.
Subsequently, these three stacked layers 21, 22, and 13 are patterned into a rectangular plane pattern shown in FIG. 3A.

  Next, as shown in FIG. 3B, the three layers 21, 22, and 13 having a rectangular planar pattern are etched so as to have a desired wiring pattern. In FIG. 3B, a horizontally long planar pattern is formed as shown in FIG.

Next, of the stacked three layers 21, 22, and 13, only the connection part with the peripheral circuit part 32 is covered with a mask such as a resist, and the whole is etched, so that the part other than the connection part with the peripheral circuit part 32 is obtained. The metal film 13 on the upper part is removed.
Thereafter, by removing the mask, the metal film 13 remains only at the connection portion with the peripheral circuit portion 32 as shown in FIG. 4C.

Next, annealing is performed to diffuse metal elements (Ti, Zr, etc.) from the metal film 13 above the connection portion with the peripheral circuit portion 32 to the memory layer 21 and the ion source layer 22. The annealing temperature is about 400 ° C., for example.
As a result, as shown in FIG. 4D, the memory layer 23 in which the metal element is diffused and the ion source layer 24 in which the metal element is diffused are formed in the connection portion 25.
In this way, the semiconductor integrated circuit device shown in FIGS. 1 and 2 can be manufactured.

According to the configuration of the semiconductor integrated circuit device of the present embodiment described above, the storage layer 21 and the ion source layer 22 constituting the storage element 20 are even on the plug layer 11 connected to the transistor Tr2 of the peripheral circuit section 32. It is formed to extend.
Since the resistance value of the ion source layer 22 is sufficiently lower than that of the memory layer 21, the ion source layer 22 can also be used as the upper electrode of the memory element 20, and each memory cell and the peripheral circuit are connected through the ion source layer 22. The part 32 is electrically connected.
Further, since the ion source layer 22 also serving as the upper electrode does not include a step, there is no problem of film breakage.

Further, in the connection portion 25 where the laminated film constituting the storage element 20 is connected to the plug layer 11 connected to the transistor Tr2 of the peripheral circuit portion 32, the storage layer 23 in which the metal element is diffused and the ion source in which the metal element is diffused. Layer 24 is formed.
The laminated films 23 and 24 of the connection portion 25 have sufficiently lower resistance values than the laminated films 21 and 22 in other portions due to diffusion of the metal element. As a result, the ion source layer 22 also serving as the upper electrode and the plug layer 11 connected to the transistor Tr2 of the peripheral circuit unit 31 can be made conductive.
Further, the memory layer 23 in which the metal element is diffused has a sufficiently low resistance value due to the diffusion of the metal element, and the resistance value does not change greatly unlike the memory layer 21 of the memory cell portion 31, and the plug layer 11 can be stabilized. Thereby, signal exchange between the control circuit of the peripheral circuit unit 32 and the memory cell of the storage element 20 can be performed stably.

Therefore, according to the present embodiment, even when the cell size is reduced, the memory element 20 itself and the connection part 25 between the memory element 20 and the peripheral circuit part 32 can be stably formed.
In addition, since signal exchange between the control circuit of the peripheral circuit portion 32 and the memory cell of the memory element 20 can be performed stably, the memory can be stably operated.

<2. Second Embodiment>
Next, FIG. 5 shows a schematic configuration diagram (schematic enlarged perspective view) of the second embodiment of the semiconductor integrated circuit device of the present invention.
In the present embodiment, as shown in FIG. 5, the memory layer 21 and the ion source layer 22 constituting the memory element 20 are formed in a plate-like plane pattern.
A connecting portion 25 is formed on the plug layer 11 connected to the transistor Tr2 (see FIG. 1) of the peripheral circuit portion 32 on the left side in the drawing.
In this connection portion 25, a storage layer 23 in which a metal element is diffused and an ion source layer 24 in which the metal element is diffused are stacked, and the layers 23 and 24 in which these metal elements are diffused are the other portions of the storage layer 21. And the same layer as the ion source layer 22.
The planar pattern of the layers 23 and 24 in which the metal element is diffused is a horizontally long pattern including the top of each plug layer 11, that is, the same pattern as that of the first embodiment.
Other configurations are the same as those of the semiconductor integrated circuit device according to the first embodiment shown in FIGS.

  When manufacturing the configuration of the second embodiment, the process of the first embodiment is omitted except that the step of patterning the stacked three layers into a wiring-shaped plane pattern shown in FIG. 3B is omitted. A semiconductor integrated circuit device can be manufactured in the same manner as the manufacturing method of the configuration.

According to the configuration of the semiconductor integrated circuit device of the present embodiment described above, the storage layer 21 and the ion source layer 22 constituting the storage element 20 are even on the plug layer 11 connected to the transistor Tr2 of the peripheral circuit section 32. It is formed to extend.
Since the resistance value of the ion source layer 22 is sufficiently lower than that of the memory layer 21, the ion source layer 22 can also be used as the upper electrode of the memory element 20, and each memory cell and the peripheral circuit are connected through the ion source layer 22. The part 32 is electrically connected.
Further, since the ion source layer 22 also serving as the upper electrode does not include a step, there is no problem of film breakage.

Further, in the connection portion 25 where the laminated film constituting the storage element 20 is connected to the plug layer 11 connected to the transistor Tr2 of the peripheral circuit portion 32, the storage layer 23 in which the metal element is diffused and the ion source in which the metal element is diffused. Layer 24 is formed.
The laminated films 23 and 24 of the connection portion 25 have sufficiently lower resistance values than the laminated films 21 and 22 in other portions due to diffusion of the metal element. As a result, the ion source layer 22 also serving as the upper electrode and the plug layer 11 connected to the transistor Tr2 of the peripheral circuit unit 31 can be made conductive.
Further, the memory layer 23 in which the metal element is diffused has a sufficiently low resistance value due to the diffusion of the metal element, and the resistance value does not change greatly unlike the memory layer 21 of the memory cell portion 31, and the plug layer 11 can be stabilized. Thereby, signal exchange between the control circuit of the peripheral circuit unit 32 and the memory cell of the storage element 20 can be performed stably.

Therefore, according to the present embodiment, even when the cell size is reduced, the memory element 20 itself and the connection part 25 between the memory element 20 and the peripheral circuit part 32 can be stably formed.
In addition, since signal exchange between the control circuit of the peripheral circuit portion 32 and the memory cell of the memory element 20 can be performed stably, the memory can be stably operated.

<3. Third Embodiment>
FIG. 6 shows a schematic configuration diagram (cross-sectional view) of a third embodiment of the semiconductor integrated circuit device of the present invention.
In the present embodiment, the material of the laminated film constituting the memory element 20 is different from that of the first embodiment.
In other words, the memory element 26 is formed of a memory layer 26 made of a material whose resistance value changes, and the upper electrode 27 made of a conductor thereon to form a laminated film of the memory element 20.
Unlike the first embodiment in which the ion source layer 22 is provided on the memory layer 21, the mechanism for changing the resistance value of the memory layer 26 is a configuration in which the resistance value can be changed by the memory layer 26 alone. And For example, the memory layer 26 has a configuration in which the resistance value changes due to a phase change that changes between crystalline and amorphous, a change in the state of the compound, and the like.

Examples of the material of the memory layer 26 include phase change materials such as GeSbTe, complex oxides having a perovskite structure such as Pr _1-x Ca _x MnO ₃ (PCMO), other complex oxides, and oxides such as cobalt oxide and tantalum oxide. As described above, various resistance change materials can be used.

  As a material of the upper electrode 27, an electrode material used in a normal semiconductor integrated circuit device can be used. Depending on the material of the memory layer 26, it is desirable to use a specific electrode material (for example, a tantalum electrode for the cobalt oxide memory layer) in order to assist the change in the resistance value of the memory layer 26.

Further, in the present embodiment, in particular, in the laminated film constituting the memory element 20, the connection portion 25 with the plug layer 11 connected to the transistor Tr 2 of the peripheral circuit portion 32 has a storage layer 28 in which a metal element is diffused. Thus, the upper electrode 29 in which the metal element is diffused is formed.
Examples of the metal element diffused in these layers 28 and 29 include Ti and Zr, which are likely to be diffused by heat.
The memory layer 28 in which the metal element is diffused and the upper electrode 29 in which the metal element is diffused are formed of the same layer as the memory layer 26 and the upper electrode 27, respectively.

As described above, since the connection portion 25 is the memory layer 28 in which the metal element is diffused and the upper electrode 29 in which the metal element is diffused, it is more sufficiently than the memory layer 26 and the upper electrode 27 due to the diffusion of the metal element. The resistance value is low. As a result, the upper electrode 27 and the plug layer 11 connected to the transistor Tr2 of the peripheral circuit section 32 can be made to conduct well.
Further, the memory layer 28 in which the metal element is diffused has a sufficiently low resistance value due to the diffusion of the metal element, and the resistance value is not greatly changed unlike the memory layer 26 of the memory cell portion 31, and the plug layer 11 can be stabilized.

  Other configurations are the same as those of the semiconductor integrated circuit device according to the first embodiment shown in FIGS.

In order to manufacture the semiconductor integrated circuit device of the present embodiment, the memory layer 26 is formed using a phase change material such as GeSbTe or a resistance change material made of various complex oxides or oxides. The upper electrode 27 is patterned in the same manner as in the first embodiment.
After that, as in the first embodiment, the metal film is formed in a pattern that remains only in the connection portion, and the metal element is diffused from the metal film to the memory layer 26 and the upper electrode 27 by annealing, so that the metal element Forms layers 28 and 29 in which is diffused.

According to the configuration of the semiconductor integrated circuit device of the present embodiment described above, the storage layer 26 and the upper electrode 27 constituting the storage element 20 extend to the plug layer 11 connected to the transistor Tr2 of the peripheral circuit section 32. Is formed. Then, each memory cell and the peripheral circuit portion 32 are electrically connected through the upper electrode 27.
Further, since the upper electrode 27 does not include a step, there is no problem of film breakage.

Further, in the connection portion 25 where the laminated film constituting the memory element 20 is connected to the plug layer 11 connected to the transistor Tr2 of the peripheral circuit portion 32, the memory layer 28 in which the metal element is diffused and the upper electrode in which the metal element is diffused. 29.
The laminated films 28 and 29 of the connection portion 25 have sufficiently lower resistance values than the laminated films 26 and 27 in other portions due to the diffusion of the metal element. As a result, the upper electrode 27 and the plug layer 11 connected to the transistor Tr2 of the peripheral circuit section 32 can be made to conduct well.
Further, the memory layer 28 in which the metal element is diffused has a sufficiently low resistance value due to the diffusion of the metal element, and the resistance value is not greatly changed unlike the memory layer 26 of the memory cell portion 31, and the plug layer 11 can be stabilized. Thereby, signal exchange between the control circuit of the peripheral circuit unit 32 and the memory cell of the storage element 20 can be performed stably.

Therefore, according to the present embodiment, even when the cell size is reduced, the memory element 20 itself and the connection part 25 between the memory element 20 and the peripheral circuit part 32 can be stably formed.
In addition, since signal exchange between the control circuit of the peripheral circuit portion 32 and the memory cell of the memory element 20 can be performed stably, the memory can be stably operated.

In the third embodiment, the upper electrode 27 is formed on the memory layer 26. However, when the resistance value of the material itself that changes the resistance value used for the memory layer is relatively low, It is also possible to omit the upper electrode and configure the memory element with a single layer of only the memory layer.
In the case of this configuration, only the memory layer in which the metal element is diffused is formed in the connection portion with the peripheral circuit portion.
By configuring the memory element with a single layer of only the memory layer, the patterning process of the memory element by etching or the like is simplified. As a result, it is possible to refine the pattern that also serves as the wiring, improve the patterning accuracy, reduce the number of manufacturing steps, and the like.

  Further, in each of the above-described embodiments, the connection portion 25 is provided at the end of the stacked film of the memory element 20, but a connection portion is provided at a portion other than the end of the stacked film of the memory element, for example, The memory cell portion may be arranged on both sides of the portion.

In the present invention, the semiconductor substrate on which circuit elements such as transistors are formed is not limited to a silicon substrate, and a semiconductor substrate made of another semiconductor material such as Ge or a compound semiconductor may be used.
Further, in the present invention, the circuit elements of the peripheral circuit section connected to the memory connection section through the plug layer are not limited to MOS transistors but other active elements (bipolar or other transistors or diodes). May be.

<4. Experimental example>
Here, the semiconductor integrated circuit device of the present invention was simply manufactured, and the characteristics were examined.

(Example)
The transistor Tr1 of the memory cell unit 31 was formed on the semiconductor substrate 1 so that the memory cells in the memory cell array unit had 4 k bits. In addition, the peripheral circuit portion 32 including the control circuit including the transistor Tr2 is formed in another portion of the semiconductor substrate 1.
Next, an interlayer insulating layer 12 was formed so as to cover the whole, and then the interlayer insulating layer on the source / drain regions 3 and 4 of the transistors Tr1 and Tr2 was removed by etching or the like to form a via hole.
Next, a conductor layer is formed by filling the via hole, the conductor layer on the interlayer insulating layer 12 is removed, and the plug layer made of a conductor film is connected to the source / drain regions 3 and 4 of the transistors Tr1 and Tr2. 11 was formed.
In order to simplify the structure, the ion source layer 22 having a low resistance is omitted, and a storage layer 21 made of AlTe and a Ti film as the metal film 13 are sequentially formed, as shown in FIG. 3A. These two layers 21 and 13 were patterned into a wiring pattern.
Next, annealing was performed at 400 ° C. for 1 hour to diffuse Ti of the metal film 13 into the memory layer 21.
Thereafter, an insulating layer was formed covering the whole.
In this manner, a semiconductor integrated circuit device was manufactured and used as a sample of the example.

(Comparative example)
A W film having the same film thickness was formed instead of the Ti film of the metal film 13, and the others were manufactured in the same manner as in the example, and a semiconductor integrated circuit device was prepared as a sample for comparison.

For each sample of the example and the comparative example, the conductance of the memory layer 21 before annealing and the conductance of the memory layer 21 after annealing were measured.
As a measurement result, changes in conductance of the memory layer before and after annealing are shown in FIGS. The result of the example is shown in FIG. 7, and the result of the comparative example is shown in FIG. 7 and 8, the conductance of the memory layer is shown by the relationship between the conductance value and the cumulative distribution (% relative to 4 kbits) at that value.

7 that the conductance increases when a Ti film is formed on the memory layer 21 and annealed.
Therefore, it can be seen that Ti diffuses into the memory layer and the resistance value is significantly reduced.
On the other hand, FIG. 8 shows that when the W film is formed on the upper portion of the connection portion and annealed, the conductance hardly changes.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Element isolation layer, 3, 4 Source / drain region, 5, 8 Gate insulating film, 6, 9 Gate electrode, 7, 10 Side wall, 11 Plug layer, 12 Interlayer insulating layer, 13 Metal film, 20 Memory element, 21, 26 memory layer, 22 ion source layer, 23, 28 memory layer in which metal element is diffused, 24 ion source layer in which metal element is diffused, 25 connection part (with peripheral circuit part), 27 upper electrode, 29 Metal electrode diffused upper electrode, 31 Memory cell array section, 32 Peripheral circuit section, Tr1 Memory cell array section transistor, Tr2 Peripheral circuit section transistor

Claims (6)

A semiconductor integrated circuit device comprising a memory and a control circuit for controlling the memory,
A semiconductor substrate;
A storage layer made of a resistance change material whose resistance value changes, and information is recorded by the resistance value;
The memory including the memory layer, the memory layer being formed in common to a plurality of memory cells, and formed above the semiconductor substrate;
A peripheral circuit portion in which a circuit element including the control circuit is formed on the semiconductor substrate;
A plug layer electrically connected to the circuit element of the peripheral circuit portion and formed in an insulating layer on the semiconductor substrate;
Each layer constituting the memory, including the storage layer, is formed to extend up to the plug layer, and is electrically connected to the plug layer, and at a connection portion near the plug layer. A semiconductor integrated circuit device in which metal elements are diffused and the resistance value is lower than other parts.   The memory layer is made of an oxide of at least one element selected from Ta, Nb, Al, Hf, Zr, Ni, Co, and Ce, and is formed by laminating with the memory layer, Cu, Ag, Zn, Al , Zr and an ion source layer including at least one element selected from Te, S, Se, and the memory is configured, and the metal element is Ti or Zr. The semiconductor integrated circuit device according to claim 1.   The semiconductor integrated circuit device according to claim 1, wherein the storage layer is made of GeSbTe, and the metal element is Ti or Zr. A method of manufacturing a semiconductor integrated circuit device including a memory and a control circuit,
Forming a circuit element of a peripheral circuit portion including the control circuit on a semiconductor substrate;
Forming a plug layer electrically connected to the circuit element in the insulating layer after forming an insulating layer over the circuit element;
Each of the layers constituting the memory is formed by extending to the plug layer, including a storage layer in which information is recorded according to the resistance value, which is made of a resistance change material whose resistance value changes.
Forming a layer containing a metal element above the storage layer;
Patterning the metal element-containing layer so as to remain only in a connection portion that electrically connects the plug layer and each layer constituting the memory;
And a step of diffusing the metal element of the layer containing the metal element into each layer constituting the memory by heat treatment. A method for manufacturing a semiconductor integrated circuit device.   The memory layer is formed using an oxide of at least one element selected from Ta, Nb, Al, Hf, Zr, Ni, Co, and Ce, and laminated with the memory layer to form Cu, Ag, Zn, An ion source layer including at least one element selected from Al and Zr and at least one element selected from Te, S, and Se is formed, and the memory includes the memory layer and the ion source layer. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the metal element is Ti or Zr.   The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein the storage layer is formed using GeSbTe, and the metal element is Ti or Zr.

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