JP2011250231A - Information transmission system and information transmission method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information transmission system and an information transmission method, capable of avoiding wasteful processing on a receiving side.SOLUTION: In the information transmission system for transmitting arbitrary information using intensity-modulated light (P) as a medium, a low speed data modulated at a predetermined low speed period and a high speed data modulated at a predetermined high speed period can be multiplexed by the light. Further, information part (19e) to retain information indicating whether the high speed data is multiplexed is provided in a logical format (19) of the low speed data.

Description

  The present invention relates to an information transmission system and an information transmission method for transmitting information using luminance-modulated light as a medium.

  One type of information transmission system that transmits information using luminance-modulated light as a medium is a so-called visible light communication system. Note that the visible light communication system uses a light source such as an LED, which has excellent responsiveness (high speed of turning on / off) compared to an incandescent lamp, etc. However, the present invention is not limited to this. Any information transmission system may be used as long as the information is transmitted using luminance-modulated light as a medium, and invisible light such as infrared light (invisible light) may be used.

  The principle of the visible light communication system will be described. This system assigns a specific pattern sequence to each bit logic (logic 1 and logic 0) of information to be transmitted (binarized digital information, hereinafter referred to as transmission information TX), and according to the pattern sequence While modulating the luminance of the light source, the receiving side converts the modulated light into an electric signal, restores the bit logic corresponding to the pattern sequence included in the electric signal, and reproduces the transmission information TX. is there. The specific pattern series is any two bit pattern series having a low degree of correlation with each other, and two series corresponding to the binary logic of the transmission information TX (hereinafter referred to as the first pattern series SA and the second pattern series SB). Is prepared in advance.

  A specific example will be described. Now, it is assumed that SA is “00101”, SB is “00101”, and transmission information TX is “01011000...”. In this case, assuming that SA is assigned to logic 1 of TX and SB is assigned to logic 0, the arrangement of SA and SB corresponding to transmission information TX is “SB, SA, SB, SA, SA, SB, SB, SB. ... ”And the light source is subjected to luminance modulation in time series according to this order.

  That is, if logic 0 of SA and SB is turned off and logic 1 is turned on, SA = “turn off, turn off, turn on, turn off, turn on” and SB = “turn on, turn on, turn off, turn on, turn off”. The blinking pattern of the light source corresponding to the transmission information TX is “ON, ON, OFF, ON, OFF, OFF, OFF, OFF, ON, OFF, ON, ON, ON, OFF, ON, OFF, OFF, OFF, ON, OFF, ON, OFF, OFF, ON, OFF, ON, ON, ON, OFF, ON, OFF, ON, ON, OFF, ON, OFF, ON, ON, OFF, ON, OFF.

  Then, on the receiving side, this blinking pattern is received and photoelectrically converted to restore a series of “SB, SA, SB, SA, SA, SB, SB, SB...” By arranging corresponding logical values, the original transmission information TX (01011000...) Can be reproduced.

  Here, in the visible light communication system, two types corresponding to the amount of information transmission are considered. If these two types are referred to as “basic type” and “development type” for the sake of convenience, the basic type defines the modulation of the first pattern sequence SA and the second pattern sequence SB in the above description of the principle as a predetermined type. The low-speed cycle is used, and the advanced type is that the above modulation is performed at a predetermined high-speed cycle. The basic type of application is simple communication (for example, beacon use), and the advanced type of application is more complicated communication (for example, traffic information communication or outdoor advertising communication).

  As a prior art of the visible light communication system corresponding to such two types, for example, the one described in Patent Document 1 below is known. In this document, the luminance change pattern of the light source is a combination of "low-speed modulation" and "high-speed modulation". A technique of multiplex modulation (hereinafter referred to as a conventional technique) in which a change pattern is observed with a short imaging period and a shutter time is described. According to this, the first process using the luminance change pattern of the low-speed modulation and the second process using the luminance change pattern of the high-speed modulation can be performed.

  FIG. 13 is a diagram showing a luminance variation pattern in the prior art. In this figure, (A) shows a luminance fluctuation pattern when viewed in a sufficiently long cycle. As a whole (envelope of the luminance fluctuation signal), the luminance corresponds to the spreading code pattern (here, for convenience, the SA). 10101) and blinks in a very short time, and the brightness at the time of lighting is changed in two steps of high and low. “Low-speed modulation” is a part of the change period Tp of the spread code pattern, and “High-speed modulation” is a part of the blinking period Tpb inside the spread code pattern. Hereinafter, the luminance at the time of extinction is referred to as OFF, the luminance at the time of high luminance lighting is referred to as ON (H), and the luminance at the time of low luminance lighting is referred to as ON (L).

  The middle stage (B) shows a pattern bit period in which transmission data bits have a fixed length (for example, one pattern of 64 bits), and the lower stage (C) shows a luminance fluctuation pattern when viewed in a short cycle.

  According to this figure, when (A) is observed with a longer imaging cycle and shutter time in the light receiving unit, it is possible to capture luminance fluctuations due to the spread code pattern (SA) that is the envelope of (A) with a low-pass filter applied. On the other hand, when (A) is observed with a shorter imaging cycle and shutter time, the luminance fluctuation of the original signal level as represented by (C) can be captured.

  FIG. 14 is a conceptual diagram of a high-speed modulation decoding mode in the prior art. In this figure, in the high-speed modulation decoding mode, logic determination is performed using a predetermined threshold level, and transmission data is determined by using a logic signal 0 below the threshold level and a logic signal 1 above the threshold level. The threshold level in the prior art is a fixed value. For example, the threshold level is set as an intermediate value between the luminance when the light is turned off and the luminance ON (L) when the low luminance is turned on.

JP 2003-179556 A

As described above, since the conventional technology multiplexes the low-speed modulation luminance change pattern and the high-speed modulation luminance change pattern, simple communication (for example, beacon use) is performed using the low-speed modulation decoded data. In addition, it is possible to obtain an advantage that complicated communication (for example, traffic information communication, outdoor advertisement communication, etc.) can be performed using decoded data of high-speed modulation.
However, in this prior art, since the receiver side always performs the decoding process of the high-speed modulation after the decoding process of the low-speed modulation, it is wasted when receiving the basic light, that is, the signal of only the low-speed modulation. I could not deny it. That is, when basic light is received, there is no need to perform high-speed modulation decoding processing, but in the prior art, wasteful processing occurs in the high-speed modulation decoding portion, and the visible light communication system. The responsiveness was worsened.

  Therefore, an object of the present invention is to provide an information transmission system and an information transmission method that can avoid useless processing on the receiving side.

According to the first aspect of the present invention, in the information transmission system for transmitting arbitrary information using luminance-modulated light as a medium, the light is modulated with low-speed data modulated with a predetermined low-speed cycle and with a predetermined high-speed cycle. Information transmission characterized in that it can be multiplexed with high-speed data and an information section is provided in the logical format of the low-speed data to hold information indicating whether the high-speed data is multiplexed System.
According to a second aspect of the present invention, in the information transmission method for transmitting arbitrary information using luminance-modulated light as a medium, the light is modulated at a low-speed data modulated at a predetermined low-speed cycle and at a predetermined high-speed cycle. Information transmission characterized in that it can be multiplexed with high-speed data and an information section is provided in the logical format of the low-speed data to hold information indicating whether the high-speed data is multiplexed Is the method.

  ADVANTAGE OF THE INVENTION According to this invention, the information transmission system and information transmission method which can avoid the useless process in the receiving side can be provided.

3 is an electrical internal configuration diagram of the light emitting unit 10. FIG. It is a figure which shows the example of a waveform of the light P output in time series via the light emission window. It is a figure which shows the logical format of the light P. 3 is an electrical internal configuration diagram of a light receiving unit 20. FIG. FIG. 4 is a diagram showing an operation flowchart of the light receiving unit 20. It is the signal waveform by which the high frequency signal was multiplex-modulated, and its sampling conceptual diagram. It is a conceptual diagram of a gain setting. It is a conceptual diagram in case the range of the maximum value and minimum value of two series covers. It is a conceptual diagram of bit decoding. It is a transition diagram from SH state to SL state. It is a figure which shows the example of improvement. It is a figure which shows the determination table. It is a figure which shows the luminance fluctuation pattern in a prior art. It is a conceptual diagram of the high-speed modulation decoding mode in a prior art.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is an electrical internal configuration diagram of the light emitting unit 10. In this figure, the light emitting unit 10 includes a transmission data memory 11, a pattern bit counter 12, a byte counter 13, a pattern data memory 14, a timing generator 15, a CPU 16, a light emitting unit 17, and a light emitting window 18.

  The timing generator 15 generates a stable clock signal CK having a predetermined period synchronized with the image capture clock signal PCK of the timing generator in the light receiving unit 20 described later.

  The CPU 16 sequentially extracts one bit of the pattern data from the pattern data memory 14 in synchronization with the clock signal CK from the timing generator 15, and sequentially extracts one byte of bit data from the transmission data memory 11. Each time, the bit logic of the pattern data is determined (determining whether it is a logic signal 0 or a logic signal 1).

  If the logic signal is 1, the first modulation condition corresponding to the bit value is applied to the 1-byte bit data extracted from the transmission data memory 11 at that time, while the logic signal is 0. The operation of applying the second modulation condition corresponding to the bit value of 1-byte bit data extracted from the transmission data memory 11 is repeated for all transmission data.

The first and second modulation conditions are as follows.
<First modulation condition>
This is applied when the bit of pattern data is 1.
When the 1-byte bit of the transmission data is 0 → the first luminance level When the 1-byte bit of the transmission data is 1, the second luminance level

<Second modulation condition>
This is applied when the bit of pattern data is 0.
When the 1-byte bit of the transmission data is 0 → the third luminance level When the 1-byte bit of the transmission data is 1, the fourth luminance level

Hereinafter, the following symbols are given to the first to fourth luminance levels.
First luminance level: SH_FH
Second luminance level: SH_FL
Third luminance level: SL_FH
Fourth luminance level: SL_FL

The meanings of these symbols are as follows.
The two characters before the underbar symbol (_) correspond to the bit period of the pattern data, and the two characters after the underbar symbol (_) correspond to the one-byte period of the transmission data. S represents low-speed modulation, F represents high-speed modulation, H represents a logic signal 1 (that is, high level), and L represents a logic signal 0 (that is, low level).

  Here, each of the first to fourth luminance levels indicates a luminance designation value for the light emitting unit 17, and the magnitude relationship thereof is “first luminance level> second luminance level> third luminance level> fourth. Therefore, the relationship of “SH_FH> SH_FL> SL_FH> SL_FL” is established.

  The light-emitting unit 17 is driven under the first modulation condition and the second modulation condition. Thus, when the bit of the pattern data is 1, if the bit of 1 byte of the transmission data is 0, the first luminance Light is emitted at the level SH_FH, and if the 1-byte bit of the transmission data is 1, light is emitted at the second luminance level SH_FL lower than the first luminance level SH_FH, or when the bit of the pattern data is 0 If the 1-byte bit of the transmission data is 0, light is emitted at the third luminance level SL_FH that is lower than the second luminance level SH_FL, and if the 1-byte bit of the transmission data is 1, the third byte is transmitted. An operation of emitting light at a fourth luminance level SL_FL having a lower luminance than the luminance level SL_FH is performed, and a time-series luminance change pattern is transmitted through the light emission window 18. And it outputs the light P with. In addition, when the lowest brightness | luminance 4th brightness level SL_FL shows the brightness | luminance value 0, naturally the light emission part 17 will be light-extinguished (it does not light-emit).

  FIG. 2 is a diagram illustrating a waveform example of the light P output in time series through the light emission window 18. In this figure, (a) shows the entire waveform, and (b) shows the waveform of the main part. As shown in (a), the light P is composed of a “low-speed modulation” period corresponding to the bit period of the pattern data and a “high-speed modulation” period corresponding to the 1-byte bit period of the transmission data. One period of “low speed modulation” is 1 mS (period of 1 KHz), and one period of “high speed modulation” is 1 μS (period of 1 MHz), that is, a frequency ratio of 1: 1000. However, this ratio is an example. Any ratio that can distinguish low-speed modulation and high-speed modulation may be used. For example, a ratio such as 1: 2 may be used.

  The light P output in time series through the light emission window 18 exhibits luminance changes of the first to fourth luminance levels according to the combination of the bit value of the pattern data and the 1-byte bit value of the transmission data. As described above, since the first to fourth luminance levels have a relationship of “SH_FH> SH_FL> SL_FH> SL_FL”, in short, the light P has the maximum luminance value SH_FH and the luminance value SH_FL next to it. The luminance changes in four stages, namely, SL_FH of the next luminance value and SL_FL of the lowest luminance value.

  In (a), two codes Lv_SH and Lv_SL shown in the figure indicate threshold levels (thresholds for logic determination) used in data decoding in the light receiving unit 20 described later. Here, Lv_SH is the threshold level used when the bit value of the pattern data in the period of “low-speed modulation” is 1, and Lv_SL is the bit of the pattern data in the period of “low-speed modulation” This is the threshold level used when the value is 0.

  The conditions for setting these two threshold levels are “SH_FH> Lv_SH> SH_FL” and “SL_FH> Lv_SL> SL_FL”, as is clear from FIG. That is, Lv_SH is smaller than the first luminance level (SH_FH) and larger than the second luminance level (SH_FL), and Lv_SL is smaller than the second luminance level (SL_FH) and the fourth luminance level (SL_FL). ) Is greater than the condition.

  The above description is for when the first to fourth luminance levels have a relationship of “SH_FH> SH_FL> SL_FH> SL_FL”. The magnitude relationship between the first to fourth luminance levels is not limited to this, and may be, for example, as shown in (b). In other words, the relationship of “SH_FH> SL_FH> SH_FL> SL_FL” as shown in (b) may be used. In this case, the two threshold level setting conditions are “SH_FH> Lv_SH> SL_FH”, “SH_FL> Lv_SL”. > SL_FL ”.

Next, the logical format of the light P of this embodiment will be described.
FIG. 3 is a diagram illustrating a logical format of the light P. In this figure, a logical format 19 is used for low-speed modulation, and this logical format 19 includes a header portion 19a, a data body portion 19b, and a data correction portion 19c such as an FCS, and further includes a header portion 19a. Includes a frame type information unit 19d, a multiplexing flag unit 19e, and a multiplexing modulation type unit 19F.

  The frame type information section 19d holds information bits indicating whether the logical format 19 is only for beacon use (position acquisition use) or includes arbitrary transmission data. 1: Transmission data, information bit 0: Beacon use only. Here, information bit 0: only beacon is used, but this is only an example. Of course, it may mean other uses than beacon.

  The multiplexing flag unit 19e holds information bits indicating whether the high-speed signal is multiplexed in the logical format 19, and the presence of the multiplexing flag unit 19e is the feature of this embodiment. It is one of the points to do. That is, information bit 1: with high-speed modulation data multiplexing and information bit 0: no multiplexing (low-speed modulation data only). Therefore, as will be described later, in the light receiving unit 20 on the receiving side, it is possible to determine the information bit of the multiplexing flag unit 19e and to prevent the data decoding process from being performed in the case of bit 0, which is useless. Processing can be avoided.

  The multiplex modulation type unit 19F holds information flag bits indicating a multiplex modulation method. For example, information bit 0: multiplication type multiplex modulation method, information bit 1: modulation pulse addition type multiplex modulation. Is the method. This is intended to coexist with the modulation method (multiplication type) in the prior art described at the beginning.

Next, the light receiving unit 20 will be described.
FIG. 4 is an electrical internal configuration diagram of the light receiving unit 20. In this figure, the light receiving unit 20 includes an optical lens unit 21, an imaging unit 22, a captured image buffer 23, a display buffer 24, a liquid crystal display 25, a timing generator 26, a reading position control memory 27, a sub-sampling control memory 28, a CPU 29, a pattern. The data list memory includes a data memory 30, a reference image buffer 31, a frame time series buffer 32, a correlation degree evaluation image buffer 33, a binarization work buffer 34, a data list memory 35, a shutter key 36, and a readout condition list 37. 35 further includes an update request list 38, a list entry 39, and a bit buffer 40.

  The imaging unit 22 is composed of a two-dimensional image sensor such as a charge-coupled devices (CCD) or a complementary metal-oxide semiconductor (CMOS), and electrically captures an image of a subject captured via the optical lens unit 21. Is converted into a typical frame image signal, and is output to the capture image buffer 23 at a period synchronized with the capture image clock signal PCK generated by the timing generator 26. In particular, a two-dimensional image capable of partial reading of an arbitrary size. It is a sensor.

  Here, “partial readout” refers to designating an arbitrary region of the entire imaging area of the two-dimensional image sensor and partially reading out an image in the region. This refers to the functions installed in many of the three-dimensional image sensors. The imaging unit 22 according to the present embodiment has a partial reading function, and in particular, full dot reading (for example, 1280 × 960 dot reading) and a smaller size than the full dot reading as necessary. The first partial readout (for example, 320 × 240 dot readout) and the second partial readout smaller in size than the first partial readout (for example, 3 × 3 dot readout) are appropriately switched. It is something that can be done.

In addition, the imaging unit 22 in the present embodiment increases the frame rate at the time of the first partial reading with respect to the frame rate at the time of the full dot reading, and further, the frame rate at the time of the second partial reading. Is a point that is faster than the frame rate at the time of the first partial readout, and these three types of frame rates are, for example,
-Frame rate for full dot readout: 30 Fps
-Frame rate for first partial reading: 2,000 Fps
-Frame rate for second partial reading: 20,000 Fps
It is.
The full dot readout is for normal camera photography, but the two partial readouts are for reception of the visible light communication system. Specifically, the first partial readout is for low-speed modulation reception of the communication system, and the second Is read for high-speed modulation reception of the communication system.

  The captured image buffer 23 has a sufficient capacity to temporarily store a frame (image) read at the time of partial reading, and the display buffer 24 has a capacity that can secure data for the total number of pixels of the imaging unit 22. have. Further, since each frame time series buffer 32 stores partial read data in time series, each frame has a capacity corresponding to at least the partial read data, and the reference image buffer 31 and the correlation evaluation image Since the buffer 33 and the binarization work buffer 34 each store partial read data in time series, each has at least a capacity corresponding to the partial read data, and further has a read position control. The memory 27 has a capacity that can hold the area information of the first and second partial readings in the full-angle image.

  The CPU 29 controls the overall operation of the light receiving unit 20, for example, when processing the frame image fetched into the capture image buffer 23 as it is to the display buffer 24 and displaying it on the liquid crystal display 25 or when operating the shutter key 36. In addition to processing for capturing an image captured in the display buffer 24 in an image memory (not shown), the following processing is further performed.

  That is, the CPU 29 sequentially stores the frame images captured in the captured image buffer 23 in synchronization with the capture clock signal PCK in each plane of the frame time-series buffer 32 for each frame image. Here, the frame time series buffer 32 includes first to nth planes each having a storage capacity corresponding to the size of one frame image, and the number of planes n is at least a pattern series in the light emitting unit 10. This corresponds to the bit number N of (pattern data read from the pattern data memory 14). For example, when the number of bits N is 5, the number of planes n of the frame time series buffer 32 is at least 5 planes from the first plane to the fifth plane. Hereinafter, for convenience of explanation, the number of bits N of the pattern sequence is set to 5 bits, and the number of planes n is also set to 5.

The order of writing frame images from the first plane to the fifth plane is as follows.
1st frame image = 1st plane 2nd frame image = 2nd plane 3rd frame image = 3rd plane 4th frame image = 4th plane 5th frame image = 5th plane 6th frame image = 7th frame image of the first plane = 8th frame image of the 2nd plane = 9th frame image of the 3rd plane = 10th frame image of the 4th plane = 5th plane. The write operation up to the plane is performed cyclically.

  The CPU 29 controls the order of writing to each plane (actually controls the value of the buffer pointer n), and in parallel, a pixel area having a time-series luminance change pattern from the frame image written to each plane. Is extracted, and the luminance change pattern is binarized by the binarization work buffer 34, and the binarized data is compared with the reference pattern series held in the pattern data memory 30. When the first reference pattern sequence is matched, a logic signal 1 is generated, and when the second reference pattern sequence is matched, a logic signal 0 is generated, and these logic signals are stored in the data list memory 35. The process of storing in is executed. The liquid crystal display 25 of the light receiving unit 20 displays a subject image including a light emitting area by the light emitting unit 10, and further blows out information related to the light emitting area to a specific portion (for example, the center of the screen) of the display area. Overlapping display imitating the figure. The reference image buffer 31 is for camera shake correction.

Next, the operation of the light receiving unit 20 in the present embodiment will be described.
FIG. 5 is a flowchart illustrating the operation of the light receiving unit 20. In this figure, the operation flowchart of the light receiving unit 20 is broadly divided into a front part that performs low-speed modulation processing (from step S11 to step S15) and a rear-stage part that performs high-speed modulation processing (from step S16 to step S26). Consists of.

<Previous part / Low-speed modulation processing>
In the first part, first, in the low speed mode, the presence or absence of the signal (light P) is searched (step S11), the low speed data is decoded (step S12), and then the information of the header portion 19a of the low speed data is read (step S13). Then, the information of the multiplexing flag portion 19e of the header portion 19a is checked to determine whether or not the high speed data is multiplexed (step S14). If the high-speed data is not a multiplexed signal, the operation / display using the low-speed data (step S15) is executed, and then the previous part is repeated. If the high-speed data is the multiplexed signal, the process proceeds to the subsequent part. .

  As described above, steps S11 to S15 are processing of the low-speed modulation signal, and as described in the prior art at the beginning, two processes are performed depending on the exposure time of the cycle time which is twice the cycle of the observation slot pulse. If the phase sequence is observed, at least one of the sequences is always at the optimum timing, and the optimum phase can be determined.

  Even when the high-frequency signal is multiplexed and modulated, if it is averaged by the exposure time, and if the high-frequency signal has a 0/1 balance of 1: 1 as in the Manchester code, the sequence of the optimum phase As for the sample data, a series of values of only the pulses before addition is obtained regardless of multiplexing of high-frequency signals.

  FIG. 6 is a signal waveform obtained by multiplex modulation of a high-frequency signal and a sampling conceptual diagram thereof. As shown in this figure, if the multiplexed high frequency signal is balanced 0/1, the optimized phase sequence A of the two phase sequences A and B is used. Sampling data can be obtained.

  Here, the determination in step S14 (determination as to whether or not the high-speed data is a multiplexed signal) can be made by examining the multiplexing flag section 19e (see FIG. 3) in the received signal. This is because if the information bit of the multiplexing flag unit 19e is “1”, “high-speed modulation data multiplexing is present” and “0” indicates “no multiplexing”. Thereby, useless processing in the case of “no multiplexing”, that is, useless processing of the subsequent part (steps S16 to S26) can be avoided, and the responsiveness of the light receiving unit 20 is not deteriorated.

<Rear part / High-speed modulation processing>
In the latter part, first, one area in the image is selected (step S16), paying attention to the selected area, the gain is adjusted in the low speed mode, and the values of Lv_SH and Lv_SL are stored (step S17).

  The processing in step S16 and step S17 is to determine the H and L levels (in-saturation levels) using low-speed observation. Here, in the low-speed reception operation, the following determination is made. Considering the case where there are various environments and various light sources, the signal may be too strong for the exposure / gain of the sensor. In such a case, when the maximum amplitude of the high-frequency pulse is considered, the H-level value of the low-frequency signal may not be a correct average value due to saturation.

  In conventional image sensor communication-related technologies proposed by the present inventor (such as Patent Document 1 at the beginning), there is no need to consider such a saturation problem at all for detection of low-frequency modulation. This is because there should have been a minimum luminance difference necessary for processing. However, in the present invention, since the bit decode value of the high-speed modulation signal is determined from the observation result of the low-speed signal, the observation value of the low-speed modulation pulse needs to be accurately within the intermediate value of the high-speed modulation. Therefore, in the processing of step S16 and step S17, the low-speed modulation signal is observed for the necessary low-speed pulse period to set an optimum gain.

  FIG. 7 is a conceptual diagram of gain setting. In this figure, it is unclear how far the level of SH_FH has been extended in the observation at a low speed cycle, so even if a pulse is taken as a low speed modulation signal, it is not suitable as a gain setting as shown in FIG. There is. This is because, as the actual pulse value, for example, when the transmission signal standard is a low speed with a value as shown in FIG. 5B, the high frequency pulse H is also within the saturation region (saturation). This is because it is averaged within the area).

  For this reason, if the range of the dynamic range is widened (gain is lowered) to satisfy the condition (b) in FIG. 9, optimum adjustment can be made so that a signal with higher luminance is not saturated.

  Even if the light source is OFF, when the light source is actually observed with a camera, the luminance of the light source does not become completely zero due to the ambient brightness such as sunlight. Therefore, as shown in FIG. 5B, it is desirable to set the expression “Lv_SH + (Lv_SH−Lv_SL) / 2 <Sat” in consideration of the value of the threshold level (Lv_SL) on the L level side. Here, Sat is a saturation level.

  The process of step S17 is repeated several times as necessary, and after fine adjustment of the exposure, the threshold levels (Lv_SH and Lv_SH) optimized according to the adjustment result are stored.

  In the present embodiment, as described above, it is assumed that there are light sources with various environments and various luminances, and the processing of step S17 is performed after determining a specific partial readout region and determining a light source to receive. If the brightness and the sensitivity of the sensor are in a fixed relationship, such gain optimization processing can be made unnecessary.

  As described above, when the optimized threshold levels (Lv_SH and Lv_SH) are stored, the threshold levels for high-speed modulation (Th_SH, Th_SL) are set (step S18). In this step S18, thresholds (threshold levels Th_SH, Th_SL) for the high-speed modulation pulse are determined from the values of the H level and L level of the low-speed modulation signal optimally observed.

  This is because gain adjustment is performed so that the dynamic range is substantially the same at the frame rate of the first partial readout and the frame rate of the second partial readout, but the same threshold value cannot be applied to both. . However, since the relationship between the two is linear, if an adjustment value that surely falls within the dynamic range with a low-speed pulse is known, the threshold setting in the case of high-speed Fps (the frame rate of the second partial read-out) is simplified accordingly. It can be done by ratio calculation. The optimally set value is calculated as a threshold for the high-speed modulation pulse (threshold level Th_SH, Th_SL) and stored.

  As a result of the above processing, preparation for capturing high-speed modulation is completed, so that a mode for high-speed partial reading is entered for a portion to be subjected to high-speed modulation reception (step S19), and then a decoding phase sequence is determined ( Step S20). In other words, the phase to be decoded is determined in the high-speed modulation signal with a sampling period twice that of the low-speed modulation signal.

  In the determination of the decoding phase sequence, the necessary number including the H level and the L level of high-speed modulation is always sampled from the modulation method. For example, since there are no three or more H level continuations or L level continuations in the case of Manchester code, only three pulses can be observed, and six samples can be observed if the period is double. Alternatively, in the case of 4-PPM, there is no continuation of the same value seven times or more, so 7 × 2 = 14 samples may be observed.

  The determination of this phase sequence is simple. If H / L is always included, the phase-locked sample must have the maximum and minimum values, so the maximum and minimum values of the two sequences are compared, and the sequence whose fluctuation range can include one is locked phase And it is sufficient. However, if this determination timing is applied when the low-speed modulation frequency is changing H / L, the range of the maximum value and the minimum value of the two sequences may be covered.

  FIG. 8 is a conceptual diagram in the case where the range of the maximum value and the minimum value of two series is covered. In the case shown in the figure, the observation result may be rejected for the simplification of the process, and the determination may be made again with the next required number of samples. Of course, as shown in the figure, it is necessary to take measures such as taking more judgment samples in order to eliminate the case where the low frequency signal changes, but in this embodiment, judgment is required. If it is not possible, the next sample series is taken by rejecting the decision.

  Next, the symbol synchronization position (interval of symbols higher in pulse level) is determined (step S21). This determination makes it possible to perform bit decoding for the time being, and it is possible to take a bit sequence. In actuality of determining the symbol synchronization position, when an arbitrary bit string “11010011...” Of Manchester code is taken as an example, a pattern in which the same value of 0 or 1 continues is a symbol break. For example, when the bit string is “110”, the first one may be discarded and determined as “1 | 10 | 10 | 01 | “|” Symbol is the determined symbol synchronization position. Incidentally, such symbol synchronization is well known and can be similarly searched by coding such as other PPM.

  Next, bit / symbol decoding is performed, and the process moves to an upper layer (step S22). That is, the normal bit decoding process is started, and the high frequency modulation signal is bit decoded (symbol decoded) to restore the original bit string (transmission data).

  FIG. 9 is a conceptual diagram of bit decoding. As shown in this figure, for example, in the low modulation H state (SH state), 1_0 decoding is performed using Th_SH as the threshold level, whereas in the low modulation L state (SL state), Th_SL May be used for the threshold level to perform 1/0 decoding.

  However, more specifically, since the process starts without knowing where the start timing of the high-speed modulation pulse is in the SL state period or the SH state period, it is quite predictable when the transition of the SH state / SL occurs. Therefore, it is desirable to consider the following points.

  FIG. 10 is a transition diagram from the SH state to the SL state. This transition diagram shows an example of Manchester coding. First, while determining 1/0 in the SH state, it is always monitored whether there is a value smaller than Th_SL, and if it is determined that a value smaller than Th_SL has been reached, the following processing is performed.

  As shown in FIGS. 5B and 5C, the first state of the symbol is immediately shifted to the SL state. However, as shown in FIGS. 9A and 9D, when the second pulse of the symbol is less than Th_SL, for example, in FIG. The bit decoding is progressing as "0 ...", but when it falls below Th_SL in the 2nd pulse, the bit is corrected and the bit decoding is performed on the assumption that the previous bit is in the SL state. judge.

  The same applies to the transition from the SL state to the SH state. That is, the state transition is performed by determining the timing when the value becomes larger than Th_SH, and the determination of the value one bit before is returned as necessary. For example, in the case of 4-PPM, this determination is a process using the previous history for four pulses.

  Through such processing, even if the synchronization between the format levels of the high-speed modulation signal and the low-speed modulation signal is arbitrary, stable decoding can be performed using the two high-speed signal threshold levels (Th_SH / Th_SL) and the symbol history. It can be carried out. That is, the transmission data from the light emitting unit 10 can be reproduced by repeatedly executing the above step S21 until it is determined that the reception of the high-speed data is completed (step S23), and the transmission data is used. Required processing (operation / display processing using high-speed data, etc.) can be performed (step S24).

  Further, after the above steps S14 to S24 are repeated until reception completion of all multiplexed signals is determined (step S25), when reception completion is determined, the low-speed full-screen mode is again restored (step S26). Can be resumed (step S11 and subsequent steps), and a new signal can be detected.

  In the above description, the partial reading of the imaging unit 22 is two, ie, the first partial reading and the second partial reading, but is not limited to this. In recent years, depending on how the architecture of the two-dimensional image sensor is made, it has become possible to set a plurality of high-speed partial selective readouts (or high-speed readout pixels) in a number that is less than the limit number instead of a single one. Partial reading may be possible.

Moreover, you may improve as follows.
FIG. 11 is a diagram illustrating an improved example. This improved example corresponds to step S22 described above and FIGS. 9 and 10, and proposes another method that does not affect the bit determination state (SH state and SL state). As shown in FIG. 11, when the output pulse has a condition in which the high-speed modulation level fluctuation in SH and the high-speed modulation level fluctuation in SL do not overlap and there is a level difference more than a certain level, for example, “(SH_FH− In the case of “SH_FL) / 3 = (SL_FH−SL_FL) / 3 = (SH_FL−SL_FH)”, a level gap of 1/3 of the fluctuation width is guaranteed between the SH side and the SL side of high-speed modulation. Therefore, in this case, it is possible to determine 1/0 of the high-speed modulation signal by uniquely determining the value region.

  FIG. 12 is a diagram showing the determination table. As shown in this table, if the value range is SH_FH to Lv_SH, a bit value 1 is set. If Lv_SH to SH_FL, a bit value 0 is set. If SH_FL to SL_FH is set, an error (bit value 0 or 1 is set). Furthermore, the bit value 1 can be determined if SL_FH to Lv_SL, and the bit value 0 can be determined if Lv_SL to SL_FL.

Since it is as mentioned above, according to this embodiment, the following effects can be acquired.
(1) Since the modulation method is simple addition modulation, not only a terminal using a two-dimensional image sensor such as a CCD but also an existing terminal using an analog filter and a PD can be interoperated. In particular, in the case of a receiving terminal that performs only high-speed communication, it can basically be configured with only a high-pass filter, and since a pulse wave of only a high-speed modulated wave can be observed, there is no change to the conventional method of making, Great versatility is obtained.
(2) In addition, since it is possible to freely select whether the low-speed signal has only the position beacon role for the high-speed signal or the low-speed signal itself also has data, Unnecessary processing can be avoided, and the response of the receiving terminal can be improved.
(3) In addition, since a bit for controlling the modulation method is provided, multiplexing of high-speed modulation can be freely selected, and high-speed decoding processing for signals that are not multiplexed can be skipped. Therefore, it is possible to improve the processing efficiency in a complicated environment where there are many light sources with and without multiplexing, and the modulation method can be separated from the method described in the previous invention. Thus, a plurality of modulation schemes can coexist.
(4) Regardless of fluctuations in low-speed modulation, it is possible to reliably decode high-speed modulation data simply by observing a time waveform, and there is no need to provide an analog frequency filter or an expensive high-speed sampling digital filter. .

P: Hikari 19: Logical format 19e: Information part

Claims (2)

In an information transmission system for transmitting arbitrary information using luminance-modulated light as a medium,
The light can be multiplexed with low-speed data modulated with a predetermined low-speed cycle and high-speed data modulated with a predetermined high-speed cycle,
An information transmission system comprising an information section for holding information indicating whether or not the high-speed data is multiplexed in the logical format of the low-speed data. In an information transmission method for transmitting arbitrary information using luminance-modulated light as a medium,
The light can be multiplexed with low-speed data modulated with a predetermined low-speed cycle and high-speed data modulated with a predetermined high-speed cycle,
An information transmission method comprising: an information part for holding information indicating whether the high-speed data is multiplexed in the logical format of the low-speed data.

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