JP2011243794A - Semiconductor device, method of controlling power supply switch and designing method of the same - Google Patents

Abstract

A conventional semiconductor device has a problem that a chip area increases in order to suppress generation of an inrush current into a power supply control region.
A semiconductor device according to the present invention includes a first switch transistor SWL having a large on-resistance and a second switch transistor SWS having a small on-resistance, and the first and second switch transistors SWL, The SWS supplies current to different regions, the first switch transistor SWS is connected in series so as to propagate the control signal CONT in series, and the second switch transistor SWL transmits the control signal in series. The second switch transistor SWL connected in series so as to propagate and disposed in the first stage among the second switch transistors SWL is the first switch transistor SWS disposed at the rearmost among the first switch transistors SWS. The control signal CONT output from is input.
[Selection] Figure 8

Description

  The present invention relates to a semiconductor device, a power switch control method, and a design method thereof, and more particularly to a semiconductor device having a power switch that connects a global power supply wiring and a local power supply wiring, a power switch control method, and a design method thereof.

    In semiconductor devices, power consumption is increasing with higher integration. Therefore, in recent years, in a semiconductor device, a control is performed such that a circuit arranged in a chip is divided into a plurality of regions for each circuit block, and supply of power to blocks that are not used is partially cut off. One of the circuits used for such power control is a power switch circuit. The power switch circuit includes a switch transistor that controls a connection state between a global power supply wiring provided for the entire circuit arranged in the chip and a local power supply wiring provided for a circuit provided in the power supply control region. . The power switch circuit controls power supply to a circuit arranged in a region where power supply is controlled (hereinafter referred to as a power control region) by switching on / off of the switch transistor.

  In the case where this power switch circuit is used, in the semiconductor device, when the supply of power to the power control region where the power is cut off is resumed, the current flowing into the power control region is increased, thereby reducing the voltage of the global power supply wiring. On the other hand, in recent semiconductor devices, the power supply voltage is often set low in order to reduce power consumption. In a semiconductor device that operates based on such a low power supply voltage, the range of power supply voltages that can operate tends to be narrow. That is, in a semiconductor device based on a low power supply voltage, the fluctuation range of the power supply voltage that can guarantee the operation is small. For this reason, when a voltage variation accompanying the operation of the power switch circuit occurs with respect to a low power supply voltage, there arises a problem that the operation of the semiconductor device becomes unstable. Therefore, Patent Documents 1 to 3 disclose techniques for preventing fluctuations in power supply voltage due to such a power supply switch circuit.

  FIG. 14 shows a block diagram of the power switch circuit described in Patent Document 1. In FIG. As shown in FIG. 14, the power switch circuit described in Patent Document 1 has a composite switch circuit 505 connected in cascade. Then, the control signal PON is input to the composite switch circuit 505 arranged at the head. The control signal PON propagates through the cascaded composite switch circuit 505 and is folded back at the composite switch circuit 505 arranged at the end. The folded control signal PON (hereinafter, the folded control signal is referred to as PGOOD) is again propagated through the cascaded composite switch circuit 505 and is output as the control signal PGOOD from the composite switch circuit 505 arranged at the head. .

  A circuit diagram of the composite switch circuit 505 is shown in FIG. As shown in FIG. 15, the composite switch circuit 505 includes inverting buffer circuits 615, 617, 620, 622, a precharge header switch 605, and a header switch 610. The composite switch circuit 505 propagates the control signal PON via the inverting buffer circuits 615 and 617. Then, the precharge header switch 605 is turned on by the output of the inverting buffer circuit 615. The composite switch circuit 505 propagates the control signal PGOOD through the inverting buffer circuits 620 and 622. Then, the header switch 610 is turned on by the output of the inverting buffer circuit 620. The precharge header switch 605 and the header switch 610 are connected in parallel between the global power supply wiring VDDC and the local power supply wiring VDD. The precharge header switch 605 has a smaller transistor size than the header switch 610.

  In Patent Document 1, first, the precharge header switch 605 is sequentially turned on in response to the input of the control signal PON, and then the header switch 610 is sequentially turned on. By controlling the precharge header switch 605 and the header switch 610 in this way, the first stage of supplying power to the local power supply wiring VDD limits the current supplied to the local power supply wiring LVDD. Then, power supply by the header switch 610 is started after all the precharge header switches 605 are turned on. By performing such control, the maximum value of the current flowing from the global power supply wiring VDDC to the local power supply wiring VDD can be suppressed. Further, by suppressing the maximum value of the current, it is possible to suppress the voltage drop of the global power supply wiring VDDC.

  Further, in the semiconductor integrated circuit described in Patent Document 2, a plurality of circuit cells, a power supply line group, a power switch cell that is at least partially included in a lower layer region of the power supply line group, and is connected to the power supply line group, A branch line group connected to the power switch cell and supplying power to the predetermined circuit cell. The power switch cell is connected to the predetermined circuit cell in the branch line group in accordance with an input control signal. The power supply to at least one branch line to be connected is cut off. The power switch cell includes a switch transistor having a driving capability set in accordance with power consumption when a predetermined circuit cell is not powered off. Thereby, in the semiconductor integrated circuit described in Patent Document 2, a drop in power supply voltage can be suppressed.

  In the semiconductor integrated circuit described in Patent Document 3, a switch transistor including a plurality of transistors having different resistances during conduction is used. The switch transistor is divided from a non-conductive state to a conductive state by dividing the plurality of transistors into a plurality of times while observing a rule that all switch transistors having higher resistance than the transistor are turned on by a plurality of signal lines. The continuity is controlled. Thereby, in the semiconductor integrated circuit described in Patent Document 3, the on-resistance of the switch transistor after conduction is reduced while suppressing a drop in the power supply voltage due to the inrush current when the switch transistor is switched from the non-conduction state to the conduction state. .

US Patent Application Publication No. 2007/0103202 JP 2005-259879 A JP 2009-170651 A

  However, in the power switch circuit described in Patent Document 1 and the semiconductor integrated circuit described in Patent Document 3, a plurality of transistors must be used to form one switch transistor, and the ratio of the switch transistor to the circuit area There is a problem that the area efficiency is poor. In addition, the semiconductor integrated circuit described in Patent Document 2 aims to suppress a drop in power supply voltage when the power switch cell is in a conductive state, and a rush that occurs in response to switching of the power switch cell in a conductive state. The drop in current and power supply voltage cannot be suppressed. In order to suppress the inrush current in the semiconductor integrated circuit described in Patent Document 2, it is necessary to apply the techniques described in Patent Documents 1 and 3.

  In other words, the techniques described in Patent Documents 1 to 3 have a problem that it is impossible to prevent a decrease in power supply voltage that occurs in response to switching of the conduction state of the power switch without deteriorating the area efficiency.

  According to one aspect of the semiconductor device of the present invention, a first circuit region that is constantly supplied with power, a second circuit region that is switched between the power supply state and the cutoff state, and a power supply from the outside A global power supply wiring, a local power supply wiring to which the power supply is applied via the global power supply wiring, and a control signal that is arranged in the second circuit region and controls a conduction state between the global power supply wiring and the local power supply wiring. And a plurality of first switch transistors whose on-resistance is set to a first resistance value, and conduction between the global power supply wiring and the local power supply wiring, which are arranged in the second circuit region. A plurality of second switch transistors which control the state based on the control signal and whose on-resistance is set to a second resistance value smaller than the first resistance value. . In the semiconductor device according to the present invention, the first and second switch transistors supply currents to different regions in the second circuit region, and the plurality of first switch transistors include the control signal. Are connected in series so as to propagate in series, and the plurality of second switch transistors are connected in series so as to propagate the control signal in series, and the first stage of the plurality of second switch transistors is The second switch transistor disposed in the first switch transistor receives a control signal output from the first switch transistor disposed rearmost among the plurality of first switch transistors.

  One aspect of a power switch control method according to the present invention includes: a first circuit region to which power is constantly supplied; a second circuit region in which the power supply state and the power supply state are switched; and power supply from the outside Based on a control signal, a global power supply wiring that receives power, a local power supply wiring to which the power is supplied via the global power supply wiring, and a conduction state between the global wiring and the local wiring arranged in the second circuit region A switch control method for a power supply switch in a semiconductor device comprising: a plurality of first switch transistors having an on-resistance set to a first resistance value; and A plurality of second switch transistors set to a second resistance value smaller than the first resistance value, and the control signal After being propagated in series in the plurality of first switch transistors, it is input to the second switch transistor, and the control signal input to the second switch transistor is serialized in the plurality of second switch transistors. To propagate.

  A semiconductor device design method according to the present invention is a semiconductor device design method for designing a semiconductor device having a power switch using an arithmetic circuit, and the arithmetic circuit includes a circuit element and an on-resistance based on circuit design data. Resulting from a physical design step of creating first layout data including a power control region in which a second switch transistor in which a second resistance value is set is arranged, and normal operation of circuit elements in the power control region Based on the circuit design data, a first power supply voltage drop calculation step for calculating a first power supply voltage drop generated to calculate a boundary between a region where the first power supply voltage drop is large and a region where the first power supply voltage drop is small. A first amount in which the on-resistance is set to a first resistance value larger than the second resistance value is calculated by calculating a current amount of an inrush current generated according to switching of the power source in the power cutoff region. An estimation step for calculating the required number of switch transistors, and a second switch transistor arranged in a region where the first power supply voltage drop amount is small in the power cutoff region is replaced with the first switch transistor. A replacement step for generating the second layout data; a second power supply voltage drop calculating step for calculating a second power supply voltage drop caused by the inrush current in the power supply control region based on the second layout data; Optimization step of increasing the number of the first switch transistors replacing the second switch transistors in the second layout data until the second power supply voltage drop amount becomes smaller than a preset target value. And executing the physical design step, the replacement step, and the optimization step. The signal wiring for propagating the control signal for controlling the conduction state of the first and second switch transistors is wired so that the control signal propagates to the second switch transistor after the first switch transistor. The

  In the semiconductor device, the power switch control method, and the design method thereof according to the present invention, the semiconductor device includes a first switch transistor having a high on-resistance and a second switch transistor having a low on-resistance. When power supply to the power supply control region is started, the number of first switch transistors that are turned on is increased stepwise, and then the number of second switch transistors that are turned on is increased stepwise. Thereby, in the semiconductor device and the power switch control method according to the present invention, the peak value of the inrush current generated at the start of power feeding to the power control region is suppressed. Further, in the semiconductor device formed based on the semiconductor device design method according to the present invention, the first switch transistor is arranged by replacing the second switch transistor. That is, in the semiconductor device formed based on the semiconductor device design method according to the present invention, the first switch transistor and the second switch transistor supply power to different regions. Thereby, in this invention, the area efficiency of a power switch can be improved.

  According to the semiconductor device, the power switch control method, and the design method according to the present invention, it is possible to suppress the power supply voltage fluctuation while improving the area efficiency of the power switch.

1 is a schematic diagram illustrating a planar layout of a semiconductor device according to a first embodiment; 1 is a schematic diagram showing a wiring layout of a semiconductor device according to a first embodiment; FIG. 3 is a schematic diagram illustrating an arrangement position of a switch transistor according to the first exemplary embodiment. FIG. 6 is a schematic diagram illustrating another example of the arrangement positions of the switch transistors according to the first exemplary embodiment. FIG. 6 is a schematic diagram illustrating another example of the arrangement positions of the switch transistors according to the first exemplary embodiment. FIG. 6 is a schematic diagram illustrating another example of the arrangement positions of the switch transistors according to the first exemplary embodiment. 3 is a flowchart showing a method for designing a semiconductor device according to the first embodiment; FIG. 3 is a schematic diagram for explaining a relationship between arrangement positions of switch transistors and standard cells according to the first exemplary embodiment; 4 is a circuit diagram for explaining a relationship between a switch transistor and a standard cell according to the first embodiment; FIG. FIG. 3 is a schematic diagram illustrating a layout of a first switch transistor having a low on-resistance among the switch transistors according to the first embodiment. FIG. 3 is a schematic diagram illustrating a layout of a second switch transistor having a high on-resistance among the switch transistors according to the first embodiment. 6 is a graph comparing the magnitudes of inrush currents associated with the switching operation of the switch transistors of the semiconductor device according to the first embodiment. 4 is a graph comparing the magnitude of power supply voltage fluctuations associated with the switching operation of the conduction state of the switch transistor of the semiconductor device according to the first exemplary embodiment; 2 is a block diagram of a power switch circuit described in Patent Document 1. FIG. 2 is a circuit diagram of a composite switch circuit described in Patent Document 1. FIG.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram of a semiconductor device according to this embodiment. As shown in FIG. 1, the semiconductor device according to the present embodiment includes an I / O region, a first circuit region (for example, a power control region), and a second circuit region (for example, a constant power supply region). .

  The I / O region is a region where an external interface circuit in the semiconductor device is arranged. The external interface circuit includes, for example, an input / output circuit and a pad. In both the power control area and the constant power supply area, functional circuits that implement various functions mounted on the semiconductor device are arranged. In this embodiment, the functional circuit is configured by combining cells (hereinafter referred to as standard cells) that realize the minimum function of the circuit.

  Further, the power control region has a power switch (hereinafter referred to as a switch transistor). The standard cells arranged in the power control region are supplied with power via the switch transistor. In other words, the standard cell arranged in the power control region is in an operable state by being supplied with power when the switch transistor is in an on state, and is in a stopped state when the switch transistor is in an off state.

  On the other hand, the standard cells arranged in the constant power supply region are supplied with the power supplied from the outside without going through the switch transistor. In other words, the standard cells arranged in the constant power supply region are always supplied with power while the power is supplied from the outside to the semiconductor device.

  Here, FIG. 2 shows a schematic diagram of a cross-sectional view of the semiconductor device along the line II-II shown in FIG. As shown in FIG. 2, the semiconductor device has a semiconductor substrate 1 and a plurality of wiring layers provided in an upper layer of the semiconductor substrate 1. In the example shown in FIG. 2, the number of wiring layers is three. However, in implementing the present invention, the number of wiring layers can be arbitrarily set.

  In the semiconductor substrate 1, a standard cell 10 constituting a functional block of the semiconductor device is formed in a region corresponding to a constant power supply region, and standard cells 10L and 10S, a first switch transistor are formed in a region corresponding to a power control region. (For example, switch transistor SWS) and a second switch transistor (for example, switch transistor SWL) are formed. The standard cell 10L is a cell with a large current consumption, and the standard cell 10S is a cell with a small current consumption. The switch transistor SWS has an on-resistance set to a first resistance value, and the switch transistor SWL has an on-resistance set to a second resistance value smaller than the first resistance value. That is, the on-resistance of the switch transistor SWS is large, and the on-resistance of the switch transistor SWL is small. In the example shown in FIG. 2, the switch transistor SWS is arranged on the outer peripheral side of the power cutoff region or in the vicinity of the standard cell 10S. The switch transistor SWL is disposed in the vicinity of the standard cell 10L.

  In the example shown in FIG. 2, the global power supply wiring GVDD is provided in the uppermost layer of the wiring layers. The global power supply wiring GVDD supplies power to a circuit formed in a circuit formation region (a region including a power control region and a constant power supply region) of the semiconductor device. The global power supply wiring GVDD is formed over the entire circuit formation region. The global power supply wiring GVDD is connected to a power supply pad provided in the I / O region, and is supplied with power from the outside.

  In the example shown in FIG. 2, the local power supply wiring LVDD is provided below the global power supply wiring GVDD. The local power supply wiring LVDD is formed separately in the power supply control region and the constant power supply region. Of the local power supply wiring LVDD, the local power supply wiring LVDD provided corresponding to the power supply control region is connected to the global power supply wiring GVDD via the switch transistors SWL and SWS. Further, the local power supply wiring LVDD provided corresponding to the power supply control region in the local power supply wiring LVDD supplies power to a circuit provided in the power supply control region. Of the local power supply wiring LVDD, the local power supply wiring LVDD provided corresponding to the constant power supply region is directly connected to the global power supply wiring GVDD. In addition, the local power supply wiring LVDD provided corresponding to the constant power supply region in the local power supply wiring LVDD supplies power to a circuit provided in the constant power supply region.

  In the example shown in FIG. 2, a cell wiring is provided below the local power supply wiring LVDD. The cell wiring is a wiring for connecting between standard cells formed on the semiconductor substrate 1 or between elements constituting the circuit. A part of the cell wiring can be used as the local power supply wiring LVDD. In this case, the cell wiring used as the local power supply wiring LVDD is directly connected to the switch transistors SWL and SWS.

  In the semiconductor device according to the present embodiment, the global power supply wiring GVDD and the local power supply wiring LVDD in the constant power supply region are connected by via wiring. The local power supply wiring LVDD and the cell wiring are connected by via wiring. The cell wiring and the standard cell are connected by contact wiring.

FIG. 3 is a schematic diagram for explaining the relationship between the switch transistor and the standard cell of the semiconductor device according to this embodiment. In FIG. 3, an inverter composed of a PMOS transistor MP and an NMOS transistor is shown as an example of one standard cell.

  As shown in FIG. 3, in the power supply control region, the global power supply wiring GVDD supplied with the power supply voltage VDD supplied from the outside and the local power supply wiring LVDD are connected via the switch transistor SWL. The standard cell is connected between the ground wiring to which the ground voltage GND is supplied and the local power supply wiring LVDD. In FIG. 3, the power supply voltage applied to the global power supply wiring GVDD is VDD, and the power supply voltage applied to the local power supply wiring LVDD via the switch transistor SWL is VSD. The gate of the switch transistor SWL is supplied with a control signal CONT from a control circuit (not shown), and the switch transistor SWL is controlled to be turned on and off by the control signal CONT. In this embodiment, the switch transistor SWL is replaced with the switch transistor SWS according to the arrangement location of the switch transistor.

  On the other hand, in the constant power supply region, the global power supply wiring GVDD supplied with the power supply voltage VDD supplied from the outside and the local power supply wiring LVDD are connected via the wiring. In the example shown in FIG. 3, the power supply voltage VDD supplied from the outside is applied to the local power supply wiring LVDD as it is. The standard cell is connected between the ground wiring to which the ground voltage GND is supplied and the local power supply wiring LVDD.

  In addition, the back gate of the PMOS transistor MP among the transistors constituting the standard cell in the power supply control region is connected to the local power supply wiring. On the other hand, the switch transistor SWL needs to operate even when the standard cell in the power supply control region is in a stopped state. Therefore, the back gate of the switch transistor SWL is connected to the global power supply line. Further, the back gate of the PMOS transistor MP among the transistors constituting the standard cell in the constant power supply region is connected to the local power supply wiring. Note that the back gate of the NMOS transistor MN is connected to the ground-side wiring in both the standard cells in the power control region and the constant power supply region.

  Next, the positional relationship between the switch transistor and the standard cell in the semiconductor device according to the present embodiment will be described. FIG. 4 is a schematic diagram for explaining the positional relationship between the switch transistor and the standard cell. In the example shown in FIG. 4, only the switch transistor SWL is shown as the switch transistor to be arranged, but actually, a part of the switch transistor SWL is replaced with the switch transistor SWS.

  As shown in FIG. 4, in the semiconductor device according to the present embodiment, standard cells are arranged in the constant power supply region and the power control region. A standard cell is an element having a predetermined height and width, and is the minimum structural unit of a functional circuit. In this embodiment, it is assumed that all standard cells have a uniform height, and a plurality of types of widths are prepared according to the function of the cell. In the example shown in FIG. 4, the height and width of all standard cells are unified. In the example shown in FIG. 4, the switch transistors SWL are arranged at regular intervals in the power supply control region. The switch transistor SWL has twice the height of the standard cell and six times the width of the standard cell. Here, the height and width of the switch transistor are preferably integer multiples of the height and width of the standard cell. By setting the height and width of the switch transistor in this way, it is possible to improve disposition and area efficiency in the semiconductor device in which the standard cell is disposed. Note that the switch transistor SWS has the same height as the switch transistor SWL and has a width smaller than that of the switch transistor SWL (for example, the width is four times that of the standard cell).

  Next, details of the switch transistors SWL and SWS will be described. FIG. 5 shows a conceptual diagram of the layout of the switch transistor SWL, and FIG. 6 shows a conceptual diagram of the layout of the switch transistor SWS.

  As shown in FIG. 5, the switch transistor SWL is formed on the N well formed in the P well. Unlike the peripheral standard cells, the N well needs to be supplied with the power supply voltage VDD from the global power supply wiring GVDD, and thus has a shape that is not continuous with the N well of the standard cell. That is, the N well of the switch transistor SWL is electrically insulated from the N well of the standard cell. A diffusion layer for forming a source / drain region is formed in the N well. The switch transistor SWL has 12 gate electrodes. The twelve gate electrodes are connected to each other by a gate wiring, and a control signal CONT is supplied from an upper layer wiring (not shown). In the source / drain regions, source and drain regions are alternately set with a gate electrode interposed therebetween. A source wiring is provided in the source region, and a drain wiring is provided in the drain region. The source wiring is connected to a global power supply wiring GVDD (not shown) arranged in the upper layer. The source wiring supplies the power supply voltage VDD supplied from the global wiring to the N well. The drain wiring is connected to the local power supply wiring LVDD via an intermediate wiring (not shown).

  As shown in FIG. 6, the switch transistor SWS has a configuration in which the gate electrode of the switch transistor SWL is reduced. In the example shown in FIG. 6, the switch transistor SWS has two gate electrodes. That is, the switch transistor SWS is set to a transistor size that is 1/6 of the switch transistor SWL.

  Next, a method for designing a semiconductor device according to this embodiment will be described. In the design method of the semiconductor device according to the present embodiment, first, the switch transistor SWL is arranged in the power supply control region, and then the switch transistor SWL is replaced with the switch transistor SWS according to the amount of power supply voltage drop in the power supply control region. . Thus, in the semiconductor device according to the present embodiment, the switch transistor SWL and the switch transistor SWS are arranged in the power supply control region. FIG. 7 is a flowchart showing the procedure of the design method according to this embodiment.

  As shown in FIG. 7, in the design method according to the present embodiment, first, the arrangement positions and areas of the constant power supply region and the power control region are designed to generate circuit design data (step S1, circuit design step). ). In step S1, circuit design of functional blocks provided in each area is also performed.

  Subsequently, first layout data in which circuit elements and switch transistors SWL are arranged is created based on the circuit design data designed in the circuit design step (step S2, physical design step). More specifically, in the physical design step, a floor plan for setting a detailed location in a chip of a circuit block to be arranged, power supply wiring, placement of a switch transistor SWL having a small on-resistance, and placement of elements by automatic placement and routing In addition, when performing signal wiring, timing analysis, and circuit correction, ECO (Engineering Change Order) for performing correction layout using existing design data is performed. In the physical design step, the switch transistor SWL is arranged and the signal wiring for supplying the control signal CONT to the switch transistor SWL is performed. The signal wiring is wired so that the control signal CONT propagates in series to the switch transistor SWL disposed in the outer peripheral portion of the power supply control region and then propagates to the switch transistor SWL disposed in the central portion.

  Subsequently, IR-Drop verification for calculating a first power supply voltage drop amount (hereinafter referred to as IR-Drop) caused by the normal operation of the circuit elements in the power control region included in the first layout data is performed. (Step S3). After that, based on the verification result, a boundary between a region with a small IR-Drop and a region with a large IR-Drop is searched (step S4). The design process combining step S3 and step S4 is the first power supply drop amount calculating step.

  Further, in parallel with the steps S2 to S4, the estimation steps S5 to S8 are performed. In the estimation step, first, the capacity of the power control region is extracted based on the circuit design data (step S5). More specifically, in the semiconductor device, power supply wiring, signal wiring, circuit elements, and the like have parasitic capacitances, and in step S5, these parasitic capacitances are extracted from circuit design data. Subsequently, an equivalent circuit is created that models the capacitance extracted in step S5 (parasitic capacitance of the power switch, parasitic capacitance of the power supply wiring, and capacitance of the capacitor arranged in the power control region) (step S6). Then, using the equivalent circuit created in step S6, the amount of inrush current generated in response to switching of the power supply in the power cut-off region is calculated (step S7). In step S7, the amount of inrush current is calculated by a simple simulation using an equivalent circuit. Then, the required number of switch transistors SWS having a large on-resistance is estimated based on the amount of inrush current calculated in step S7 (step S8). More specifically, since the peak value of the inrush current is determined by the resistance value of the power supply wiring and the switch transistor SWL and the capacitance value of the power supply control region, the peak value of the inrush current is sufficiently suppressed in step S8. The number of possible switch transistors SWS is estimated. That is, in the estimation step, the amount of inrush current generated according to the switching of the power supply in the power cutoff region is calculated based on the circuit design data, and the required number of switch transistors SWS having a large on-resistance is calculated.

  Subsequently, second layout data is generated by replacing the switch transistor SWL disposed in the region where the IR-Drop is small in the power cutoff region with the switch transistor SWS (step S9, replacement step). Note that the number of switch transistors SWL to be replaced in the replacement step corresponds to the number of switch transistors SWS calculated in step S8. In steps S10 and S11, a second power supply drop amount calculating step is performed. In the second power supply drop amount calculating step, first, a second inrush current simulation is performed based on the second layout data (step S10). In step S10, the wiring and element parasitic capacitances of the power supply control region and the resistance values of the wiring and wiring are extracted from the second layout data, and the detailed inrush current amount is calculated using them. Then, power supply noise generated due to the amount of inrush current calculated in step S10 is calculated, and the power supply noise is compared with a preset target value (step S11).

  If the power supply noise exceeds the target value in step S11 (NO in step S11), an optimization step (step S12) is performed. In the optimization step, the number of replacements from the switch transistor SWL to the switch transistor SWS is further increased. This replacement is performed for the switch transistor SWL disposed in a region where IR-Drop is small. In the optimization step, the switch transistor SWL disposed on the outer periphery of the power cutoff region is preferentially replaced with the switch transistor SWS. Further, in the optimization step, the switch transistor SWL provided in the region where the input circuit and the output circuit of the circuit block provided in the power shut-off region are arranged is preferentially replaced with the switch transistor SWS. In the replacement step and the optimization step, the switch transistor SWL is replaced with the switch transistor SWS. At this time, the control signal CONT is first input to the switch transistor SWS in the signal wiring for propagating the control signal CONT, and Then, after being propagated in series through the switch transistor SWS, rewiring is performed so as to be input to the switch transistor SWL. Then, the optimization step is repeated until the power supply noise falls below the target value in step S11 of the second power supply fall amount calculation step.

  If the power supply noise falls below the target value in step S11 (YES in step S11), the design process is completed. In the semiconductor device design method according to the present embodiment, in the region where the IR-Drop calculated in step S4 is small, the IR-Drop is sufficiently small in the specification even if the switch transistor SWS having a large on-resistance is used. Set as an area. As a result, even if the switch transistor SWL disposed in the region where the IR-Drop is low is replaced with the switch transistor SWS, it is possible to prevent the IR-Drop from not satisfying the specifications. Further, it is possible to reduce the redesign time generated by replacing the switch transistor SWL with the switch transistor SWS.

  In the semiconductor device according to this embodiment formed by the above design method, a plurality of switch transistors SWL and switch transistors SWS are arranged in the power control region. In the semiconductor device according to the present embodiment, the control signal CONT propagates to the switch transistor SWL after the control signal CONT propagates in series to the switch transistor SWS. Here, the wiring generally has a parasitic capacitance and a parasitic resistance, and a delay occurs in signal propagation. In the semiconductor device according to the present embodiment, a plurality of switch transistors are made conductive in stages using this wiring delay. The control signal CONT is output by a control circuit (not shown). In the semiconductor device formed by the above design method, a plurality of variations can be considered in the arrangement form of the switch transistor SWL and the switch transistor SWS depending on the circuit formed in the power supply control region. 8 to 11 are schematic views showing the positional relationship of the switch transistors. Since the IR-Drop and the current consumption of the circuit block have a high correlation, the current consumption of the circuit block is used as an index corresponding to the magnitude of IR-Drop in the examples of FIGS. .

  In the example illustrated in FIG. 8, there are a region where the current consumption is small and a region where the power consumption is large. This is because the density of the standard cells 10 to be arranged varies from region to region. When a semiconductor device is designed by automatic placement and routing, the current consumption in the outer peripheral portion is reduced in this way, and the current consumption is increased in the central portion. In this embodiment, switch transistors SWS and SWL are arranged in a matrix in the power supply control region.

  In this embodiment, switch transistors having different on-resistances are arranged in accordance with current consumption in a region where the switch transistors are arranged. In the example shown in FIG. 8, there are regions of low current consumption along the four sides of the outer periphery of the power control region. Therefore, the switch transistor SWS is disposed along the outer periphery of the power control region. In addition, a region with a large current consumption exists in the central portion of the power supply control region. For this reason, the switch transistor SWL is arranged in a region including the central portion of the power control region.

  Here, in FIG. 8, the transmission path of the control signal CONT is indicated by an arrow. In the example shown in FIG. 8, the control signal CONT is input to the switch transistor SWS arranged at the upper left of the drawing. The control signal CONT propagates in series between the plurality of switch transistors SWS. The control signal CONT output from the switch transistor SWS to which the control signal CONT is transmitted last is input to the switch transistor SWL. In the example shown in FIG. 8, the switch transistor SWL is connected so that the control signal CONT is propagated in series. In the example shown in FIG. 8, a plurality of signal propagation sequences having a plurality of switch transistors SWL are provided. The control signal CONT propagates in parallel between signal propagation sequences. As described above, the control signal CONT need only have at least one serial propagation sequence, and can be propagated in parallel between the propagation sequences.

  In the example shown in FIG. 9, a region with a small current consumption exists on one side of the outer periphery of the power supply control region, and the other portion is a region with a large current consumption. In such a case, the switch transistor SWS is disposed only on the side of the outer periphery where the current consumption region is small, and the switch transistor SWL is disposed in the other region. The control signal CONT propagates in series in the plurality of switch transistors SWS, and then propagates in series in the plurality of switch transistors SWL.

  In the example shown in FIG. 10, there are regions with small current consumption on the left side of the drawing, the lower side of the drawing, and part of the right side of the drawing. Therefore, the switch transistor SWS is arranged in an area where the power consumption is small. Further, the switch transistor SWL is disposed in the other region. Also in the example shown in FIG. 10, the control signal CONT propagates in series in the plurality of switch transistors SWS, and then propagates in series in the plurality of switch transistors SWL.

  The example shown in FIG. 11 is different from the example shown in FIG. 10 in that a region with a large current consumption is included in a part of the lower side of the drawing. In such a case, the switch transistor SWL is arranged in a region with large power consumption on the lower side of the drawing. The control signal CONT is propagated except for the switch transistor SWL in the process of propagating the lower row in the drawing. That is, the control signal CONT propagates through the switch transistor SWS and then propagates to the switch transistor SWL.

  In any of the examples in FIGS. 8 to 11, the control signal CONT propagates from the outer periphery to the inner periphery of the power control region. By propagating the control signal CONT in this way, in the power supply control region, power supply from a standard cell is started from the outer peripheral portion. In many cases, an input / output circuit for exchanging signals with other circuit blocks (for example, a circuit block in the constant power supply region) is arranged on the outer periphery. In the semiconductor device according to the present embodiment, since the input of the standard cell is determined from the outer periphery of the power control region, when the supply of power to the standard cell arranged inside the power control region is started, the standard cell The logic level of the input signal input to is determined. Therefore, by turning on the power to the standard cells arranged in the outer periphery ahead of the standard cells arranged in the central part, the time when the input of the standard cells is indefinite is shortened, and this indefinite state is achieved. The resulting through current can be reduced.

  Here, the power supply voltage fluctuation suppressing effect in the semiconductor device according to the present embodiment will be described. FIG. 12 shows a graph for comparing the magnitude of the through current between the semiconductor device according to the present embodiment and the semiconductor device in which the switch transistor size is not optimized. FIG. 13 shows a graph for comparing the magnitude of power supply voltage fluctuation between the semiconductor device according to the present embodiment and the semiconductor device in which the switch transistor size is not optimized. 12 and 13, it is assumed that the switch transistor SWS to which the control signal CONT is input earliest at the origin of the time axis (horizontal axis) is turned on.

  As shown in FIG. 12, the inrush current is determined when the transistor size of the switch transistor is not optimized (for example, when all the switch transistors are formed by the second switch transistors having a small on-resistance), When the switch transistor is turned on, an extremely large inrush current is generated compared to other times. On the other hand, when the transistor size of the switch transistor is optimized (for example, when the switch transistor is arranged as in the example shown in FIG. 8), the inrush current is reduced even when the operation of the switch transistor is started. The amount of current only increases slightly compared to other times. In the example shown in FIG. 12, there is a difference of 10 times or more in the peak value of the inrush current.

  Further, as shown in FIG. 13, when the transistor size of the switch transistor is not optimized, the power supply voltage (the voltage of the global power supply wiring) greatly decreases as the switch transistor is switched from OFF to ON. . On the other hand, when the transistor size of the switch transistor is optimized, the voltage drop of the power supply voltage is reduced to about half that when the optimization is not performed.

  From the above description, the semiconductor device according to the present embodiment first transmits the power supplied from the global power supply wiring to the local power supply wiring by the first switch transistor having a large on-resistance. Then, after the first switch transistor (switch transistor SWS) in the power supply control region is turned on, the second switch transistor (switch transistor SWL) having a small on-resistance is turned on. By performing such arrangement and control of the switch transistors, in the semiconductor device according to the present invention, immediately after the start of power supply to the power supply control region, the first switch transistor having a large on-resistance passes through the first switch transistor in the power supply control region. Charges are accumulated in the capacitor and the parasitic capacitor. Since a certain amount of charge is accumulated in the power supply control region when the second switch transistor having a low on-resistance is turned on, the amount of charge to be charged by the switch transistor is less than that at the start of activation. Since the voltage of the power supply side electrode of the parasitic capacitance also rises to some extent, it is possible to prevent a large inrush current from flowing in accordance with the switching of the second switch transistor having a small on-resistance from off to on. In the semiconductor device according to the present embodiment, the inrush current is reduced, so that a rapid change in the current flowing through the global power supply wiring is suppressed, and fluctuations in the power supply voltage of the global power supply wiring are suppressed.

  Further, in the conventional semiconductor device (for example, Patent Documents 1 to 3), as described above, it is necessary to configure one switch transistor using a plurality of transistors in order to suppress the inrush current at the start of conduction of the switch transistor. It was. However, in the semiconductor device according to the present embodiment, the switch transistor provided for one region is configured by one transistor. That is, in the semiconductor device according to the present embodiment, the area efficiency of the switch transistor can be increased.

  In the semiconductor device according to the present embodiment, the cell size of the first and second switch transistors has a height and a width that are integral multiples of the height and width of the standard cell. The first switch transistor is set to a cell size such that the arrangement region is included in the arrangement region of the second switch transistor. Thereby, the replacement from the second switch transistor to the first switch transistor can be realized without redesign. That is, in the semiconductor device according to this embodiment, the time required for redesign can be reduced.

  Further, in the semiconductor device according to the present embodiment, the second switch transistor having a low on-resistance is disposed in a region where the current consumption is large in the power supply control region, and the region having a low current consumption is provided with the on-resistance. A large first switch transistor is arranged. That is, in the semiconductor device according to the present embodiment, since the on-resistance of the second switch transistor is small in a path through which a large amount of current flows, the power supply voltage fluctuation due to the on-resistance of the second switch transistor is small. Further, in a path with a small amount of flowing current, even if the first switch transistor having a large on-resistance is arranged, since the flowing current is small, the power supply voltage fluctuation due to the on-resistance of the first switch transistor is small. That is, in the semiconductor device according to the present embodiment, the power supply voltage fluctuation in the case where the internal circuit in the power supply control region operates is arranged by arranging in the path with a small amount of current flowing through the first switch transistor having a large on-resistance. Suppress. Further, in the semiconductor device according to the present embodiment, the power supply voltage fluctuation is suppressed by arranging the second switch transistor having a small on-resistance in the path with a large amount of flowing current.

  Further, in the semiconductor device according to the present embodiment, control is performed so that the control signal CONT for switching between the conduction state and the interruption state of the switch transistor is propagated from the switch transistor arranged along the outer periphery of the power supply control region. As a result, the standard cells in the power supply control area start to operate from those arranged on the outer periphery. In many cases, an input terminal and an output terminal of a functional block formed in the power control area are arranged on the outer periphery of the power control area. Further, in the logic circuit, generally, when the logic level of the input signal is indefinite, a through current flows through the logic circuit. However, by propagating the control signal CONT as in the semiconductor device according to this embodiment, power is supplied to the processing circuit in a state where the logic level of the input signal of the processing circuit in the circuit block is determined. can do. That is, in this embodiment, since the logic level of the input signal is fixed at the start of the operation of the logic circuit, the through current caused by the input signal being in an indefinite state can be reduced.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

1 Semiconductor substrate 10, 10L, 10S Standard cell CONT Control signal MN NMOS transistor MP PMOS transistor SWL Switch transistor SWS Switch transistor GVDD Global power supply wiring LVDD Local power supply wiring

Claims (17)

A first circuit region that is constantly supplied with power;
A second circuit region that is switched between a power supply state and a cut-off state;
Global power supply wiring that receives power supply from outside,
The power supply is provided through the global power supply wiring, and local power supply wiring;
A plurality of first resistors arranged in the second circuit region, controlling a conduction state between the global power supply wiring and the local power supply wiring based on a control signal, and having an on-resistance set to a first resistance value; A switch transistor;
A second resistor disposed in the second circuit region, for controlling a conduction state between the global power supply wiring and the local power supply wiring based on the control signal, and having an on-resistance smaller than the first resistance value; A plurality of second switch transistors set to a value,
The first and second switch transistors supply current to different regions in the second circuit region,
The plurality of first switch transistors are connected in series so as to propagate the control signal in series,
The plurality of second switch transistors are connected in series so as to propagate the control signal in series,
Among the plurality of second switch transistors, the second switch transistor arranged at the first stage receives a control signal output by the first switch transistor arranged at the rearmost among the plurality of first switch transistors. Semiconductor device.   The first switch transistor is provided corresponding to a region where a circuit element with low power consumption is arranged in the second circuit region, and the second switch transistor is provided in the second circuit region. 2. The semiconductor device according to claim 1, wherein the semiconductor device is provided corresponding to a region where a circuit element with large power consumption is disposed.   The first switch transistor is disposed along at least a part of the outer periphery of the second circuit region, and the second switch transistor is disposed in a region including a central portion of the second circuit region. The semiconductor device according to claim 1 or 2.   The first switch transistor is disposed in a region where an input circuit or an output circuit of a circuit formed in the second circuit region is disposed, and the second switch transistor is a signal transmitted from the input circuit. 4. The semiconductor device according to claim 1, wherein the semiconductor device is disposed in a region where a functional circuit that operates based on the circuit is disposed. 5.   The second switch transistor is configured such that the control signal is propagated in parallel and is divided into a plurality of signal propagation sequences having the plurality of second switch transistors, and the control signal is serially connected in the signal propagation sequence. The semiconductor device according to claim 1, wherein the semiconductor device propagates automatically.   The semiconductor device according to claim 1, wherein the first switch transistor and the second switch transistor are arranged in a lattice pattern in the circuit region. In the second circuit region, a standard cell in which the height and width of the cell are determined in advance is arranged,
7. The semiconductor according to claim 1, wherein height and width of the first switch transistor and the second switch transistor have an integer multiple of the height and width of the standard cell. apparatus. A first circuit area to which power is always supplied, a second circuit area in which the power supply state and the power supply state are switched, a global power supply line that receives external power supply, and the global power supply line A power switch in a semiconductor device, comprising: a local power supply line to which the power is supplied; and a switch transistor disposed in the second circuit region and controlling a conduction state between the global line and the local line based on a control signal. A control method,
The switch transistor includes a plurality of first switch transistors whose on-resistance is set to a first resistance value, and a plurality of first switches whose on-resistance is set to a second resistance value smaller than the first resistance value. Two switch transistors,
The control signal is propagated in series in the plurality of first switch transistors and then input to the second switch transistor,
A power switch control method for causing the control signal input to the second switch transistor to propagate in series in a plurality of second switch transistors.   The control signal is propagated to the plurality of first switch transistors provided corresponding to a region where a circuit element with low power consumption is disposed in the second circuit region, and then the second circuit region. The power switch control method according to claim 8, wherein the power switch control method propagates to the plurality of second switch transistors provided corresponding to a region where a circuit element with large power consumption is disposed.   The control signal is propagated to the plurality of first switch transistors disposed along at least a part of the outer periphery of the circuit region, and then disposed in a region including a central portion in the second circuit region. The power switch control method according to claim 8, wherein the power switch control method propagates to the plurality of second switch transistors.   Propagating the control signal to the plurality of first switch transistors arranged in a region where an input circuit or an output circuit of a circuit formed in the second circuit region is arranged, and then from the input circuit 11. The power switch control method according to claim 8, wherein the power switch control method propagates to the plurality of second switch transistors arranged in a region where a functional circuit that operates based on a transmitted signal is arranged.   The plurality of second switch transistors have a plurality of signal propagation sequences in which the control signal propagates in series, and propagate the control signals in parallel in the plurality of signal propagation sequences. The power switch control method according to any one of the above. A semiconductor device design method for designing a semiconductor device having a power switch using an arithmetic circuit,
The arithmetic circuit is
A physical design step of creating first layout data including a power control region in which a circuit element and a second switch transistor in which an on-resistance is set to a second resistance value are arranged based on the circuit design data;
Calculating a first power supply voltage drop caused by a normal operation of the circuit element in the power supply control region, and calculating a boundary between a region where the first power supply voltage drop is large and a region where the power supply voltage drop is small Power supply drop calculation step,
Based on the circuit design data, the amount of inrush current generated in response to switching of the power supply in the power cut-off region is calculated, and the on-resistance is set to a first resistance value larger than the second resistance value. An estimation step for calculating the required number of one switch transistor;
A replacement step of generating second layout data in which the second switch transistor disposed in a region where the first power supply voltage drop amount is small in the power cutoff region is replaced with the first switch transistor;
A second power supply drop amount calculating step for calculating a second power supply voltage drop amount caused by the inrush current of the power supply control region based on the second layout data;
Optimization step of increasing the number of the first switch transistors replacing the second switch transistors in the second layout data until the second power supply voltage drop amount becomes smaller than a preset target value. And run
In the physical design step, the replacement step, and the optimization step, a signal wiring that propagates a control signal that controls the conduction state of the first and second switch transistors is configured such that the control signal is the same as that of the first switch transistor. A method for designing a semiconductor device to be wired so as to be propagated to the second switch transistor later. The number of the second switch transistors replaced with the first switch transistors in the replacement step corresponds to the required number calculated in the estimation step,
14. The method of designing a semiconductor device according to claim 13, wherein in the optimization step, the second switch transistor disposed in a region where the first power supply drop amount is small is further replaced with the first switch transistor.   15. The method of designing a semiconductor device according to claim 13, wherein, in the optimization step, the second switch transistor disposed on the outer periphery of the power cut-off region is preferentially replaced with the first switch transistor.   The said optimization step WHEREIN: The said 2nd switch transistor provided in the area | region where the input circuit and output circuit of a circuit block provided in the said power supply cutoff area | region are arrange | positioned is replaced with the said 1st switch transistor preferentially. 16. A method for designing a semiconductor device according to any one of 13 to 15.   In the estimating step, an equivalent circuit is created based on circuit information including at least a capacitance value of the power control region obtained from the design data, a parasitic capacitance of the second switch transistor, and a parasitic capacitance of a power supply wiring, and the equivalent circuit The method for designing a semiconductor device according to claim 13, wherein a current amount of the inrush current is calculated by using.

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