JP2011138364A - Memory system - Google Patents

Abstract

【Task】
The present invention provides a memory system capable of reducing the storage capacity of the number of erasures by a simple method.
[Solution]
A storage unit capable of storing data in a block which is a unit of erasing data; a counter storage unit 33 for storing the number of times of erasure calculation stored each time the data stored in the storage unit is erased; and the storage unit When the data stored in is erased, the random number acquisition unit 30 that acquires a random number, the condition determination unit 31 that determines whether the random number satisfies a predetermined condition, and the condition determination unit 31 When it is determined that the random number satisfies a predetermined condition, the erasure count step 32 for incrementing the erasure calculation count, and when the erasure calculation count stored in the storage section exceeds a predetermined count, A memory system comprising: a changing unit 34 for changing a predetermined condition.
[Selection] Figure 5

Description

  The present invention relates to a memory system using a flash memory having a limit on the number of times of reading.

Nonvolatile semiconductor memories, such as flash memories, are mounted on various electronic devices. In a nonvolatile semiconductor memory, for example, as in a NAND flash memory, erasing / writing / reading is performed in units of blocks when erasing data, and in units of pages when writing / reading data. Some management units are different.

  When data is written into the nonvolatile semiconductor memory using a host device such as a personal computer, the address area of the nonvolatile semiconductor memory is designated and written.

  Since such a nonvolatile semiconductor memory cannot overwrite data, when rewriting the data of the nonvolatile semiconductor memory, the data without a rewrite request from the host device in the original block in which the data before rewriting is saved, It is necessary to move to a new block where the data after rewriting is written, write the data requested to be rewritten from the host device to the new block, and then erase the data stored in the original block. In other words, when data is rewritten to an address designated from the outside, rewriting, that is, erasing processing concentrates in a specific area in a short time, and the bias of erasure frequency in the specific area increases.

  Therefore, in the nonvolatile semiconductor memory, a process called wear leveling is performed in which data rewrite locations are evenly distributed. In order to perform the wear leveling process, it is necessary to store the number of erases of the block of the nonvolatile semiconductor memory in the memory.

  With the recent increase in capacity of nonvolatile semiconductor memories, there is a problem that the number of blocks of the nonvolatile semiconductor memory increases and the storage capacity for storing the number of erasures also increases.

Japanese Patent No. 3401742

  The present invention provides a memory system capable of reducing the storage capacity of the number of erasures by a simple method.

  A memory system according to one embodiment of the present invention includes a storage unit that can store data in a block that is a unit of data erasing, and an erase operation count that is saved each time the data stored in the storage unit is erased. A counter storage unit that stores data, a random number acquisition unit that acquires a random number when the data stored in the storage unit is erased, and a condition determination unit that determines whether or not the random number satisfies a predetermined condition , When the condition determining unit determines that the random number satisfies a predetermined condition, the erasure count step for incrementing the erasure calculation count, and the erasure calculation count stored in the storage unit are set to a predetermined count. And a changing unit that changes the predetermined condition when exceeding the predetermined condition.

  According to the present invention, it is possible to provide a memory system capable of reducing the storage capacity of the number of erasures by a simple method.

1 is a block diagram showing a configuration of a memory system including a NAND flash memory that is an aspect of a memory system according to a first embodiment of the present invention. 1 is a circuit diagram showing a configuration of a NAND flash memory cell array which is an aspect of a memory system according to a first embodiment of the present invention. 1 is a block diagram showing an outline of functions of a NAND controller according to a first embodiment of the present invention. The flowchart figure which shows the count operation by the NAND controller in the 1st Embodiment of this invention. The block diagram which shows the outline of the function of the NAND controller in the modification 3 of the 1st Embodiment of this invention. The conceptual diagram which shows the random number table of the memory system in the 2nd Embodiment of this invention. The flowchart figure which shows the count operation | movement of the frequency | count of erasing or reading of the data of the memory system in the 2nd Embodiment of this invention.

(First embodiment)
First, the configuration of the memory system according to the first embodiment of the present invention will be described with reference to FIG. 1 and FIG. FIG. 1 is a block diagram showing a configuration of a memory system including a NAND flash memory which is an aspect of the memory system according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a NAND flash memory cell array which is an aspect of the memory system according to the first embodiment of the present invention.

[Memory system configuration]
As shown in FIG. 1, the memory system includes a NAND flash memory 10 and a NAND controller 11.

<NAND flash memory>
The NAND flash memory 10 includes a plurality of blocks, each of which is a unit for erasing data, in which a plurality of memory cells are connected in series and NAND strings each having a selection gate transistor connected to both ends thereof are formed in a plurality of memory cell arrays.

  More specifically, as shown in FIG. 2, the plurality of NAND strings 20 formed in the memory cell array include a plurality of electrically rewritable nonvolatile memory cells M1 to Mn connected in series and both ends thereof. The portion includes a first selection gate transistor T1 for connection to the bit line BL and a second selection gate transistor T2 for connection to the source line. The control gates of the nonvolatile memory cells in the NAND string 20 are connected to different word lines.

  One word line is shared by the corresponding nonvolatile memory cells in the plurality of NAND strings 20. The control gates of the first and second selection gate transistors T1 and T2 are connected to first and second selection gate lines SGD and SGS that are parallel to the word line, respectively. A set of nonvolatile memory cells M sharing one word line constitutes a page that is a unit for reading or writing data. A set of a plurality of pages constitutes a block serving as a data erasing unit. For ease of understanding, it is assumed that each block is ordered when a plurality of blocks are described.

<NAND controller>
Next, the NAND controller 11 will be described with reference to FIG. The NAND controller 11 includes a host interface circuit (host I / F in FIG. 1) 12, an arithmetic processing unit (hereinafter referred to as MPU) 13, a ROM (Read-only memory) 14, and a RAM (Random access memory) 15. , And a NAND interface circuit (NAND I / F in FIG. 1) 16.

  The host interface circuit 12 controls input / output of information (command CMD, address ADD, data DAT) between the NAND controller 11 and the host device.

  The MPU 13 is for controlling the entire operation of the NAND controller 11. The MPU 13 creates various tables on the RAM 15 by, for example, receiving power from the memory system, reading the firmware (control program) stored in the ROM 14 onto the RAM 15 and executing predetermined processing.

  The ROM 14 stores a control program controlled by the MPU 13.

  The RAM 15 is used as a work area for the MPU 13 and stores control programs and various tables read from the ROM 14. The RAM 15 is provided with a block counter table 17a and a page counter table 17b. The block counter table 17a stores the number of data erase operations in each block in the memory cell array, and the page counter table 17b stores the number of data read operations in each page.

  The NAND interface circuit 16 controls input / output of information between the NAND controller 11 and the NAND flash memory 10.

  Next, an outline of the counter function among the functions of the NAND controller 11 in the first embodiment will be described with reference to the block diagram of FIG.

  As shown in FIG. 3, the part that controls the counter function of the NAND controller 11 includes a random number acquisition unit 30, a condition determination unit 31, an erase count step unit 32, and a counter storage unit 33. The random number acquisition unit 30 generates random numbers stored on the ROM 14 using the MPU 13 when data in a certain block is erased by a request from the host device or when data in a page is read by a request from the host device. The program is read, and the random number generated by the random number generation program is stored on the RAM 15.

  The condition determination unit 31 is for determining whether or not a random number generated by the random number generation program satisfies a predetermined condition. Specifically, using a condition determination program stored on the ROM 14, it is determined whether a random number stored on the RAM 15 satisfies a predetermined condition described later, and an erasure count stepping unit 32 described later is incremented. Whether or not is transferred.

  Here, the condition determination unit 31 determines whether the random number satisfies a predetermined condition and transfers the determination data to the erasure count stepping unit 32. For example, when the random number generated by the random number generation program is 0 or 1, This means that the judgment data to be advanced is transferred to the erasure count step 32 only when is 1.

  The predetermined condition is, for example, (1) based on a threshold (for example, 127) in which random numbers generated by the random number generation program within a certain range (for example, within an integer range of 0 to 255) are stored in the RAM 15 in advance. Or (2) a random number generated by a random number generation program within a certain range (for example, an integer range from 0 to 255) falls within a certain value (for example, 127), or (3) It is possible to set whether or not a random number generated in a specific range (for example, 127 to 255) within the above-mentioned fixed range belongs.

  The erase count step 32 is used to increment the erase count or read count based on the determination data transferred from the condition determination section 31.

  When data stored in a specific block is erased and the determination data is received by the erasure count stepping unit 32, the erasure count stepping unit 32 selects a specific one of the block counter tables 17a provided in the RAM 15. The number of data erasure operations in this block is read onto the RAM 15. When the generated random number receives the determination data that satisfies the above-mentioned predetermined condition, the erase count increment unit 32 increments the number of data erase operations in a specific block in the block counter table 17a. And store it again in the block counter table 17a.

  When data stored in a specific page is read out, the erasure count stepping unit 32 reads out the read operation count of data in a specific page in the page counter table 17b and reads out the read operation. When incrementing the number of times, it is stored again in the page counter table 17b.

  The counter storage unit 33 includes a block counter table 17a in which the number of erase operations for each block in the NAND flash memory 10 is stored, and a page counter table 17b in which the number of read operations for each page is stored.

[Counting the number of times of erasing or reading]
Next, the counting operation of the number of times of erasing or the number of times of reading by the NAND controller 11 in the present embodiment will be described with reference to FIGS. FIG. 4 is a flowchart showing the count operation by the NAND controller 11 in the first embodiment of the present invention.

  In order to simplify the description, consider a case where there are two blocks (first block and second block) formed in the memory cell array.

  First, in step S1, for example, the host device issues a request to erase data in the first block, and the MPU 13 erases data in the first block.

  Next, in step S2, when the data of the first block is erased, the random number generation program stored in the ROM 14 is read onto the RAM 15 by the MPU 13 to generate random numbers. The random number to be generated is a random number within a certain range (for example, 0 to 63). This random number is temporarily stored in the RAM 15.

  In step S3, the MPU 13 is used to read a condition determination program on the RAM 15 and determine whether the random number satisfies a predetermined condition. Here, for example, the predetermined condition is a condition that the random number is “0” or not. If the random number generated in step S2 is “0” (Yes in step S3), the MPU 13 is used to calculate the number of erase operations for the first block in the block counter table 17a stored on the RAM 15. Read to RAM 15 and temporarily store. Thereafter, the MPU 13 is used to increment the erase operation count of the first block by the erase count increment program (step S4). The incremented erase operation count is stored again in the block counter table 17a as the first block erase operation count (step S5).

  On the other hand, when the random number generated in step S2 is other than “0” (in the case of No in step S3), the MPU 13 is used to store the first block in the block counter table 17a stored on the RAM 15. The number of erasure operations is stored as it is (step S5).

  Then, after storing the number of erasure operations in step S5, the process ends (step S6).

  The above steps S1 to S5 are performed not only when erasing data in the first block but also when erasing data in the second block.

  As described above, it is possible to provide a memory system capable of reducing the storage capacity of the number of erasures by a simple method.

  In the memory system according to the present embodiment, the number of erase operations in the block counter table 17a is not incremented every time the block data is erased. Even if the block data is erased, the erase in the block counter table 17a is not performed. There are cases where the number of computations is not incremented.

  For this reason, the number of erase operations to be incremented is smaller than the number of erase operations. As a result, the number of erase operations in the block counter table 17a can be made smaller than the actual number of erase operations, and the storage capacity stored in the block counter table 17a can be reduced.

  In the present embodiment, an example in which the predetermined condition is whether the random number is “0” or not is shown. However, as the predetermined condition, the number of erasures or the number of readings may be increased stochastically. Well, there is no need to be constrained by the above conditions. For example, it may be a condition that whether or not a random number generated under a predetermined condition belongs within a certain range, and whether the random number generated under a predetermined condition is larger or smaller than a certain threshold stored in advance in the memory system It is good also as conditions for judging.

  As for the count operation of the number of readings, the same operation is performed up to step S3, and when the generated random number satisfies a predetermined condition, the reading counter in the page counter table 17b is incremented. On the other hand, when the generated random number does not satisfy the predetermined condition, the read counter in the page counter table 17b is not incremented and stored as it is.

[Modification 1 of the first embodiment]
In the first embodiment of the present invention, for example, when erasing data in the first block, the random number generation program is read and one random number is generated. However, as a modification of the first embodiment, random number generation is performed. A plurality of random numbers for reading and generating a program may be used.

  Specifically, a plurality of random numbers (for example, two, for example, hereinafter referred to as a first random number and a second random number) are generated within a certain range. Then, the plurality of random numbers are ordered and temporarily stored in the RAM 15 as a table (for example, the first random number is the first and the second random number is the second). First, when the data in the first block is erased, the above-described steps S1 to S4 are performed using the first random number (first random number), and the second data is erased when the data in the next second block is erased. Steps S1 to S4 are performed using the random number (second random number).

  This eliminates the need to read the random number generation program every time data is erased by the MPU 13. For this reason, the time required for random number generation can be shortened.

[Modification 2 of the first embodiment]
The memory system according to the first embodiment of the present invention is intended for a storage device connected to a host device, but as a modification of the first embodiment of the present invention, the memory system connects the storage device to the host device. The entire system may be included. At this time, the random number generation program, the condition determination program, and the erase count step program according to the present embodiment are stored in the host device, and the above-mentioned erase count or read count is calculated using the central processing unit of the host device. May be stored in the block counter table 17a or the page counter table 17b on the RAM 15.

[Modification 3 of the first embodiment]
A modification of the random number generation program and the condition determination program in the memory system according to the first embodiment of the present invention will be described. In order to simplify the description, a predetermined condition of the condition determination program is set as a condition whether or not the generated random number is “0”.

  The random number generated in the first embodiment of the present invention is a random number within a certain range (for example, “0 to 63”). In the third modification of the first embodiment, a certain range of this random number is set wide. For example, it is set to generate a random number within a certain range of “0 to 255”. As a result, the probability that the generated random number is “0” is lower than in the first embodiment.

  Accordingly, data in a certain block is erased or data is read out from a certain page, and the number of erase operations of the block in the block counter table 17a or the reading of the page in the page counter table 17b is performed by the erasure count stepping unit 23. The probability that the number of operations is incremented is also reduced. As a result, the storage capacity for the number of erase operations and the number of read operations stored in the block counter table 17a can be reduced.

  On the other hand, you may set the fixed range of the random number in the modification 3 of 1st Embodiment narrowly with respect to 1st Embodiment. For example, it is set to generate a random number within a certain range of “0 to 16”. As a result, the probability that the generated random number is “0” is higher than in the first embodiment.

  As a result, the block counter table 17a or the page counter table 17b can accurately indicate the number of times the data of a certain block is erased or the number of times the data of a certain page is read compared to the first embodiment.

  As shown in FIG. 5, a change unit 34 that changes the above-mentioned fixed range when the number of erase operations in each block exceeds a predetermined number may be further provided in the memory system. FIG. 5 is a block diagram showing an outline of functions of the NAND controller in the third modification of the first embodiment of the present invention.

  A memory cell has an upper limit on the number of times data can be erased. When the number of data erasures exceeds a number close to this upper limit, the change may be made by using the changing unit 34 in which the predetermined number of times is set so as to narrow a certain range of random numbers generated. For example, the predetermined number of times is set to a number that is close to the upper limit of the number of times of erasing the memory cell multiplied by the probability that the number of erasing operations is incremented. It changes using the part 34.

  Thus, when the certain range is changed to be narrowed, the number of data erasures or the number of data readings can be accurately indicated.

  That is, it is possible to reduce the storage capacity of the number of erase operations or the number of read operations stored in the block counter table 17a or the page counter table 17b, and more accurately indicate the number of data erase times or the number of data read times. . As a result, the data erase count or the data read count can be leveled for each memory cell. The lifetime of the memory cell can be extended.

(Second Embodiment)
Next, the configuration of the memory system according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a conceptual diagram showing a random number table of the memory system in the second embodiment of the present invention.

  Note that the memory system in the second embodiment stores a random number table (random number storage unit) in which random numbers previously stored in the memory system are stored in the memory system of the first embodiment. Random numbers are read in order each time data is erased. For example, it is determined whether or not to increment the number of erasure operations in the block counter table 17a, and the other components have the same configuration. Have. Therefore, in the following description, detailed description of the same components as those in the first embodiment will be omitted, and different components will be described.

[Memory system configuration]
Unlike the memory system according to the first embodiment, the memory system according to the second embodiment of the present invention does not include a random number generation program. In the memory system of this embodiment, a random number table in which ordered random numbers are stored is stored in, for example, the RAM 15.

  For example, as shown in FIG. 6, a plurality of random numbers of 0 or 1 are stored, and each random number is ordered by a pointer number. The stored random number is read out along the pointer number. The number of stored random numbers is a prime number (67 in FIG. 6), and the number of pointers is the same number of prime numbers (67 in FIG. 6), forming a random number table.

[Counting the number of times of erasing or reading]
Next, the operation of counting the number of times data is erased or the number of times data is read from the memory system will be described with reference to FIG. FIG. 7 is a flowchart showing the counting operation of the number of times of erasing or reading of data in the memory system according to the second embodiment of the present invention.

  Note that a block range (hereinafter referred to as a step determination range) for simultaneously determining whether to increment the number of erase operations or the number of read operations is n (n is a natural number) blocks. The number of blocks within the step determination range changes in response to an erase request from the host device.

  First, in step S1, the MPU 13 is used to read the pointer i set in the random number table in the initial state. In step S2, for example, the host device makes an erase request for n blocks in the progress determination area, and the MPU 13 erases data in the n blocks in the progress determination area. At this time, the MPU 13 sets the same number of pointers corresponding to n blocks in the progress determination area as the number of blocks in the progress determination area starting from the pointer i (n blocks corresponding to the ascending / descending order of blocks). Pointers are set as pointer i to pointer i + n−1).

  To simplify the following description, the number of blocks formed in the memory cell array is two (first block and second block), which is smaller than the number of random numbers stored in the random number table. Assume that two blocks that are numbers are always step determination areas.

  In this case, in step S2, for example, when the data of the first block and the second block are erased by a request from the host device, the pointer 1 is set for the first block and the pointer 2 is set for the second block.

  Next, after step S2, the random number table stored in the RAM 15 is read by the MPU 13, and out of this random number table, the random number corresponding to each pointer set by the MPU 13 in step S2 is read onto the RAM 15. In the case of the above example, “0” corresponding to the pointer 1 set in the first block and “0” corresponding to the pointer 2 set in the second block are read (step S3).

  In step S4, the MPU 13 is used to read a condition determination program on the RAM 15, and determine whether each read random number satisfies a predetermined condition. For example, the predetermined condition is a condition that the random number is “0” or not. If the random number generated in step S3 is “0” (Yes in step S4), the MPU 13 is used to store the number of erase operations for each block in the block counter table 17a stored in the RAM 15 in the RAM 15. And store it temporarily. Thereafter, the MPU 13 increments the number of erase operations for each block using an erase count increment program (step S5). In the above example, since the random number corresponding to the first block is “0”, the number obtained by adding 1 to the number of erase operations in the first block is incremented as the number of erase operations in the first block (step S5). . Similarly, since the random number corresponding to the second block is also “0”, the number of erase operations of the second block is also incremented by 1 (step S5).

  The number of erase operations advanced in the first block and the number of erase operations advanced in the second block are stored again in the block counter table 17a (step S6).

  On the other hand, if the random number generated in step S2 is other than “0” (No in step S4), the MPU 13 is used to erase each block in the block counter table 17a stored on the RAM 15. The number of calculations is stored as it is (step S6).

  After storing the number of block erase operations in the block counter table 17a, the pointer used in steps S1 to S6 is incremented by 1 and set in the random number table. The process ends (step S7). In the case of the above example, since the pointer with the largest pointer number is the pointer 2, the process is terminated by stepping the pointer 3 and setting it in the random number table.

  After step S7, for example, when the host device makes a data erasure request again in the first block and the second block, the MPU 13 is used to read the pointer 3 set in the random number table. Similarly to the above step S2, when the data of the first block and the second block is erased by the MPU 13, the random number table stored in the RAM 15 is read using the MPU 13, and the pointer 3 set by the MPU 13 in the random number table is read. , 4 are read out on the RAM 15.

  In this way, for example, every time the host device makes a data erasure request in two blocks in the progress determination area, the two pointers are shifted by two according to the order, and the pointers after the shift are respectively changed. Get the corresponding random number. A condition determination program is applied using each random number. However, the pointer 67 is set when the data of the first block and the second block are erased again after applying the condition determination program using the pointer 65 and the random number corresponding to the pointer 66. The pointer next to the pointer 67 is returned to the pointer 1 in the random number table, and the condition determination program is applied. That is, after using all the pointers in the random number table, the pointer is shifted to the pointer 1 and the condition determination program is applied.

  As described above, by applying the condition determination program to the acquired random number, it is possible to provide a memory system that can reduce the storage capacity of the number of erasures by a simple method.

  In the present embodiment, a random number table that stores pre-ordered random numbers is stored in the memory system. For this reason, it is not necessary to generate a random number every time data in a certain block is erased. Therefore, compared with the first embodiment, it is possible to speed up the processing of counting the number of times of erasure or the number of times of reading.

  In the present embodiment, the random numbers stored in the random number table are prime numbers. Further, when erasing block data, the pointer returns to the pointer 1 again after using the pointer in the random number table all the time, so the pointer may be used a plurality of times. For this reason, a block that uses a certain pointer for the first time may be different from a block that uses a certain pointer for a plurality of times (for example, the second time). In the above example, the pointer 1 is used for the first time for the first block, and the second time is used for the second block.

  As a result, it is difficult to cause a bias in the number of erase operations for each block in the block counter table 17a. As a result, the number of erases of the memory cell can be leveled, and the life of the memory cell can be extended.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

DESCRIPTION OF SYMBOLS 10 ... NAND type flash memory 11 ... NAND controller 12 ... Host interface circuit 13 ... MPU
14 ... ROM
15 ... RAM
16 ... NAND interface circuit 17a ... block counter table 17b ... page counter table 30 ... random number acquisition unit 31 ... condition determination unit 32 ... erase count step unit 33 ... counter storage unit 34 ... change unit

Claims (6)

A storage unit capable of storing data in a block which is a unit of data erasure;
A counter storage unit for storing the number of erasure operations stored each time the data stored in the storage unit is erased;
A random number acquisition unit for acquiring a random number when the data stored in the storage unit is erased;
A condition determination unit for determining whether or not the random number satisfies a predetermined condition;
When the condition determination unit determines that the random number satisfies a predetermined condition, an erasure count stepping unit that increments the erasure calculation count;
A memory system comprising: a changing unit that changes the predetermined condition when the number of erasure operations stored in the storage unit exceeds a predetermined number. The changing unit is
2. The predetermined condition is changed to a condition that has a higher probability that the random number satisfies the predetermined condition when the number of erasure operations stored in the storage unit exceeds a predetermined number. The described memory system. The random number acquisition unit
A random number storage unit in which the ordered random numbers are stored;
3. The memory system according to claim 1, wherein when the data stored in the storage unit is erased, the random numbers in an order corresponding to the number of times of erasure are acquired. A plurality of the blocks in the storage unit are provided,
The ordered random numbers in the random number storage unit are provided as prime numbers,
4. The memory system according to claim 3, wherein a step determination range for simultaneously determining whether to increment the number of erasure operations is set for each block smaller than the prime number. The memory system according to claim 1, wherein the predetermined condition is set so as to reduce a probability that the random number satisfies the predetermined condition. 5. The memory system according to claim 1, wherein the predetermined condition is set so as to increase a probability that the random number satisfies the predetermined condition.

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